JP2501869Y2 - Negative power supply high frequency integrated circuit mounting structure - Google Patents

Negative power supply high frequency integrated circuit mounting structure

Info

Publication number
JP2501869Y2
JP2501869Y2 JP1989085985U JP8598589U JP2501869Y2 JP 2501869 Y2 JP2501869 Y2 JP 2501869Y2 JP 1989085985 U JP1989085985 U JP 1989085985U JP 8598589 U JP8598589 U JP 8598589U JP 2501869 Y2 JP2501869 Y2 JP 2501869Y2
Authority
JP
Japan
Prior art keywords
integrated circuit
power supply
high frequency
negative power
frequency integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1989085985U
Other languages
Japanese (ja)
Other versions
JPH0325255U (en
Inventor
幹人 柳生
千隆 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1989085985U priority Critical patent/JP2501869Y2/en
Publication of JPH0325255U publication Critical patent/JPH0325255U/ja
Application granted granted Critical
Publication of JP2501869Y2 publication Critical patent/JP2501869Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は集積回路チップの実装構造に関し、特に基準
電位が負電位である高周波集積回路の実装構造に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a mounting structure of an integrated circuit chip, and more particularly to a mounting structure of a high frequency integrated circuit in which a reference potential is a negative potential.

〔従来の技術〕[Conventional technology]

従来、この種の負電源高周波集積回路チップ1を実装
する構造は第2図に示すように集積回路搭載用基板3の
負電源パターン上に集積回路チップ1を実装し、集積回
路チップ1の基準電位は負電源パターンよりチップコン
デンサ5、さらに集積回路基板上のスルーホール4を介
して交流的な接地を行う実装構造となっていた。また、
図中、6はマイクロチップコンデンサである。
Conventionally, the structure for mounting the negative power supply high frequency integrated circuit chip 1 of this type is such that the integrated circuit chip 1 is mounted on the negative power supply pattern of the integrated circuit mounting substrate 3 as shown in FIG. The potential has a mounting structure in which the AC power supply is grounded through the chip capacitor 5 and the through hole 4 on the integrated circuit board from the negative power source pattern. Also,
In the figure, 6 is a microchip capacitor.

〔考案が解決しようとする課題〕[Problems to be solved by the device]

上述した従来の負電源高周波集積回路チップ1の実装
は、高周波集積回路チップの基準電位を集積回路搭載用
基板3の負電源パターン(導体パターン)、チップコン
デンサ5を介して交流的に接地する構成となっているた
め、特にGHzを超えるような高周波領域では負電源パタ
ーン(導体パターン)及びチップコンデンサ5に寄生の
キャパシタンスやインダクタンスが存在するために基準
電位の交流的な接地が不十分であり、集積回路の入出力
端子間の絶縁性が保てない等により、発振や漏話の原因
となり得る。また、チップコンデンサをバイパスコンデ
ンサとして使用するため、実装規模が大きくなるという
欠点があった。
The mounting of the above-described conventional negative power supply high frequency integrated circuit chip 1 is configured such that the reference potential of the high frequency integrated circuit chip is AC grounded via the negative power supply pattern (conductor pattern) of the integrated circuit mounting substrate 3 and the chip capacitor 5. Therefore, especially in a high frequency region exceeding GHz, the negative power supply pattern (conductor pattern) and the chip capacitor 5 have parasitic capacitance and inductance, and therefore the AC grounding of the reference potential is insufficient. The insulation between input / output terminals of the integrated circuit cannot be maintained, which may cause oscillation or crosstalk. Further, since the chip capacitor is used as a bypass capacitor, there is a drawback that the mounting scale becomes large.

本考案の目的は前記課題を解決した負電源高周波集積
回路実装構造を提供することにある。
An object of the present invention is to provide a negative power supply high frequency integrated circuit mounting structure that solves the above problems.

〔課題を解決するための手段〕[Means for solving the problem]

前記目的を達成するため、本考案に係る負電源高周波
集積回路実装構造は、負電源高周波集積回路チップと、
負電源高周波集積回路搭載用台座コンデンサと、集積回
路搭載基板とを有する負電源高周波集積回路実装構造で
あって、 負電源高周波集積回路チップは、負電源高周波集積回
路搭載用台座コンデンサの表面電極に実装されたもので
あり、 負電源高周波集積回路搭載用台座コンデンサは、裏面
電極が集積回路搭載基板の導体パターンに実装されたも
のであり、 集積回路搭載基板は、該基板に実装された負電源高周
波集積回路搭載用台座コンデンサの裏面電極を、該基板
に設けたスルーホールにより基板裏面の接地面に接続し
たものである。
To achieve the above object, a negative power supply high frequency integrated circuit packaging structure according to the present invention comprises a negative power supply high frequency integrated circuit chip,
A negative power supply high frequency integrated circuit mounting structure having a negative power supply high frequency integrated circuit mounting base capacitor and an integrated circuit mounting substrate, wherein the negative power supply high frequency integrated circuit chip is a surface electrode of the negative power supply high frequency integrated circuit mounting base capacitor. Negative power supply The pedestal capacitor for high frequency integrated circuit mounting has the back surface electrode mounted on the conductor pattern of the integrated circuit mounting board, and the integrated circuit mounting board is the negative power supply mounted on the substrate. A backside electrode of a pedestal capacitor for mounting a high frequency integrated circuit is connected to a ground plane on the backside of the substrate through a through hole provided in the substrate.

〔実施例〕〔Example〕

次に、本考案について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a),(b)は本考案の一実施例を示す図で
ある。
1 (a) and 1 (b) are views showing an embodiment of the present invention.

負電源高周波集積回路チップ1は高誘電率誘電体によ
る薄板状平行板構造をもつ負電源集積回路搭載用台座コ
ンデンサ2の表面電極に実装され、さらに、集積回路搭
載基板3の導体パターン上に裏面電極を実装し、集積回
路搭載基板3上のスルーホール4により裏面接地面に接
続される。5はチップコンデンサである。
The negative power supply high frequency integrated circuit chip 1 is mounted on the surface electrode of a negative power supply integrated circuit mounting pedestal capacitor 2 having a thin plate parallel plate structure made of a high dielectric constant dielectric material. The electrodes are mounted and are connected to the back surface ground plane by through holes 4 on the integrated circuit mounting substrate 3. 5 is a chip capacitor.

〔考案の効果〕[Effect of device]

以上説明したように本考案は負電源高周波集積回路チ
ップをコンデンサ上に実装することにより、集積回路チ
ップの基準電位面の交流的な接地が真近にて可能とな
り、高周波集積回路の入出力端子間の絶縁性が保たれ高
周波特性を向上させ、さらに実装規模を小さくできる効
果がある。
As described above, according to the present invention, by mounting the negative power supply high frequency integrated circuit chip on the capacitor, it becomes possible to ground the reference potential surface of the integrated circuit chip in an AC manner in the immediate vicinity, and the input / output terminals of the high frequency integrated circuit. The insulation between them is maintained, high-frequency characteristics are improved, and the mounting scale can be reduced.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)は本考案の一実施例を示す分解斜視図、
(b)は同平面図、第2図は従来の負電源高周波集積回
路の実装構造を示す平面図である。 1……負電源高周波集積回路チップ 2……負電源集積回路搭載用台座コンデンサ 3……集積回路搭載用基板 4……スルーホール 5……チップコンデンサ 6……マイクロチップコンデンサ
FIG. 1 (a) is an exploded perspective view showing an embodiment of the present invention,
2B is a plan view of the same, and FIG. 2 is a plan view showing a mounting structure of a conventional negative power supply high frequency integrated circuit. 1 ... Negative power supply high frequency integrated circuit chip 2 ... Negative power supply integrated circuit mounting base capacitor 3 ... Integrated circuit mounting substrate 4 ... Through hole 5 ... Chip capacitor 6 ... Microchip capacitor

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項1】負電源高周波集積回路チップと、負電源高
周波集積回路搭載用台座コンデンサと、集積回路搭載基
板とを有する負電源高周波集積回路実装構造であって、 負電源高周波集積回路チップは、負電源高周波集積回路
搭載用台座コンデンサの表面電極に実装されたものであ
り、 負電源高周波集積回路搭載用台座コンデンサは、裏面電
極が集積回路搭載基板の導体パターンに実装されたもの
であり、 集積回路搭載基板は、該基板に実装された負電源高周波
集積回路搭載用台座コンデンサの裏面電極を、該基板に
設けたスルーホールにより基板裏面の接地面に接続した
ものであることを特徴とする負電源高周波集積回路実装
構造。
1. A negative power supply high frequency integrated circuit mounting structure comprising a negative power supply high frequency integrated circuit chip, a negative power supply high frequency integrated circuit mounting base capacitor, and an integrated circuit mounting substrate, wherein the negative power supply high frequency integrated circuit chip comprises: Negative power supply high frequency integrated circuit mounting pedestal capacitor is mounted on the front surface electrode, and negative power supply high frequency integrated circuit mounting pedestal capacitor has the back surface electrode mounted on the conductor pattern of the integrated circuit mounting board. The circuit mounting board is characterized in that a back surface electrode of a pedestal capacitor for mounting a negative power supply high frequency integrated circuit mounted on the board is connected to a ground plane on the back surface of the board by a through hole provided in the board. Power supply high frequency integrated circuit packaging structure.
JP1989085985U 1989-07-21 1989-07-21 Negative power supply high frequency integrated circuit mounting structure Expired - Lifetime JP2501869Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989085985U JP2501869Y2 (en) 1989-07-21 1989-07-21 Negative power supply high frequency integrated circuit mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989085985U JP2501869Y2 (en) 1989-07-21 1989-07-21 Negative power supply high frequency integrated circuit mounting structure

Publications (2)

Publication Number Publication Date
JPH0325255U JPH0325255U (en) 1991-03-15
JP2501869Y2 true JP2501869Y2 (en) 1996-06-19

Family

ID=31635389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989085985U Expired - Lifetime JP2501869Y2 (en) 1989-07-21 1989-07-21 Negative power supply high frequency integrated circuit mounting structure

Country Status (1)

Country Link
JP (1) JP2501869Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001015231A1 (en) * 1999-08-19 2001-03-01 Seiko Epson Corporation Wiring board, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110052U (en) * 1987-01-08 1988-07-15

Also Published As

Publication number Publication date
JPH0325255U (en) 1991-03-15

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