JP2025514088A - 処理要素のアレイを含む畳み込みエンジンを使用して実行される行列乗算 - Google Patents
処理要素のアレイを含む畳み込みエンジンを使用して実行される行列乗算 Download PDFInfo
- Publication number
- JP2025514088A JP2025514088A JP2024562065A JP2024562065A JP2025514088A JP 2025514088 A JP2025514088 A JP 2025514088A JP 2024562065 A JP2024562065 A JP 2024562065A JP 2024562065 A JP2024562065 A JP 2024562065A JP 2025514088 A JP2025514088 A JP 2025514088A
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- matrix
- processor
- processing elements
- processing
- multiplication
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
- G06F17/153—Multidimensional correlation or convolution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Algebra (AREA)
- Software Systems (AREA)
- Databases & Information Systems (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202263336586P | 2022-04-29 | 2022-04-29 | |
| US63/336,586 | 2022-04-29 | ||
| PCT/US2023/020213 WO2023212203A1 (en) | 2022-04-29 | 2023-04-27 | Matrix multiplication performed using convolution engine which includes array of processing elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025514088A true JP2025514088A (ja) | 2025-05-02 |
| JP2025514088A5 JP2025514088A5 (https=) | 2026-04-30 |
Family
ID=86469086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024562065A Pending JP2025514088A (ja) | 2022-04-29 | 2023-04-27 | 処理要素のアレイを含む畳み込みエンジンを使用して実行される行列乗算 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20250284767A1 (https=) |
| EP (1) | EP4515426A1 (https=) |
| JP (1) | JP2025514088A (https=) |
| KR (1) | KR20250002449A (https=) |
| CN (1) | CN119278445A (https=) |
| WO (1) | WO2023212203A1 (https=) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11157287B2 (en) | 2017-07-24 | 2021-10-26 | Tesla, Inc. | Computational array microprocessor system with variable latency memory access |
| US11157441B2 (en) | 2017-07-24 | 2021-10-26 | Tesla, Inc. | Computational array microprocessor system using non-consecutive data formatting |
| US11409692B2 (en) | 2017-07-24 | 2022-08-09 | Tesla, Inc. | Vector computational unit |
| US11256977B2 (en) * | 2017-12-29 | 2022-02-22 | Facebook, Inc. | Lowering hardware for neural networks |
| EP3674982A1 (en) * | 2018-12-27 | 2020-07-01 | IMEC vzw | Hardware accelerator architecture for convolutional neural network |
-
2023
- 2023-04-27 EP EP23725527.8A patent/EP4515426A1/en active Pending
- 2023-04-27 CN CN202380043098.6A patent/CN119278445A/zh active Pending
- 2023-04-27 JP JP2024562065A patent/JP2025514088A/ja active Pending
- 2023-04-27 US US18/859,039 patent/US20250284767A1/en active Pending
- 2023-04-27 KR KR1020247037544A patent/KR20250002449A/ko active Pending
- 2023-04-27 WO PCT/US2023/020213 patent/WO2023212203A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20250284767A1 (en) | 2025-09-11 |
| WO2023212203A1 (en) | 2023-11-02 |
| CN119278445A (zh) | 2025-01-07 |
| KR20250002449A (ko) | 2025-01-07 |
| EP4515426A1 (en) | 2025-03-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20260421 |
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| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20260421 |