JP2024501015A5 - - Google Patents

Info

Publication number
JP2024501015A5
JP2024501015A5 JP2023539265A JP2023539265A JP2024501015A5 JP 2024501015 A5 JP2024501015 A5 JP 2024501015A5 JP 2023539265 A JP2023539265 A JP 2023539265A JP 2023539265 A JP2023539265 A JP 2023539265A JP 2024501015 A5 JP2024501015 A5 JP 2024501015A5
Authority
JP
Japan
Prior art keywords
subset
miss
cache
subsets
computing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023539265A
Other languages
English (en)
Japanese (ja)
Other versions
JP7650983B2 (ja
JP2024501015A (ja
Filing date
Publication date
Priority claimed from US17/134,790 external-priority patent/US11720499B2/en
Application filed filed Critical
Publication of JP2024501015A publication Critical patent/JP2024501015A/ja
Publication of JP2024501015A5 publication Critical patent/JP2024501015A5/ja
Application granted granted Critical
Publication of JP7650983B2 publication Critical patent/JP7650983B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2023539265A 2020-12-28 2021-12-22 キャッシュラインに対するミス要求の選択的生成 Active JP7650983B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/134,790 US11720499B2 (en) 2020-12-28 2020-12-28 Selective generation of miss requests for cache lines
US17/134,790 2020-12-28
PCT/US2021/064797 WO2022146810A1 (en) 2020-12-28 2021-12-22 Selective generation of miss requests for cache lines

Publications (3)

Publication Number Publication Date
JP2024501015A JP2024501015A (ja) 2024-01-10
JP2024501015A5 true JP2024501015A5 (enExample) 2024-12-23
JP7650983B2 JP7650983B2 (ja) 2025-03-25

Family

ID=82117109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023539265A Active JP7650983B2 (ja) 2020-12-28 2021-12-22 キャッシュラインに対するミス要求の選択的生成

Country Status (6)

Country Link
US (1) US11720499B2 (enExample)
EP (1) EP4268178B1 (enExample)
JP (1) JP7650983B2 (enExample)
KR (1) KR102917918B1 (enExample)
CN (1) CN116745800A (enExample)
WO (1) WO2022146810A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117132446B (zh) * 2023-05-26 2024-07-23 摩尔线程智能科技(北京)有限责任公司 Gpu的数据访问处理方法、装置及存储介质
CN116467227B (zh) * 2023-06-19 2023-08-25 深流微智能科技(深圳)有限公司 Tmu系统和tmu系统的运算优化方法
US12596650B2 (en) 2023-09-29 2026-04-07 Advanced Micro Devices, Inc. Preemptive flushing of processing-in-memory data structures
CN117555824B (zh) * 2024-01-12 2024-07-30 深圳中微电科技有限公司 基于mvp架构的gpu模拟器中高速缓存器存储架构

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724391B1 (en) * 2000-06-30 2004-04-20 Intel Corporation Mechanism for implementing Z-compression transparently
US7348988B2 (en) 2005-05-06 2008-03-25 Via Technologies, Inc. Texture cache control using an adaptive missing data table in a multiple cache computer graphics environment
US7467280B2 (en) * 2006-07-05 2008-12-16 International Business Machines Corporation Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
KR101393454B1 (ko) * 2007-03-13 2014-05-13 프리스케일 세미컨덕터, 인크. 캐시 사용자 시작 프리-페치 요청들을 생성하기 위한 장치 및 방법
US9214007B2 (en) * 2008-01-25 2015-12-15 Via Technologies, Inc. Graphics processor having unified cache system
US9110810B2 (en) * 2011-12-06 2015-08-18 Nvidia Corporation Multi-level instruction cache prefetching
US9046916B2 (en) 2012-11-06 2015-06-02 Intel Corporation Cache prefetch for NFA instructions
KR102061069B1 (ko) 2013-02-28 2020-01-02 삼성전자주식회사 텍스쳐 맵핑 파이프라인을 위한 논블로킹 방식의 텍스쳐 캐쉬 메모리 시스템 및 논블로킹 방식의 텍스쳐 캐쉬 메모리의 동작 방법
KR102147356B1 (ko) * 2013-09-30 2020-08-24 삼성전자 주식회사 캐시 메모리 시스템 및 그 동작방법
US10261901B2 (en) 2015-09-25 2019-04-16 Intel Corporation Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
US10181176B2 (en) * 2016-03-04 2019-01-15 Samsung Electronics Co., Ltd. Efficient low-power texture cache architecture
US20180018266A1 (en) * 2016-07-18 2018-01-18 Advanced Micro Devices, Inc. Stride prefetcher for inconsistent strides
US10783694B2 (en) * 2017-08-25 2020-09-22 Advanced Micro Devices, Inc. Texture residency checks using compression metadata
GB2566733B (en) * 2017-09-25 2020-02-26 Advanced Risc Mach Ltd Performimg convolution operations in graphics texture mapping units
US10896141B2 (en) * 2019-03-26 2021-01-19 Intel Corporation Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor
GB2584440B (en) 2019-06-03 2021-12-08 Advanced Risc Mach Ltd Cache arrangement for graphics processing systems

Similar Documents

Publication Publication Date Title
JP2024501015A5 (enExample)
JP2004164641A5 (enExample)
JP4360766B2 (ja) Ｄｒａｍキャッシュ・メモリ中のデータをリフレッシュする方法および装置
US9773476B2 (en) Cache memory system for a pixel shader and method of operating the same
US10769837B2 (en) Apparatus and method for performing tile-based rendering using prefetched graphics data
US10691347B2 (en) Extended line width memory-side cache systems and methods
CN101361049B (zh) 用于高级高速缓存驱逐候选对象标识的巡查窥探
JP2021506033A5 (enExample)
US20170185528A1 (en) A data processing apparatus, and a method of handling address translation within a data processing apparatus
JP2020531994A5 (enExample)
CA2649567A1 (en) Graphics system with configurable caches
US9256536B2 (en) Method and apparatus for providing shared caches
US20170192886A1 (en) Cache management for nonvolatile main memory
TW200502679A (en) Access request for a data processing system having no system memory
JP2014164769A5 (enExample)
CN101493796A (zh) 存储器内、页面内目录高速缓存一致性配置
CN115878507B (zh) 系统级芯片的内存访问方法、装置及电子设备
CN106339330B (zh) 高速缓存刷新的方法及系统
CN115794673A (zh) 系统级芯片non-Cacheable数据的访问方法、装置及电子设备
JP2005531847A (ja) キャッシュメモリへのプリフェッチを制御するための方法ならびに装置
JP2013174997A (ja) キャッシュ制御装置、及びキャッシュ制御方法
US10310981B2 (en) Method and apparatus for performing memory prefetching
CN100416610C (zh) 图形处理系统、装置及其纹理数据的处理方法
US20180189179A1 (en) Dynamic memory banks
CN115794675B (zh) 写数据方法、装置、图形处理系统、电子组件及电子设备