CN116745800A - 针对高速缓存行的未命中请求的选择性生成 - Google Patents

针对高速缓存行的未命中请求的选择性生成 Download PDF

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Publication number
CN116745800A
CN116745800A CN202180088052.7A CN202180088052A CN116745800A CN 116745800 A CN116745800 A CN 116745800A CN 202180088052 A CN202180088052 A CN 202180088052A CN 116745800 A CN116745800 A CN 116745800A
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CN
China
Prior art keywords
miss
cache
response
subset
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180088052.7A
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English (en)
Chinese (zh)
Inventor
法塔内·F·古德拉特
斯蒂芬·W·苏木杰
柳真洪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Advanced Micro Devices Inc
Original Assignee
Samsung Electronics Co Ltd
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd, Advanced Micro Devices Inc filed Critical Samsung Electronics Co Ltd
Publication of CN116745800A publication Critical patent/CN116745800A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Generation (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CN202180088052.7A 2020-12-28 2021-12-22 针对高速缓存行的未命中请求的选择性生成 Pending CN116745800A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/134,790 US11720499B2 (en) 2020-12-28 2020-12-28 Selective generation of miss requests for cache lines
US17/134,790 2020-12-28
PCT/US2021/064797 WO2022146810A1 (en) 2020-12-28 2021-12-22 Selective generation of miss requests for cache lines

Publications (1)

Publication Number Publication Date
CN116745800A true CN116745800A (zh) 2023-09-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180088052.7A Pending CN116745800A (zh) 2020-12-28 2021-12-22 针对高速缓存行的未命中请求的选择性生成

Country Status (6)

Country Link
US (1) US11720499B2 (enExample)
EP (1) EP4268178B1 (enExample)
JP (1) JP7650983B2 (enExample)
KR (1) KR102917918B1 (enExample)
CN (1) CN116745800A (enExample)
WO (1) WO2022146810A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555824A (zh) * 2024-01-12 2024-02-13 深圳中微电科技有限公司 基于mvp架构的gpu模拟器中高速缓存器存储架构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117132446B (zh) * 2023-05-26 2024-07-23 摩尔线程智能科技(北京)有限责任公司 Gpu的数据访问处理方法、装置及存储介质
CN116467227B (zh) * 2023-06-19 2023-08-25 深流微智能科技(深圳)有限公司 Tmu系统和tmu系统的运算优化方法
US12596650B2 (en) 2023-09-29 2026-04-07 Advanced Micro Devices, Inc. Preemptive flushing of processing-in-memory data structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218309A (zh) * 2011-12-06 2013-07-24 辉达公司 多级指令高速缓存预取
US20140129775A1 (en) * 2012-11-06 2014-05-08 Lsi Corporation Cache prefetch for nfa instructions
US20170091093A1 (en) * 2015-09-25 2017-03-30 Zhe Wang Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
CN107154012A (zh) * 2016-03-04 2017-09-12 三星电子株式会社 图形处理器及其操作方法
US20200310992A1 (en) * 2019-03-26 2020-10-01 Intel Corporation Gather-Scatter Cache Architecture For Single Program Multiple Data (SPMD) Processor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724391B1 (en) * 2000-06-30 2004-04-20 Intel Corporation Mechanism for implementing Z-compression transparently
US7348988B2 (en) 2005-05-06 2008-03-25 Via Technologies, Inc. Texture cache control using an adaptive missing data table in a multiple cache computer graphics environment
US7467280B2 (en) * 2006-07-05 2008-12-16 International Business Machines Corporation Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
KR101393454B1 (ko) * 2007-03-13 2014-05-13 프리스케일 세미컨덕터, 인크. 캐시 사용자 시작 프리-페치 요청들을 생성하기 위한 장치 및 방법
US9214007B2 (en) * 2008-01-25 2015-12-15 Via Technologies, Inc. Graphics processor having unified cache system
KR102061069B1 (ko) 2013-02-28 2020-01-02 삼성전자주식회사 텍스쳐 맵핑 파이프라인을 위한 논블로킹 방식의 텍스쳐 캐쉬 메모리 시스템 및 논블로킹 방식의 텍스쳐 캐쉬 메모리의 동작 방법
KR102147356B1 (ko) * 2013-09-30 2020-08-24 삼성전자 주식회사 캐시 메모리 시스템 및 그 동작방법
US20180018266A1 (en) * 2016-07-18 2018-01-18 Advanced Micro Devices, Inc. Stride prefetcher for inconsistent strides
US10783694B2 (en) * 2017-08-25 2020-09-22 Advanced Micro Devices, Inc. Texture residency checks using compression metadata
GB2566733B (en) * 2017-09-25 2020-02-26 Advanced Risc Mach Ltd Performimg convolution operations in graphics texture mapping units
GB2584440B (en) 2019-06-03 2021-12-08 Advanced Risc Mach Ltd Cache arrangement for graphics processing systems

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218309A (zh) * 2011-12-06 2013-07-24 辉达公司 多级指令高速缓存预取
US20140129775A1 (en) * 2012-11-06 2014-05-08 Lsi Corporation Cache prefetch for nfa instructions
US20170091093A1 (en) * 2015-09-25 2017-03-30 Zhe Wang Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
CN107154012A (zh) * 2016-03-04 2017-09-12 三星电子株式会社 图形处理器及其操作方法
US20200310992A1 (en) * 2019-03-26 2020-10-01 Intel Corporation Gather-Scatter Cache Architecture For Single Program Multiple Data (SPMD) Processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117555824A (zh) * 2024-01-12 2024-02-13 深圳中微电科技有限公司 基于mvp架构的gpu模拟器中高速缓存器存储架构

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WO2022146810A1 (en) 2022-07-07
US11720499B2 (en) 2023-08-08
US20220206950A1 (en) 2022-06-30
EP4268178B1 (en) 2025-10-29
EP4268178A1 (en) 2023-11-01
EP4268178A4 (en) 2024-08-21
JP7650983B2 (ja) 2025-03-25
KR20230127291A (ko) 2023-08-31
KR102917918B1 (ko) 2026-01-23
JP2024501015A (ja) 2024-01-10

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