JP2024089922A - Wiring Board - Google Patents

Abstract

To form a uniform and thin seed layer onto an internal wall surface of an open of a via.SOLUTION: A wiring board includes: a core substrate; a first build-up part; a second build-up part; a third build-up part; and a fourth build-up part. An outermost surface of the wiring board is constructed by the outermost of the third build-up part and the outermost of the fourth build-up part. The minimum value of a distance between a wiring width in a wiring contained in a third conductive layer and the wiring is smaller than the minimum value of the distance between the wiring width in the wiring contained in a first conductive layer, a second conductive layer, and a fourth conductive layer and the wirings. A third insulation layer includes; a via open; and a via conductor that is formed in the via open and connects the third conductive layer with the third conductive layer of a lower layer. The third conductive layer and the via conductor are formed by a seed layer and an electrolyte plating layer on the seed layer. The third insulation layer contains a first inorganic particle forming an inner wall surface of a resin and the via open, and a second inorganic particle embedded into the third insulation layer. A shape of the first inorganic particle has a different shape of the second inorganic particle.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board having multiple build-up sections.

Patent Document 1 discloses an example of a conventional printed wiring board. In the technology disclosed in Patent Document 1, as shown in FIG. 4, the printed wiring board has a first conductor layer 51, an insulating layer 52 formed on the first conductor layer 51, and a via opening 53 formed in the insulating layer 52 to expose a part of the first conductor layer 51. The insulating layer 52 contains a resin 54 and inorganic particles 55. In the intermediate body of the printed wiring board shown in FIG. 4, a seed layer is formed on the upper surface 52a of the insulating layer 52, the inner wall surface 53a of the via opening 53, and the exposed portion 51a of the first conductor layer 51. Then, on the seed layer, a via conductor is formed on the inner wall surface 53a of the via opening 53 and the exposed portion 51a of the first conductor layer 51, and a second conductor layer is formed on the via conductor and the upper surface 52a of the insulating layer 52.

JP 2015-126103 A

In this case, because the via opening 53 is formed by laser processing, inorganic particles 55 may protrude from the inner wall surface 53a of the via opening 53, as shown in the enlarged portion of FIG. 4. Therefore, when attempting to form a seed layer on the inner wall surface 53a of the via opening 53 by sputtering, the lower part of the protruding inorganic particle 55 becomes a shadow area S relative to the particles injected in the vertical direction, and the seed layer may not adhere to the shadow area S.

The wiring board according to the present invention is a wiring board having a core substrate having a first surface and a second surface opposite to the first surface, a first build-up section formed on the first surface and including a plurality of first insulating layers and a plurality of first conductor layers that are alternately stacked, a second build-up section formed on the second surface and including a plurality of second insulating layers and a plurality of second conductor layers that are alternately stacked, a third build-up section formed on the first build-up section and including a plurality of third insulating layers and a plurality of third conductor layers that are alternately stacked, and a fourth build-up section formed on the second build-up section and including at least one fourth insulating layer and at least one fourth conductor layer that are alternately stacked, wherein the outermost surface of the wiring board is composed of the outermost surface of the third build-up section and the outermost surface of the fourth build-up section, and the minimum value of the wiring width of the wiring included in the third conductor layer is the minimum value of the wiring width of the wiring included in the first conductor layer. The minimum value of the wiring width of the wiring included in the conductor layer, the second conductor layer, and the fourth conductor layer is smaller, and the minimum value of the wiring distance of the wiring included in the third conductor layer is smaller than the minimum value of the wiring distance of the wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer. The third insulating layer has the first surface, a second surface opposite to the first surface, a via opening extending from the first surface to the second surface, and a via conductor formed in the via opening and connecting the third conductor layer to the third conductor layer below. The third conductor layer and the via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer. The third insulating layer contains inorganic particles and a resin, and the inorganic particles include first inorganic particles that form the inner wall surface of the via opening and second inorganic particles that are embedded in the third insulating layer, and the shape of the first inorganic particles is different from the shape of the second inorganic particles.

1 is a cross-sectional view showing a schematic diagram of an embodiment of a build-up portion in a wiring board according to the present invention. 5A to 5C are cross-sectional views each showing a characteristic portion of each layer of a third buildup portion in a wiring board according to the present invention; 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. 5A to 5C are cross-sectional views that diagrammatically show an embodiment of a method for manufacturing each layer of the third buildup section. FIG. 1 is a diagram showing an example of a conventional printed wiring board.

<About the wiring board of the present invention>
An embodiment of a wiring board according to the present invention will be described with reference to the drawings. In the example shown in Figures 1 to 3, the dimensions of each component, particularly the height dimension, are shown in dimensions different from the actual dimensions in order to make it easier to understand the features of the present invention.

Figure 1 is a cross-sectional view for explaining one embodiment of the build-up section in the wiring board according to the present invention. In Figure 1, CS is a core substrate having, for example, a first surface CS1 on the upper side in the figure and a second surface CS2 on the lower side. BU1 is a first build-up section formed on the first surface CS1 of the core substrate CS and including a plurality of first insulating layers 12 and a plurality of first conductor layers 11 that are alternately stacked. BU2 is a second build-up section formed on the second surface CS2 of the core substrate CS and including a plurality of second insulating layers 22 and a plurality of second conductor layers 21 that are alternately stacked. BU3 is a third build-up section formed on the first build-up section BU1 and including a plurality of third insulating layers 32 and a plurality of third conductor layers 31 that are alternately stacked. BU4 is a fourth build-up section formed on the second build-up section BU2 and including at least one layer of fourth insulating layer 42 and at least one layer of fourth conductor layer 41 that are alternately stacked. In this embodiment, chip 1 and chip 2 are mounted on the third build-up section BU3 of the wiring board 1 configured as described above.

In the wiring board according to the present invention shown in FIG. 1, it is preferable to use a glass core as the core substrate CS. When a glass core is used as the core substrate, it becomes easier to form high density wiring compared to wiring boards using core substrates of other materials. Any conventionally known material can be used as the glass core. For example, borosilicate glass, which has excellent heat resistance and impact resistance and a thermal expansion coefficient close to that of silicon, can be used.

The wiring board 1 according to this embodiment is characterized by the structure of the third build-up section BU3. That is, the minimum values of the wiring width and the distance between the wirings included in the third conductor layer are smaller than the minimum values of the wiring width and the distance between the wirings included in the first conductor layer, the second conductor layer, and the fourth conductor layer. The third insulating layer has a first surface, a second surface opposite to the first surface, a via opening extending from the first surface to the second surface, and a via conductor connecting the third conductor layer and the third conductor layer below, and the third conductor layer and the via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer. Furthermore, the third insulating layer contains inorganic particles and a resin, and the inorganic particles include first inorganic particles forming the inner wall surface of the via opening and second inorganic particles embedded in the third insulating layer, and the shape of the first inorganic particles is different from the shape of the second inorganic particles.

In the wiring board according to this embodiment, the third buildup section BU3 has the above-mentioned configuration, which makes it possible to achieve high density wiring in the third buildup section BU3 and reduce the difference in signal transmission speed between the wiring.

Figure 2 is a schematic diagram for explaining characteristic parts of one embodiment of each layer of the third buildup section BU3 in the wiring board according to this embodiment. In Figure 2, the layer L2 below the layer L1 to be explained has the same configuration as the layer L1. The layer L1 to be explained is formed continuously on the lower layer L2.

In the wiring board according to this embodiment, each layer in the third buildup section BU3 includes the configuration shown in FIG. 2. FIG. 2 shows the third conductor layer 31 of the lower layer L2, the third insulating layer 32 of the layer L1 formed on the third conductor layer 31, and a via opening 37 formed in the third insulating layer 32 that exposes a portion of the third conductor layer 31 of the lower layer L2 as a conductor pad 31a. The third insulating layer 32 includes resin 33 and inorganic particles 34.

In the wiring board according to this embodiment, the inorganic particles 34 include first inorganic particles 34-1 that form the inner wall surface 37a of the via opening 37, and second inorganic particles 34-2 that are embedded in the resin 33 of the third insulating layer 32. The shape of the first inorganic particles 34-1 is different from the shape of the second inorganic particles 34-2. In a preferred embodiment, the inner wall surface 37a of the via opening 37 is formed by the first inorganic particles 34-1 and the resin 33, and is a flat surface due to the flat portions of the first inorganic particles 34-1 and the resin 33.

Therefore, in the intermediate wiring board shown in FIG. 2, even if a seed layer is formed by sputtering on the upper surface 32a of the third insulating layer 32 of layer L1, the inner wall surface 37a of the via opening 37, and the exposed conductor pad 31a of the third conductor layer 31 of the lower layer L2, since the inner wall surface 37a of the via opening 37 is a flat surface, there is no obstacle to the particles sprayed in the vertical direction, and a uniform and thin seed layer can be formed on the inner wall surface 37a of the via opening 37.

<Regarding the manufacturing method of the third buildup section BU3, which is a feature of the wiring board of the present invention>
For the first buildup section BU1, the second buildup section BU2, and the fourth buildup section BU4, the formation of the alternating first insulating layers 12 and the alternating first conductor layers 11, the formation of the alternating second insulating layers 22 and the alternating second conductor layers 21, and the formation of at least one alternating fourth insulating layer 42 and at least one alternating fourth conductor layer 41 can be performed by a conventionally known method. Detailed description of these methods will be omitted here.

With reference to Figures 3A to 3I, we will explain the manufacturing method of the third build-up section BU3, which is a characteristic of the wiring board of the present invention.

First, as shown in FIG. 3A, a third insulating layer 32 and a protective film 36 made of the resin 33 and inorganic particles 34 of the target layer L1 are formed on the lower layer L2. The upper surface 32a of the third insulating layer 32 is formed only of the resin 33, and the inorganic particles 34 are not exposed. Therefore, no irregularities are formed on the upper surface 32a of the third insulating layer 32. The protective film 36 completely covers the upper surface 32a of the third insulating layer 32. An example of the protective film 36 is a film made of polyethylene terephthalate (PET). A release agent is formed between the protective film 36 and the upper surface 32a of the third insulating layer 32.

Next, as shown in FIG. 3B, a laser beam is irradiated from above the protective film 36. The laser beam penetrates the protective film 36 and the third insulating layer 32 at the same time. This forms a via opening 37 for forming a via conductor that connects the third conductor layer 31 of the lower layer L2 and the conductor pad 31a. In the via opening 37, the first inorganic particles 34-1 protrude from the inner wall surface 37a. The laser beam is, for example, a UV laser beam or a _CO2 laser beam. The third conductor layer 31 of the lower layer is exposed by the via opening 37. When the via opening 37 is formed, the upper surface 32a of the third insulating layer 32 is covered with the protective film 36. Therefore, even if the resin 33 scatters when the via opening 37 is formed, the adhesion of the resin 33 to the upper surface 32a of the third insulating layer 32 is suppressed.

Next, as shown in FIG. 3C, in a state where the upper surface 32a of the third insulating layer 32 is covered with the protective film 36, a desmear process is performed on the inside of the via opening 37 by a dry process (plasma). As a result, the inner wall surface 37a of the via opening 37 is roughened, but the upper surface 32a of the third insulating layer 32 is not roughened. Since the upper surface 32a of the third insulating layer 32 is not roughened, the upper surface 32a of the third insulating layer 32 is formed only by the resin 33. The desmear process can be performed under conditions that preferentially etch the inorganic particles 34 over the resin 33 in the third insulating layer 32, for example, by reactive ion etching (RIE) containing a fluorocarbon gas. As a result, the portion of the first inorganic particles 34-1 protruding from the inner wall surface 37a of the via opening 37 can be etched and flattened. As a result, the inner wall surface 37a of the via opening 37 can be made into a flat surface consisting of the flat portion of the first inorganic particles 34-1 and the resin 33.

Next, as shown in FIG. 3D, the protective film 36 is removed from the upper surface 32a of the third insulating layer 32. After the protective film 36 is removed, the upper surface 32a of the third insulating layer 32 is not roughened.

Next, as shown in FIG. 3E, a seed layer 31c is formed on the upper surface 32a of the third insulating layer 32. The seed layer 31c is formed by sputtering. The seed layer 31c is formed by a dry process. The seed layer 31c is also formed on the upper surface of the lower third conductor layer 31 exposed from the via opening 37 and on the inner wall surface 37a of the via opening 37. In this embodiment, the seed layer 31c is composed of a first layer 31c-1 formed by sputtering an alloy containing copper, silicon, and aluminum, and a second layer 31c-2 formed by sputtering copper thereon.

Next, as shown in FIG. 3F, a plating resist 38 is formed on the seed layer 31c. The plating resist 38 has openings for forming the third conductor layer 31, which is composed of the conductor pads 31a and the wiring 31b.

Next, as shown in FIG. 3G, electrolytic plating film 31d is formed on seed layer 31c exposed from plating resist 38. Electrolytic plating film 31d fills via opening 37. Electrolytic plating film 31d is formed higher than plating resist 38. That is, for example, as shown in FIG. 3G, electrolytic plating film 31d is formed outside the upper surface of plating resist 38 so that the upper surface has a convex spherical shape.

Next, as shown in FIG. 3H, the electrolytic plating film 31d and a portion of the upper side of the plating resist 38 are removed by polishing. Polishing is performed until the thickness of the electrolytic plating film 31d reaches the desired thickness. The polishing is performed, for example, by chemical mechanical polishing (CMP). This polishing forms the upper surface of the electrolytic plating film 31d to have an arithmetic mean roughness Ra of 0.3 μm or less.

Then, the plating resist 38 and the seed layer 31c thereunder are removed. As a result, as shown in FIG. 3I, the seed layer 31c on the upper surface 32a of the third insulating layer 32 and the electrolytic plating film 31d form wiring 31b. The seed layer 31c and the electrolytic plating film 31d in the via opening 37 form a via conductor in the via opening 37 and a conductor pad 31a thereon. In this manner, as shown in FIG. 3I, a wiring board according to one embodiment of the present invention is obtained.

In the wiring board according to one embodiment of the present invention, in the third build-up section BU3, the first inorganic particles 34-1 do not protrude from the inner wall surface 37a of the via opening 37, and the inner wall surface 37a of the via opening 37 is a flat surface consisting of the flat portions of the first inorganic particles 34-1 and the resin 33. This allows a uniform and thin seed layer 31c to be formed on the inner wall surface 37a of the via opening 37. As a result, the third conductor layer 31 consisting of the conductor pads 31a and the wiring 31b can be formed accurately and reliably on the seed layer 31c. This makes it possible to provide a wiring board with high quality.

The following describes a preferred embodiment of the wiring board according to the present invention.

In the wiring board according to one embodiment of the present invention, as a preferred example in the third buildup section BU3, it is preferable that the minimum wiring width of the wiring 31b in the third conductor layer 31 is 3 μm or less, and the minimum wiring spacing is 3 μm or less. Furthermore, it is preferable that the wiring 31b included in the third conductor layer 31 is formed so that the aspect ratio is 2.0 or more and 4.0 or less. In this way, since the third buildup section BU3 has wiring 31b with a relatively small wiring width and distance between wirings and a relatively high aspect ratio, a wiring board having a relatively high density of wiring 31b in the surface layer portion can be realized. More appropriate wiring corresponding to the electrical signals carried in the surface layer portion of the wiring board is provided.

In a wiring board according to one embodiment of the present invention, as a preferred example of the third build-up section BU3, the upper surface of the wiring 31b included in the third conductor layer 31 is preferably a polished surface. By making the upper surface of the wiring included in the third conductor layer a polished surface, the upper surface of the third conductor layer 31 has a relatively small roughness and is flat, and therefore the third conductor layer 31 has a relatively uniform thickness. Specifically, the upper surface of the third conductor layer 31 has an arithmetic mean roughness Ra of 0.3 μm or less. By forming the thickness of the wiring 31b relatively uniformly, the insertion loss of the signal carried by the wiring 31b is kept small. Good signal transmission by the wiring 31b can be realized.

In the wiring board according to one embodiment of the present invention, as a preferred example of the third build-up section BU3, it is preferable that the maximum particle size of the inorganic particles 34 contained in the third insulating layer 32 is smaller than the maximum particle size of the inorganic particles contained in the first insulating layer 12 and the second insulating layer 22. When inorganic particles 34 are contained in the third insulating layer 32 that contacts the wiring 31b formed at a relatively high density, if inorganic particles 34 with a relatively large particle size are located between adjacent wirings 31b, 31b, migration through the surface of the inorganic particles 34 may cause a short circuit between the wiring 31b and the adjacent wiring 31b. Therefore, by making the maximum particle size of the inorganic particles 34 that can be contained in the third insulating layer 32 relatively small, the risk of a short circuit in the wirings 31b, 31b can be reduced.

In the wiring board according to one embodiment of the present invention, as a preferred example of the third buildup section BU3, the wiring 31b included in the third conductor layer 31 is preferably composed of a conductor that fills a groove formed in the third insulating layer 32. That is, instead of the above-mentioned third conductor layer 31 protruding upward from the upper surface 32a of the third insulating layer 32, the third conductor layer 31 can also be embedded (buried) in the third insulating layer 32 from the upper surface 32a of the third insulating layer 32. In that case, the upper surface of the third conductor layer 31 embedded in the groove can be a polished surface.

In the wiring board according to one embodiment of the present invention, as a preferred example of the third buildup section BU3, it is preferable that the volume of the third insulating layer 32 constituting the third buildup section BU3 and the volume of the fourth insulating layer 42 constituting the fourth buildup section BU4 are approximately equal. It is also preferable that the volume occupied by the conductors in the third buildup section BU3 and the volume occupied by the conductors in the fourth buildup section BU4 are approximately equal. By satisfying these conditions, it is possible to reduce warping of the wiring board 1.

In the wiring board according to one embodiment of the present invention, as a preferred example of the third build-up section BU3, the inner wall surface 37a of the via opening 37 is preferably formed by the first inorganic particles 34-1 and the resin 33, the first inorganic particles 34-1 having a flat portion, and the flat portion forms the inner wall surface 37a. In addition, it is preferable that the arithmetic mean roughness of the inner wall surface 37a of the via opening 37 is 1.0 μm or less. Furthermore, it is preferable that the inner wall surface 37a of the via opening 37 is formed by the resin 33 and the flat portion of the first inorganic particles 34-1. Furthermore, it is preferable that the flat portion of the first inorganic particles 34-1 and the surface of the resin 33 forming the inner wall surface 37a form an almost common surface. Note that the shape of the second inorganic particles 34-2 is a sphere, the shape of the first inorganic particles 34-1 is obtained by cutting a sphere with a plane, and the shape of the first inorganic particles 34-1 is obtained by cutting the second inorganic particles 34-2 with a plane are all preferred embodiments. Either configuration is a suitable embodiment for forming a uniform and thin seed layer 31c on the inner wall surface 37a of the via opening 37.

1 wiring board 11 first conductor layer 12 first insulating layer 21 second conductor layer 22 second insulating layer 31 third conductor layer 31a conductor pad 31b wiring 31c seed layer 31c-1 first layer 31c-2 second layer 31d electrolytic plating film 32 third insulating layer 32a upper surface 33 resin 34 inorganic particles 34-1 first inorganic particles 34-2 second inorganic particles 36 protective film 37 via opening 37a inner wall surface 38 plating resist 41 fourth conductor layer 42 fourth insulating layer BU1 first buildup section BU2 second buildup section BU3 third buildup section BU4 fourth buildup section CS core substrate CS1 first surface CS2 second surface L1 target layer L2 lower layer

Claims (16)

a first buildup section formed on the first surface and including a plurality of first insulating layers and a plurality of first conductor layers that are alternately stacked; a second buildup section formed on the second surface and including a plurality of second insulating layers and a plurality of second conductor layers that are alternately stacked; a third buildup section formed on the first buildup section and including a plurality of third insulating layers and a plurality of third conductor layers that are alternately stacked; and a fourth buildup section formed on the second buildup section and including at least one fourth insulating layer and at least one fourth conductor layer that are alternately stacked,
an outermost surface of the wiring board is constituted by an outermost surface of the third buildup section and an outermost surface of the fourth buildup section;
a minimum value of a wiring width of the wiring included in the third conductor layer is smaller than a minimum value of a wiring width of the wiring included in the first conductor layer, the second conductor layer, and the fourth conductor layer;
a minimum value of a distance between wirings included in the third conductor layer is smaller than a minimum value of a distance between wirings included in the first conductor layer, the second conductor layer, and the fourth conductor layer;
the third insulating layer has a first surface, a second surface opposite to the first surface, a via opening extending from the first surface to the second surface, and a via conductor formed in the via opening and connecting the third conductor layer to a third conductor layer below;
the third conductor layer and the via conductor are formed of a seed layer and an electrolytic plating layer on the seed layer,
the third insulating layer contains inorganic particles and a resin;
the inorganic particles include first inorganic particles forming an inner wall surface of the via opening and second inorganic particles embedded in the third insulating layer;
The shape of the first inorganic particles is different from the shape of the second inorganic particles. In the wiring board according to claim 1, the core substrate is a glass core. In the wiring board described in claim 1, the minimum wiring width of the wiring included in the third conductor layer is 3 μm or less, and the minimum wiring spacing is 3 μm or less. In the wiring board described in claim 1, the aspect ratio of the wiring included in the third conductor layer is 2 or more and 4 or less. In the wiring board described in claim 1, the upper surface of the wiring included in the third conductor layer is a polished surface. In the wiring board according to claim 1, the maximum particle size of the inorganic particles contained in the third insulating layer is smaller than the maximum particle size of the inorganic particles contained in the first insulating layer and the second insulating layer. In the wiring board described in claim 1, the wiring included in the third conductor layer is composed of a conductor that fills a groove formed in the third insulating layer. In the wiring board according to claim 1, the volume of the third insulating layer constituting the third build-up section and the volume of the fourth insulating layer constituting the fourth build-up section are approximately equal. In the wiring board described in claim 1, the volume occupied by the conductor in the third buildup section is approximately equal to the volume occupied by the conductor in the fourth buildup section. In the wiring board according to claim 1, the inner wall surface is formed by the first inorganic particles and the resin, the first inorganic particles have flat portions, and the flat portions form the inner wall surface. In the wiring board described in claim 1, the arithmetic mean roughness of the inner wall surface is 1.0 μm or less. In the wiring board according to claim 10, the inner wall surface is formed by the resin and the flat portion. In the wiring board according to claim 12, the flat portion and the resin surface forming the inner wall surface form a substantially common surface. In the wiring board described in claim 10, the second inorganic particles have a spherical shape. In the wiring board described in claim 10, the shape of the first inorganic particles is obtained by cutting a sphere with a plane. 15. The wiring board according to claim 14, wherein the shape of the first inorganic particles is obtained by cutting the second inorganic particles along a plane.

Images