JP2024088045A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of improving electrical characteristics, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device of an embodiment comprises a substrate and a transistor. The substrate includes an activation region and an element separation part. The element separation part surrounds the activation region. The transistor comprises a first diffusion layer region, a second diffusion layer region, a gate insulation film, and a gate electrode. The first diffusion layer region and the second diffusion layer region are provided in the activation region. The gate insulation film is provided on the activation region. The gate electrode is positioned on the opposite side of the substrate with respect to the gate insulation film. In a second direction crossing a first direction in which the first diffusion layer region and the second diffusion layer region line and along a surface of the substrate, a width of the gate electrode is the same or small compared to a width of the activation region.SELECTED DRAWING: Figure 2

Description

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

A semiconductor device is known that includes a semiconductor substrate and a transistor disposed on the semiconductor substrate.

JP 2018-049968 A

One embodiment of the present invention provides a semiconductor device that can improve electrical characteristics, and a method for manufacturing the semiconductor device.

The semiconductor device of the embodiment includes a substrate and a transistor. The substrate includes an activation region and an isolation portion. The isolation portion surrounds the activation region. The transistor has a first diffusion layer region and a second diffusion layer region, a gate insulating film, and a gate electrode. The first diffusion layer region and the second diffusion layer region are provided in the activation region. The gate insulating film is provided on the activation region. The gate electrode is located on the opposite side of the gate insulating film to the substrate. In a second direction that intersects with a first direction in which the first diffusion layer region and the second diffusion layer region are aligned and runs along the surface of the substrate, the width of the gate electrode is the same as or smaller than the width of the activation region.

1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment; FIG. 2 is a diagram showing a configuration example of a semiconductor device related to one transistor of the first embodiment. 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 13 is a diagram showing a configuration example of a semiconductor device related to one transistor of a second embodiment. 6A to 6C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. 6A to 6C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. 6A to 6C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. 6A to 6C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. 6A to 6C are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment. 13A to 13C are diagrams illustrating modified examples of a semiconductor device.

The semiconductor device and the manufacturing method of the semiconductor device according to the embodiment will be described below with reference to the drawings. In the following description, the same reference numerals are used for components having the same or similar functions. The duplicated description of those components may be omitted. "Parallel", "orthogonal", or "same" may include the cases of "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection, but may include electrical connection. In other words, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected with another element interposed therebetween. "Facing" means that two members overlap when viewed in a certain direction, and may also include the case where another member exists between the two members.

First, the X-direction, the Y-direction, and the Z-direction are defined. The X-direction and the Y-direction are directions along the surface 20a of the semiconductor substrate 20 (see FIG. 1 and FIG. 2). The X-direction is the direction in which the source region 31 and the drain region 32 are aligned in the transistor 30 (see FIG. 2). In this embodiment, for example, the direction from the source region 31 toward the drain region 32 is the X-direction (see FIG. 2). The Y-direction intersects (e.g., perpendicular to) the X-direction and is a direction along the surface 20a of the semiconductor substrate 20. Furthermore, one side in the Y-direction is the first side, and the opposite side to the first side in the Y-direction is the second side. The Z-direction is a thickness direction that intersects with the surface 20a of the semiconductor substrate 20 and intersects (e.g., perpendicular to) the X-direction and the Y-direction (see FIG. 1 and FIG. 2). In the following description, the side on which the transistor 30 is located with respect to the semiconductor substrate 20 may be referred to as "upper" and the opposite side as "lower". However, these expressions are for convenience and do not define the direction of gravity. The X direction is an example of a "first direction." The Y direction is an example of a "second direction." The Z direction is an example of a "third direction" and a "thickness direction."

First Embodiment
1. Configuration example of semiconductor device
A first embodiment will be described. Fig. 1 is a cross-sectional view showing a configuration example of a semiconductor device 1. The semiconductor device 1 is, for example, a semiconductor memory device such as a NAND type flash memory. The semiconductor device 1 includes, for example, an array chip 2, a circuit chip 3, and the like.

The array chip 2 is a chip capable of storing information. The array chip 2 includes, for example, a stack 11, a plurality of memory pillars 12, a source line SL, and a plurality of bit lines BL. The stack 11 includes a plurality of word lines 11a and a plurality of insulating layers 11b. The plurality of word lines 11a and the plurality of insulating layers 11b are stacked alternately, one layer at a time, in the Z direction.

The multiple memory pillars 12 extend in the Z direction within the stack 11. Each memory pillar 12 includes, from the center of the memory pillar 12 toward the outer periphery, an insulating portion, a channel layer, a tunnel insulating film, a charge storage portion, and a block insulating film. One end of each memory pillar 12 is connected to a source line SL. The other end of each memory pillar 12 is connected to a bit line BL. A memory cell transistor MC is formed at the intersection of each memory pillar 12 and each word line 11a. The memory cell transistor MC is a memory element that can store information by accumulating electric charge.

The circuit chip 3 is a control circuit that controls the operation of the array chip 2. The circuit chip 3 includes, for example, a semiconductor substrate 20, a plurality of transistors 30, a plurality of wirings L, a first insulating film 23 described below, and contact electrodes C1, C2, and C3. The plurality of transistors 30 are provided on the semiconductor substrate 20. The wirings L connect the transistors 30 and the array chip 2.

2. Configuration of Semiconductor Substrate and Transistor
Next, the configurations of the semiconductor substrate 20 and the transistor 30 will be described in detail.

2.1 Semiconductor substrate
FIG. 2 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 relating to one transistor 30. As shown in FIG.
The semiconductor substrate 20 is, for example, a silicon substrate. The semiconductor substrate 20 is an example of a “substrate.” As shown in FIG 2, the semiconductor substrate 20 has, for example, a substrate body 21 and an element isolation portion 22 (Shallow Trench Isolation; STI).

The substrate body 21 is a base on which the transistor 30 is provided. The substrate body 21 includes a silicon material. The substrate body 21 has an active region A. The substrate body 21 has a well region of a different polarity (different conductivity type) from the source region 31 and drain region 32 of the transistor 30, which will be described later, in at least a part of the region of the active region A where the transistor 30 is provided.

The element isolation portion 22 is an isolation portion that electrically isolates a plurality of transistors 30 provided on the semiconductor substrate 20. The element isolation portion 22 is an insulating layer that fills the first space S1 formed to surround the activation region A when viewed from the Z direction. In other words, the element isolation portion 22 surrounds the activation region A of each transistor 30 when viewed from the Z direction. The element isolation portion 22 is formed of, for example, silicon oxide or the like.

At the boundary 25 between the activation region A and the element isolation section 22 in the Y direction, a first insulating film 23 is provided adjacent to the boundary 25. The first insulating film 23 extends in the Z direction from the surface 22a of the element isolation section 22. To explain in more detail, in this embodiment, the first insulating film 23 is formed at the boundary between the gate 33 described later and the element isolation section 22 in the Y direction and at the boundary between the gate 33 and the element isolation section 22 in the X direction, and extends from the surface 22a of the element isolation section 22 and the surface 21a of the substrate body 21 in the Z direction. Therefore, the first insulating film 23 in this embodiment is formed in a ring shape having a second space S2 on the inside when viewed from the Z direction.

The first insulating film 23 also contains a first material. An example of the first material is silicon oxide. That is, in this embodiment, the first insulating film 23 is formed of, for example, silicon oxide, similar to the element isolation portion 22.

2.2 Transistors
Each of the transistors 30 is a field effect transistor, for example a metal oxide semiconductor field effect transistor (MOSFET). A plurality of the transistors 30 constitute a complementary MOS (CMOS) circuit.

Transistor 30 may be, for example, an n-type transistor or a p-type transistor. As shown in FIG. 2, transistor 30 has a source region 31, a drain region 32, and a gate 33.

The source region 31 and the drain region 32 are provided as part of the upper part of the semiconductor substrate 20. The source region 31 and the drain region 32 are provided in an activation region A corresponding to one transistor 30. That is, the source region 31 and the drain region 32 are provided in an activation region A surrounded by an element isolation portion 22. The source region 31 and the drain region 32 are separated from each other in the X direction. The source region 31 and the drain region 32 are formed by doping the upper part of the semiconductor substrate 20 with impurities that act as carriers, for example, by ion implantation. The source region 31 is an example of a "first diffusion layer region." The drain region 32 is an example of a "second diffusion layer region."

Above the source region 31, for example, a contact electrode C1 is provided. The contact electrode C1 is connected to the source region 31 in the Z direction. In this embodiment, two contact electrodes C1 are provided on the source region 31 with a gap therebetween in the Y direction. Above the drain region 32, for example, a contact electrode C2 is provided. The contact electrode C2 is connected to the drain region 32 in the Z direction. In this embodiment, two contact electrodes C2 are provided on the drain region 32 with a gap therebetween in the Y direction.

The gate 33 is provided on the activation region A. The gate 33 spans the source region 31 and the drain region 32. The gate 33 is provided in the second space S2 inside the first insulating film 23 when viewed from the Z direction. The gate 33 has a gate insulating film 34, a functional film 35, and a gate electrode 36.

The gate insulating film 34 is an insulating film located between the semiconductor substrate 20 and the gate electrode 36, and electrically insulates the semiconductor substrate 20 from the gate electrode 36. The gate insulating film 34 is provided on the activation region A surrounded by the element isolation portion 22. At least a portion of the gate insulating film 34 faces the region between the source region 31 and the drain region 32 in the Z direction. The gate insulating film 34 is formed of, for example, silicon oxide.

In this embodiment, the gate insulating film 34 is provided along the substrate body 21 and the first insulating film 23. Therefore, a part of the gate insulating film 34 (a second portion 34b described later) is provided between the gate electrode 36 described later and the first insulating film 23 in the Y direction. The gate insulating film 34 has a first portion 34a and a second portion 34b. The first portion 34a is provided along the surface 21a of the substrate body 21. The second portion 34b extends in the Z direction from the first portion 34a. In this embodiment, the second portion 34b is formed along the first insulating film 23. The second portion 34b is formed in a ring shape when viewed from the Z direction.

The functional film 35 is provided between the gate insulating film 34 and the gate electrode 36. The functional film 35 is an insulating film that suppresses leakage current between the source region 31 and the drain region 32. The functional film 35 is formed on the gate insulating film 34. The functional film 35 includes a second material having a higher dielectric constant than the first material. The functional film 35 of this embodiment is a high-K film that uses a high-K material such as a hafnium-based, tungsten-based, or cobalt-based material as the second material.

In this embodiment, the functional film 35 is provided along the substrate body 21 and the first insulating film 23 via the gate insulating film 34. Therefore, a part of the functional film 35 (a second portion 35b described later) is provided between the gate electrode 36 and the first insulating film 23 in the Y direction. The functional film 35 has a first portion 35a and a second portion 35b. The first portion 35a is provided along the surface 21a of the substrate body 21 via the gate insulating film 34. The second portion 35b extends in the Z direction from the first portion 35a. In this embodiment, the second portion 35b is formed along the first insulating film 23 via the gate insulating film 34. The second portion 35b is formed in a ring shape when viewed from the Z direction.

The gate electrode 36 is formed in the second space S2. The gate electrode 36 fills the area in the second space S2 other than the gate insulating film 34 and the functional film 35. The gate electrode 36 is located on the opposite side of the gate insulating film 34 to the semiconductor substrate 20. In this embodiment, at least a part of the gate electrode 36 faces the area between the source region 31 and the drain region 32 of the semiconductor substrate 20 in the Z direction, with the gate insulating film 34 sandwiched therebetween. The gate electrode 36 is formed of, for example, a metal material. A contact electrode C3 that applies a voltage to the gate electrode 36 is provided above the gate electrode 36. The contact electrode C3 is connected to the gate electrode 36 in the Z direction.

In this embodiment, in the Y direction, the width W2 of the gate electrode 36 is smaller than the width W1 of the activation region A surrounded by the element isolation portion 22 by the gate insulating film 34 and the functional film 35.

In another expression, the gate electrode 36 has a first end P1 located on the first side in the Y direction. The active region A has a second end P2 located on the first side in the Y direction. When viewed from the Z direction, the position of the first end P1 is on the second side in the Y direction from the position of the second end P2. Furthermore, the gate electrode 36 has a third end P3 located on the second side in the Y direction. The active region A has a fourth end P4 located on the second side in the Y direction. When viewed from the Z direction, the position of the third end P3 is on the first side in the Y direction from the position of the fourth end P4.

The space on the semiconductor substrate 20 described above other than the transistor 30 and the contact electrodes C1, C2, and C3 is filled with, for example, an interlayer insulating film 15.

<3. Method for manufacturing semiconductor device>
Next, a method for manufacturing the semiconductor device 1 will be described. Here, a manufacturing method for the transistor 30 will be described. As for the manufacturing steps of the other components of the semiconductor device 1, known methods can be used.

3 to 12 are diagrams for explaining a manufacturing method of the semiconductor device 1 of the first embodiment.
First, as shown in Fig. 3, a sacrificial film 101 is formed on the semiconductor substrate 20, extending in the X-direction and the Y-direction along the surface 20a of the semiconductor substrate 20. The sacrificial film 101 has, for example, a first sacrificial film 102 and a second sacrificial film 103. The first sacrificial film 102 is formed on the surface 21a of the substrate body 21. The first sacrificial film 102 is formed of, for example, polysilicon. After the formation of the first sacrificial film 102, a second sacrificial film 103d is formed as a cap on the first sacrificial film 102. The second sacrificial film is formed of, for example, silicon nitride.

Next, as shown in FIG. 4, the semiconductor substrate 20 and a portion of the sacrificial film 101 are removed by etching (e.g., reactive ion etching (RIE)). This forms a first space S1 surrounding the sacrificial film 101. After that, an NSG (nondoped silicate glass) film is formed on the semiconductor substrate 20 by, for example, chemical vapor deposition. Then, the NSG film on the region A1 surrounded by the element isolation portion 22 is removed by, for example, chemical mechanical polishing (CMP). This forms the element isolation portion 22 in the first space S1.

Next, as shown in FIG. 5, a resist film 104 is formed. The resist film 104 is provided in the middle of the region A1 in the X direction. The resist film 104 extends in the Y direction and bridges the element isolation portions 22 on both sides of the region A1 in the Y direction.

Next, as shown in FIG. 6, the sacrificial film 101 on region A1 is etched to remove the sacrificial film 101 except where the resist film 104 is formed. This leaves the sacrificial film 101 below the resist film 104. Hereinafter, the sacrificial film 101 remaining below the resist film 104 may be referred to as a dummy gate 105, and the sacrificial film 102 constituting the dummy gate 105 may be referred to as a dummy poly.

7, the element isolation portion 22 is removed in the Z direction toward the boundary 106 between the semiconductor substrate 20 and the sacrificial film 101 by, for example, RIE. Here, the removal range of the element isolation portion 22 includes a case where the removal range is slightly shifted in the Z direction from the boundary 106 between the semiconductor substrate 20 and the sacrificial film 101. In this process, it is preferable to remove the element isolation portion 22 so that the boundary 106 between the semiconductor substrate 20 and the sacrificial film 101 and the surface 22a of the element isolation portion 22 are flush with each other. After removing the element isolation portion 22 toward the boundary 106 between the semiconductor substrate 20 and the sacrificial film 101, halo ion implantation is performed near the dummy gate 105.

Next, as shown in FIG. 8, a first insulating film 23 extending from the element isolation portion 22 in the Z direction is formed around the remaining sacrificial film 101 (dummy gate 105). That is, the first insulating film 23 is formed along the side surface 101a of the sacrificial film 101 (dummy gate 105) facing the Y direction. In this embodiment, the first insulating film 23 is formed not only on the side surface 101a of the sacrificial film 101 facing the Y direction, but also on the side surface of the sacrificial film 101 facing the X direction. After the first insulating film 23 is formed, ion implantation is performed on the extension portion. In this embodiment, impurities are doped into the region A1 in this process to form the activation region A. The timing of forming the activation region A can be changed as appropriate.

Next, as shown in FIG. 9, an NSG layer is deposited on the element isolation portion 22 to form an insulating film 107. After that, the insulating film 107 on the sacrificial film 101 (dummy gate 105) is removed by, for example, CMP.

Next, as shown in FIG. 10, the sacrificial film 101 (dummy gate 105) is removed from above the semiconductor substrate 20 by, for example, etching, to form a second space S2 inside the first insulating film 23.

Next, as shown in FIG. 11, a gate insulating film 34, a functional film 35, and a gate electrode 36 are formed, for example, by chemical vapor deposition, in a region on the semiconductor substrate 20 including the second space S2. In this process, for example, the gate insulating film 34 is formed on the semiconductor substrate 20, and then the functional film 35 is formed on the gate insulating film 34. The gate insulating film 34 and the functional film 35 are formed as thin films with a uniform thickness. After that, the gate electrode 36 is formed on the functional film 35.

Next, as shown in FIG. 12, for example, CMP is performed to remove unnecessary insulating films 50, 51 and metal layer 52 (see FIG. 11) on the insulating film 107. As a result, the gate insulating film 34, functional film 35, and gate electrode 36 remain in the second space S2, and the gate 33 is formed.

Then, contact electrodes C1, C2, and C3 are formed on the source region 31, drain region 32, and gate electrode 36, respectively. Then, the insulating film 107 is replaced or grown to form the interlayer insulating film 15. After that, the upper structures such as the array chip 2 and the circuit chip 3 are formed, and the semiconductor device 1 having the transistor 30 shown in FIG. 2 is manufactured.

<4 Advantages>
In conventional CMOS transistors fabricated after the so-called STI, the end of the gate is formed to protrude toward the isolation region when viewed from the thickness direction, taking into consideration the alignment of the gate with the active region. However, this conventional method results in a larger dimension due to the gate protrusion. Furthermore, the halo ion implantation is hindered in the region where the isolation region overlaps with the gate in the thickness direction, which also causes shadowing of the halo implantation.

Therefore, in this embodiment, in the Y direction, the width W2 of the gate electrode 36 is smaller than the width W1 of the activation region A surrounded by the element isolation portion 22. As a result, when viewed from the Z direction, the gate 33 is formed in the same range in the Y direction as the activation region A surrounded by the element isolation portion 22, and the gate 33 does not protrude toward the element isolation portion 22 and overlap with the element isolation portion 22 in the Z direction. This reduces the dimension at least in the Y direction. This prevents the semiconductor device 1 from becoming larger, improving manufacturability. Furthermore, in the manufacturing process of the semiconductor device 1, the sacrificial film 101 (dummy gate 105) formed in the region of the gate 33 does not hinder the halo ion implantation. This prevents the shadowing of the halo implantation, improving the electrical characteristics.

In addition, in this embodiment, the second portion 34b of the gate insulating film 34 is provided between the gate electrode 36 and the first insulating film 23 in the Y direction. This ensures that the gate insulating film 34 is formed over the entire Y direction of the activation region A, further suppressing leakage current.

In addition, in the manufacturing method of the semiconductor device 1 according to this embodiment, the element isolation portion 22 is removed in the Z direction toward the boundary 106 between the semiconductor substrate 20 and the sacrificial film 101. Next, a first insulating film 23 is formed extending from the element isolation portion 22 in the Z direction along the side surfaces 101a in the X and Y directions of the sacrificial film 101. Then, the sacrificial film 101 is removed from above the semiconductor substrate 20 to form the second space S2. After that, a gate insulating film 34 is formed in the second space S2. After the gate insulating film 34 is formed, a functional film 35 is formed in the second space S2. After the functional film 35 is formed, a gate electrode 36 is formed in the second space S2.

Through this manufacturing procedure, the gate insulating film 34, the functional film 35, and the gate electrode 36 are formed along the first insulating film 23. As a result, when viewed from the Z direction, the gate 33 and the activation region A are formed in the same range in the Y direction, so that it is possible to suppress the protrusion of the gate 33 in a simple manner. This prevents the semiconductor device 1 from becoming larger, improving manufacturability, and also suppresses shadowing of the halo implant during the manufacturing process, improving electrical characteristics.

Second Embodiment
Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the gate 33 has a gate wiring 37 protruding in the Y direction from the gate electrode 36. Note that the configuration other than that described below is the same as that of the first embodiment.

Figure 13 is a diagram showing an example of the configuration of a semiconductor device 1 relating to one transistor 30. As shown in Figure 13, the gate 33 has a gate wiring 37 in addition to a gate insulating film 34, a functional film 35, and a gate electrode 36. In the Z direction, a third space S3 is provided at the end of the second space S2 in which the gate electrode 36 is arranged, opposite the semiconductor substrate 20, and extending from the second space S2 to the first side in the Y direction.

In this embodiment, the gate insulating film 34 and the functional film 35 are formed from the second space S2 to the third space S3. Therefore, the second portion 34b of the gate insulating film 34 on the first side in the Y direction and the second portion 35b of the functional film 35 are formed in a stepped shape. That is, the second portion 34b of the gate insulating film 34 on the first side in the Y direction further has a first portion 34b1 extending in the Z direction along the first insulating film 23, a second portion 34b2 extending from the end of the first portion 34b1 opposite the semiconductor substrate 20 in the Z direction to the first side in the Y direction, and a third portion 34b3 extending in the Z direction from the end of the second portion 34b2 opposite the gate electrode 36 in the Y direction. In addition, the second portion 35b of the functional film 35 on the first side in the Y direction further includes a first portion 35b1 extending in the Z direction along the first portion 34b1 of the gate insulating film 34, a second portion 35b2 extending in the Y direction along the second portion 34b2 of the gate insulating film 34, and a third portion 35b3 extending in the Z direction along the third portion 34b3 of the gate insulating film 34.

In addition, in this embodiment, the portion of the gate electrode 36 that overlaps with the activation region A in the Z direction is formed to have a width equal to or narrower than that of the contact electrode C3 in the X direction. This makes it relatively difficult to provide the contact electrode C3 on the activation region A. As a countermeasure to this, in this embodiment, the gate wiring 37 is provided.

The gate wiring 37 is formed so as to fill the third space S3 other than the gate insulating film 34 and the functional film 35. The gate wiring 37 extends from the side surface of the gate electrode 36 on the first side in the Y direction to one side in the Y direction. In this embodiment, the surface of the gate wiring 37 on the opposite side to the semiconductor substrate 20 in the Z direction is formed flush with the surface of the gate electrode 36. The position of the gate wiring 37 in the Z direction can be changed to any position as appropriate.

A contact electrode C3 that applies a voltage to the gate electrode 36 is connected to the gate wiring 37. The gate wiring 37 includes a first portion 37a and a second portion 37b. The first portion 37a is provided on a side surface on the first side in the Y direction from the gate electrode 36. The second portion 37b is located on the opposite side of the gate electrode 36 in the Y direction with respect to the first portion 37a, and is formed integrally with the first portion 37a. The width W4 in the X direction of the second portion 37b is larger than the width W3 in the X direction of the gate electrode 36. The contact electrode C3 is connected to the second portion 37b. One contact electrode C3 is provided for one gate wiring 37.

The gate wiring 37 described above is disposed away from the element isolation section 22 in the Z direction. The element isolation section 22, the first insulating film 23, the gate insulating film 34, the functional film 35, and the gate wiring 37 are arranged in this order in the Z direction. Therefore, in this embodiment, a part of the functional film 35 is disposed between the element isolation section 22 and the gate wiring 37 in the Z direction.

Next, a method for manufacturing the semiconductor device 1 according to the second embodiment will be described. The same steps as in the first embodiment are performed up until the insulating film 107 is formed around the dummy gate 105. Descriptions of steps similar to those in the first embodiment will be omitted as appropriate.

Figures 14 to 18 are diagrams for explaining the manufacturing method of the semiconductor device 1 of the second embodiment. After the dummy gate 105 is formed, as shown in Figure 14, a resist film 120 having a hole 120a penetrating in the Z direction is formed on the semiconductor substrate 20. The hole 120a is provided on the first side in the Y direction with respect to the remaining sacrificial film 101 (dummy gate 105). The other end of the hole 120a in the Y direction overlaps with the dummy gate 105 in the Z direction. The dimension of the hole 120a in the X direction is larger than the dimension of the dummy gate 105 in the X direction and the dimension of the contact electrode C3 in the X direction.

Next, etching is performed to remove half of the insulating film 107 in the Z direction. Then, as shown in FIG. 15, etching is performed only in the region that overlaps with the hole 120a in the Z direction. As a result, half of the height of the insulating film 107, first insulating film 23, and dummy gate 105 that overlap with the hole 120a in the Z direction is removed in the Z direction. In this way, a third space S3 is formed on the first side of the sacrificial film 101 in the Y direction.

Next, as shown in FIG. 16, the sacrificial film 101 (dummy gate 105) is removed from the semiconductor substrate 20 by, for example, etching to form a second space S2 inside the first insulating film 23. The formed second space S2 communicates with the third space S3.

Next, as shown in FIG. 17, a gate insulating film 34, a functional film 35, a gate electrode 36, and a gate wiring 37 are formed, for example, by chemical vapor deposition, in the region on the semiconductor substrate 20 including the second space S2 and the third space S3. In this process, the gate insulating film 34 is formed on the semiconductor substrate 20, and then the functional film 35 is formed on the gate insulating film 34. The gate insulating film 34 and the functional film 35 are formed as thin films with a uniform thickness. After that, the gate electrode 36 is formed on the functional film 35, and the gate wiring 37 is formed all at once.

Next, as shown in FIG. 18, for example, CMP is performed to remove unnecessary insulating films 50, 51 and metal layer 52 (see FIG. 17) on the insulating film 107. As a result, the gate insulating film 34, functional film 35, gate electrode 36, and gate wiring 37 remain in the second space S2 and the third space S3, and the gate 33 is formed.

Then, contact electrodes C1, C2, and C3 are formed on the source region 31, drain region 32, and gate wiring 37, respectively. Then, the insulating film 107 is replaced or grown to form the interlayer insulating film 15. After that, the upper structures such as the array chip 2 and the circuit chip 3 are formed, and the semiconductor device 1 having the transistor 30 shown in FIG. 13 is manufactured.

In this embodiment, the transistor 30 has a gate wiring 37. The gate wiring 37 is disposed away from the element isolation portion 22 in the Z direction. The gate wiring 37 includes a second portion 37b whose width W4 in the X direction is larger than the width W3 in the X direction of the gate electrode 36. A contact electrode C3 is connected to the second portion 37b. This allows the gate electrode 36 to be formed without having to consider securing an installation area for the contact electrode C3, further improving manufacturability.

In addition, in the method for manufacturing the semiconductor device 1 according to this embodiment, the gate wiring 37 is formed at the same time as the gate electrode 36 is formed. This makes it possible to shorten the manufacturing time of the semiconductor device 1, and further improves manufacturability.

In the second embodiment, the gate wiring 37 is formed only on the first side in the Y direction relative to the gate electrode 36, but this is not limited to the above. The gate wiring 37 may be provided on the second side in the Y direction relative to the gate electrode 36, or on both sides in the Y direction.

The above describes the embodiments. However, the embodiments are not limited to the above examples.

In the embodiment, the first diffusion layer region is the source region 31 and the second diffusion layer region is the drain region 32, but this is not limited to the above. The first diffusion layer region may be the drain region 32 and the second diffusion layer region may be the source region 31.

In the embodiment, the case where the gate insulating film 34 and the functional film 35 are formed after the dummy poly sacrificial film 102 and the sacrificial film 103 are formed has been described, but this is not limited thereto. The gate insulating film 34 and the functional film 35 may be formed before the formation of the sacrificial film 102. In this case, as shown in FIG. 19, the entire gate insulating film 34 and the functional film 35 are provided so as to follow the surface 21a of the substrate body 21. In this case, for example, the gate electrode 36 and the first insulating film 23 are in contact with each other in the Y direction, and in the Y direction, the width W2 of the gate electrode 36 is the same as the width W1 of the activation region A. That is, when viewed from the Z direction, the position of the first end P1 of the gate electrode 36 coincides with the position of the second end P2 of the activation region A, and the position of the third end P3 of the gate electrode 36 coincides with the position of the fourth end P4 of the activation region A. In such a modified example, the formation region of the gate electrode 36 can be expanded in the Y direction. Therefore, the contact electrode C3 can be easily installed, and manufacturability can be improved.

According to at least one embodiment described above, the semiconductor device includes a substrate and a transistor. The substrate includes an activation region and an isolation portion. The isolation portion surrounds the activation region. The transistor has a first diffusion layer region and a second diffusion layer region, a gate insulating film, and a gate electrode. The first diffusion layer region and the second diffusion layer region are provided in the activation region. The gate insulating film is provided on the activation region. The gate electrode is located on the opposite side of the gate insulating film to the substrate. In a second direction that intersects with a first direction in which the first diffusion layer region and the second diffusion layer region are aligned and runs along the surface of the substrate, the width of the gate electrode is the same as or smaller than the width of the activation region. With this configuration, it is possible to improve electrical characteristics.

Although an embodiment of the present invention has been described, the embodiment is presented as an example and is not intended to limit the scope of the invention. The embodiment can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. The embodiment and its modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention.

1...semiconductor device, 20...semiconductor substrate (substrate), 20a...surface, 22...element isolation portion, 23...first insulating film, 25...boundary, 30...transistor, 31...source region (first diffusion layer region), 32...drain region (second diffusion layer region), 34...gate insulating film, 34b...second portion (part), 35...functional film, 35b...second portion (part), 36...gate electrode, 37...gate wiring, 37b...second portion (part), 101...sacrificial film, 101a...side, A...active region, C3...contact electrode, S1...first space, S2...second space

Claims (9)

a substrate including an active region and an isolation portion surrounding the active region;
a transistor having a first diffusion layer region and a second diffusion layer region provided in the activation region, a gate insulating film provided on the activation region, and a gate electrode located on the opposite side of the gate insulating film to the substrate;
Equipped with
a width of the gate electrode is equal to or smaller than a width of the active region in a second direction that intersects with a first direction in which the first diffusion layer region and the second diffusion layer region are aligned and that is along a surface of the substrate;
Semiconductor device. a first insulating film provided adjacent to a boundary between the active region and the element isolation portion in the second direction and extending from the element isolation portion in a third direction intersecting the first direction and the second direction;
The semiconductor device according to claim 1 . the gate electrode is in contact with the first insulating film in the second direction;
The semiconductor device according to claim 2 . a portion of the gate insulating film is provided between the gate electrode and the first insulating film in the second direction;
The semiconductor device according to claim 2 . the first insulating film includes a first material;
The transistor further includes a functional film including a second material having a higher dielectric constant than the first material;
a portion of the functional film is provided between the gate electrode and the first insulating film in the second direction;
The semiconductor device according to claim 2 . a contact electrode for applying a voltage to the gate electrode;
The transistor further includes a gate wiring,
the gate wiring is disposed apart from the element isolation portion in the third direction, includes a portion whose width in the first direction is larger than the width in the first direction of the gate electrode, and the contact electrode is connected to the portion.
The semiconductor device according to claim 2 . the first insulating film includes a first material;
The transistor further includes a functional film including a second material having a higher dielectric constant than the first material;
a portion of the functional film is disposed between the element isolation portion and the gate line in the third direction;
The semiconductor device according to claim 6. forming a sacrificial film extending in a first direction along a surface of a substrate and in a second direction along the surface of the substrate and intersecting the first direction;
removing a portion of the substrate and the sacrificial film by etching to form a first space surrounding the sacrificial film;
forming an element isolation portion in the first space;
removing the element isolation portion in a thickness direction of the substrate toward a boundary between the substrate and the sacrificial film;
forming a first insulating film extending in the thickness direction from the element isolation portion along a side surface of the sacrificial film facing the second direction;
removing the sacrificial film to form a second space;
forming a gate electrode in the second space;
A method for manufacturing a semiconductor device. forming a gate wiring extending from the gate electrode in the second direction and connected to a contact electrode at the same time;
The method for manufacturing a semiconductor device according to claim 8 .

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