JP2024086983A - Gaming Machines - Google Patents

Abstract

An object of the present invention is to enable a notification corresponding to the state of an opening/closing body that is provided so as to be able to be opened and closed to be suitably executed.
[Solution] When the supply of operating power is started, the main MPU 72 executes a setting change process based on the fact that a setting change operation is being performed. In the setting change process, after executing a process of clearing the storage area of the main RAM 74, the setting value to be selected is changed based on the operation of pressing the reset button. In this case, when the setting change process ends, reset state information is set in a door status area 74e provided in the main RAM 74. Then, when the front door is in an open state in a situation where the reset state information is set in the door status area 74e, a door open notification is executed, and when the front door is in a closed state in a situation where the reset state information is set in the door status area 74e, a door closed notification is executed.
[Selection diagram] Figure 9

Description

The present invention relates to gaming machines.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward a gaming area in response to a player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet on and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is given to the player (see, for example, Patent Document 1).

JP 2014-045989 A

Here, in gaming machines such as those exemplified above, the lottery process needs to be executed appropriately, and there is still room for improvement in this regard.

The present invention was made in consideration of the circumstances exemplified above, and aims to provide a gaming machine that allows the lottery process to be executed in an optimal manner.

In order to solve the above problem, the present invention provides a sequential change means for sequentially changing a selection object to be selected from among a plurality of selection objects;
a numerical information acquiring means for acquiring numerical information for selection corresponding to the selection object that is the object of the lottery;
a winning determination means for determining whether or not the selected object to be selected by the lottery is a winning object by utilizing the lottery numerical information acquired by the numerical information acquisition means;
Equipped with
The determination of whether or not a win has been made by the winning determination means is performed in each of a plurality of game states,
In a predetermined game status among the plurality of game statuses, the selection target of a predetermined type does not become the winning target,
The predetermined type of selection object is selected as the selection object by the sequential change means even in the predetermined game state,
a correspondence information group is set corresponding to each of the plurality of types of selection objects,
the numerical information acquiring means acquires the numerical information for selection by comparing information corresponding to a current game status with the corresponding information group corresponding to the selection object to be selected;
The corresponding information group includes information for identifying the selected object that has become a winner in subsequent processing when the selected object corresponding to the corresponding information group is determined to be a winner by the winner determination means.

According to the present invention, it is possible to ensure that the lottery process is carried out optimally.

1 is a front view of a slot machine according to a first embodiment. 1 is an oblique view of the slot machine with the front door open. FIG. FIG. 2 is a diagram showing the arrangement of symbols on each reel. 10 is an explanatory diagram showing the relationship between the patterns visible through the display window and the combination lines. FIG. FIG. 13 is an explanatory diagram showing the relationship between winning modes and benefits provided. 1A is a front view of a common display area, and FIG. 1B is an explanatory diagram for explaining the contents of information corresponding to a stop order displayed on the common display section. 13A and 13B are diagrams illustrating the relationship between the notification content of the stop order on the image display device and the display content of the stop order on the combined display unit. FIG. 2 is an electrical configuration diagram of the slot machine. 4 is a flowchart showing a main process executed by a main MPU; FIG. 2 is an explanatory diagram for explaining a signal path of a power outage signal. 11A to 11E are time charts showing how, when the main processing is started, the progress of the processing is suspended until the power failure signal becomes a HI level. 13 is a flowchart showing a power outage process executed by the main MPU. 13A to 13D are time charts showing how an information anomaly is identified in the main RAM by using an information anomaly flag. 13 is a flowchart showing a setting change process executed by a main MPU. FIG. 2 is an explanatory diagram for explaining the contents of a storage area of a main RAM. 13A to 13H are time charts showing how the main RAM clearing process is executed during the setting change process. 13 is a flowchart showing a setting change execution process executed by a main MPU. 13 is a flowchart showing a timer interrupt process executed by a main MPU. FIG. 1A is a flowchart showing a sensor monitoring process executed by the main MPU, and FIG. 1B is an explanatory diagram for explaining the contents of a memory area provided in the main RAM. 13A to 13K are time charts showing how, when the supply of operating power is started while the reset button is pressed, the setting value that is to be selected is not changed by maintaining the pressing of the reset button. 10 is a flowchart showing a door open sensor monitoring process executed by the main MPU. 13 is a flowchart showing a notification process executed by a main MPU. 13A to 13I are time charts showing how various notifications are issued when the supply of operating power is started and a setting change process is executed. 13 is a flowchart showing normal processing executed by a main MPU. 13 is a flowchart showing a start waiting process executed by a main MPU. 13 is a flowchart showing a bet corresponding process executed by the master MPU. 13 is a flowchart showing a control process of the bet display unit executed by the main MPU. FIG. 11 is an explanatory diagram for explaining the contents of an index value. 13 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning patterns that are achieved. FIG. (a) is an explanatory diagram for explaining the contents of the data in the main ROM for performing the lottery processing of roles, and (b) is an explanatory diagram for explaining the contents of the memory area of the main RAM for performing the lottery processing of roles. An explanatory diagram for explaining the contents of the role selection table group. FIG. 1A is an explanatory diagram for explaining a data group for IV=1; FIG. 1B is an explanatory diagram for explaining a data group for IV=16; and FIG. 1C is an explanatory diagram for explaining a data group for IV=17. 13 is a flowchart showing the role selection process executed by the main MPU. 13 is a flowchart showing a process for acquiring a judgment value executed by a main MPU. 13 is a flowchart showing a PV acquisition process executed by the main MPU. 13 is a flowchart showing the winning data acquisition process executed by the main MPU. 13 is a flowchart showing a reel control process executed by a main MPU. 13 is a flowchart showing the corresponding processing executed by the main MPU when a game ends. 1 is an explanatory diagram for explaining the game states and game zones existing in a slot machine. FIG. FIG. 2A is an explanatory diagram for explaining the first and second intervals, and FIG. 2B is an explanatory diagram for explaining the contents of each game state in the second interval. (a) is an explanatory diagram for explaining the first CB role and the second CB role, and (b) is an explanatory diagram for explaining the first CB state and the second CB state. 13 is a flowchart showing the first control processing of the game area executed by the main MPU. A flowchart showing the second control processing of the game area executed by the main MPU. 13 is a flowchart showing an ending handling process executed by a main MPU. 13 is a flowchart showing the advantageous lottery processing executed by the master MPU at the start of a game. 13 is a flowchart showing a normal process executed by a main MPU. FIG. 13A is an explanatory diagram for explaining the selection probability of the number of games mode, and FIG. 13B is an explanatory diagram for explaining the selection probability of the winning rate mode. (a) is an explanatory diagram to explain the latch area, (b) is an explanatory diagram to explain an example of a second random number stored in the latch area, (c) is an explanatory diagram to explain an example of an upper byte, and (d) is an explanatory diagram to explain an example of a 7-bit random number. 13 is a flowchart showing a second initial setting process executed by the main MPU. FIG. 13A is an explanatory diagram for explaining a game number mode lottery table, and FIG. 13B is an explanatory diagram for explaining a win rate mode lottery table. 13 is a flowchart showing an LV acquisition process executed by a main MPU. 13 is a flowchart showing the freeze setting process at the time of bonus transition executed by the main MPU. 6A to 6E are time charts showing how a freeze period is set. 13 is a flowchart showing the processing for advantageous states at the start of a game executed by the main MPU. 13 is a flowchart showing a pseudo bonus process executed by the main MPU. 13 is a flowchart showing the clearing process at the end of a bonus executed by the main MPU. (a) to (e) are time charts showing the timing of execution of various processes when the pseudo bonus state ends. 13 is a flowchart showing the AT state processing executed by the main MPU at the start of a game. 11 is a flowchart showing an AT process executed by a main MPU. 13 is a flowchart showing an external output setting process executed by a main MPU. 13 is a flowchart showing an external output process executed by a main MPU. 5A to 5H are time charts showing how the output modes of the first external signal and the second external signal are appropriately changed. FIG. 11 is an explanatory diagram for explaining the electrical configuration of a main MPU in a second embodiment. 13A and 13B are diagrams for explaining the state of a jump status flag when a predetermined storage area is cleared to "0" by a CLR execution circuit. 13A and 13B are diagrams illustrating the state of a jump status flag when a value in a specific storage area is decremented by 1 by a DEC execution circuit. FIG. 2A is an explanatory diagram for explaining the data structure of a JR instruction, and FIG. 2B is an explanatory diagram for explaining the data structure of a JRS instruction. FIG. 11 is an explanatory diagram for explaining an example of the contents of a program in which both a JR instruction and a JRS instruction are executed as a JP instruction. 13A to 13C are explanatory diagrams for explaining a stack area provided in a main RAM in a third embodiment. 13 is a flowchart showing the advantageous lottery processing executed by the master MPU at the start of a game. 13 is a flowchart showing the processing for advantageous states at the start of a game executed by the main MPU. 13 is a flowchart showing the AT state processing executed by the main MPU at the start of a game. 13 is a flowchart showing an ending determination process executed by a main MPU. 13 is a flowchart showing an ending determination process of a comparative example. 13 is a flowchart showing advantageous state processing at the start of a game in a comparative example. 13 is a flowchart showing a wait period calculation process executed by a main MPU in the fourth embodiment; 13A to 13C are diagrams for explaining the contents of the subtraction process of the wait counter. 13 is a flowchart showing a medal monitoring process executed by the main MPU. 13A to 13C are explanatory diagrams for explaining the contents of the increment process of the monitoring period counter, and FIG. 13D is an explanatory diagram for explaining the contents of a comparative example in which the increment process of the monitoring period counter is performed without executing the "SBC" command. 13 is a flowchart showing a wait period calculation process executed by a main MPU in the fifth embodiment; 13A and 13B are diagrams illustrating the contents of the addition process of a wait counter. 13 is a flowchart showing a medal monitoring process executed by the main MPU. 13A and 13B are explanatory diagrams for explaining the contents of the decrement process of the monitoring period counter, and FIG. 13C is an explanatory diagram for explaining the contents of a comparative example in which the decrement process of the monitoring period counter is performed without executing an “ADC” command. 23 is a flowchart showing a main process executed by a main MPU in the sixth embodiment; 23 is a flowchart showing a main process executed by a main MPU in the seventh embodiment.

First Embodiment
A first embodiment of the present invention applied to a slot machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a front view of the slot machine 10, Fig. 2 is a perspective view of the slot machine 10 with the front door 12 open, and Fig. 3 is a front view of the cabinet 11.

As shown in Figures 2 and 3, the slot machine 10 has a housing 11 that forms its outer shell. The housing 11 is formed into a box shape that is open at the front as a whole by fixing multiple wooden panels.

A front door 12 is attached to the front side of the housing 11 as shown in Figs. 1 and 2. The front door 12 is supported by the housing 11 around an axis 15 provided on the left side of the housing 11 as a pivot axis so that the internal space of the housing 11 can be opened and closed. The front door 12 is locked so that it cannot be opened by a locking device 13 provided on the back side of the front door, and this locked state is released by unlocking the key cylinder 14 with a specified key.

A door open sensor 16 is provided on the top of the housing 11. The door open sensor 16 is for detecting whether the front door 12 is open relative to the housing 11. The door open sensor 16 is electrically connected to the main control device 70 described below, and when the front door 12 is closed relative to the housing 11, a signal corresponding to the closed state is sent from the door open sensor 16 to the main control device 70, and when the front door 12 is open relative to the housing 11, a signal corresponding to the open state is sent from the door open sensor 16 to the main control device 70.

As shown in FIG. 1, a game panel 20 is provided near the upper center of the front door 12. The game panel 20 has three vertically long display windows 21L, 21M, and 21R arranged side by side. The display windows 21L, 21M, and 21R are made of a transparent or translucent material, and the interior of the slot machine 10 can be seen through each of the display windows 21L, 21M, and 21R.

2 and 3, the inside of the housing 11 is divided into two parts, an upper part and a lower part, by a partition plate 11a, and a reel unit 31 is attached to the upper part of the partition plate 11a. The reel unit 31 includes a left reel 32L, a center reel 32M, and a right reel 32R, each of which is formed in a cylindrical shape. Each of the reels 32L, 32M, and 32R is supported so that it can rotate with its central axis being the axis of rotation of the reel 32L, 32M, and 32R. The axes of rotation of the reels 32L, 32M, and 32R are arranged on the same axis extending in a substantially horizontal direction, and each of the reels 32L, 32M, and 32R corresponds one-to-one to each of the display windows 21L, 21M, and 21R. Therefore, a part of the surface of each of the reels 32L, 32M, and 32R is visible through the corresponding display window 21L, 21M, and 21R. Furthermore, when reels 32L, 32M, and 32R rotate forward, the surfaces of reels 32L, 32M, and 32R are displayed through display windows 21L, 21M, and 21R as if they are moving from top to bottom.

As shown in FIG. 1, a start lever 41 is provided on the lower left side of the game panel 20, which is operated to start the rotation of each of the reels 32L, 32M, and 32R. When the start lever 41 is operated when a predetermined number or more of game media (or game value), which are either medals or virtual medals, have been bet, each of the reels 32L, 32M, and 32R starts to rotate simultaneously.

On the right side of the start lever 41, there are stop buttons 42, 43, 44 that are operated to individually stop each of the spinning reels 32L, 32M, 32R. Each stop button 42, 43, 44 is located directly below the display window 21L, 21M, 21R that corresponds to the reel 32L, 32M, 32R to be stopped. Each stop button 42, 43, 44 becomes capable of stopping the left reel 32L when a predetermined time has elapsed since the reel started spinning.

One game (play) is the period from when the start lever 41 is operated to when the reels 32L, 32M, and 32R start to rotate, when the stop buttons 42, 43, and 44 are operated to when the reels 32L, 32M, and 32R stop to when the various processes, such as the awarding of game media and management of the game status, are completed.

A medal insertion port 45 for inserting medals is provided on the lower right side of the display window parts 21L, 21M, and 21R. The medals inserted from the medal insertion port 45 are guided to a hopper device 53 by a selector 52 provided on the back side of the front door 12 when reception is permitted, and are guided to a medal receiving tray 59 from a medal discharge port 58 provided on the lower front side of the front door 12 when reception is prohibited (see FIG. 1). The hopper device 53 has a function of discharging medals stored in a storage tank to the medal receiving tray 59 through the medal discharge port 58 when a winning event corresponding to the award of game media is established on the main line ML described later. Below the medal insertion port 45, a return button 46 is provided, which is pressed when a medal inserted into the medal insertion port 45 gets stuck in the selector 52, as shown in FIG. 1.

On the lower left side of the display windows 21L, 21M, and 21R, there are provided a first credit insertion button 47 for inserting the maximum number of credited virtual medals that can be bet at one time, and a second credit insertion button 48 for inserting two virtual medals at one time. In this slot machine 10, there are two situations in which the number of gaming media (medals or virtual medals) that can be bet (i.e., bet setting) at one time is "3" and "2".

When the first credit insertion button 47 is operated in a situation where the number of bets that can be made at one time is "3", the current number of bets is "0", and three or more virtual medals are stored and stored, the number of bets is reduced by three virtual medals and becomes "3". When the first credit insertion button 47 is operated in a situation where the number of bets that can be made at one time is "3", the current number of bets is "1", and two or more virtual medals are stored and stored, the number of bets is reduced by two virtual medals and becomes "3". When the first credit insertion button 47 is operated in a situation where the number of bets that can be made at one time is "3", the current number of bets is "2", and one or more virtual medals are stored and stored, the number of bets is reduced by one virtual medal and becomes "3". When the first credit insertion button 47 is operated in a situation where the number of bets that can be made at one time is "2", the current number of bets is "0", and two or more virtual medals are stored and stored, the number of bets is reduced by two virtual medals and becomes "2". When the number of bets that can be made at one time is "2", the current number of bets is "1", and one or more virtual medals are stored and stored, if the first credit insertion button 47 is operated, one virtual medal will be deducted and the number of bets will become "2".

If the first credit insertion button 47 is operated when the number of stored virtual medals is less than the difference between the available number of bets and the current number of bets, the number of bets increases by the number of virtual medals, and the number of virtual medals becomes 0.

In a situation where the number of bets that can be made at one time is "3", the current number of bets is "0", and two or more virtual medals are stored and stored, when the second credit insertion button 48 is operated, the number of bets decreases by two virtual medals and becomes "2". In a situation where the number of bets that can be made at one time is "3", the current number of bets is "1", and one or more virtual medals are stored and stored, when the second credit insertion button 48 is operated, the number of bets decreases by one virtual medal and becomes "2". In a situation where the number of bets that can be made at one time is "2", the current number of bets is "0", and two or more virtual medals are stored and stored, when the second credit insertion button 48 is operated, the number of bets decreases by two virtual medals and becomes "2". In a situation where the number of bets that can be made at one time is "2", the current number of bets is "1", and one or more virtual medals are stored and stored, when the second credit insertion button 48 is operated, the number of bets decreases by one virtual medal and becomes "2".

If the second credit insertion button 48 is operated when the number of stored virtual medals is one and the current number of bets is "0," the number of bets becomes "1" and the number of virtual medals becomes zero.

The first credit insertion button 47 has a larger pressing surface that is pressed when the player operates the button than the second credit insertion button 48. This improves the operability of the first credit insertion button 47.

A settlement button 51 is provided to the left of the start lever 41. This slot machine 10 has a credit function that stores and memorizes, as virtual medals, any surplus medals inserted up to a predetermined maximum value (equivalent to 50 medals) and any medals paid out when a prize is won. When the settlement button 51 is operated while virtual medals are stored and memorized, the virtual medals are paid out from the medal outlet 58 as real medals.

As shown in Figures 2 and 3, inside the cabinet 11, a power supply unit 54 is provided to the left of the hopper unit 53. The power supply unit 54 is provided with a power switch 55 that is operated when the power is turned on or off, a reset button 56 for resetting various states of the slot machine 10, and a setting key insertion hole 57 into which a setting key held by the amusement hall manager is inserted and operated to change the setting value of the slot machine 10 within the range of "1" to "6."

Next, we will explain the symbols on each reel 32L, 32M, and 32R.

Figure 4 shows the arrangement of symbols on the left reel 32L, center reel 32M, and right reel 32R. As shown in the figure, 21 symbols are arranged in a row on each of the reels 32L, 32M, and 32R. Numbers from "0" to "20" are also assigned to each of the reels 32L, 32M, and 32R, but these numbers are numbers that the main control device 70, which will be described later, uses to identify the symbols that are visible through the display windows 21L, 21M, and 21R, and are not actually assigned to the reels 32L, 32M, and 32R. However, these numbers will be used in the following explanation.

There are seven types of symbols: "Bell" symbol (e.g., 20th on left reel 32L), "Replay" symbol (e.g., 19th on left reel 32L), "Watermelon" symbol (e.g., 18th on left reel 32L), "Red 7" symbol (e.g., 15th on left reel 32L), "BAR" symbol (e.g., 10th on left reel 32L), "Cherry" symbol (e.g., 9th on left reel 32L), and "White 7" symbol (e.g., 5th on left reel 32L). The number and arrangement order of the various symbols are different on each reel 32L, 32M, and 32R.

Figure 5 is a front view of the display window sections 21L, 21M, and 21R. Each display window section 21L, 21M, and 21R is formed so that of the 21 symbols on the corresponding reel 32L, 32M, and 32R, only three symbols are visible in their entirety. Therefore, when each reel 32L, 32M, and 32R is all stopped, 3 x 3 = 9 symbols are visible through the display window section 21L, 21M, and 21R.

In this slot machine 10, one main line ML is set to connect the positions where the symbols on each of the reels 32L, 32M, and 32R are visible. The main line ML is a line that connects the middle symbols on the left reel 32L, the middle symbols on the middle reel 32M, and the middle symbols on the right reel 32R. When a predetermined number or more of gaming media have been bet, the rotation of each of the reels 32L, 32M, and 32R begins, and if a winning combination corresponding to a winning combination is established on the main line ML, either a benefit in the form of gaming media, a benefit in the form of a replay, or a transition to a gaming state is awarded.

In other words, in this slot machine 10, only one main line ML is set as a line that can result in a win. The main line ML is set as a line that extends in a straight line. Therefore, even if a combination of symbols that can result in a win is formed on a line that extends in a straight line, such as the subline SL1 connecting the upper pattern of the left reel 32L, the middle pattern of the middle reel 32M, and the lower pattern of the right reel 32R, the subline SL2 connecting the upper pattern of the left reel 32L, the upper pattern of the middle reel 32M, and the upper pattern of the right reel 32R, the subline SL3 connecting the lower pattern of the left reel 32L, the lower pattern of the middle reel 32M, and the lower pattern of the right reel 32R, and the subline SL4 connecting the lower pattern of the left reel 32L, the middle pattern of the middle reel 32M, and the upper pattern of the right reel 32R, no win is formed.

Below, we will explain the relationship between winning symbol combinations and the benefits that will be awarded if a prize is won, with reference to Figure 6. Figure 6 is an explanatory diagram for explaining the relationship between winning symbol combinations and the benefits that will be awarded if a prize is won.

The minor prizes that result in the awarding of gaming media include the first compensation prize, the second compensation prize, the third compensation prize, the fourth compensation prize, the fifth compensation prize, the sixth compensation prize, the seventh compensation prize, the eighth compensation prize, the ninth compensation prize, the first bell prize, the second bell prize, the first watermelon prize, the second watermelon prize, and the cherry prize. In detail, when the stopping pattern on the left reel 32L on the main line ML is a "bell" pattern, the stopping pattern on the middle reel 32M is a "bell" pattern, and the stopping pattern on the right reel 32R is a "red 7" pattern, it is the first compensation prize. If the stopping pattern on the left reel 32L is a "bell" pattern, the stopping pattern on the middle reel 32M is a "red 7" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern on the main line ML, a second supplementary win will be made. If the stopping pattern on the left reel 32L is a "red 7" pattern, the stopping pattern on the middle reel 32M is a "bell" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern on the main line ML, a fourth supplementary win will be made. If the stopping pattern on the left reel 32L is a "bell" pattern, the stopping pattern on the middle reel 32M is a "BAR" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern on the main line ML, a fifth supplementary win will be made. If the stopping pattern on the left reel 32L is a "BAR" pattern, the stopping pattern on the middle reel 32M is a "bell" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern on the main line ML, a sixth supplementary win will be made. If the stopping pattern on the left reel 32L is a "bell" pattern, the stopping pattern on the middle reel 32M is a "bell" pattern, and the stopping pattern on the right reel 32R is a "white 7" pattern on the main line ML, a seventh supplementary win will be made. If the stopped pattern on the left reel 32L on the main line ML is a "bell" pattern, the stopped pattern on the middle reel 32M is a "white 7" pattern, and the stopped pattern on the right reel 32R is a "bell" pattern, then an 8th supplementary win is awarded. If the stopped pattern on the left reel 32L on the main line ML is a "white 7" pattern, the stopped pattern on the middle reel 32M is a "bell" pattern, and the stopped pattern on the right reel 32R is a "bell" pattern, then a 9th supplementary win is awarded. If any of the 1st to 9th supplementary wins are awarded, the number of game media to be awarded will be "1".

When the stopped pattern on the left reel 32L on the main line ML is a "bell" pattern, the stopped pattern on the middle reel 32M is a "bell" pattern, and the stopped pattern on the right reel 32R is a "bell" pattern, the first bell win is achieved. When the stopped pattern on the left reel 32L on the main line ML is a "bell" pattern, the stopped pattern on the middle reel 32M is a "bell" pattern, and the stopped pattern on the right reel 32R is a "replay" pattern, the second bell win is achieved. When either the first bell win or the second bell win is achieved, the number of gaming media to be awarded becomes "15".

If the stopping pattern on the left reel 32L on the main line ML is a "watermelon" pattern, the stopping pattern on the middle reel 32M is a "watermelon" pattern, and the stopping pattern on the right reel 32R is a "watermelon" pattern, the first watermelon win is obtained. If the stopping pattern on the left reel 32L on the main line ML is a "watermelon" pattern, the stopping pattern on the middle reel 32M is a "watermelon" pattern, and the stopping pattern on the right reel 32R is a "BAR" pattern, the second watermelon win is obtained. If either the first watermelon win or the second watermelon win is obtained, the number of game media to be awarded is "5". If the stopping pattern on the left reel 32L on the main line ML is a "cherry" pattern, a cherry win is obtained regardless of the stopping pattern on the middle reel 32M or the right reel 32R. If a cherry wins, the number of gaming media awarded will be "2".

Winnings that grant a replay privilege, which allows the player to play the next game without betting gaming media, include the normal replay winning, the first chance replay winning, and the second chance replay winning. In detail, if the stopping pattern on the left reel 32L on the main line ML is a "replay" pattern, the stopping pattern on the middle reel 32M is a "replay" pattern, and the stopping pattern on the right reel 32R is a "replay" pattern, if the stopping pattern on the left reel 32L on the main line ML is a "red 7" pattern, the stopping pattern on the middle reel 32M is a "red 7" pattern, and the stopping pattern on the right reel 32R is a "BAR" pattern, then If the stopping pattern is a "red 7" and the stopping pattern on the right reel 32R is a "replay", if the stopping pattern on the left reel 32L on the main line ML is a "replay", the stopping pattern on the middle reel 32M is a "red 7" and the stopping pattern on the right reel 32R is a "BAR", or if the stopping pattern on the left reel 32L on the main line ML is a "watermelon", the stopping pattern on the middle reel 32M is a "red 7" and the stopping pattern on the right reel 32R is a "bell", a normal replay is won. If the stopping pattern on the left reel 32L on the main line ML is a "replay", the stopping pattern on the middle reel 32M is a "cherry", and the stopping pattern on the right reel 32R is a "bell", a first chance replay is won. If the stopped symbol on the left reel 32L along the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, a second chance replay win will occur.

If any of the above replay wins are won, a replay bonus will be awarded, which allows you to play the next game without having to bet on a gaming medium. Specifically, if any of the replay wins are won in a game where you have bet on gaming medium "3", you will be able to start playing the next game with gaming medium "3" betted, without having to bet on a gaming medium. Also, if any of the replay wins are won in a game where you have bet on gaming medium "2", you will be able to start playing the next game with gaming medium "2" betted, without having to bet on a gaming medium.

State transition winnings that only result in a transition of the game state include the first CB winning and the second CB winning. In detail, if the stopped pattern on the left reel 32L on the main line ML is a "red 7" pattern, the stopped pattern on the center reel 32M is a "red 7" pattern, and the stopped pattern on the right reel 32R is a "white 7" pattern, then the first CB winning occurs. If the stopped pattern on the left reel 32L on the main line ML is a "white 7" pattern, the stopped pattern on the center reel 32M is a "white 7" pattern, and the stopped pattern on the right reel 32R is a "red 7" pattern, then the second CB winning occurs. When the first CB winning occurs, the game state transitions to the first CB state ST2, and when the second CB winning occurs, the game state transitions to the second CB state ST3 (see FIG. 40).

The first CB state ST2 and the second CB state ST3 are game states in which, when a combination of symbols corresponding to a minor winning combination stops on the main line ML, a winning combination is established and medals are paid out regardless of whether or not a winning combination is achieved. For example, even if the winning data corresponding to the first bell winning combination has not been set, gaming media will be awarded to the player when the combination of symbols corresponding to the first bell winning combination stops on the main line ML. On the other hand, a replay winning combination is established on the condition that the corresponding combination has been won in a lottery.

In the first CB state ST2 and the second CB state ST3, reel control different from that in the non-CB state is performed. In the non-CB state, reel control that allows the reels 32L, 32M, and 32R to slide up to four symbols after the stop buttons 42 to 44 are operated is performed for each reel 32L, 32M, and 32R. In other words, in the non-CB state, reel control that stops the reels 32L, 32M, and 32R within a specified time (190 milliseconds) after the stop buttons 42 to 44 are operated is performed for each reel 32L, 32M, and 32R. On the other hand, in the first CB state ST2 and the second CB state ST3, the above reel control is performed for the center reel 32M and the right reel 32R, that is, the same reel control as in the normal game, but the above reel control is not performed for the left reel 32L. For the left reel 32L, reel control that allows the reel to slide up to one symbol after the left stop button 42 is operated is performed. In other words, in the first CB state ST2 and the second CB state ST3, reel control is performed on the left reel 32L to stop it within a specified time (75 msec) that is shorter than the specified time after the left stop button 42 is operated.

In the first CB state ST2 and the second CB state ST3, the reel control that only slides a maximum of one symbol is not limited to the left reel 32L, but may be performed on the reel corresponding to the first operated stop button only to slide a maximum of one symbol, or may be performed on a predetermined reel only to slide a maximum of one symbol. Furthermore, reel control that only slides a maximum of one symbol on the reel corresponding to the stop button operated in a certain order may be performed, such as reel control that only slides a maximum of one symbol on the reel corresponding to the second or last operated stop button.

In the first CB state ST2 and the second CB state ST3, if a combination corresponding to a replay win is won, the replay win takes priority, and if a replay win is not possible, the first bell win may occur. Also, the first bell win may occur even if a combination corresponding to a replay win is not won.

The first CB state ST2 and the second CB state ST3 are both game states that do not increase the number of game media owned by the player. Furthermore, the first CB state ST2 and the second CB state ST3 are both game states that reduce the number of game media owned by the player at the end of the game state compared to the number of game media owned by the player at the start of the game state. Details of the first CB state ST2 and the second CB state ST3 will be explained later.

Next, we will explain the devices used to make various announcements and perform various effects.

As shown in FIG. 1, an upper lamp 61 and a speaker 62 are provided on the upper part of the front door 12, and an image display device 63 is also provided. When an abnormality occurs in the slot machine 10, the upper lamp 61 is controlled to emit light in a manner corresponding to the abnormality, and is also controlled to emit light in a manner corresponding to the winning result. Furthermore, the upper lamp 61 is controlled to emit light so that a light-emitting effect corresponding to the display effect on the image display device 63 is performed. The speakers 62 are provided as a pair on the left and right, and are controlled to output sound or audio corresponding to the abnormality when an abnormality occurs in the slot machine 10, and are also controlled to output sound or audio corresponding to the winning result. Furthermore, the speakers 62 are controlled to output sound so that a sound output effect corresponding to the display effect on the image display device 63 is performed.

The image display device 63 has a display surface and is configured as a liquid crystal display device equipped with a liquid crystal display, but is not limited to a liquid crystal display device and may be another display device having a display surface such as a plasma display device, an organic EL display device or a CRT, or may be a dot matrix display device. When an abnormality occurs in the slot machine 10, the display is controlled so that an image corresponding to the abnormality is displayed on the display surface. The image display device 63 is also controlled so that an image corresponding to the winning combination in the internal lottery and the winning result in each game is displayed on the display surface. In other words, a display performance is executed on the image display device 63.

The gaming panel 20 of the front door 12 is provided below the display windows 21L, 21M, and 21R with a bet display section 64 that displays the number of gaming media currently bet, a credit display section 65 that displays the number of virtual medals stored, a dual-purpose display section 66 that displays the number of gaming media to be awarded when a small winning combination is won and also displays a display corresponding to the content notified when the stopping order of the reels 32L, 32M, and 32R is notified on the image display device 63, and further displays the results of the management of the gaming history, and a section display section 67 that displays a display corresponding to the fact that the gaming section is the second section.

The bet display unit 64 has three light-emitting units arranged vertically, and each light-emitting unit is a single-color LED such as red. When the number of game media currently betted is "1", the bottom light-emitting unit is lit and the remaining light-emitting units are turned off. When the number of game media currently betted is "2", the bottom and center light-emitting units are lit and the top light-emitting unit is turned off. When the number of game media currently betted is "3", all three light-emitting units are lit. After all reels 32L, 32M, and 32R have stopped spinning in one game, all light-emitting units of the bet display unit 64 are turned off regardless of whether any replay wins have been achieved in that game. In this case, if it is the final game of the pseudo bonus state ST4 described later, when the process to end the pseudo bonus state ST4 is executed, all of the light-emitting parts of the bet display unit 64 are turned off, and if it is a game other than the final game, all of the light-emitting parts of the bet display unit 64 are turned off when all the processes for one game are completed. Also, if a replay win is not established, the light-emitting parts remain turned off until a new bet on the game medium is made, and if any replay win is established, the light-emitting parts are turned on after being turned off for a predetermined period (e.g., 2 seconds). The credit display unit 65 is composed of a 7-segment display, and each segment uses a single-color LED such as green.

Figure 7(a) is a front view of a common display area 68 in which a combined display unit 66 and a section display unit 67 are provided. In the common display area 68, as shown in Figure 7(a), a combined display unit 66 in which two seven-segment displays 66a, 66b are arranged side by side in the horizontal direction, and a section display unit 67 consisting of one light-emitting element are integrated.

When any of the small prize winnings (first to ninth compensation winnings, first bell winning, second bell winning, first watermelon winning, second watermelon winning, or cherry winning) corresponding to the award of game media is achieved, the number of game media awarded corresponding to the small prize winning is displayed on the dual-purpose display unit 66 at the end of the game in which the small prize winning is achieved. Specifically, when any of the first to ninth compensation winnings is achieved in a non-CB state, the left 7-segment display 66a is not displayed and the right 7-segment display 66b displays "1", thereby notifying that "1" game media has been awarded. When any of the first bell winning and the second bell winning are achieved in a non-CB state, the left 7-segment display 66a displays "1" and the right 7-segment display 66b displays "5", thereby notifying that "15" game media have been awarded. In addition, when either the first watermelon winning or the second watermelon winning occurs in the non-CB state, the left 7-segment display 66a becomes non-displayable and the right 7-segment display 66b displays "5", thereby notifying that "5" gaming media have been awarded. In addition, when a cherry winning occurs in the non-CB state, the left 7-segment display 66a becomes non-displayable and the right 7-segment display 66b displays "2", thereby notifying that "2" gaming media have been awarded.

In the first CB state ST2 and the second CB state ST3, the number of game media awarded in response to a small win is "1", as described in detail below. Therefore, when a small win is achieved in the first CB state ST2 or the second CB state ST3, the left 7-segment display 66a is hidden and the right 7-segment display 66b displays "1", thereby indicating that "1" game media has been awarded.

On the other hand, even if a winning event that does not award gaming media, such as any of the replay winning events or any of the CB winning events, occurs, no display corresponding to that winning event is made on the dual-purpose display unit 66, and in this case the seven-segment displays 66a, 66b remain in a hidden state. The display of the number of awarded gaming media on the dual-purpose display unit 66 ends when gaming media is bet on to start the game following the game for which the display was made, and at the time this bet is made the seven-segment displays 66a, 66b go into a hidden state.

When the image display device 63 notifies the stop order of the reels 32L, 32M, and 32R, information corresponding to the notified stop order is displayed on the combined display unit 66. FIG. 7(b) is an explanatory diagram for explaining the contents of the information corresponding to the stop order displayed on the combined display unit 66. As shown in FIG. 7(b), in this slot machine 10, the stop order of the reels 32L, 32M, and 32R notified on the image display device 63 includes a stop order in which the first stop is the left reel 32L, the second stop is the center reel 32M, and the third stop is the right reel 32R, a stop order in which the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the center reel 32M, a stop order in which the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, and a stop order in which the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R. There are stopping sequences where the second stop is on the right reel 32R and the third stop is on the left reel 32L, where the first stop is on the right reel 32R, the second stop is on the left reel 32L and the third stop is on the center reel 32M, where the first stop is on the right reel 32R, the second stop is on the center reel 32M and the third stop is on the left reel 32L, where the first stop is on the left reel 32L and the rest is optional, where the first stop is on the center reel 32M and the rest is optional, and where the first stop is on the right reel 32R and the rest is optional.

The notification of the stop order on the image display device 63 may be executed when a role that includes the first bell winning data and any one of the first to sixth compensation winning data is won in the lottery process of the role in the non-CB state, or when a role that includes the second bell winning data and any one of the seventh to ninth compensation winning data is won. Specifically, when a role that includes the first bell winning data and any one of the first to sixth compensation winning data is won, the first bell winning is established if the reels 32L, 32M, and 32R are stopped in the stopping order corresponding to the current winning role among the above stopping orders, and any one of the first to sixth compensation winnings may be established if the reels 32L, 32M, and 32R are not stopped in the stopping order corresponding to the current winning role. When the first bell winning is established, the game medium "15" is awarded to the player as already explained, and when any one of the first to sixth compensation winnings is established, the game medium "1" is awarded to the player as already explained.

When a player wins a combination that includes the second bell winning data and any one of the seventh to ninth compensation winning data, the second bell win occurs if reels 32L, 32M, and 32R stop in the stopping order that corresponds to the current winning combination, and any one of the seventh to ninth compensation wins may occur if reels 32L, 32M, and 32R do not stop in the stopping order that corresponds to the current winning combination. If the second bell win occurs, the player is awarded "15" gaming media as already explained, and if any of the seventh to ninth compensation wins occurs, the player is awarded "1" gaming media as already explained.

When any of the above stop orders is notified by the image display device 63, the left 7-segment display 66a of the combined display unit 66 remains in a non-display state, while the right 7-segment display 66b displays the stop order of the order to be notified. The display contents are as shown in FIG. 7(b), and the display contents of the stop order of the combined display unit 66 are set in a one-to-one correspondence with the notification contents of the stop order of the image display device 63. However, this is not limited to this, and a configuration may be adopted in which multiple types of display contents of the combined display unit 66 are set in correspondence with some or all of the notification contents of the stop order of the image display device 63.

The display content of the stop order on the dual-purpose display unit 66 is different from the display content that is displayed when the dual-purpose display unit 66 displays a display corresponding to the awarding of game media. This makes it easier to distinguish whether the content displayed on the dual-purpose display unit 66 corresponds to the number of game media awarded or the stop order of the reels 32L, 32M, and 32R.

Figures 8(a) and 8(b) are explanatory diagrams for explaining the relationship between the notification content of the stop order on the image display device 63 and the display content of the stop order on the combined display unit 66.

When the stopping order of reels 32L, 32M, and 32R is announced on the image display device 63, as shown in Fig. 8(a), the image display device 63 displays the same number of unit display images G1 to G3 as the number of stopping operations required to end the game, and each unit display image G1 to G3 displays an image corresponding to the stopping order of reels 32L, 32M, and 32R. Specifically, a left unit display image G1 corresponding to the left reel 32L, a middle unit display image G2 corresponding to the middle reel 32M, and a right unit display image G3 corresponding to the right reel 32R are displayed. FIG. 8(a) shows the stop order being notified when the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, so the left unit display image G1 displays an image of "2" corresponding to the stop order of the left reel 32L, the middle unit display image G2 displays an image of "1" corresponding to the stop order of the middle reel 32M, and the right unit display image G3 displays an image of "3" corresponding to the stop order of the right reel 32R.

In the image display device 63, an image is displayed that notifies the stop order of the reels 32L, 32M, and 32R as described above, whereas in the combined display unit 66, as shown in FIG. 8(b), an "L" corresponding to the stop order of the reels 32L, 32M, and 32R is displayed. In other words, in the image display device 63, unit display images G1 to G3 corresponding to the number of reels 32L, 32M, and 32R are displayed, and an image corresponding to the stop order of the corresponding reels 32L, 32M, and 32R is displayed in each unit display image G1 to G3, whereas in the combined display unit 66, a display unrelated to the number of reels 32L, 32M, and 32R is displayed. As a result, even if the combined display unit 66 displays a display corresponding to the notification of the stop order of the reels 32L, 32M, and 32R, it is possible to draw the player's attention to the display content on the image display device 63.

The display range of the combined display unit 66 is narrower than that of the image display unit 63. This also makes it possible to reduce the player's attention to the combined display unit 66 compared to the image display unit 63. The combined display unit 66 is also located on the opposite side to the image display unit 63, across the display windows 21L, 21M, and 21R that allow the reels 32L, 32M, and 32R to be viewed. This means that the combined display unit 66 is positioned away from the image display unit 63, which also makes it possible to reduce the player's attention to the combined display unit 66.

When the stop order of reels 32L, 32M, and 32R is notified, the display corresponding to the stop order of reels 32L, 32M, and 32R on the combined display unit 66 and the display corresponding to the stop order of reels 32L, 32M, and 32R on the image display unit 63 are started after the lottery process for the winning combination is performed and before the stop operation of reels 32L, 32M, and 32R is enabled. In this case, the display corresponding to the stop order of reels 32L, 32M, and 32R on the combined display unit 66 is started before the display corresponding to the stop order of reels 32L, 32M, and 32R on the image display unit 63, but these displays may be configured to start simultaneously or approximately simultaneously, or the display start order may be reversed. In addition, the display corresponding to the stop order of reels 32L, 32M, and 32R on the combined display unit 66 and image display device 63 ends when a stop command is issued for all reels 32L, 32M, and 32R in the game for which the display is executed.

The dual-purpose display unit 66 is disposed in the center of the common display area 68, whereas the section display unit 67 is disposed in a corner of the common display area 68. The section display unit 67 is a display unit for notifying that the game section is the second section SC2 of the first section SC1 and the second section SC2. The second section SC2 is a section in which an advantageous game state (specifically, a pseudo bonus state ST4 and an AT state ST5) can be started in which the expected value of game media in one game (the value obtained by subtracting the "number of game media bet in one game" from the "expected number of game media to be awarded in one game") can be 1 or more when the winning combination that is the target of winning is different depending on the stopping order of the reels 32L, 32M, and 32R is won, and the advantageous game state can be continued. On the other hand, the first section SC1 is a section in which the advantageous game state does not start and does not continue.

The section display unit 67 is turned on when the player is in a favorable gaming state in which the expected value of the gaming medium is 1 or more by being notified of the stopping order of the reels 32L, 32M, and 32R, which allows the player to win a winning combination that is favorable to the player when the player wins a winning combination that is favorable to the player depending on the stopping order of the reels 32L, 32M, and 32R, or when the player wins a winning combination that is favorable to the player depending on the stopping order of the reels 32L, 32M, and 32R. In this case, the pseudo bonus state ST4 and the AT state ST5 correspond to the above-mentioned favorable gaming state, while the second section SC2, which is neither the pseudo bonus state ST4 nor the AT state ST5, does not correspond to the above-mentioned favorable gaming state. Therefore, when moving from the first section SC1 to the second section SC2, the section display unit 67 may or may not switch from the off state to the on state. If the section display unit 67 remains off when moving to the second section SC2, the section display unit 67 will change from an off state to an on state when the pseudo bonus state ST4 or AT state ST5 starts in the second section SC2. If the section display unit 67 becomes on, it will remain on until the second section SC2 ends, and will become off when the second section SC2 ends and the first section SC1 moves on.

As described above, in a configuration in which the section display unit 67 is turned on once in the second section SC2 and the turned on state is maintained until the end of the second section SC2, the dual-purpose display unit 66, which is provided in a concentrated manner in the common display area 68, is turned on when a game medium is awarded and turned off when the next game starts, and is turned on when the stopping order of the reels 32L, 32M, and 32R is displayed on the image display device 63 and turned off when the game ends. Therefore, in a configuration in which the section display unit 67 is arranged in the common display area 68 so as not to be too noticeable to the player, it is possible to actively create a situation in which only the section display unit 67 is turned on in the common display area 68 during the second section SC2, making it easier for the manager of the game parlor to check the section display unit 67.

In addition, instead of maintaining the section display unit 67 in the lit state during the second section SC2, the section display unit 67 may be configured to flash at a predetermined cycle during the second section SC2. Also, other displays such as liquid crystal display devices may be used as the combined display unit 66 and the section display unit 67.

The slot machine 10 is provided with various control devices. Specifically, as shown in FIG. 3, a main control device 70 is provided above the reel unit 31. The main control device 70 is attached to the back plate 11b that forms the back surface of the housing 11. The main control device 70 is configured by housing a main control board 71 in a board box 81. An MPU 72 is mounted on one of the board surfaces of the main control board 71, which is the element mounting surface. The board box 81 is formed transparent so that the MPU 72 housed in the board box 81 can be seen from the outside of the board box 81. Note that the board box 81 is formed colorless and transparent, but it may be formed colored and transparent as long as the MPU 72 housed in the board box 81 can be seen from the outside of the board box 81. The main control device 70 is mounted on the back plate 11b of the housing 11 so that the opposing wall portion 82 facing the element mounting surface of the main control board 71 in the board box 81 faces the front of the slot machine 10. Therefore, by opening the front door 12 toward the front of the slot machine 10 relative to the cabinet 11 and exposing the internal space of the cabinet 11, it becomes possible to visually observe the opposing wall portion 82 of the board box 81 and the MPU 72 through the opposing wall portion 82.

The board box 81 is formed by combining a number of case bodies in front and behind, and these case bodies are provided with joints 83 that prevent the separation of these case bodies and leave a trace when the case bodies are separated. The joints 83 are arranged in a row on one side of the board box 81, which is approximately a rectangular parallelepiped. As a result, even if some of the joints 83 are used to prevent the separation of the case bodies and the case bodies are separated by destroying the part of the joints 83, it is possible to prevent the separation of the case bodies again by connecting another joint 83 thereafter. In addition, since the joints 83 are destroyed when the case bodies are separated and a trace is left, it is possible to visually check the joints 83 to see whether the separation of the case bodies is being performed illegally. In addition, a seal seal 84 is attached to one side of the board box 81 other than the side on which the joints 83 are arranged in a row so as to straddle the boundary between the case bodies. When the seal seal 84 is peeled off, an adhesive layer remains on the case body. This makes it possible to leave a trace if the seal 84 is peeled off when the case body is separated.

As shown in FIG. 2, the slot machine 10 is provided with a performance control device 90 in addition to the main control device 70. The performance control device 90 is arranged behind the image display device 63 and stacked on the front door 12. The performance control device 90 controls the upper lamp 61, speaker 62, and image display device 63 based on commands received from the main control device 70. Note that the performance control device 90 is configured with a control board housed in a board box, similar to the main control device 70.

Next, the electrical configuration of the slot machine 10 will be explained based on the block diagram in FIG. 9.

As already explained, the main control board 71 of the main control device 70 is equipped with an MPU 72. The MPU 72 is provided with a ROM 73 that stores various control programs and fixed value data executed by the MPU 72, a RAM 74 that is a memory for temporarily storing various data when executing the control programs stored in the ROM 73, a first random number circuit 75 that sequentially updates a first random number within a predetermined numerical range based on a clock signal output from a clock circuit, a second random number circuit 76 that sequentially updates a second random number within a predetermined numerical range based on a clock signal output from the clock circuit, and a clock circuit that outputs a rectangular wave of a predetermined frequency. In addition to the above, the MPU 72 also includes an interrupt circuit, a data input/output circuit, and the like. It is not essential that the ROM 73 and RAM 74 are integrated into a single chip for the MPU 72, and each may be integrated into a separate chip.

The MPU 72 is provided with an input port and an output port. On the input side of the MPU 72, various sensors are connected, such as the door opening sensor 16, the reel unit 31, the start detection sensor 41a that detects the operation of the start lever 41, the stop detection sensors 42a, 43a, 44a that individually detect the operation of each stop button 42, 43, 44, the medal insertion detection sensor 45a that detects medals inserted from the medal insertion slot 45, the credit insertion detection sensors 47a, 48a that individually detect the operation of each credit insertion button 47, 48, the settlement detection sensor 51a that detects the operation of the settlement button 51, the payout detection sensor of the hopper device 53, the reset detection sensor that detects the operation of the reset button 56 provided on the power supply device 54, and the setting key detection sensor that detects the insertion of the setting key into the setting key insertion hole 57. The signals from each of these sensors are input to the MPU 72.

The output side of the MPU 72 is connected to the reel unit 31, the selector drive unit 52a provided on the selector 52, the payout motor of the hopper device 53, the bet display unit 64, the credit display unit 65 (not shown in FIG. 9), the combined display unit 66, the section display unit 67, the external output terminal board 78, the performance control device 90, and the like. In each game, the rotation drive control of each reel 32L, 32M, and 32R of the reel unit 31 is performed by the MPU 72. The selector 52 has a function of guiding a medal inserted from the medal insertion port 45 to the hopper device 53 after detecting it with the inserted medal detection sensor 45a when the medal is permitted to be accepted, and discharging it to the medal tray 59 without detecting it with the inserted medal detection sensor 45a when the medal is prohibited to be accepted. The selector drive unit 52a has a function of switching the state of the selector 52 between the acceptance permitted state and the acceptance prohibited state, and specifically, it operates the path switching piece provided on the selector 52 between the acceptance permitted position and the acceptance prohibited position. The MPU 72 switches the state of the selector 52 between an acceptance permission state and an acceptance prohibition state by switching between the output state and the stop state of the drive signal to the selector drive unit 52a.

When a small winning combination is achieved and a medal is paid out, the MPU 72 executes drive control of the hopper device 53. In addition, when a bet of game media is made, the MPU 72 controls the display of the bet display unit 64 so that the number of bets is notified. In addition, when virtual game media are stored, the MPU 72 controls the display of the credit display unit 65 so that the number of virtual game media stored is displayed. In addition, when game media is awarded, the MPU 72 controls the display of the dual-purpose display unit 66 so that the number of game media that are the subject of the award is displayed. In addition, when the second section SC2 is reached, the MPU 72 controls the display of the section display unit 67 so that an announcement is made that the second section SC2 is being recognized when an announcement start trigger occurs. In addition, the MPU 72 controls the display of the dual-purpose display unit 66 so that an announcement corresponding to the game management result is made. In addition, the external output terminal board 78 is installed on the internal space side of the housing 11, and the MPU 72 outputs a signal to the external output terminal board 78, thereby outputting a signal (specifically, a first external signal and a second external signal) to the management computer of the gaming hall through the external output terminal board 78.

The MPU 72 transmits commands to the performance control device 90 at each timing of each game, and when transmitting a command to the performance control device 90 to notify the image display device 63 of the stop order of the reels 32L, 32M, and 32R, the MPU 72 executes display control of the combined display unit 66 so that a display corresponding to the content to be notified is performed. In this case, the direct display control of the image display device 63 is performed by the performance control device 90, whereas the direct display control of the combined display unit 66 is performed by the MPU 72. In other words, the direct display control is performed by the performance control device 90 for the image display device 63, which is the subject of relatively complex display control, and the direct display control is performed by the MPU 72 for the combined display unit 66, which is the subject of relatively simple display control. This makes it possible to perform both a display that emphasizes increasing attention to the performance and a display that emphasizes reliability, while reducing the processing load of the MPU 72.

The power failure monitoring circuit 54b provided in the power supply device 54 is connected to the input side of the MPU 72 (see FIG. 11). The power supply device 54 is equipped with a power supply unit 54a and a power failure monitoring circuit 54b that supply drive power to each electronic device of the slot machine 10, including the main control device 70. The power failure monitoring circuit 54b monitors the voltage applied to the power supply unit 54a from an external power source, and when the voltage exceeds a reference voltage (e.g., 5V), the output level of the power failure signal to the MPU 72 is set to a HI level, and when the voltage becomes equal to or lower than the reference voltage, the output level of the power failure signal to the MPU 72 is set to a LOW level. The MPU 72 executes a power failure process by receiving a LOW level power failure signal, and enables the processing state before the power failure to be restored after the power is restored. In addition, the power supply device 54 is provided with a power failure power supply unit for supplying backup power to the RAM 74 as power failure power in a situation where the supply of operating power from the external power source is cut off. As a result, even if the supply of operating power from an external power source is cut off, data is stored and maintained in RAM 74 as long as the power supply unit during power outage is capable of supplying backup power (for example, for one or two days).

The performance control device 90 is equipped with a performance control board 91 for controlling the execution of various notifications and various performances. The performance control board 91 is equipped with an MPU 92. The MPU 92 has a built-in ROM 93 that stores various control programs and fixed value data executed by the MPU 92, and a RAM 94 that is a memory for temporarily storing various data when the control programs stored in the ROM 93 are executed. It also has built-in a clock circuit that outputs a rectangular wave of a predetermined frequency, an interrupt circuit, a data input/output circuit, a random number generating circuit, etc.

It is not essential that the ROM 93 and RAM 94 are integrated into a single chip for the MPU 92, and each may be integrated into a separate chip. In addition, while backup power is not supplied to the RAM 94 from the power-off power supply unit of the power supply device 54 when the supply of operating power from the external power source is cut off, backup power may be supplied to the RAM 94.

The MPU 92 is provided with an input port and an output port. As already explained, the MPU 72 of the main control device 70 is connected to the input side of the MPU 92, and various commands are received from the MPU 72. The upper lamp 61, the speaker 62, and the image display device 63 are connected to the output side of the MPU 92. Based on the commands received from the MPU 72 of the main control device 70, the MPU 92 controls the light emission of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63, thereby enabling various notifications and various performances to be performed.

Although not shown, the performance control board 91 is equipped with a video display processor (VDP), character ROM, video RAM, etc. in addition to the MPU 92. The VDP is a type of drawing circuit that directly operates an image processing device as a liquid crystal display driver built into the image display device 63. The VDP is involved in reading and writing data from the video RAM, and reads image data to be stored in the video RAM from the character ROM at a predetermined timing and displays it on the image display device 63. The character ROM serves as an image data library for storing character data such as patterns to be displayed on the image display device 63. This character ROM holds bitmap format image data of various display patterns, a color palette table to be referenced when determining the expression color of each dot of the bitmap image, etc. The video RAM is a memory for storing display data to be displayed on the image display device 63. When the MPU 92 determines the execution content of the performance based on a command received from the MPU 72 of the main control device 70, it outputs a drawing list to the VDP that indicates the content of the image corresponding to each update timing according to the determined execution content of the performance. The VDP reads image data from the character ROM according to the drawing list, and creates display data in the video RAM using the read image data. The VDP then outputs an image signal corresponding to the created display data to the image display device 63, causing the image display device 63 to display an image corresponding to the display data.

For ease of explanation, in the following explanation, the MPU 72, ROM 73, and RAM 74 of the main control device 70 are referred to as the main MPU 72, main ROM 73, and main RAM 74, respectively, and the MPU 92, ROM 93, and RAM 94 of the performance control device 90 are referred to as the performance MPU 92, performance ROM 93, and performance RAM 94, respectively.

<Various processes executed by the main MPU 72>
Next, a description will be given of the processing executed by the main MPU 72. First, a main processing executed by the main MPU 72 when the supply of operating power to the main MPU 72 is started will be described with reference to the flowchart of FIG.

First, the power failure signal is read (step S101). Here, the power failure signal will be described. FIG. 11 is an explanatory diagram for explaining the signal path of the power failure signal. As shown in FIG. 11, the power supply device 54 includes a power supply unit 54a that uses power supplied from an external power source to supply operating power to various electronic devices including the main control device 70, and a power failure monitoring circuit 54b that monitors the voltage applied from the external power source to the power supply unit 54a and sets the output level of the power failure signal to a LOW level when the voltage falls below a reference voltage. The power supply unit 54a and the main control device 70 are electrically connected by a power line ELN, and operating power is supplied from the power supply unit 54a to the main control device 70 through the power line ELN.

The power failure monitoring circuit 54b and the main MPU 72 are electrically connected by a signal line LN, and a power failure signal is transmitted from the power failure monitoring circuit 54b to the main MPU 72 through the signal line LN. The main MPU 72 is provided with an input port 72a, and information corresponding to the state of the power failure signal is stored in a predetermined bit (specifically, the most significant bit) of the input port 72a. In this case, when power is normally supplied from the external power source to the power supply unit 54a, a HI level power failure signal is transmitted from the power failure monitoring circuit 54b to the main MPU 72. Specifically, a 5V signal is transmitted as a HI level power failure signal, but the voltage of this power failure signal is arbitrary. When a HI level power failure signal is transmitted, the predetermined bit of the input port 72a stores information of "1", which is one of the binary information, as information corresponding to the power failure signal. When power is not normally supplied from the external power source to the power supply unit 54a, a LOW level power failure signal is transmitted from the power failure monitoring circuit 54b to the main MPU 72. Specifically, a LOW level power failure signal is a signal of less than 5V. When a LOW level power failure signal is being transmitted, the above-mentioned predetermined bit of the input port 72a stores the other binary information, "0", as information corresponding to the power failure signal. Note that the HIGH/LOW relationship of the power failure signal may be reversed, and a power failure signal may be transmitted when power is being normally supplied from the external power source to the power supply unit 54a, and the power failure signal may not be transmitted when power is not normally supplied from the external power source to the power supply unit 54a.

The main MPU 72 is basically configured to periodically determine whether a power outage has occurred by monitoring the above-mentioned specific bit of the input port 72a in the power outage processing (step S503) in the timer interrupt processing (Figure 19) described later. However, when the main processing is started, the execution of the timer interrupt processing (Figure 19) is prohibited, and the execution of the timer interrupt processing (Figure 19) is first permitted when the main processing is terminated. Therefore, when the supply of operating power begins, the above-mentioned specific bit of the input port 72a is monitored in step S101 to determine whether a power outage has occurred without waiting for the execution of the timer interrupt processing (Figure 19). Thereafter, it is determined whether the power outage signal received from the power outage monitoring circuit 54b is at HI level by determining whether "1" is stored in the above-mentioned specific bit of the input port 72a (step S102).

If the power failure signal is at a LOW level (step S102: NO), the process returns to step S101, where the information stored in the predetermined bit of the input port 72a is read again (step S101), and the process determines whether the information is "1" to determine whether the power failure signal received from the power failure monitoring circuit 54b is at a HIGH level (step S102). If the power failure signal is at a HIGH level (step S102: YES), the process proceeds to step S103 and subsequent steps.

The state in which the progress of processing is suspended until the power failure signal becomes HIGH when the main processing is started will be described with reference to the time chart of FIG. 12. FIG. 12(a) shows the period during which operating power is supplied to the main MPU 72, FIG. 12(b) shows the state of the power failure signal transmitted from the power failure monitoring circuit 54b, FIG. 12(c) shows the period during which the main processing is being executed by the main MPU 72, FIG. 12(d) shows the period during which the progress of the main processing is suspended, and FIG. 12(e) shows the period during which processing at the time of a power failure is executed after it is determined in the timer interrupt processing (FIG. 19) that the power failure signal is LOW.

At the timing of t1, as shown in FIG. 12(a), the supply of operating power from the power supply unit 54a to the main MPU 72 is started, and as shown in FIG. 12(c), the main processing (FIG. 10) is started in the main MPU 72. In this case, the power supply may not be stable immediately after the power supply to the power supply unit 54a is started, and the voltage level of the power failure signal may not be stable. In the case shown in the example of the time chart of FIG. 12, the voltage of the power failure signal becomes unstable at less than 5V from the timing of t1 to the timing of t2 as shown in FIG. 12(b). In contrast, in the main processing (FIG. 10), as already explained, the processing of steps S101 and S102 is executed, and the processing of steps S103 and after is waited until the power failure signal becomes HI level from the timing of t1 to the timing of t2 as shown in FIG. 12(d).

After that, at timing t2, the power failure signal stabilizes at HI level as shown in FIG. 12(b). Therefore, as shown in FIG. 12(d), the state in which the processing is pending (i.e., the state in which a negative judgment is made in step S102) is released, and processing proceeds to step S103 and onwards. This makes it possible to complete the main processing (FIG. 10) under circumstances in which the power failure signal is stable at HI level, and to start processing to proceed with the subsequent game.

After that, at timing t3, the main processing (FIG. 10) ends as shown in FIG. 12(c). In this case, execution of the timer interrupt processing (FIG. 19) changes from a prohibited state to a permitted state. By permitting execution of the timer interrupt processing (FIG. 19), the timer interrupt processing (FIG. 19) is periodically executed, and the timer interrupt processing (FIG. 19) determines whether or not a "1" is stored in the above-mentioned predetermined bit of the input port 72a, thereby determining whether or not the power failure signal is at a HI level.

After that, at timing t4, as shown in FIG. 12(a), the supply of operating power from the external power source to the power supply unit 54a is stopped, causing the power failure signal to go from HI to LOW as shown in FIG. 12(b). Then, the timer interrupt process (FIG. 19) identifies that the power failure signal has gone LOW, and the process to be performed when a power failure occurs is executed from timing t4 to timing t5 as shown in FIG. 12(e).

Figure 13 is a flowchart showing the power outage processing executed in step S503 of the timer interrupt processing (Figure 19).

In the power outage processing, first, it is determined whether or not the power outage signal is at a HIGH level by determining whether or not "1" is stored in the predetermined bit of the input port 72a (step S201). If the power outage signal is at a HIGH level (step S201: YES), the power outage processing ends without executing the processing at the time of a power outage shown in steps S202 to S205.

If the value of the above-mentioned predetermined bit of the input port 72a is "0", that is, if the power failure signal is at a LOW level (step S201: NO), the power failure flag in the main RAM 74 is set to "1" (step S202), a checksum is calculated using information stored in the checksum calculation target area among the many storage areas in the main RAM 74 (step S203), and the calculated checksum is stored in the storage area of the main RAM 74 that was not the target of the checksum calculation (step S204). Then, after clearing all the output ports of the main MPU 72 to "0" (step S205), an infinite loop is created. This infinite loop continues until the supply of operating power for power failure to the main MPU 72 is completely stopped. As a result, if the processing at the time of power failure is normally executed when the supply of operating power to the main MPU 72 is stopped, the power failure flag in the main RAM 74 is set to "1", and the checksum is stored in the main RAM 74.

As described above, when the supply of operating power to the main MPU 72 is started, the execution of the processes from step S103 onwards in the main process (Figure 10) is put on hold until the power failure signal is stable at HI level. This makes it possible to start the process for progressing the game when the HI level power failure signal is being stably output.

When the main processing (Figure 10) is started, the timer interrupt processing (Figure 19) is prohibited from being executed, so even if the power failure signal is not stable at a HIGH level, the power failure processing is not executed, and as a result, the processing at the time of a power failure is not executed. In this case, the main processing (Figure 10) repeatedly monitors the above-mentioned specified bit of the input port 72a until the power failure signal becomes a HIGH level. This makes it possible to monitor whether the power failure signal is at a HIGH level even in a situation where the timer interrupt processing (Figure 19) is prohibited from being executed.

Returning to the explanation of the main process (FIG. 10), if a positive determination is made in step S102, the internal function setting process is executed (step S103). In the internal function setting process, various initial settings are made for the registers and I/O devices within the main MPU 72.

Then, the information abnormality flag 74g (see FIG. 9) in the main RAM 74 is set to "1" (step S104). The information abnormality flag 74g is a flag that allows the main MPU 72 to determine whether an information abnormality has occurred in the main RAM 74 when the supply of operating power begins.

After that, in order to identify whether an information anomaly has occurred, it is first determined whether the power outage flag in the main RAM 74 is set to "1" (step S105). In addition, a checksum is calculated using information stored in a checksum calculation target area among many storage areas provided in the main RAM 74 (step S106), and it is determined whether the calculated checksum matches the checksum calculated in step S203 of the power outage processing (FIG. 13) at the time of the previous power outage supply stop and stored in the main RAM 74 (steps S107 and S108). In addition, it is determined whether the setting value data stored in the setting value storage area provided in the main RAM 74 is 6 or more (step S109). The setting value data of "0" corresponds to the setting value of "1", the setting value data of "1" corresponds to the setting value of "2", the setting value data of "2" corresponds to the setting value of "3", the setting value data of "3" corresponds to the setting value of "4", the setting value data of "4" corresponds to the setting value of "5", and the setting value data of "5" corresponds to the setting value of "6". Setting value data between "0" and "5" is normal, and anything above 6 is abnormal.

If the power outage flag is set to "1" (step S105: YES), the checksums match (step S108: YES), and the set value data is less than 6 (step S109: NO), this means that no information abnormality has occurred in the main RAM 74. In this case, the information abnormality flag 74g of the main RAM 74 is cleared to "0" (step S110). On the other hand, if the power outage flag is not set to "1" (step S105: NO), the checksums do not match (step S108: NO), or the set value data is 6 or more (step S109: YES), the information abnormality flag 74g is maintained set to "1".

If a negative judgment is made in step S105, if a negative judgment is made in step S108, if a positive judgment is made in step S109, or if the processing of step S110 is executed, it is determined whether or not a setting change operation is performed when the supply of operating power is started (step S111). Specifically, it is determined whether or not the setting key inserted into the setting key insertion hole 57 is turned ON. If a setting change operation is not performed (step S111: NO), it is determined whether or not the information abnormality flag 74g of the main RAM 74 is set to "1" (step S112).

If the information abnormality flag 74g is not set to "1" (step S112: NO), this means that the power outage processing at the time of the previous power outage was performed normally and no information abnormality has occurred in the main RAM 74. In this case, the value of the stack pointer saved in the main RAM 74 is written to the stack pointer of the main MPU 72, and the data saved in the main RAM 74 is restored to the register of the main MPU 72, thereby restoring the state of the register of the main MPU 72 to the state before the power was cut off (step S113). In addition, the power outage flag of the main RAM 74 is cleared to "0" (step S114). In addition, a power restoration command is sent to the production side MPU 92 to make it recognize that the power restoration processing has been performed (step S115).

Then, the timer interrupt process (FIG. 19) is permitted to run (step S116). At the timing when the supply of operating power to the main MPU 72 starts, the timer interrupt process (FIG. 19) is not permitted to run, but the execution of step S116 allows the timer interrupt process (FIG. 19) to run. This causes the timer interrupt process (FIG. 19) to be started periodically. Then, the address before the power was cut off is returned to (step S117).

If the information abnormality flag 74g is set to "1" (step S112: YES), an operation prohibition process is executed. In the operation prohibition process, all output ports of the main MPU 72 are cleared to "0" to turn off all actuators connected to those output ports (step S118), and an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S119). This then becomes an infinite loop. Even if the supply of operating power to the main MPU 72 is stopped, the operation prohibition process is executed again when the supply of operating power is started until the setting change process (Figure 15) described below is executed. When the setting change process (Figure 15) described below is executed, the execution of the operation prohibition process is avoided.

Figure 14 is a time chart showing how the information anomaly flag 74g is used to identify that an information anomaly has occurred in the main RAM 74. Figure 14(a) shows the period during which the main process (Figure 10) is being executed, Figure 14(b) shows the state of the information anomaly flag 74g, Figure 14(c) shows the period during which the process for detecting an anomaly (steps S105 to S109) is being executed, and Figure 14(d) shows the period during which the operation prohibition process (steps S118 and S119) is being executed.

First, we will explain the case where no information abnormality occurs in the main RAM 74.

When the supply of operating power to the main MPU 72 is started, the main processing (FIG. 10) is started in the main MPU 72 at timing t1, as shown in FIG. 14(a). Then, after the information abnormality flag 74g is set to "1" at timing t2, as shown in FIG. 14(b), the abnormality detection processing (steps S105 to S109) is executed from timing t3 to timing t4, as shown in FIG. 14(c). In this case, the abnormality detection processing (steps S105 to S109) does not identify that an information abnormality has occurred in the main RAM 74. Therefore, since the information abnormality flag 74g is cleared to "0" at timing t4, as shown in FIG. 14(b), the operation prohibition processing (steps S118 and S119) is not executed, as shown in FIG. 14(d). After that, at timing t5, as shown in FIG. 14(a), the main process (FIG. 10) ends, and the process for progressing the game (timer interrupt process (FIG. 19), normal process (FIG. 25)) starts.

Next, we will explain what happens when an information abnormality occurs in the main RAM 74.

When the supply of operating power to the main MPU 72 is started, the main processing (FIG. 10) is started in the main MPU 72 at timing t6, as shown in FIG. 14(a). Then, after the information abnormality flag 74g is set to "1" at timing t7, as shown in FIG. 14(b), the abnormality detection processing (steps S105 to S109) is executed from timing t8 to timing t9, as shown in FIG. 14(c). In this case, the abnormality detection processing (steps S105 to S109) identifies that an information abnormality has occurred in the main RAM 74. Therefore, by maintaining the state in which the information abnormality flag 74g is set to "1" as shown in FIG. 14(b), the operation prohibition processing (steps S118 and S119) is started at timing t9, as shown in FIG. 14(d).

As described above, after the information abnormality flag 74g, which is a flag for the main MPU 72 to determine whether an information abnormality has occurred in the main RAM 74, is set to "1", an abnormality detection process is executed to perform various determinations as to whether an information abnormality has occurred in the main RAM 74. If the abnormality detection process determines that an information abnormality has occurred in the main RAM 74, the information abnormality flag 74g is maintained in a state where it is set to "1", and if the abnormality detection process determines that no information abnormality has occurred in the main RAM 74, the information abnormality flag 74g is cleared to "0". If the information abnormality flag 74g is maintained in a state where it is set to "1", an operation prohibition process is executed, and if the value of the information abnormality flag 74g is "0", a process for progressing the game without executing the operation prohibition process is started. In this way, by first setting the information abnormality flag 74g to "1" and then clearing the information abnormality flag 74g to "0" if it is determined that no information abnormality has occurred in the main RAM 74, it is possible to execute the operation prohibition process even if various determinations as to whether or not an information abnormality has occurred in the main RAM 74 due to the occurrence of electrical noise, despite the fact that an information abnormality has actually occurred.

Returning to the explanation of the main process (Figure 10), if the setting key inserted into the setting key insertion hole 57 is turned ON when the supply of operating power begins, i.e., if a setting change operation is being performed (step S111: YES), the setting change process is executed (step S120), and then normal processing is executed (step S121).

Figure 15 is a flowchart showing the setting change process in step S120.

First, a start address setting process is executed (step S301). In the start address setting process, the address of the memory area of the main RAM 74 that is the start target of the clear process when the clear process is executed to clear and initialize the memory area of the main RAM 74 to "0" at the start of the setting change process is set. FIG. 16 is an explanatory diagram for explaining the contents of the memory areas of the main RAM 74. As shown in FIG. 16, an address is set in each memory area of the main RAM 74. The addresses are set as consecutive number information. Specifically, the address "0000" is set as the initial address, the address "0001" is set as the next sequential address, the address "0002" is set as the next sequential address, and the addresses are set so that they are consecutive numbers thereafter.

The second CB winning data area, which is an area for storing second CB winning data, is set as the memory area corresponding to the starting address "0000". When second CB winning data is selected in the role selection process (FIG. 34) described below, the second CB winning data is set in the second CB winning data area, and when a second CB win is achieved, the second CB winning data is cleared from the second CB winning data area.

The first CB winning data area, which is an area for storing the first CB winning data, is set as a memory area corresponding to the next sequential address "0001" relative to the starting address "0000". When the first CB winning data is selected in the role selection process (FIG. 34) described below, the first CB winning data is set in the first CB winning data area, and when a first CB win is achieved, the first CB winning data is cleared from the first CB winning data area.

A setting value storage area, which is an area for storing the setting value to be used, is set as the storage area corresponding to "0002", which is the next setting value after "0001". The setting value selected in the setting change process (Figure 15) is stored in the setting value storage area.

The number of continued games counter 74c is set as the memory area corresponding to "0003", the total number of winnings counter 74d is set as the memory area corresponding to "0004", the credit counter 74b is set as the memory area corresponding to "0005", and the door state area 74e is set as the memory area corresponding to "0006". Various memory areas are also set in the memory areas corresponding to "0007" to "k-3". These various memory areas include the second section flag, which will be described later. In addition, the number of bets history counter 74f is set as the memory area corresponding to "k-2", the number of awards history counter is set as the memory area corresponding to "k-1", the pseudo bonus state flag is set as the memory area corresponding to "k", the pseudo bonus continuation counter is set as the memory area corresponding to "k+1", the number of bets setting counter 74a is set as the memory area corresponding to "k+2", and the medium award counter is set as the memory area corresponding to "k+3". In addition, for example, the information abnormality flag 74g is set as the memory area of the address from "k+4" onwards. The information abnormality flag 74g has already been explained, and the counters 74a-74e and various areas 74f other than the information abnormality flag 74g will be explained later.

In the start address setting process in step S301, "0001" is set as the start address in the address to be cleared provided in the register of the main MPU 72. As will be described in detail later, the memory area of the main RAM 74 is cleared to "0" and initialized for the memory area of the address set in the address to be cleared, and then the address to be cleared is incremented by 1 so that the address to be cleared becomes the next address in the sequence, and the memory area corresponding to the address to be cleared after the increment is cleared to "0" and initialized. In this case, if "0001" is set as the start address in the address to be cleared, the memory areas corresponding to addresses after "0001" are subject to "0" clear and initialization, and the memory area corresponding to the address "0000" is not subject to "0" clear and initialization.

Then, by determining whether the information anomaly flag 74g of the main RAM 74 is set to "1", it is determined whether an information anomaly has occurred in the main RAM 74 (step S302). It is also determined whether the reset button 56 was pressed when the supply of operating power was started (step S303). If the determination is negative in both steps S302 and S303, a start address correction process is executed (step S304). In the start address correction process, the address to be cleared in the main MPU 72 is overwritten with "0000" as the corrected start address. If "0000" is set as the start address in the address to be cleared, all memory areas in the main RAM 74 are cleared to "0" and initialized.

In other words, if a setting change process is started in a situation where an information abnormality has occurred in the main RAM 74 and the information abnormality flag 74g is set to "1", the memory areas that are cleared to "0" and initialized when the setting change process is started are all of the memory areas in the main RAM 74. Also, even if a setting change process is started in a situation where no information abnormality has occurred in the main RAM 74 and the value of the information abnormality flag 74g is "0", if not only the setting key is turned ON but also the reset button 56 is pressed when the supply of operating power is started, the memory areas that are cleared to "0" and initialized when the setting change process is started are all of the memory areas in the main RAM 74.

If the determination is affirmative in step S302, if the determination is affirmative in step S303, or if the processing of step S304 is executed, the storage area of the main RAM 74 corresponding to the address set in the address to be cleared is cleared to "0" and initialization is executed (step S305). Then, the update processing of the address to be cleared is executed (step S306). In the update processing, the value of the address to be cleared is added by 1, and the address set in the address to be cleared is changed to the next address in the order of addresses in the main RAM 74. Then, it is determined whether the address after the update exceeds the end address, which is the last address in the order in the main RAM 74 (step S307). If the determination is negative in step S307, the storage area of the address after the update is cleared to "0" and initialization is executed (step S305), and the processing of steps S306 and S307 is executed again. If the determination is affirmative in step S307, it means that the clear processing of the main RAM 74 has ended. In this case, proceed to step S308.

Here, the manner in which the clearing process of the main RAM 74 is executed in the setting change process will be described with reference to the time chart of FIG. 17. FIG. 17(a) shows the period during which operating power is supplied to the main MPU 72, FIG. 17(b) shows the period during which the main process (FIG. 10) is executed in the main MPU 72, FIG. 17(c) shows the period during which the setting key inserted into the setting key insertion hole 57 is turned on as a setting change operation, FIG. 17(d) shows the period during which the reset button 56 is pressed, FIG. 17(e) shows the state of the information anomaly flag 74g, FIG. 17(f) shows the period during which the setting change process (FIG. 15) is executed in the main MPU 72, FIG. 17(g) shows the period during which the clearing process is executed for a part of the memory area of the main RAM 74, and FIG. 17(h) shows the period during which the clearing process is executed for the entire memory area of the main RAM 74.

First, we will explain the case where the supply of operating power is started without pressing the reset button 56 and the setting change process is executed in a situation where no information abnormality has occurred in the main RAM 74.

At time t1, as shown in FIG. 17(a), the supply of operating power to the main MPU 72 is started, and at time t1, as shown in FIG. 17(b), the main MPU 72 starts the main processing (FIG. 10). Also, as shown in FIG. 17(c), a setting change operation is performed when the supply of operating power is started. After that, at time t2, as shown in FIG. 17(e), the information abnormality flag 74g is set to "1", but the abnormality detection process (steps S105 to S109) in the main processing (FIG. 10) determines that no information abnormality has occurred in the main RAM 74, and the information abnormality flag 74g is cleared to "0" at time t3.

After that, at the timing of t4, the setting change process (FIG. 15) is started in the main MPU 72 as shown in FIG. 17(f). When the setting change process (FIG. 15) is started, the clear process of the main RAM 74 is executed. However, since no information abnormality has occurred in the main RAM 74 at the start of the current supply of operating power, the value of the information abnormality flag 74g is "0" as shown in FIG. 17(e), and the reset button 56 has not been pressed at the start of the current supply of operating power as shown in FIG. 17(d). Therefore, in the current clear process of the main RAM 74, a partial clear process is executed in which "0001" is set as the starting address as shown in FIG. 17(g). In this case, as already explained, the second CB winning data area, which is the memory area in which the initial address is set in the main RAM 74, is excluded from the targets of "0" clearing and initialization, and "0" clearing and initialization are executed sequentially for the memory areas other than the area, and the process ends at the timing of t5 as shown in FIG. 17(g). This makes it possible to maintain the information in the second CB winning data area in the state it was in before the last power supply was stopped, even when the setting change process (Figure 15) is executed.

Next, we will explain the case where the supply of operating power is started when the reset button 56 is pressed and no information abnormality has occurred in the main RAM 74, and the setting change process is executed.

At time t6, as shown in FIG. 17(a), the supply of operating power to the main MPU 72 is started, and at time t6, as shown in FIG. 17(b), the main MPU 72 starts the main processing (FIG. 10). Also, as shown in FIG. 17(c), a setting change operation is performed when the supply of operating power is started, and as shown in FIG. 17(d), the reset button 56 is pressed. Then, at time t7, as shown in FIG. 17(e), the information anomaly flag 74g is set to "1", but the anomaly detection process (steps S105 to S109) in the main processing (FIG. 10) determines that no information anomaly has occurred in the main RAM 74, and the information anomaly flag 74g is cleared to "0" at time t8.

After that, at the timing of t9, the setting change process (FIG. 15) is started in the main MPU 72 as shown in FIG. 17(f). When the setting change process (FIG. 15) is started, the clear process of the main RAM 74 is executed, but since no information abnormality has occurred in the main RAM 74 at the start of the current supply of operating power, the value of the information abnormality flag 74g is "0" as shown in FIG. 17(e). On the other hand, the reset button 56 is pressed at the start of the current supply of operating power as shown in FIG. 17(d), and the pressing operation continues at the timing of t9. Therefore, in the current clear process of the main RAM 74, as shown in FIG. 17(h), a full clear process is executed in which "0000" is set as the starting address. In this case, as already explained, the "0" clear and initialization are sequentially executed for all memory areas of the main RAM 74, including the second CB winning data area, which is the memory area in which the initial address is set in the main RAM 74, and the process ends at the timing of t10 as shown in FIG. 17(h). This makes it possible to initialize all storage areas of the main RAM 74 when the setting change process (Figure 15) is executed.

Next, we will explain the case where the supply of operating power is started when the reset button 56 has not been pressed and a setting change process is executed when an information abnormality has occurred in the main RAM 74.

At time t11, as shown in FIG. 17(a), the supply of operating power to the main MPU 72 is started, and at time t11, as shown in FIG. 17(b), the main MPU 72 starts the main processing (FIG. 10). Also, as shown in FIG. 17(c), a setting change operation is performed when the supply of operating power is started. After that, at time t12, as shown in FIG. 17(e), the information anomaly flag 74g is set to "1", and the information anomaly flag 74g is maintained in the "1" state as a result of the anomaly detection process (steps S105 to S109) in the main processing (FIG. 10) identifying that an information anomaly has occurred in the main RAM 74.

After that, at the timing of t13, the setting change process (FIG. 15) is started in the main MPU 72 as shown in FIG. 17(f). When the setting change process (FIG. 15) is started, the clear process of the main RAM 74 is executed, but since an information abnormality occurs in the main RAM 74 when the supply of operating power starts this time, the value of the information abnormality flag 74g is "1" as shown in FIG. 17(e). Therefore, in the clear process of the main RAM 74 this time, as shown in FIG. 17(h), a full clear process is executed in which "0000" is set as the starting address. In this case, as already explained, the "0" clear and initialization are executed sequentially for all memory areas of the main RAM 74, including the second CB winning data area, which is the memory area in which the initial address is set in the main RAM 74, and the process ends at the timing of t14 as shown in FIG. 17(h). As a result, when the setting change process (FIG. 15) is executed in a situation where an information abnormality has occurred in the main RAM 74, it is possible to initialize all storage areas of the main RAM 74 and then start the process to change the setting value.

Returning to the explanation of the setting change process (FIG. 15), if a positive judgment is made in step S307, a setting change start command is sent to the production side MPU 92 (step S308). When the production side MPU 92 receives the setting change start command, it controls the upper lamp 61, speaker 62, and image display device 63 so that an announcement is made indicating that the setting value is being changed. In this case, the image display device 63 may be configured to display an image that allows the amusement hall manager to recognize the operation content for changing the setting value.

Then, the setting change execution process is executed (step S309). Figure 18 is a flowchart showing the setting change execution process.

First, the timer interrupt process (FIG. 19) is permitted to run (step S401). When the supply of operating power to the main MPU 72 starts, the timer interrupt process (FIG. 19) is not permitted to run. However, when the setting change process (FIG. 15) is executed in the main process (FIG. 10), step S401 of the setting change execution process (FIG. 18) is executed, and the timer interrupt process (FIG. 19) is permitted to run. This causes the timer interrupt process (FIG. 19) to be started periodically.

Figure 19 is a flowchart showing the timer interrupt process. Note that the timer interrupt process is initiated, for example, every 1.49 milliseconds.

First, further interrupts of the timer interrupt process (FIG. 19) are prohibited (step S501). Then, a register save process is executed (step S502). In the register save process, the values of all registers in the main MPU 72 used in the normal process (FIG. 25) described below are saved to the main RAM 74. Then, a power outage process is executed (step S503). The contents of the power outage process have already been explained. Then, in order to spin each of the reels 32L, 32M, and 32R, a stepping motor control process is executed (step S504) to drive the stepping motors provided on each of the reels 32L, 32M, and 32R. Then, a sensor monitoring process is executed (step S505).

Figure 20 (a) is a flowchart showing the sensor monitoring process. First, a shift process of the detection state storage area is executed (step S601). Figure 20 (b) is an explanatory diagram for explaining the contents of the detection state storage area provided in the main RAM 74. As shown in Figure 20 (b), the main RAM 74 is provided with a reset current state storage area 74h and a previous reset storage area 74i as detection state storage areas. The reset current state storage area 74h stores information corresponding to the state of the reset button 56 grasped in the sensor monitoring process of the most recent processing (Figure 20 (a)). Specifically, when a HI level signal indicating that the reset button 56 is being pressed is received as a detection signal from the reset button 56 in the sensor monitoring process of the most recent processing (Figure 20 (a)), information of "1" is stored in the reset current state storage area 74h, and when a LOW level signal indicating that the reset button 56 is not being pressed is received, the reset current state storage area 74h is cleared to "0". Furthermore, the previous reset memory area 74i stores information corresponding to the state of the reset button 56 grasped in the sensor monitoring process of the previous processing cycle (FIG. 20(a)). Specifically, if a HI level signal indicating that the reset button 56 is being pressed is received as a detection signal from the reset button 56 in the sensor monitoring process of the previous processing cycle (FIG. 20(a)), the information "1" is stored in the previous reset memory area 74i, and if a LOW level signal indicating that the reset button 56 is not being pressed is received, the information in the previous reset memory area 74i is "0".

In the shift process of the detection state storage area in step S601, the information stored in the reset current state storage area 74h is overwritten in the previous reset state storage area 74i. After that, the signal received from the reset button 56 is identified, and if the identified signal is at a high level (step S602: YES), the reset current state storage area 74h is set to "1" (step S603), and if the identified signal is at a low level (step S602: NO), the reset current state storage area 74h is cleared to "0" (step S604).

If the processing of step S603 or step S604 is executed, other processing is executed (step S605). In the other processing, processing is executed to identify the contents of the detection signals from various sensors other than the sensor that detects the pressing operation of the reset button 56.

Returning to the explanation of the timer interrupt process (FIG. 19), after executing the sensor monitoring process, a timer subtraction process is executed to subtract the values of each counter and timer (step S506). Also, a command output process is executed to send various commands to the performance side MPU 92 (step S507). Also, a port output process is executed to output data corresponding to the I/O device from the input/output port (step S508). In the port output process, the display of the dual-purpose display unit 66 is controlled so that a number corresponding to the value of the medium provision counter of the main side RAM 74 described later is displayed in a situation where the notification of the stop order of the reels 32L, 32M, and 32R is not executed. Note that, when the value of the medium provision counter is "0" in a situation where the notification of the stop order of the reels 32L, 32M, and 32R is not executed, the dual-purpose display unit 66 is turned off. Also, a control process of the bet display unit 64 is executed so that a display corresponding to the number of bets is executed on the bet display unit 64 (step S509). In addition, a management process is executed to manage the game history and display the results of the management on the combined display unit 66 (step S510). Specifically, the ratio of the total number of games in the second section SC2 (described later) to the total number of games is calculated, and the calculated ratio is displayed on the combined display unit 66. After that, the values of each register saved in the main RAM 74 in the previous step S502 are restored to the corresponding registers in the main MPU 72 (step S511), and the next timer interrupt process (FIG. 19) is permitted to be executed (step S512).

Returning to the explanation of the setting change execution process (Figure 18), after allowing execution of the timer interrupt process (Figure 19) in step S401, it is determined whether or not the timer interrupt process (Figure 19) has been executed (step S402), and the process waits in step S402 until the timer interrupt process (Figure 19) is executed. Any process configuration can be used to determine whether or not the timer interrupt process (Figure 19) has been executed, but in this slot machine 10, an execution completion flag is provided in the register of the main MPU 72, and when the supply of operating power to the main MPU 72 is started, the execution completion flag is cleared to "0", and thereafter, a process is executed to set the execution completion flag to "1" each time the timer interrupt process (Figure 19) is executed. In this case, in step S402, it is determined whether the execution flag in the register of the master MPU 72 is set to "1". If the execution flag is not set to "1", a negative determination is made in step S402, and if the execution flag is set to "1", a positive determination is made in step S402. If a positive determination is made in step S402, the execution flag in the register of the master MPU 72 is cleared to "0" (step S403).

Then, it is determined whether the value of the setting value storage area provided in the main RAM 74 is 6 or more (step S404). The setting value storage area is an area for the main MPU 72 to specify the setting value that is currently the selection target. If the value of the setting value storage area is "0", the setting value that is the selection target is "1", if the value of the setting value storage area is "1", if the value of the setting value storage area is "2", if the value of the setting value storage area is "2", if the value of the setting value storage area is "3", if the value of the setting value storage area is "3", if the value of the setting value storage area is "4", if the value of the setting value storage area is "4", if the value of the setting value storage area is "5", if the value of the setting value storage area is "5", if the value of the setting value storage area is "6". If the value of the setting value storage area is 6 or more, this means that the value of the setting value storage area has exceeded the maximum value, so the setting value storage area is cleared to "0" (step S405). As a result, the setting value that is the selection target becomes "1".

If a negative judgment is made in step S404 or if the processing of step S405 is executed, it is judged whether or not the timer interrupt processing (FIG. 19) has been executed (step S406), and the process waits in step S406 until the timer interrupt processing (FIG. 19) is executed. Specifically, as in step S402, it is judged whether or not the execution flag in the register of the main MPU 72 is set to "1". If a positive judgment is made in step S402, the execution flag is cleared to "0", and as already explained, processing is executed to set the execution flag to "1" each time the timer interrupt processing (FIG. 19) is executed. Therefore, in step S406, it is judged whether or not the timer interrupt processing (FIG. 19) has been executed at least once after the positive judgment is made in step S402. If the execution flag is not set to "1", a negative judgment is made in step S406, and if the execution flag is set to "1", a positive judgment is made in step S406. If the determination is positive in step S406, the execution completion flag in the register of the main MPU 72 is cleared to "0" (step S407).

Then, it is determined whether the start lever 41 is turned ON (step S408). When the start lever 41 is turned ON while the setting change execution process is being executed, the setting value to be selected is confirmed as the setting value to be used. When the start lever 41 is not turned ON (step S408: NO), it is determined whether the pressing operation of the reset button 56 has started (step S409). Specifically, it is determined whether the information stored in the previous reset memory area 74i of the main RAM 74 is "0" corresponding to the reset button 56 not being pressed, and whether the information stored in the current reset memory area 74h of the main RAM 74 is "1" corresponding to the reset button 56 being pressed. If a negative determination is made in step S409, the process returns to step S406. If a positive determination is made in step S409, the value of the setting value memory area of the main RAM 74 is incremented by 1 (step S410). Then, the process returns to step S404. If the value in the setting value storage area after adding 1 is 6 or more (step S404: YES), the setting value storage area is cleared to "0" (step S405) and the process from step S406 onwards is executed. If the start lever 41 is turned ON (step S408: YES), the process waits until the setting key inserted in the setting key insertion hole 57 is turned OFF (step S411: NO), and if the setting key is turned OFF (step S411: YES), this setting change execution process ends.

In other words, when the setting change execution process is being performed, each time the reset button 56 is pressed, the setting value that is the subject of selection is changed to a setting value with one level of advantage that is one step higher. Also, when the reset button 56 is pressed when the setting value is already at "6", which has the highest degree of advantage, the setting value storage area is cleared to "0", and the setting value is changed to "1", which has the lowest degree of advantage. Also, when the start lever 41 is turned ON, the setting value that is the subject of selection is confirmed as the setting to be used, and then the setting key inserted into the setting key insertion hole 57 is turned OFF, thereby terminating the setting change execution process.

In the setting change execution process, the processes of steps S402 and S406 are executed as described above, and thus, from the start of the setting change execution process (FIG. 18) to the start of the first process for determining whether the reset button 56 has been pressed, two interrupt waiting periods occur during which the process waits for the timer interrupt process (FIG. 19) to be newly executed. By setting these interrupt waiting periods, even if the supply of operating power to the main MPU 72 is started when the reset button 56 is pressed, and further, the setting change execution process (FIG. 18) is started while the reset button 56 is maintained pressed, the setting value of the selection target is not changed by the maintained pressing of the reset button 56. This will be explained with reference to the time chart in FIG. 21.

Figure 21 is a time chart showing how, when the supply of operating power is started with the reset button 56 pressed, the setting value to be selected is not changed by the continued pressing of the reset button 56. Figure 21(a) shows the period during which operating power is supplied to the main MPU 72, Figure 21(b) shows the period during which the main processing (Figure 10) is being executed by the main MPU 72, Figure 21(c) shows the period during which the ON operation is being performed by the setting key inserted into the setting key insertion hole 57, Figure 21(d) shows the period during which the reset button 56 is being pressed, Figure 21(e) shows the period during which the clearing process is being executed for the entire memory area of the main RAM 74, and Figure 21(f) shows the period during which the setting change execution process is being executed. FIG. 21(g) shows the period during which the timer interrupt process (FIG. 19) is being executed, FIG. 21(h) shows the interrupt waiting period by steps S402 and S406 of the setting change execution process (FIG. 18), FIG. 21(i) shows the state of the current reset memory area 74h of the main RAM 74, FIG. 21(j) shows the state of the previous reset memory area 74i of the main RAM 74, and FIG. 21(k) shows the specific timing for triggering a change in the setting value to be selected.

At time t1, the supply of operating power to the main MPU 72 begins as shown in FIG. 21(a), and at time t1, the main processing (FIG. 10) begins in the main MPU 72 as shown in FIG. 21(b). In addition, when the supply of operating power begins as shown in FIG. 21(c), the setting key is turned ON, and the reset button 56 is pressed as shown in FIG. 21(d).

As described above, the setting key has been turned ON, and the setting change process (Figure 15) is then started. When the setting change process (Figure 15) is started, the main RAM 74 is cleared, but the reset button 56 was pressed when the current supply of operating power began, as described above, and this pressing operation continues at timing t2. Therefore, at timing t2, as shown in Figure 21 (e), a clear process is started for all of the memory areas of the main RAM 74. In this case, the current reset memory area 74h and previous reset memory area 74i are also cleared to "0" by the clear process.

After that, the clear process is completed at timing t3 as shown in FIG. 21(e). At timing t3, the setting change execution process (FIG. 18) is started as shown in FIG. 21(f). In this case, in the setting change execution process (FIG. 18), execution of the timer interrupt process (FIG. 19) is permitted in step S401, and the process waits until execution of the timer interrupt process (FIG. 19) in step S402. In other words, an interrupt waiting period occurs as shown in FIG. 21(h).

At the timing of t4 in the interrupt waiting period, as shown in FIG. 21(g), the timer interrupt process (FIG. 19) is executed by interrupting the setting change execution process (FIG. 18). At the timing of t5 when the timer interrupt process (FIG. 19) is being executed, the sensor monitoring process (FIG. 20(a)) of step S505 in the timer interrupt process (FIG. 19) is executed to determine whether the reset button 56 is being pressed. At the timing of t5, as shown in FIG. 21(d), the reset button 56 continues to be pressed. Therefore, at the timing of t5, as shown in FIG. 21(i), "1" is set in the current reset storage area 74h. The information in the previous reset storage area 74i is maintained at "0". The timer interrupt process (FIG. 19) ends at the timing of t6 as shown in FIG. 21(g). As a result, the process executed by the main MPU 72 returns to the setting change execution process (FIG. 18).

In the setting change execution process (Fig. 18), since the timer interrupt process (Fig. 19) has already been executed, a positive determination is made in step S402 and the processes from step S403 onwards are executed. Then, in step S406, the process waits until the timer interrupt process (Fig. 19) is executed again. In other words, an interrupt waiting period occurs at timing t7 as shown in Fig. 21 (h).

At the timing of t8 in the interrupt waiting period, the timer interrupt process (FIG. 19) is executed by interrupting the setting change execution process (FIG. 18) as shown in FIG. 21(g). At the timing of t9 when the timer interrupt process (FIG. 19) is being executed, the sensor monitoring process (FIG. 20(a)) of step S505 in the timer interrupt process (FIG. 19) is executed. In this case, the information stored in the reset current state storage area 74h is first shifted to the previous reset state storage area 74i, but since "1" has already been set in the reset current state storage area 74h, "1" is set in the previous reset state storage area 74i at the timing of t9 as shown in FIG. 21(j). In addition, the sensor monitoring process (FIG. 20(a)) specifies whether the reset button 56 is being pressed. At the timing of t9, the reset button 56 continues to be pressed as shown in FIG. 21(d). Therefore, at the timing t9, as shown in FIG. 21(i), "1" is set in the reset current state storage area 74h. The timer interrupt process (FIG. 19) ends at the timing t10 as shown in FIG. 21(g). As a result, the process executed by the main MPU 72 returns to the setting change execution process (FIG. 18).

In the setting change execution process (FIG. 18), since the timer interrupt process (FIG. 19) has already been executed, a positive judgment is made in step S406 and the process from step S408 onwards is executed. Then, at the timing of t11, as shown in FIG. 21(k), a process is executed to judge whether the pressing operation of the reset button 56 has started in step S409. Specifically, it is judged whether the information stored in the previous reset memory area 74i of the main RAM 74 is "0" corresponding to the reset button 56 not being pressed, and whether the information stored in the current reset memory area 74h of the main RAM 74 is "1" corresponding to the reset button 56 being pressed. In this case, as shown in FIG. 21(j), the information in the previous reset memory area 74i is "1", and as shown in FIG. 21(i), the information in the current reset memory area 74h is "1". Therefore, in step S409, it is not judged that the pressing operation of the reset button 56 has started. This makes it possible to prevent the setting value that is the selection target from being changed by maintaining the reset button 56 pressed when the supply of operating power is started while the reset button 56 is pressed.

Then, at timing t12, step S406 of the setting change execution process (FIG. 18) is executed. Step S406 waits until the timer interrupt process (FIG. 19) is executed again. That is, an interrupt waiting period occurs at timing t12 as shown in FIG. 21(h). At timing t13 during the interrupt waiting period, as shown in FIG. 21(d), the pressing of the reset button 56 is released. At timing t14, as shown in FIG. 21(g), the setting change execution process (FIG. 18) is interrupted and the timer interrupt process (FIG. 19) is executed. At timing t15 when the timer interrupt process (FIG. 19) is being executed, the sensor monitoring process (FIG. 20(a)) of step S505 in the timer interrupt process (FIG. 19) is executed. In this case, the information stored in the reset current state storage area 74h is first shifted to the previous reset state storage area 74i. However, since "1" has already been set in the reset current state storage area 74h, "1" is set in the previous reset state storage area 74i at the timing of t15 as shown in FIG. 21(j). In addition, the sensor monitoring process (FIG. 20(a)) determines whether the reset button 56 has been pressed. At the timing of t15, as shown in FIG. 21(d), the reset button 56 has not been pressed. Therefore, at the timing of t15, as shown in FIG. 21(i), the reset current state storage area 74h is cleared to "0". The timer interrupt process (FIG. 19) ends at the timing of t16 as shown in FIG. 21(g). As a result, the process executed by the main MPU 72 returns to the setting change execution process (FIG. 18).

In the setting change execution process (FIG. 18), since the timer interrupt process (FIG. 19) has already been executed, a positive determination is made in step S406 and the process from step S408 onwards is executed. Then, at the timing of t17, as shown in FIG. 21(k), a process is executed to determine whether or not the pressing operation of the reset button 56 has started in step S409. Specifically, it is determined whether or not the information stored in the previous reset memory area 74i of the main RAM 74 is "0", which corresponds to the reset button 56 not being pressed, and the information stored in the current reset memory area 74h of the main RAM 74 is "1", which corresponds to the reset button 56 being pressed. In this case, as shown in FIG. 21(j), the information in the previous reset memory area 74i is "1", and as shown in FIG. 21(i), the information in the current reset memory area 74h is "0". Therefore, in step S409, it is not determined that the pressing operation of the reset button 56 has started.

Then, at the timing of t18, step S406 of the setting change execution process (FIG. 18) is executed. In step S406, the process waits until the timer interrupt process (FIG. 19) is executed again. That is, as shown in FIG. 21(h), an interrupt waiting period occurs at the timing of t18. As shown in FIG. 21(g), the timer interrupt process (FIG. 19) is executed by interrupting the setting change execution process (FIG. 18) at the timing of t19 during the interrupt waiting period. At the timing of t20 when the timer interrupt process (FIG. 19) is being executed, the sensor monitoring process (FIG. 20(a)) of step S505 in the timer interrupt process (FIG. 19) is executed. In this case, the information stored in the reset current state storage area 74h is first shifted to the reset previous state storage area 74i, but since the information in the reset current state storage area 74h is "0", the reset previous state storage area 74i is cleared to "0" at the timing of t20 as shown in FIG. 21(j). Furthermore, the sensor monitoring process (FIG. 20(a)) determines whether the reset button 56 has been pressed. At the time t20, the reset button 56 has not been pressed, as shown in FIG. 21(d). Therefore, at the time t20, the reset current state storage area 74h is cleared to "0" as shown in FIG. 21(i). The timer interrupt process (FIG. 19) ends at the time t21, as shown in FIG. 21(g). As a result, the process executed by the main MPU 72 returns to the setting change execution process (FIG. 18).

If a positive determination is made in step S406, the execution completion flag of the main MPU 72 is cleared to "0" in step S407, and the timer interrupt process (FIG. 19) is not executed after the process of step S407 is executed until step S406 is executed again. Therefore, if a positive determination is made in step S406 and then step S406 is executed again, an interrupt waiting period is generated at that time, and the interrupt waiting period is released by executing the timer interrupt process (FIG. 19) once.

As described above, in the setting change execution process (FIG. 18), the processes of steps S402 and S406 are executed, and thus, from the start of the setting change execution process (FIG. 18) to the start of the first determination process of whether the pressing operation of the reset button 56 has started, an interrupt waiting period, which is a period for waiting for the progress of the process until the timer interrupt process (FIG. 19) is newly executed, occurs twice. Because these interrupt waiting periods are set, even if the supply of operating power to the main MPU 72 is started when the reset button 56 is pressed, and the setting change execution process (FIG. 18) is started in a situation in which the pressing operation of the reset button 56 is maintained, the contents of the information in the previous reset memory area 74i and the current reset memory area 74h indicate that the pressing operation of the reset button 56 is continuing at the time when the first determination process of whether the pressing operation of the reset button 56 has started after the setting change execution process (FIG. 18) is started. Therefore, in step S409, it is not determined that the pressing operation of the reset button 56 has started. This makes it possible to prevent the setting value that is the selection target from being changed by maintaining the reset button 56 pressed when the supply of operating power is started while the reset button 56 is pressed.

Returning to the explanation of the setting change process (Figure 15), after executing the setting change execution process in step S309, a setting change end command is sent to the production side MPU 92 (step S310). When the production side MPU 92 receives the setting change end command, it controls the upper lamp 61, speaker 62, and image display device 63 so that the notification indicating that the setting value is being changed is ended. After that, reset state information is set in the door state area 74e of the main side RAM 74 (step S311).

The door status area 74e is an area that is referenced when the main MPU 72 determines whether a change has occurred in the open/closed state of the front door 12 relative to the housing 11. Figure 22 is a flowchart showing the monitoring process of the door open sensor 16 that is executed in the main MPU 72 in other processes (step S605) of the sensor monitoring process (Figure 20(a)).

If a signal corresponding to the front door 12 being in an open state is received from the door open sensor 16 (step S701: YES), it is determined whether the information stored in the door status area 74e is open information (step S702). Open information is information indicating that a signal corresponding to the front door 12 being in an open state was received from the door open sensor 16 in the processing time immediately prior to this monitoring process. If open information is stored in the door status area 74e (step S702: YES), this monitoring process is terminated. If the information in the door status area 74e is information other than open information (step S702: NO), that is, if closed information is stored in the door status area 74e, if reset state information is stored in the door status area 74e, or if the information in the door status area 74e is "0", an open command is sent to the performance side MPU 92 (step S703). If the performance side MPU 92 receives an open command, it controls the upper lamp 61, the speaker 62, and the image display device 63 so that an announcement indicating that the front door 12 is in an open state is executed.

Then, open information is stored in the door status area 74e (step S704). As a result, even if a signal corresponding to the front door 12 being in an open state continues to be received from the door open sensor 16 in the next processing round of this monitoring process, a positive judgment is made in step S702 because the open information has been stored in the door status area 74e, and a new open command is not sent. This makes it possible to prevent the open command from being sent repeatedly in a situation where the front door 12 is maintained in an open state.

If a signal corresponding to the front door 12 being in a closed state is received from the door open sensor 16 (step S701: NO), it is determined whether the information stored in the door status area 74e is closed information (step S705). Closed information is information indicating that a signal corresponding to the front door 12 being in a closed state was received from the door open sensor 16 in the processing time immediately prior to this monitoring process. If closed information is stored in the door status area 74e (step S705: YES), this monitoring process is terminated as is. If information other than closed information is stored in the door status area 74e (step S705: NO), that is, if open information is stored in the door status area 74e, if reset state information is stored in the door status area 74e, or if the information in the door status area 74e is "0", a close command is sent to the performance side MPU 92 (step S706). When the production side MPU 92 receives a close command, it ends the notification indicating that the front door 12 is in an open state, and then controls the upper lamp 61, speaker 62, and image display device 63 to execute a notification indicating that the front door 12 has changed from an open state to a closed state. The notification indicating that the front door 12 has changed from an open state to a closed state continues for 30 seconds unless the front door 12 is newly opened. If the front door 12 is newly opened, the notification indicating that the front door 12 is in an open state is restarted.

Then, the closed information is stored in the door status area 74e (step S707). As a result, even if the signal corresponding to the front door 12 being closed continues to be received from the door open sensor 16 in the next processing round of this monitoring process, a positive judgment is made in step S705 because the closed information is stored in the door status area 74e, and a new close command is not sent. This makes it possible to prevent the close command from being repeatedly sent in a situation where the front door 12 is maintained in a closed state.

Figure 23 is a flowchart showing the notification process executed by the production side MPU 92. The notification process is repeatedly executed by the production side MPU 92 at a relatively short interval (e.g., every 2 milliseconds).

If a setting change start command has been received (step S801: YES), a setting change notification start process is executed (step S802). In this start process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that a setting change notification is started to indicate that the setting value is being changed. In this case, the image display device 63 may be configured to display an image that allows the amusement hall manager to recognize the operation content for changing the setting value. After this start process is executed, other processes in step S818 control the upper lamp 61, speaker 62, and image display device 63 so that the content of the setting change notification is continued or updated until a setting change end command is received from the main MPU 72.

If an open command has been received (step S803: YES), and if a setting change notification is being executed (step S804: YES), the notification process is terminated without executing any process in response to the reception of the open command. This allows the setting change notification to be prioritized over the door open notification indicating that the front door 12 is open. If an open command has been received (step S803: YES), and a setting change notification is not being executed (step S804: NO), a door open notification start process is executed (step S805). In this start process, the upper lamp 61, the speaker 62, and the image display device 63 are controlled so that a door open notification indicating that the front door 12 is open is started. After this start process is executed, the upper lamp 61, the speaker 62, and the image display device 63 are controlled so that the contents of the door open notification are continued or updated in other processes in step S818 until a close command is received from the main MPU 72.

If a setting change end command has been received (step S806: YES), an end process for the setting change notification is executed (step S807). In this end process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the setting change notification is ended. In addition, a clear process for the performance side RAM 94 is executed (step S808). In this clear process, each storage area of the performance side RAM 94 is cleared to "0" and initialized. This makes it possible to initialize not only each storage area of the main side RAM 74, but also each storage area of the performance side RAM 94 when the setting value to be used is set by the master MPU 72. When the performance side RAM 94 is initialized, a post-initialization notification is executed by the upper lamp 61, speaker 62, and image display device 63.

If a close command has been received (step S809: YES), or if a setting change notification is being executed (step S810: YES), the notification process is terminated without performing any processing in response to the reception of the close command. This allows the setting change notification to be prioritized over the door closed notification indicating that the front door 12 has changed from an open state to a closed state. If a close command has been received (step S809: YES) and a setting change notification is not being executed (step S810: NO), termination processing of the door open notification is executed (step S811). In this termination processing, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the door open notification indicating that the front door 12 is in an open state is terminated.

After that, a door closing notification start process is executed (step S812). In this start process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that a door closing notification is started to indicate that the front door 12 has changed from an open state to a closed state. In addition, after this start process is executed, other processes in step S818 control the upper lamp 61, speaker 62, and image display device 63 so that the contents of the door closing notification are continued or updated until the door closing notification period (specifically, 30 seconds) has elapsed. In addition, a setting process of a door closing notification counter provided in the performance side RAM 94 is executed (step S813). In this setting process, information corresponding to the door closing notification period (specifically, 30 seconds) is set in the door closing notification counter.

If the value of the door closing notification counter in the performance side RAM 94 is 1 or more (step S814: YES), the value of the door closing notification counter is decremented by 1 (step S815). Then, by determining whether the value of the door closing notification counter after decrementing by 1 is "0" or not, it is determined whether the door closing notification period has elapsed since the start of the door closing notification (step S816). If the value of the door closing notification counter is "0" (step S816: YES), an end process for the door closing notification is executed (step S817). In this end process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the door closing notification, which indicates that the front door 12 has changed from an open state to a closed state, is ended.

Next, the manner in which various notifications are executed when the supply of operating power is started and the setting change process (FIG. 15) is executed will be described with reference to the time chart of FIG. 24. FIG. 24(a) shows the period during which operating power is supplied to the main MPU 72, FIG. 24(b) shows the period during which the main process (FIG. 10) is executed by the main MPU 72, FIG. 24(c) shows the period during which the front door 12 is open, FIG. 24(d) shows the period during which the clear process of the memory area of the main RAM 74 is executed, FIG. 24(e) shows the period during which the setting change execution process (FIG. 18) is executed, FIG. 24(f) shows the period during which the setting change notification is executed, FIG. 24(g) shows the timing when reset state information is set in the door state area 74e of the main RAM 74, FIG. 24(h) shows the period during which the door open notification is executed, and FIG. 24(i) shows the period during which the door closed notification is executed.

At the timing of t1, when the front door 12 is in an open state as shown in FIG. 24(c), the supply of operating power to the main MPU 72 is started as shown in FIG. 24(a), and at the timing of t1, the main processing (FIG. 10) is started in the main MPU 72 as shown in FIG. 24(b). In addition, since the front door 12 is in an open state and the ON operation is performed using the setting key when the supply of operating power is started, the setting change processing (FIG. 15) is started at the timing of t2. When the setting change processing (FIG. 15) is started, the clear processing of the main RAM 74 is executed, but the reset button 56 was not pressed when the supply of operating power was started this time, and no information abnormality has occurred in the main RAM 74. Therefore, at the timing of t2, the clear processing of a part of the storage area of the main RAM 74 is started as shown in FIG. 24(d). In this case, the door status area 74e is also cleared to "0" by the clear processing, so that neither open information nor closed information is stored in the door status area 74e. Note that the timer interrupt process (Figure 19) remains disabled from the time the supply of operating power begins.

After that, the clear process is completed at the timing of t3 as shown in FIG. 24(d). At the timing of t3, the setting change execution process (FIG. 18) is started as shown in FIG. 24(e). Also, immediately before the setting change execution process (FIG. 18) is started, the process of step S308 in the setting change process (FIG. 15) is executed, and a setting change start command is sent from the master MPU 72 to the performance side MPU 92. Therefore, a setting change notification is started at the timing of t3 as shown in FIG. 24(f). In the setting change execution process (FIG. 18), the timer interrupt process (FIG. 19) is permitted to be executed in step S401, and open information is not stored in the door status area 74e. Therefore, an open command is sent to the performance side MPU 92 in the monitoring process of the door open sensor 16 in the timer interrupt process (FIG. 19). However, since the setting change notification has already started, the door open notification is not started.

Then, at timing t4, the setting change execution process (FIG. 18) ends, as shown in FIG. 24(e). In this case, the process of step S310 in the setting change process (FIG. 15) is executed, and a setting change end command is sent from the master MPU 72 to the performance MPU 92. Therefore, the setting change in progress notification ends at timing t4, as shown in FIG. 24(e).

After that, at the timing of t5, step S311 in the setting change process (FIG. 15) is executed, and reset state information that is neither open nor closed is stored in the door status area 74e. Then, the timer interrupt process (FIG. 19) is executed, and at the timing of t6, the timer interrupt process (FIG. 19) executes the door open sensor 16 monitoring process (FIG. 22). In this case, as shown in FIG. 24(c), when the front door 12 is in the open state, the reset state information is stored in the door status area 74e, so an open command is sent to the performance side MPU 92. Therefore, at the timing of t6, a door open notification is started as shown in FIG. 24(h). Note that open information is set in the door status area 74e at the timing of t6, so the door status area 74e is in a state where no reset state information is stored, as shown in FIG. 24(g).

After that, at the timing of t7, the front door 12 is closed as shown in FIG. 24(c). In this case, since open information is stored in the door status area 74e, when the door open sensor 16 monitoring process (FIG. 22) is executed in the timer interrupt process (FIG. 19), a close command is sent to the performance side MPU 92. Therefore, at the timing of t7, the door open notification is ended as shown in FIG. 24(h), and the door closed notification is started as shown in FIG. 24(i). Note that closed information is set in the door status area 74e at the timing of 7. After that, the door closed notification period (specifically 30 seconds) has elapsed at the timing of t8, and the door closed notification is ended as shown in FIG. 24(i).

In the configuration in which the clear process of the storage area of the main RAM 74 is executed when the setting change process (FIG. 15) is executed to set the setting value to be used as described above, when the setting change execution process (FIG. 18) is completed, reset state information that is neither open information nor closed information is stored in the door state area 74e. As a result, if the front door 12 is in an open state when the setting change execution process (FIG. 18) is completed, the setting change notification ends and then the door open notification starts. Also, if the front door 12 is in a closed state when the setting change execution process (FIG. 18) is completed, the setting change notification ends and then the door closed notification starts. Therefore, when the setting change execution process (FIG. 18) is completed, it is possible to execute either the door open notification or the door closed notification following the setting change notification. Therefore, it is possible to reliably notify that the front door 12 is in an open state or that the front door 12 is in a closed state.

If the front door 12 is in a closed state at the time when the setting change execution process (Figure 18) is completed and the reset state information is set in the door status area 74e, the monitoring process (Figure 22) of the door open sensor 16 in the timer interrupt process (Figure 19) determines that the front door 12 is in a closed state in a situation where the reset state information is stored in the door status area 74e, and a close command is sent to the performance side MPU 92. In this case, a door closed notification is executed instead of a door open notification being executed after the setting change notification.

Next, the normal processing executed by the main MPU 72 will be explained based on the flowchart in Figure 25.

First, the start waiting process is executed (step S901). FIG. 26 is a flowchart showing the start waiting process. First, it is determined whether or not the replay bet setting flag provided in the master RAM 74 is set to "1" (step S1001). The replay bet setting flag is a flag for the master MPU 72 to determine whether or not the same number of bets as the previous bet number have already been set when any replay winning has been established in the previous game. If a negative determination is made in step S1001, the value of the bet number history counter 74f also provided in the master RAM 74 is set to the bet number setting counter 74a (see FIG. 9) provided in the master RAM 74, on the condition that any replay winning has been established in the previous game (step S1002: YES) (step S1003). The bet number setting counter 74a is a counter for the master MPU 72 to specify the number of bets for the game to be executed, and the bet number history counter 74f is a counter for the master MPU 72 to specify the number of bets for the previous game. After that, the replay bet setting flag is set to "1" (step S1004).

If a positive determination is made in step S1001, if a negative determination is made in step S1002, or if the processing of step S1004 is executed, a bet handling process is executed (step S1005). Figure 27 is a flowchart showing the bet handling process.

If the current gaming state is not the second CB state ST3 (step S1101: NO), the bet upper limit, which is the upper limit of gaming media that can be bet on in the current game, is set to "3" (step S1102). If the current gaming state is the second CB state ST3 (step S1101: YES), the bet upper limit, which is the upper limit of gaming media that can be bet on in the current game, is set to "2" (step S1103). In other words, in this slot machine 10, when the state is the second CB state ST3, the bet upper limit is set to "2", and when the state is not the second CB state ST3, the bet upper limit is set to "3".

When the process of step S1102 or step S1103 is executed, on the condition that the value of the bet number setting counter 74a of the main RAM 74 is not the current bet upper limit number (step S1104: NO), it is determined whether or not the number of virtual medals stored is one or more and a valid bet operation has been performed (step S1105). The main RAM 74 is provided with a credit counter 74b (see FIG. 9) as an area for storing the number of virtual medals stored. In step S1105, it is determined whether or not the number of virtual medals stored is one or more by determining whether or not the value of the credit counter 74b is one or more. In addition, if the first credit insertion button 47 is operated, it is determined that a valid bet operation has been performed, and if the second credit insertion button 48 is operated, it is determined that a valid bet operation has been performed on the condition that the value of the bet number setting counter 74a is one or less.

If the determination in step S1105 is affirmative, a bet setting process is executed (step S1106). In the bet setting process, when the first credit insertion button 47 is operated, if the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is equal to or greater than the upper limit number of bets, the value of the bet number setting counter 74a is set to the upper limit number of bets, and the value of the number of virtual medals used in the setting is subtracted from the credit counter 74b. If the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is less than the upper limit number of bets, the value of the credit counter 74b is added to the bet number setting counter 74a, and then the value of the credit counter 74b is cleared to "0". Furthermore, in the bet number setting process, when the second credit insertion button 48 is operated, if the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is 2 or more, the value of the bet number setting counter 74a is set to "2" and the value of the number of virtual medals used in the setting is subtracted from the credit counter 74b, and if the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is less than 2, the value of the credit counter 74b is added to the bet number setting counter 74a and then the value of the credit counter 74b is cleared to "0."

If a positive judgment is made in step S1104, if a negative judgment is made in step S1105, or if the processing of step S1106 is executed, it is judged whether or not one medal is detected by the inserted medal detection sensor 45a due to a medal being inserted into the medal insertion slot 45 (step S1107). If a positive judgment is made in step S1107, if the value of the bet number setting counter 74a in the main RAM 74 is less than the upper limit number of bets (step S1108: NO), the value of the bet number setting counter 74a is incremented by 1 (step S1109), and if the value of the bet number setting counter 74a is equal to or greater than the upper limit number of bets (step S1108: YES), the value of the credit counter 74b in the main RAM 74 is incremented by 1 (step S1110). When the processing of step S1109 or step S1110 is executed, on the condition that the value of the bet number setting counter 74a is equal to or greater than the upper limit number of bets and the value of the credit counter 74b is equal to or greater than the upper limit number of accumulated memories (specifically, "50") (step S1111: YES), the reception prohibition process is executed (step S1112). By executing the reception prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal is discharged into the medal tray 59 without being detected by the inserted medal detection sensor 45a.

If a negative judgment is made in step S1107, if a negative judgment is made in step S1111, or if the processing of step S1112 is executed, it is judged whether or not the current gaming state is the first CB state ST2 (step S1113). If the current gaming state is the first CB state ST2 (step S1113: YES), the bet setting completion flag at the time of acceptance provided in the main RAM 74 is set to "1" (step S1115) on the condition that the value of the bet number setting counter 74a is "3" (step S1114: YES). On the other hand, if the current gaming state is not the first CB state ST2 (step S1113: NO), the bet setting completion flag at the time of acceptance is set to "1" (step S1115) on the condition that the value of the bet number setting counter 74a is 2 or more (step S1116: YES).

The bet set flag at the time of acceptance is a flag for the main MPU 72 to determine whether or not a sufficient number of gaming media have been bet to start one game. If the gaming state is the first CB state ST2, one game cannot be started unless "3" gaming media have been bet, and one game can be started only when "3" gaming media have been bet. Also, if the gaming state is not the first CB state ST2, one game cannot be started unless two or more gaming media have been bet, and one game can be started only when two or more gaming media have been bet.

Returning to the explanation of the start waiting process (FIG. 26), after the bet corresponding process is executed in step S1005, it is determined whether the settlement button 51 has been operated (step S1006). If the settlement button 51 has been operated (step S1006: YES), the settlement process is executed (step S1007), and the bet setting completion flag at the time of acceptance in the main RAM 74 is cleared to "0" (step S1008). In the settlement process in step S1007, if the bet setting completion flag at the time of replay in the main RAM 74 is not set to "1", the hopper device 53 is driven and controlled so that the number of medals corresponding to the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b are discharged to the medal tray 59. In this case, the bet number setting counter 74a is cleared to "0" and the credit counter 74b is cleared to "0". On the other hand, if the replay bet setting flag in the main RAM 74 is set to "1", the hopper device 53 is controlled and driven so that the number of medals corresponding to the value of the credit counter 74b is discharged into the medal tray 59. In this case, the credit counter 74b is cleared to "0".

As described above, the start waiting process is executed, and the bet number setting counter 74a is set. As already explained, the slot machine 10 is provided with a bet display unit 64 on the front side of the slot machine 10, and the bet display unit 64 displays a value corresponding to the value of the bet number setting counter 74a. The display control of the bet display unit 64 is executed by the control process of the bet display unit 64 in step S509 of the timer interrupt process (Figure 19). Figure 28 is a flowchart showing the control process of the bet display unit 64.

If the value of the bet number setting counter 74a is "0" (step S1201: YES), a full light-off process is executed (step S1202). By executing the full light-off process, all three light-emitting elements arranged vertically in the bet display unit 64 are turned off.

If the value of the bet number setting counter 74a is "1" (step S1203: YES), a first lighting process is executed (step S1204). By executing the first lighting process, the bottommost light-emitting element of the three light-emitting elements arranged vertically in the bet display unit 64 is turned on and the remaining light-emitting elements are turned off.

If the value of the bet number setting counter 74a is "2" (step S1205: YES), a second lighting process is executed (step S1206). By executing the second lighting process, the bottom and center light-emitting sections of the three light-emitting sections arranged vertically in the bet display section 64 are turned on and the top light-emitting section is turned off.

If the value of the bet number setting counter 74a is "3" (step S1205: NO), a third lighting process is executed (step S1207). By executing the third lighting process, all three light-emitting elements arranged vertically in the bet display unit 64 are lit up.

Returning to the explanation of the normal processing (FIG. 25), after executing the start waiting processing in step S901, it is determined whether or not either the replay bet set flag or the acceptance bet set flag in the main RAM 74 is set to "1" (step S902). If a negative determination is made in step S902, the process returns to step S901. If a positive determination is made in step S902, it is determined whether or not the start lever 41 has been operated (step S903). If the start lever 41 has not been operated, the process returns to step S901.

When the start lever 41 is operated (step S903: YES), the main line ML is activated and then the acceptance prohibition process is executed (step S904). By executing the acceptance prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal is discharged into the medal tray 59 without being detected by the inserted medal detection sensor 45a. In addition, in step S905, a start-time setting process is executed to perform various settings when the game is started. In the start-time setting process, both the replay bet setting flag and the acceptance bet setting flag are cleared to "0".

Then, in step S906, a role selection process is executed to select a role for the current game, and in step S907, a freeze setting process at the time of bonus transition is executed to set a freeze period during which the reels 32L, 32M, and 32R are awaiting the start of rotation in the current game, and in step S908, if a freeze period has been set, the process waits for execution of subsequent processes. If a freeze period has not been set or if measurement of the freeze period has been completed, in step S909, a reel control process is executed to drive and control each of the reels 32L, 32M, and 32R in a manner corresponding to the result of the current role selection process.

Then, in step S910, a medium granting process is executed. In the medium granting process, when a small win is established in the current game, a process is executed to grant the player a number of game media corresponding to the small win. Specifically, when a virtual medal is granted, a value corresponding to the current small win is added to the credit counter 74b of the main RAM 74, and when the value of the credit counter 74b has reached the upper limit of the stored memory number, the hopper device 53 is driven and controlled so that the number of medals exceeding the upper limit of the stored memory number are paid out to the medal tray 59. In addition, in the medium granting process, information on the number of game media to be granted this time is stored in the medium granting counter provided in the main RAM 74. In a situation where the stop order of the reels 32L, 32M, and 32R is not notified in the dual-purpose display unit 66, the dual-purpose display unit 66 is displayed and controlled in the port output process (step S508) in the timer interrupt process (FIG. 19) so that a value corresponding to the information stored in the medium granting counter is displayed. As a result, when a small win is achieved, the player can check the combined display unit 66 to ascertain the number of gaming media awarded as a result of the small win. The information stored in the media awarding counter is cleared to "0" when the pseudo bonus state ST4 ends or when a new gaming media bet is made. If the value of the media awarding counter becomes "0" when the notification of the stopping order of reels 32L, 32M, and 32R has not been executed, the combined display unit 66 does not display the number "0" but turns off.

Then, in step S911, a history storage process is executed (step S911). In the history storage process, the value of the bet number setting counter 74a in the main RAM 74 is set to the bet number history counter 74f in the main RAM 74. In addition, the value of the medium award counter in the main RAM 74 is set to the award number history counter in the main RAM 74.

After that, in step S912, a response process is executed at the end of the game to enable the setting of the game state and game zone corresponding to the result of this game. In addition, in step S913, an external output setting process is executed to output the state of the slot machine 10 to the management computer of the gaming hall. After that, in step S914, an acceptance permission process is executed. By executing the acceptance permission process, the medal inserted from the medal insertion port 45 is detected by the inserted medal detection sensor 45a and then collected by the hopper device 53.

<About the lottery process for winning roles>
Next, the lottery process for determining a winning combination executed in step S906 of the normal process (FIG. 25) will be described.

In the process of selecting a winning combination, the index value IV is selected using the first random number obtained from the first random number circuit 75. FIG. 29 is an explanatory diagram for explaining the contents of the index value IV. There are 17 index values IV set, ranging from "1" to "17", and winning data is set in correspondence with each index value IV. In the following explanation, the explanatory diagram in FIG. 30 will be referred to as appropriate.

As shown in FIG. 29, the first bell winning data is set to the index values IV=1 to 6, and one of the first to sixth compensation winning data is set. When the index value IV=1 is a winning, as shown in FIG. 30, if the first stop (the reel on which the stop command was first issued) is the left reel 32L, the second stop (the reel on which the stop command was second issued) is the center reel 32M, and the third stop (the reel on which the stop command was last issued) is the right reel 32R, the first bell winning is surely achieved regardless of the operation timing of each stop button 42 to 44, and the first compensation winning may be achieved in other cases. When the index value IV=2 is a winning, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the center reel 32M, the first bell winning is surely achieved regardless of the operation timing of each stop button 42 to 44, and the fourth compensation winning may be achieved in other cases. In the case where the winning is made with an index value IV=3, if the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, the first bell winning is surely made regardless of the operation timing of each stop button 42-44, and in other cases, the third supplementary winning may be made. In the case where the winning is made with an index value IV=4, if the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the first bell winning is surely made regardless of the operation timing of each stop button 42-44, and in other cases, the sixth supplementary winning may be made. In the case where the winning is made with an index value IV=5, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the center reel 32M, the first bell winning is surely made regardless of the operation timing of each stop button 42-44, and in other cases, the second supplementary winning may be made. When an index value IV=6 is reached and a win occurs, if the first stop is on the right reel 32R, the second stop is on the center reel 32M, and the third stop is on the left reel 32L, the first bell win will occur regardless of the operation timing of each stop button 42-44, and in all other cases the fifth supplementary win may occur.

As already explained, in the slot machine 10, when in the non-CB state, reel control is performed on each of the reels 32L, 32M, and 32R, which allows the reels to slide up to four symbols after the stop buttons 42-44 are operated. In other words, reel control is performed on each of the reels 32L, 32M, and 32R, which stops the reels within a specified time (190 milliseconds) after the stop buttons 42-44 are operated. By performing such reel control, it becomes easier to achieve a winning combination that corresponds to a winning role, and it becomes possible to prevent a winning combination that corresponds to a non-winning role from being achieved. However, because the amount of rotation of the reels 32L, 32M, and 32R that can be slid is limited as described above, if there are five or more symbols among the constituent symbols that make up the combination of symbols for establishing a win on one reel 32L, 32M, and 32R, the constituent symbols may not stop on the main line ML depending on the timing of the operation of the corresponding stop buttons 42 to 44 (this phenomenon is also called a "missed win"). The first bell win, the second bell win, and the various replay wins are winning modes that do not cause a miss if the reels 32L, 32M, and 32R are stopped in the corresponding order, while the first to ninth compensation wins, the first watermelon win, the second watermelon win, the cherry win, the first CB win, and the second CB win are winning modes that may cause a miss depending on the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation position of the reels 32L, 32M, and 32R.

As shown in FIG. 29, the index values IV=7 to IV=9 are set with the second bell winning data and with any of the seventh to ninth compensation winning data. When the index value IV=7 is a winning combination, as shown in FIG. 30, if the first stop is the left reel 32L, the second bell winning combination is guaranteed regardless of the type of the second and third stop targets reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44, and otherwise the seventh compensation winning combination may be achieved. When the index value IV=8 is a winning combination, if the first stop is the center reel 32M, the second bell winning combination is guaranteed regardless of the type of the second and third stop targets reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44, and otherwise the ninth compensation winning combination may be achieved. If the index value IV=9 is a win, and the first stop is the right reel 32R, the second bell win will be achieved regardless of the type of the second and third stop targets, reels 32L, 32M, and 32R, and the operation timing of each stop button 42-44; otherwise, the eighth supplementary win may be achieved.

As shown in FIG. 29, the first bell winning data is set for index value IV=10. If a win occurs with index value IV=10, as shown in FIG. 30, the first bell win is guaranteed to occur regardless of the stopping order of reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44.

As shown in FIG. 29, only the first watermelon winning data is set for index value IV=11. When a win occurs with index value IV=11, as shown in FIG. 30, the first watermelon winning can be achieved regardless of the stopping order of reels 32L, 32M, and 32R. However, depending on the operation timing of each stop button 42-44, the first watermelon winning may not be achieved. As shown in FIG. 29, only the second watermelon winning data is set for index value IV=12. When a win occurs with index value IV=12, as shown in FIG. 30, the second watermelon winning may be achieved regardless of the stopping order of reels 32L, 32M, and 32R. However, depending on the operation timing of each stop button 42-44, the second watermelon winning may not be achieved.

As shown in FIG. 29, only cherry winning data is set for index value IV=13. When a win occurs with index value IV=13, a cherry winning can occur regardless of the stopping order of reels 32L, 32M, and 32R, as shown in FIG. 30. However, depending on the operation timing of left stop button 42 relative to the spinning position of left reel 32L, there is a possibility that a cherry winning will not occur.

As shown in FIG. 29, only the first chance replay winning data is set for index value IV=14. When a win occurs with index value IV=14, as shown in FIG. 30, the first chance replay winning is surely established regardless of the stopping order of reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44. Also, as shown in FIG. 29, only the second chance replay winning data is set for index value IV=15. When a win occurs with index value IV=15, as shown in FIG. 30, the second chance replay winning is surely established regardless of the stopping order of reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44. Also, as shown in FIG. 29, only the normal replay winning data is set for index value IV=16. If a win occurs with index value IV = 16, as shown in Figure 30, a normal replay win is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R and the operation timing of each stop button 42 to 44.

Only the CB winning data is set for the index value IV=17 as shown in FIG. 29. In this case, if the number of bets on the gaming medium is "3" and the index value IV=17 is a winning, the first CB winning data is won, and if the number of bets on the gaming medium is "2" and the index value IV=17 is a winning, the second CB winning data is won. In other words, the first CB winning data is data that is set as a winning role only when the number of bets on the gaming medium is "3". The first CB winning can only be achieved when the number of bets on the gaming medium is "3". The second CB winning data is data that is set as a winning role only when the number of bets on the gaming medium is "2". The second CB winning can only be achieved when the number of bets on the gaming medium is "2". When the first CB winning data is set, if the number of bets on the gaming medium is "3", the first CB winning can be achieved regardless of the stopping order of the reels 32L, 32M, and 32R, as shown in FIG. 30. However, depending on the operation timing of each stop button 42 to 44, there is a possibility that the first CB winning will not be achieved. When the second CB winning data is set, if the number of gaming media bets is "2", as shown in FIG. 30, the second CB winning can be achieved regardless of the stopping order of reels 32L, 32M, and 32R. However, depending on the operation timing of each stop button 42 to 44, there is a possibility that the second CB winning will not be achieved.

Here, winning data other than the first CB winning data and the second CB winning data is erased in the game in which the winning occurred regardless of whether the corresponding winning event is achieved or not, and is not carried over to subsequent games following the game in which the winning event is achieved. In contrast, the first CB winning data and the second CB winning data are stored and retained until the corresponding winning event is achieved, even in subsequent games following the game in which the winning event is achieved, except when the main RAM 74 is cleared. In this case, in a game in which either the first CB winning data or the second CB winning data is carried over, the index values IV corresponding to the first CB winning data and the second CB winning data are excluded from the lottery.

In other words, if the first CB winning data is set in the main RAM 74 as a result of a game being played with the number of bets being "3", and the first CB winning data is carried over because the first CB winning data is not established, the index value IV corresponding to the first CB winning data is excluded from the lottery even if the game is played with the number of bets being "3", and the index value IV corresponding to the second CB winning data is excluded from the lottery even if the game is played with the number of bets being "2". Also, if the second CB winning data is set in the main RAM 74 as a result of a game being played with the number of bets being "2", and the second CB winning data is carried over because the second CB winning data is not established, the index value IV corresponding to the first CB winning data is excluded from the lottery even if the game is played with the number of bets being "3", and the index value IV corresponding to the second CB winning data is excluded from the lottery even if the game is played with the number of bets being "2". This makes it possible to prevent either the first CB winning data or the second CB winning data from being newly stored even if either the first CB winning data or the second CB winning data has already been stored, and makes it possible to prevent multiple CB winning data from being accumulated and stored.

The second CB winning data is stored in the second CB winning data area corresponding to the address "0000" in the main RAM 74, and the first CB winning data is stored in the first CB winning data area corresponding to the address "0001" in the main RAM 74 (see FIG. 16). As already explained, when the setting change process (FIG. 15) is executed, the clear process of the main RAM 74 is executed. In this case, when the supply of operating power is started, if the reset button 56 is not pressed and no information abnormality occurs in the main RAM 74, the clear process is executed on the memory area of the main RAM 74 except for the second CB winning data area, whereas when the supply of operating power is started, if the reset button 56 is pressed or an information abnormality occurs in the main RAM 74, the clear process is executed on all memory areas of the main RAM 74 including the second CB winning data area. As a result, in a situation where no information abnormality occurs in the main RAM 74, it is possible to select whether or not to erase the second CB winning data depending on whether or not the reset button 56 is pressed. In addition, if an information abnormality occurs in the main RAM 74, it is possible to execute a clear process on all of the storage areas of the main RAM 74, including the second CB winning data.

In the configuration in which the index values IV are set as described above, a point value PV is set for each index value IV in accordance with each game state. Specifically, in the first CB state ST2 or the second CB state ST3, only the index value IV=16 is set as the lottery object, and the index values IV=1 to 15 and 17 are not set as the lottery object. In addition, in a non-CB state in which neither the first CB winning data nor the second CB winning data is stored, all the index values IV=1 to 17 are set as the lottery object, and in a non-CB state in which either the first CB winning data or the second CB winning data is stored, the index values IV=1 to 16 are set as the lottery object, but the index value IV=17 is not set as the lottery object.

When the number of bets is "2" in the non-CB state, the point values PV set for each of the index values IV = 1 to 16 are the same regardless of whether the first CB winning data or the second CB winning data is stored. As a result, when the number of bets is "2" in the non-CB state, the winning probability of each of the index values IV = 1 to 16 is the same when either the first CB winning data or the second CB winning data is stored and when neither the first CB winning data nor the second CB winning data is stored. Also, when the number of bets is "3" in the non-CB state, the point values PV set for each of the index values IV = 1 to 16 are the same regardless of whether either the first CB winning data or the second CB winning data is stored. As a result, when the number of bets is "3" in the non-CB state, the winning probability for each of the index values IV = 1 to 16 is the same whether the first CB winning data or the second CB winning data is stored or whether neither the first CB winning data nor the second CB winning data is stored.

When the number of bets is "2" in the non-CB state, the probability of winning for each of the index values IV = 1 to 16 is lower than when the number of bets is "3" in the non-CB state. Specifically, when the number of bets is "2" in the non-CB state, the probability of winning for each of the index values IV = 1 to 16 is 2/3 or less than when the number of bets is "3" in the non-CB state. This makes it possible to increase the probability of a small win accompanied by the award of gaming media and a replay win that awards a replay in a game executed when the number of bets is "3" compared to a game executed when the number of bets is "2".

However, in the non-CB state where neither the first CB winning data nor the second CB winning data is stored, the probability of winning when the index value IV=17 is approximately 1/2.2, whereas in the non-CB state where neither the first CB winning data nor the second CB winning data is stored, the probability of winning when the index value IV=17 is approximately 1/3.3. This makes it possible to make the probability of a game with a bet number of "2" being executed and the second CB winning data being stored in the main RAM 74 higher in the non-CB state where neither the first CB winning data nor the second CB winning data is stored than the probability of a game with a bet number of "3" being executed and the first CB winning data being stored in the main RAM 74 in the non-CB state where neither the first CB winning data nor the second CB winning data is stored.

In this slot machine 10, six setting values from "1" to "6" are prepared in advance, and the setting value to be used can be set by executing the setting change process (FIG. 15) already described. Then, in the lottery process for the role, a lottery is performed for the index value IV that will win according to the winning probability corresponding to the setting value to be used. The setting value "n+1" has a more advantageous winning probability for the player than "n". Specifically, since the winning probability of a predetermined index value IV (i.e., a predetermined role) is higher when the setting value is "n+1" than when the setting value is "n", the setting value "n+1" is more advantageous for the player than when the setting value is "n". In the non-CB state, the winning probability of each index value IV varies depending on the setting value. However, this is not limited to this, and the winning probability of some index values IV may vary depending on the setting value, but the winning probability of other index values IV may not vary depending on the setting value. Note that the point value PV illustrated in FIG. 29 has a setting value of "3". In the CB state, as mentioned above, only the index value IV=16 is eligible for the lottery, but the point value PV of that index value IV is the same regardless of the setting value.

The specific configuration for performing the lottery process for winning combinations will be described. Figure 31 (a) is an explanatory diagram for explaining the contents of the data in the main ROM 73 for performing the lottery process for winning combinations.

The main ROM 73 stores in advance the following data to be referenced when the lottery process for winning roles is executed: a group of winning lottery tables 73a for setting 1, which is referenced when the setting value of the target to be used is "1", a group of winning lottery tables 73b for setting 2, which is referenced when the setting value of the target to be used is "2", a group of winning lottery tables 73c for setting 3, which is referenced when the setting value of the target to be used is "3", a group of winning lottery tables 73d for setting 4, which is referenced when the setting value of the target to be used is "4", a group of winning lottery tables 73e for setting 5, which is referenced when the setting value of the target to be used is "5", and a group of winning lottery tables 73f for setting 6, which is referenced when the setting value of the target to be used is "6". In each of the groups of winning lottery tables 73a to 73f, data is set for the corresponding setting value to enable the lottery process for winning roles to be executed based on the relationship between the index value IV and the point value PV in each game state, as shown in FIG. 29.

Figure 32 is an explanatory diagram for explaining the contents of the role selection table group 73a to 73f. Note that in Figure 32, the role selection table group 73c for setting 3 is shown as an example, but the other role selection table groups 73a, 73b, 73d to 73f have the same basic data structure although the specific point value PV contents differ.

In the role selection table groups 73a to 73f, data groups 101a to 10q are set corresponding to the index values IV=1 to 17, respectively. Specifically, a data group 101a for IV=1 is referenced when performing a role selection process for an index value IV=1, a data group 101b for IV=2 is referenced when performing a role selection process for an index value IV=2, a data group 101c for IV=3 is referenced when performing a role selection process for an index value IV=3, a data group 101d for IV=4 is referenced when performing a role selection process for an index value IV=4, and a data group 101e for IV=5 is referenced when performing a role selection process for an index value IV=6. a data group 101e for IV=5 that is referenced when a lottery process for a hand is executed for an index value IV=6; a data group 101f for IV=6 that is referenced when a lottery process for a hand is executed for an index value IV=6; a data group 101g for IV=7 that is referenced when a lottery process for a hand is executed for an index value IV=7; a data group 101h for IV=8 that is referenced when a lottery process for a hand is executed for an index value IV=8; A data group 101i for IV=9, a data group 101j for IV=10 that is referred to when a lottery process for a role is executed for an index value IV=10, a data group 101k for IV=11 that is referred to when a lottery process for a role is executed for an index value IV=11, a data group 101l for IV=12 that is referred to when a lottery process for a role is executed for an index value IV=12, and a data group 101l for IV=13 that is referred to when a lottery process for a role is executed for an index value IV=13. m, a data group 101n for IV=14 that is referenced when a lottery process for a role is performed for index value IV=14, a data group 101o for IV=15 that is referenced when a lottery process for a role is performed for index value IV=15, a data group 101p for IV=16 that is referenced when a lottery process for a role is performed for index value IV=16, and a data group 101q for IV=17 that is referenced when a lottery process for a role is performed for index value IV=17 are set.

Details will be described later, but in the process of drawing the winning combination in any game state, data groups 101a-101q are referenced in order, starting with data group 101a for IV=1. Each of these data groups 101a-101q contains data indicating whether or not a particular game state is eligible for drawing, data indicating the type of winning data that is set if the corresponding index value IV is selected, and data indicating the point value PV in each game state that is eligible for drawing.

The contents of data groups 101a to 101q will be explained with reference to the diagram in Figure 33. Figure 33(a) is an explanatory diagram for explaining data group 101a for IV=1, Figure 33(b) is an explanatory diagram for explaining data group 101p for IV=16, and Figure 33(c) is an explanatory diagram for explaining data group 101q for IV=17. Note that although the data contents of data groups 101b to 101o for IV=2 to 15 differ, the basic data structure is the same.

As shown in Figures 33(a) to 33(c), game state data 102a, 103a, 104a is set in each data group 101a, 101p, 101q as data indicating whether or not a lottery is selected in each game state. The game state data 102a, 103a, 104a has a data capacity of 1 byte. The game states classified in the game state data 102a, 103a, 104a include a CB state (first CB state ST2 or second CB state ST3), a non-CB state in which CB winning data (first CB winning data or second CB winning data) is not stored and the number of bets is "2" (hereinafter referred to as a non-internal two-coin bet state), a non-CB state in which CB winning data (first CB winning data or second CB winning data) is not stored and the number of bets is "2" (hereinafter referred to as a non-internal two-coin bet state), and a non-CB state in which CB winning data (first CB winning data or second CB winning data) is not stored and the number of bets is "1". There are five types of states: a state where the bet number is "3" (hereinafter referred to as a 3-coin bet state during non-internal play); a state where the CB winning data (first CB winning data or second CB winning data) is stored and the bet number is "2" (hereinafter referred to as a 2-coin bet state during internal play); and a state where the CB winning data (first CB winning data or second CB winning data) is stored and the bet number is "3" (hereinafter referred to as a 3-coin bet state during internal play). Of these five game states, the CB state is assigned the lowest bit D0 in the game state data 102a, 103a, and 104a, the non-internal 2-coin bet state is assigned the second lowest bit D1 in the game state data 102a, 103a, and 104a, the non-internal 3-coin bet state is assigned the third lowest bit D2 in the game state data 102a, 103a, and 104a, the internal 2-coin bet state is assigned the fourth lowest bit D3 in the game state data 102a, 103a, and 104a, and the internal 3-coin bet state is assigned the fifth lowest bit D4 in the game state data 102a, 103a, and 104a. The remaining bits D5 to D7 in the game state data 102a, 103a, and 104a are blank and not assigned to any game state.

As for the data group 101a for IV=1 in detail, as already explained, the index value IV=1 is not set as a lottery object in the CB state, but is set as a lottery object in the 2-coin bet state while not inside, the 3-coin bet state while not inside, the 2-coin bet state while inside, and the 3-coin bet state while inside. Therefore, as shown in FIG. 33(a), in the game state data 102a, the lowest bit D0 is set to "0", and the second to fifth lowest bits D1 to D4 are set to "1". The contents of this data are the same for the data groups 101b to 101o for IV=2 to 15.

As for the data group 101p for IV=16 in detail, as already explained, the index value IV=16 is set as a lottery target in all of the following states: CB state, 2-coin bet state while not inside, 3-coin bet state while not inside, 2-coin bet state while inside, and 3-coin bet state while inside. Therefore, as shown in FIG. 33(b), the lowest to fifth bits D0 to D4 in the game status data 103a are set to "1".

As for the data group 101q for IV=17 in detail, as already explained, the index value IV=17 is not set as a selection object in the CB state, the 2-coin bet state in the internal state, and the 3-coin bet state in the internal state, but is set as a selection object in the 2-coin bet state in the non-internal state and the 3-coin bet state in the non-internal state. Therefore, as shown in FIG. 33(c), in the game state data 104a, the lowest bit D0, the fourth lowest bit D3, and the fifth lowest bit D4 are set to "0", and the second lowest bit D1 and the third lowest bit D2 are set to "1".

By setting the game status data 102a, 103a, and 104a as described above, it becomes possible to determine whether or not the index value IV of the corresponding data group 101a to 101q is eligible for selection in the game status corresponding to the bit in the game status data 102a, 103a, and 104a to which "1" is set.

As shown in Fig. 33(a) to Fig. 33(c), in each data group 101a, 101p, 101q, winning target data 102b, 103b, 104b is set as data indicating the type of winning data to be set when the corresponding index value IV is won. Winning target data 102b, 103b, 104b has a data capacity of 2 bytes. For the data group 101a for IV=1, as shown in Fig. 33(a), the first bell winning data and the first compensation winning data are set in the winning target data 102b. For the data group 101p for IV=16, as shown in Fig. 33(b), the normal replay winning data is set in the winning target data 103b. For the data group 101q for IV=17, as shown in Fig. 33(c), the CB winning data is set in the winning target data 104b.

By setting the winning data 102b, 103b, and 104b as described above, when the lottery process for the winning role is performed with reference to the data groups 101a to 101q, if the index value IV of a specific data group 101a to 101q is a winning combination, it is possible to identify the type of winning data by referring to the specific data group 101a to 101q.

As shown in Figures 33(a) to 33(c), in each data group 101a, 101p, 101q, point value data 102c, 103c, 104c are set as data indicating the point value PV in each game state to be selected. In the point value data 102c, 103c, 104c, combinations of address data, which is 1 byte of data capacity, and point value PV, which is 2 bytes of data capacity, are set for the number of bits set to "1" in the corresponding game state data 102a, 103a, 104a, and are set corresponding to each bit set to "1". In this case, when there are multiple combinations of address data and point value PV in the point value data 102c, 103c, 104c, the combinations corresponding to the lower bits in the corresponding game state data 102a, 103a, 104a are set to addresses earlier in the address data.

As for the data group 101a for IV=1, as already explained, the index value IV=1 is not set as a lottery object in the CB state, but is set as a lottery object in the non-internal 2-coin bet state, the non-internal 3-coin bet state, the internal 2-coin bet state, and the internal 3-coin bet state. In this case, as shown in FIG. 33(a), four combinations of address data and point value PV are set in the point value data 102c. The first address data A(0) corresponds to the second lowest bit D1 in the game state data 102a, i.e., the non-internal 2-coin bet state, and a point value PV of "900" is set in association with the A(0). The next address data A(1) corresponds to the third lowest bit D2 in the game state data 102a, i.e., the non-internal 3-coin bet state, and a point value PV of "3000" is set in association with the A(1). The next address data, A(2), corresponds to the fourth lowest bit D3 in the game status data 102a, i.e., the internal two-coin bet state, and a point value PV of "900" is set in association with A(2). The next address data, A(3), corresponds to the fourth lowest bit D3 in the game status data 102a, i.e., the internal three-coin bet state, and a point value PV of "3000" is set in association with A(3).

As already explained, the index value IV=16 is set as a lottery target in all of the following states: CB state, 2-coin bet state in non-internal state, 3-coin bet state in non-internal state, 2-coin bet state in internal state, and 3-coin bet state in internal state. In this case, as shown in FIG. 33(b), five combinations of address data and point value PV are set in the point value data 103c. The first address data B(0) corresponds to the lowest bit D0 in the game state data 103a, i.e., the CB state, and a point value PV of "9000" is set in association with B(0). The next address data B(1) corresponds to the second lowest bit D1 in the game state data 103a, i.e., the 2-coin bet state in non-internal state, and a point value PV of "5500" is set in association with B(1). The next address data, B(2), corresponds to the third lowest bit D2 in the game status data 103a, i.e., the non-internal 3-coin bet state, and a point value PV of "9000" is set in association with B(2). The next address data, B(3), corresponds to the fourth lowest bit D3 in the game status data 103a, i.e., the internal 2-coin bet state, and a point value PV of "5500" is set in association with B(3). The next address data, B(4), corresponds to the fourth lowest bit D3 in the game status data 103a, i.e., the internal 3-coin bet state, and a point value PV of "9000" is set in association with B(4).

As for the data group 101q for IV=17, as already explained, the index value IV=17 is not set as a lottery object in the CB state, the 2-coin bet state in the internal state, and the 3-coin bet state in the internal state, but is set as a lottery object in the 2-coin bet state in the non-internal state and the 3-coin bet state in the non-internal state. In this case, as shown in FIG. 33(c), two combinations of address data and point value PV are set in the point value data 104c. The first address data C(0) corresponds to the second lowest bit D1 in the game state data 102a, i.e., the 2-coin bet state in the non-internal state, and a point value PV of "30000" is set in association with the C(0). The next address data C(1) corresponds to the third lowest bit D2 in the game state data 102a, i.e., the 3-coin bet state in the non-internal state, and a point value PV of "20000" is set in association with the C(1).

By setting the point value data 102c, 103c, and 104c as described above, when it is determined that a lottery target is in the current game state by referring to the game state data 102a, 103a, and 104a of the data groups 101a to 101q, it is possible to determine the point value PV corresponding to the current game state by referring to the point value data 102c, 103c, and 104c.

As described above, the data groups 101a to 101q for IV=1 to 17 are used to perform the lottery process for the winning combination, and various areas of the main RAM 74 are used to perform the lottery process for the winning combination. Figure 31(b) is an explanatory diagram for explaining the contents of the memory areas of the main RAM 74 for performing the lottery process for the winning combination.

As shown in FIG. 31(b), the main RAM 74 is provided with a judgment value counter 74j, a number of selections counter 74k, and an address counter 74l. The judgment value counter 74j is used to determine whether the current game state is a CB state, a 2-coin bet state in a non-internal state, a 3-coin bet state in a non-internal state, a 2-coin bet state in an internal state, or a 3-coin bet state in an internal state. The number of selections counter 74k is used to determine which index value IV is the subject of selection in the role selection process. The address counter 74l is used to determine which address data is the subject of reference among the point value data 102c, 103c, and 104c of the data groups 101a to 101q for IV=1 to 17 that are the subject of reference.

The processing configuration for the role selection process will be explained below with reference to the flowchart in Figure 34.

First, a first random number used to determine whether a winning combination has been achieved is obtained (step S1301). In this slot machine 10, when the start lever 41 is operated, the first random number at that time is latched from the first random number circuit 75. The first random number circuit 75 generates a first random number between "0" and "65535", and when the main MPU 72 confirms the operation of the start lever 41, it stores the value latched in the first random number circuit 75 in the main RAM 74. With this configuration, it is possible to quickly obtain the first random number when the start lever 41 is operated. The first random number circuit 75 is configured to latch the value of the free-running counter each time the start lever 41 is operated.

After obtaining the first random number, the setting value to be used is identified by referring to the setting value storage area of the main RAM 74, and the role selection table group 73a to 73f corresponding to the identified setting value is read from the main ROM 73 to the main RAM 74 (step S1302). In this case, if the setting value to be used is "1", the role selection table group 73a for setting 1 is read, if the setting value to be used is "2", the role selection table group 73b for setting 2 is read, if the setting value to be used is "3", the role selection table group 73c for setting 3 is read, if the setting value to be used is "4", the role selection table group 73d for setting 4 is read, if the setting value to be used is "5", the role selection table group 73e for setting 5 is read, and if the setting value to be used is "6", the role selection table group 73f for setting 6 is read.

After that, the judgment value acquisition process is executed (step S1303). Figure 35 is a flowchart showing the judgment value acquisition process. If the current game state is the CB state (first CB state ST2 or second CB state ST3) (step S1401: YES), the judgment value counter 74j in the main RAM 74 is set to "1" (step S1402), and then this acquisition process is terminated. Note that the judgment value counter 74j is cleared to "0" when the judgment value acquisition process is started. Therefore, when the process of step S1402 is executed, the value of the judgment value counter 74j becomes "1".

If the current game state is not the CB state (step S1401: NO), the value of the bet number setting counter 74a in the master RAM 74 is added to the judgment value counter 74j (step S1403). In this case, if the value of the bet number setting counter 74a is "2", i.e., if the number of bets in the current game is "2", the value of the judgment value counter 74j becomes "2", and if the value of the bet number setting counter 74a is "3", i.e., if the number of bets in the current game is "3", the value of the judgment value counter 74j becomes "3".

After that, if CB winning data (first CB winning data or second CB winning data) is stored in the main RAM 74 (step S1404: YES), the judgment value counter 74j is incremented by "2" (step S1405), and the acquisition process ends. If CB winning data (first CB winning data or second CB winning data) is not stored in the main RAM 74 (step S1404: NO), the acquisition process ends.

By executing the judgment value acquisition process (FIG. 35) as described above, if the game state is a CB state, the value of the judgment value counter 74j becomes "1", if the game state is a non-internal 2-coin bet state, the value of the judgment value counter 74j becomes "2", if the game state is a non-internal 3-coin bet state, the value of the judgment value counter 74j becomes "3", if the game state is an internal 2-coin bet state, the value of the judgment value counter 74j becomes "4", and if the game state is an internal 3-coin bet state, the value of the judgment value counter 74j becomes "5". As a result, by checking the value of the judgment value counter 74j, it is possible to specify whether the current game state is a CB state, a non-internal 2-coin bet state, a non-internal 3-coin bet state, an internal 2-coin bet state, or an internal 3-coin bet state.

Returning to the explanation of the role selection process (Figure 34), after the judgment value acquisition process is executed in step S1303, the number of selections counter 74k in the main RAM 74 is set to "1" (step S1304). As already explained, the number of selections counter 74k is used to identify which index value IV is the subject of selection in the role selection process. When the number of selections counter 74k is set to "1", the index value IV that is the subject of selection in the role selection process becomes "1".

After that, the PV acquisition process is executed (step S1305). Figure 36 is a flowchart showing the PV acquisition process. First, of the data groups 101a to 101q for IV=1 to 17 in the role selection table group 73a to 73f that have been read into the master RAM 74 in step S1302 of the role selection process (Figure 34), the data groups 101a to 101q that correspond to the value of the lottery number counter 74k in the master RAM 74 are read (step S1501). In this case, if the value of the lottery number counter 74k is X (X=any of 1 to 17), the data groups 101a to 101q for IV=X are read out.

Then, each bit of the game status data 102a-104a in the data group 101a-101q read in step S1501 is shifted one bit to the lower side (i.e., to the right) (step S1502). For example, in the case of the game status data 102a in FIG. 33(a), the data of bit Dm (m = any one of 1 to 7) is shifted to bit D(m-1). In addition, the data of bit D0, which is the lowest bit, is shifted to the carry flag 77 (see FIG. 9) provided in the main MPU 72. Then, it is determined whether the value of the carry flag 77 is "1" (step S1503). In the case of the game status data 102a in FIG. 33(a), if the processing of step S1502 is executed once, the value of the carry flag 77 is "0", and in the case of the game status data 103a in FIG. 33(b), if the processing of step S1502 is executed once, the value of the carry flag 77 is "1".

If the value of the carry flag 77 is "1" (step S1503: YES), the value of the address counter 74l in the main RAM 74 is incremented by 1 (step S1504). As already explained, the address counter 74l is used to identify which address data is being referenced among the point value data 102c, 103c, 104c of the data groups 101a to 101q for IV=1 to 17 that are being referenced. Note that the address counter 74l is cleared to "0" when the processing of step S1501 is executed.

If a negative judgment is made in step S1503, or if the processing of step S1504 is executed, the value of the judgment value counter 74j in the main RAM 74 is decremented by 1 (step S1505). As already explained, a value corresponding to the current game state is set in the judgment value counter 74j in step S1303 of the role selection processing (FIG. 34). Then, it is determined whether the value of the judgment value counter 74j after decrementing by 1 is "0" (step S1506). If the value of the judgment value counter 74j is not "0" (step S1506: NO), the processing of steps S1502 to S1505 is executed again.

If the value of the judgment value counter 74j is "0" (step S1506: YES), it is determined whether the value of the carry flag 77 of the main MPU 72 is "1" (step S1507). If the value of the carry flag 77 is "1" (step S1507: YES), address data corresponding to the current value of the address counter 74l in the main RAM 74 is identified from the point value data 102c-104c in the data group 101a-101q read in step S1501, and the point value PV corresponding to the identified address data is obtained from the point value data 102c-104c (step S1508). The point value PV becomes the point value PV of the index value IV that is currently the target of the lottery. On the other hand, if the value of the carry flag is "0" (step S1507: NO), "0" is grasped as the point value PV of the index value IV that is currently the target of the lottery (step S1509).

As described above, in the PV acquisition process (FIG. 36), the value of the judgment value counter 74j is decremented by 1 in step S1505, and when the value of the judgment value counter 74j after the decrement becomes "0", the process of steps S1507 to S1509 is executed to acquire the point value PV. Therefore, if the gaming state is a CB state, the process of steps S1502 to S1505 is executed once to acquire the point value PV, if the gaming state is a non-internal two-coin bet state, the process of steps S1502 to S1505 is executed twice to acquire the point value PV, and if the gaming state is a non-internal three-coin bet state, the process of steps S1502 to S1505 is executed three times. If the game state is an internal two-coin bet state, the process of steps S1507 to S1509 is executed to obtain the point value PV, if the game state is an internal two-coin bet state, the process of steps S1502 to S1505 is executed four times to obtain the point value PV, if the game state is an internal three-coin bet state, the process of steps S1507 to S1509 is executed five times to obtain the point value PV.

On the other hand, in step S1502, the game status data 102a to 104a are shifted, and if the carry flag 77 of the master MPU 72 is set to "1" as a result of the shift, the address counter 74l of the master RAM 74 is incremented by 1 in step S1504. In the process for acquiring the point value PV in steps S1507 to S1509, if the value of the judgment value counter 74j becomes "0" in step S1506 and the value set in the carry flag 77 in the shift process in the previous step S1502 is "1", the point value PV that is paired with the address data corresponding to the address counter 74l of the master RAM 74 in the point value data 102c to 104c is acquired, and if the value of the carry flag 77 is "0", the point value PV becomes "0".

In the CB state, as described above, when the processing of steps S1502 to S1505 is executed once, the processing of steps S1507 to S1509 is executed to obtain the point value PV. Therefore, in the CB state, when the processing of steps S1502 to S1505 is executed once, if the carry flag 77 is "1", the point value PV corresponding to the first address data is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV becomes "0".

If the game state is a non-internal two-coin bet state, the process of steps S1502 to S1505 is executed twice as described above, and then the process of steps S1507 to S1509 is executed to obtain the point value PV. Therefore, if the game state is a non-internal two-coin bet state, and the process of steps S1502 to S1505 is executed twice, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

If the game state is a non-internal three-coin bet state, the process of steps S1502 to S1505 is executed three times as described above, and then the process of steps S1507 to S1509 is executed to obtain the point value PV. Therefore, if the game state is a non-internal three-coin bet state, and the process of steps S1502 to S1505 is executed three times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

If the game state is an internal two-coin bet state, the process of steps S1507 to S1509 is executed to obtain the point value PV when the process of steps S1502 to S1505 is executed four times as described above. Therefore, if the game state is an internal two-coin bet state, when the process of steps S1502 to S1505 is executed four times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

If the game state is an internal 3-coin bet state, the process of steps S1507 to S1509 is executed to obtain the point value PV when the process of steps S1502 to S1505 is executed five times as described above. Therefore, if the game state is an internal 3-coin bet state, when the process of steps S1502 to S1505 is executed five times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

When the value of the lottery number counter 74k in the main RAM 74 is "1" and the data group 101a for IV=1 is read out in step S1501, the game status data 102a has the lowest bit D0 set to "0" and the second to fifth lowest bits D1 to D4 set to "1" as shown in FIG. 33(a). Therefore, when step S1502 in the PV acquisition process (FIG. 36) is executed once, the value of the carry flag 77 is "0", and when step S1502 is executed two to five times, the value of the carry flag 77 is "1".

In other words, in the CB state, when the process to obtain the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "0", so the point value PV is "0". In the non-internal 2-coin bet state, when the process to obtain the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, the process in step S1504 has been executed once before the process in steps S1507 to S1509 is executed, so the value of the address counter 74l is "1". Therefore, the address data corresponding to the value of the address counter 74l is A(0), and the point value PV of "900" corresponding to that address data is acquired. If the state is a non-internal 3-coin bet state, the carry flag 77 is "1" when the process for acquiring the point value PV of steps S1507 to S1509 is executed, and the value of the address counter 74l is "2" because the process of step S1504 has been executed twice before the process of steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is A(1), and the point value PV of "3000" corresponding to the address data is acquired. If the state is an internal 2-coin bet state, the carry flag 77 is "1" when the process for acquiring the point value PV of steps S1507 to S1509 is executed, and the process of step S1504 has been executed three times before the process of steps S1507 to S1509 is executed, and the value of the address counter 74l is "3". Therefore, the address data corresponding to the value of the address counter 74l is A(2), and the point value PV of "900" corresponding to the address data is acquired. If three coins are bet inside, the carry flag 77 is "1" when the process to obtain the point value PV of steps S1507 to S1509 is executed, and the value of the address counter 74l is "4" because the process of step S1504 has been executed four times before the process of steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is A(3), and the point value PV of "3000" corresponding to that address data is acquired.

When the value of the lottery number counter 74k in the main RAM 74 is "16" and the data group 101p for IV=16 is read out in step S1501, the game status data 102a has all of the least significant to fifth bits D0 to D4 set to "1" as shown in FIG. 33(b). Therefore, when the process for obtaining the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "1".

In other words, in the CB state, when the process for obtaining the point value PV of steps S1507 to S1509 is executed, the carry flag 77 is "1", and the value of the address counter 74l is "1" because the process of step S1504 has been executed once before the process of steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is B (0), and the point value PV of "9000" corresponding to the address data is obtained. In the non-internal 2-coin bet state, when the process for obtaining the point value PV of steps S1507 to S1509 is executed, the carry flag 77 is "1", and the process of step S1504 has been executed twice before the process of steps S1507 to S1509 is executed, and the value of the address counter 74l is "2". Therefore, the address data corresponding to the value of the address counter 74l is B (1), and the point value PV of "5500" corresponding to the address data is obtained. If the state is a three-coin bet state in the non-internal state, the carry flag 77 is "1" when the process for acquiring the point value PV in steps S1507 to S1509 is executed, and the value of the address counter 74l is "3" because the process of step S1504 has been executed three times before the process of steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is B(2), and the point value PV of "9000" corresponding to the address data is acquired. If the state is a two-coin bet state in the internal state, the carry flag 77 is "1" when the process for acquiring the point value PV in steps S1507 to S1509 is executed, and the process of step S1504 has been executed four times before the process of steps S1507 to S1509 is executed, and the value of the address counter 74l is "4". Therefore, the address data corresponding to the value of the address counter 74l is B(3), and the point value PV of "5500" corresponding to the address data is acquired. If three coins are bet inside, the carry flag 77 is "1" when the process to obtain the point value PV of steps S1507 to S1509 is executed, and the value of the address counter 74l is "5" because the process of step S1504 has been executed five times before the process of steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is B(4), and the point value PV of "9000" corresponding to that address data is acquired.

When the value of the lottery number counter 74k in the main RAM 74 is "17" and the data group 101q for IV=17 is read out in step S1501, the game status data 102a has the lowest bit D0, the fourth lowest bit D3, and the fifth lowest bit D4 set to "0", and the second lowest bit D1 and the third lowest bit D2 set to "1" as shown in FIG. 33(c). Therefore, when step S1502 in the PV acquisition process (FIG. 36) is executed once, four times, or five times, the value of the carry flag 77 is "0", and when step S1502 is executed twice or three times, the value of the carry flag 77 is "1".

In other words, in the CB state, when the process to obtain the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "0", so the point value PV is "0". In the non-internal 2-coin bet state, when the process to obtain the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, the process in step S1504 has been executed once before the process in steps S1507 to S1509 is executed, so the value of the address counter 74l is "1". Therefore, the address data corresponding to the value of the address counter 74l becomes C(0), and the point value PV of "30000" corresponding to the address data is acquired. If the state is in a non-internal three-coin bet state, the carry flag 77 is "1" when the process for obtaining the point value PV in steps S1507 to S1509 is executed, and the address counter 74l has a value of "2" because the process in step S1504 has been executed twice before the process in steps S1507 to S1509 is executed. Therefore, the address data corresponding to the value of the address counter 74l is C(1), and the point value PV of "20000" corresponding to the address data is acquired. If the state is in an internal two-coin bet state, the carry flag 77 is "0" when the process for obtaining the point value PV in steps S1507 to S1509 is executed, so the point value PV is "0". If the state is in an internal three-coin bet state, the carry flag 77 is "0" when the process for obtaining the point value PV in steps S1507 to S1509 is executed, so the point value PV is "0".

As described above, in a configuration in which the type of index value IV to which a point value PV of 1 or more is set can differ depending on the game state, the numerical range of the index value IV is not made different depending on each game state, but rather the index value IV is set to a certain range and the type of winning data associated with each index value IV is made the same, while the type of index value IV to which a point value PV of 1 or more is set within that certain range is made different. This makes it possible to simplify the data format, since there is no need to change the numerical range of the index value IV for each game state, or to change the correspondence between the index value IV and the winning data for each game state.

Data groups 101a-101q for IV=1-17 are provided in one-to-one correspondence with the index values IV=1-17, and data for acquiring the point value PV (including "0") in each game state is set in each of the data groups 101a-101q for IV=1-17. This makes it possible to simplify the data structure, as there is no need to prepare a separate lottery table for each game state.

A judgment value corresponding to each game state is calculated, and if that judgment value corresponds to a bit set to "1" in game state data 102a-104a set in each of data groups 101a-101q for IV=1-17, the point value PV corresponding to the bit set to "1" is obtained from point value data 102c-104c of data groups 101a-101q for IV=1-17. This makes it possible to obtain the point value PV corresponding to each game state, even if data groups 101a-101q for IV=1-17 are set to be common to each game state.

Returning to the explanation of the role selection process (FIG. 34), after the PV acquisition process is executed in step S1305, the lottery value DV used when determining whether the role is a win or a loss is set (step S1306). In this lottery value setting process, the point value PV acquired in step S1305 is added to the current lottery value DV to set a new lottery value DV. In the initial lottery value setting process, the value of the first random number (any of 0 to 65535) acquired in step S1301 is set as the current lottery value DV, and the point value PV acquired in step S1305 is added to the value of this first random number to set a new lottery value DV. Note that if the point value PV acquired in step S1305 is "0", the lottery value DV will not change even if the process of step S1306 is executed. In other words, if the point value PV is "0" in the first lottery value setting process, the first random number (any number between 0 and 65535) becomes the lottery value DV as is, and if the point value PV is "0" in the second or subsequent lottery value setting processes, the lottery value DV from the previous lottery value setting process becomes the lottery value DV this time.

After that, a win/loss determination is performed for the index value IV corresponding to the current value of the lottery number counter 74k (step S1307). In the win/loss determination, it is determined whether the lottery value DV exceeds "65535". If it exceeds "65535" (step S1307: YES), a process to obtain winning data is executed (step S1308). Figure 37 is a flowchart showing the process to obtain winning data.

First, by referring to the winning target data 102b-104b of the data group 101a-101q corresponding to the current value in the lottery number counter 74k of the master RAM 74, the winning data corresponding to the currently winning index value IV is grasped (step S1601). If the winning data is CB winning data (step S1602: YES), and if the value of the bet number setting counter 74a of the master RAM 74 is "3" (step S1603: YES), the first CB winning data is stored in the master RAM 74 (step S1604), and if the value of the bet number setting counter 74a is "2" (step S1603: NO), the second CB winning data is stored in the master RAM 74 (step S1605). Also, if the winning data corresponding to the currently winning index value IV is not CB winning data (step S1602: NO), the winning data grasped in step S1601 is stored as it is in the master RAM 74 (step S1606).

Returning to the explanation of the role selection process (FIG. 34), if the selection value DV does not exceed "65535" (step S1307: NO), this means that the role corresponding to the index value IV has not been selected. In such a case, the value of the selection number counter 74k in the main RAM 74 is incremented by 1 (step S1309), and then it is determined whether or not there is a role corresponding to the index value IV, i.e., whether or not there is a selection item for which a win/loss judgment is to be made (step S1310). Specifically, it is determined whether or not the value of the selection number counter 74k incremented by 1 has exceeded the maximum value of "17". If the value of the selection number counter 74k is equal to or less than the maximum value (step S1310: NO), the process returns to step S1305, and the role selection judgment is continued. At this time, in step S1305, the data group 101a-101q corresponding to the value of the lottery number counter 74k after adding 1 is read out to obtain the point value PV, and in step S1306, the lottery value DV used to determine whether the previous role was a hit (i.e., the current lottery value DV) is added to the point value PV newly obtained in step S1305 to obtain a new lottery value DV, and in step S1307, a win/loss determination of the role is made based on the lottery value DV.

When the processing of step S1308 is executed, or when a positive judgment is made in step S1310, it means that the judgment of the winning or losing combination has been completed. In this case, a first stop information setting process is executed to set stop information for reel stop control (step S1311). After that, a first control process for the game area is executed in step S1312, and an advantageous lottery process at the start of the game is executed in step S1313. The processing contents of steps S1311 to S1313 will be explained in detail later.

Then, the stop order notification control process is executed (step S1314). In the stop order notification control process, under the condition that the game state is the pseudo bonus state ST4 or the AT state ST5 described later and the number of bets on the game media is "3", the display control of the dual-purpose display unit 66 is executed so that the stop order of the reels 32L, 32M, and 32R that allows the first bell to be won is notified when any of the index values IV = 1 to 6 is won, and the stop order of the reels 32L, 32M, and 32R that allows the second bell to be won is notified when any of the index values IV = 7 to 9 is won, and a command is sent to the production side MPU 92 so that the notification is executed on the image display device 63.

After that, a process for transmitting a game start command is executed (step S1315). In this transmission process, if any role is won in the current role lottery process (FIG. 34), information corresponding to the winning role, information corresponding to the current game state, and information corresponding to the processing results of steps S1312 and S1313 are set in the game start command, and the game start command is transmitted to the production side MPU 92. The game start command is a command for making the production side MPU 92 recognize that a new game has started, and is a command for making the production side MPU 92 recognize various information determined by the master MPU 72.

When the production side MPU 92 receives a game start command, it grasps various information about the current game from the game start command. The production side MPU 92 then determines the content of the presentation in a manner that corresponds to the various information that it has grasped. It then reads a data table corresponding to the determined content of the presentation from the production side ROM 93 to the production side RAM 94, and executes light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 according to the read data table.

Next, the reel control process executed in step S909 of the normal process (FIG. 25) will be explained with reference to the flowchart in FIG. 38.

First, a rotation start process is performed to start the rotation of each reel 32L, 32M, 32R (step S1701). In the rotation start process, it is confirmed whether a predetermined wait time (specifically, 4.1 seconds) has elapsed since the rotation of the reels 32L, 32M, 32R was started in the previous game, and if not, the process waits until the wait time has elapsed. If the wait time has elapsed, the process resets the wait time for the next game and sets the rotation start information in the motor control storage area provided in the main RAM 74. By performing this process, the stepping motor acceleration process is started in the stepping motor control process of step S504 in the timer interrupt process (FIG. 19), and each reel 32L, 32M, 32R starts to rotate. After that, the process waits until each reel 32L, 32M, 32R rotates at a constant speed at a predetermined rotation speed, and the rotation start process ends. In addition, when the rotation speed of each reel 32L, 32M, and 32R reaches a constant speed, the main MPU 72 lights up the lamps (not shown) of each stop button 42-44 to notify the player that it is possible to issue a stop command.

Then, it is determined whether any of the stop buttons 42 to 44 has been operated (step S1702). If none of the stop buttons 42 to 44 has been operated, the process of step S1702 is repeated until any of the stop buttons 42 to 44 is operated. If it is determined that any of the stop buttons 42 to 44 has been operated, it is determined whether or not the stop button 42 to 44 corresponding to the reels 32L, 32M, and 32R that are spinning has been operated, that is, whether or not a stop command has been generated (step S1703). If a stop command has not been generated, the process returns to step S1702, and the process of step S1702 is repeated until any of the stop buttons 42 to 44 is operated. If a stop command has been generated, a stop command command is sent to the production side MPU 92 (step S1704). The stop command command is a command for causing the production side MPU 92 to recognize which of the stop buttons 42 to 44 has been operated to generate a stop command. When a stop command is sent, the stop control process shown in steps S1705 to S1711 is performed to stop the reels that are spinning.

In the stop control process, the symbol number of the reaching symbol that has reached the base position (specifically, the lower row) at the time the stop buttons 42 to 44 are operated is confirmed (step S1705). Specifically, the symbol number of the reaching symbol that has reached the base position is confirmed based on the number of excitation pulses output from the time the detection signal of the reel index sensor is input. After that, the number of slips of the reels 32L, 32M, and 32R that should be stopped this time is calculated based on the stop information stored in the main RAM 74 (step S1706).

In this slot machine 10, five stop patterns are prepared for stopping each reel 32L, 32M, 32R when the stop buttons 42 to 44 are operated: a stop pattern in which the reaching symbol that has reached the base position is stopped as is, a stop pattern in which the corresponding reel 32L, 32M, 32R is stopped after sliding for one symbol, a stop pattern in which the reel is stopped after sliding for two symbols, a stop pattern in which the reel is stopped after sliding for three symbols, and a stop pattern in which the reel is stopped after sliding for four symbols. Therefore, in step S1706, one of the values "0" to "4" is calculated as the number of slips based on the stop information stored in the main RAM 74.

Then, the calculated slip count is added to the symbol number of the reached symbol, and the symbol number of the stopped symbol that will actually stop at the base position is determined (step S1707). Then, it is determined whether the symbol number of the reached symbol of reels 32L, 32M, and 32R that should be stopped this time is equal to the symbol number of the stopped symbol (step S1708), and if so, a reel stop process is performed to stop the rotation of reels 32L, 32M, and 32R (step S1709). Then, it is determined whether all reels 32L, 32M, and 32R have stopped (step S1710). If all reels 32L, 32M, and 32R have not stopped, a second stop information setting process is performed (step S1711), and the process returns to step S1702.

The stop information here refers to information for making the stop mode of each reel 32L, 32M, 32R correspond to the result of the lottery process (FIG. 34), and by using this stop information, it is possible to calculate the number of slips (specifically, "0" to "4") for the reaching symbol that reaches the base position when each stop button 42 to 44 is stopped. As the stop information, slip number data showing the correspondence between each symbol and the slip number is stored in advance in the main ROM 73 in correspondence with each lottery result and the stop order of each reel 32L, 32M, 32R. However, this is not limited to this, and the slip number data corresponding to each lottery result and the stop order of each reel 32L, 32M, 32R may be configured to be derived during the rotation of the reels 32L, 32M, 32R, etc.

The processes for setting the above stop information include a first stop information setting process executed in step S1311 of the role selection process (FIG. 34) and a second stop information setting process executed in step S1711 of the reel control process (FIG. 38). In the first stop information setting process, the stop information is set according to the result of the role selection process. In the second stop information setting process, the stop information stored in the main RAM 74 in the first stop information setting process or the previous second stop information setting process is changed after some of the reels 32L, 32M, and 32R have stopped. In the second stop information setting process, the stop information is changed based on the set winning data, the stop order of the reels 32L, 32M, and 32R, and the stop results of the stopped reels 32L, 32M, and 32R.

When it is determined in step S1710 that all reels 32L, 32M, and 32R are stopped, a winning determination process is executed in step S1712. In the winning determination process, the type of symbols stopped on the main line ML on each reel 32L, 32M, and 32R is identified. Then, based on the contents of the winning data stored in the main RAM 74, it is determined whether or not the combination of symbols stopped and displayed on the main line ML on each reel 32L, 32M, and 32R is a combination of symbols corresponding to a winning role in the role selection process, and if it is a combination of symbols corresponding to a winning role, a winning role is established and a winning corresponding process is executed. In the winning corresponding process, if the winning is a small role winning, information on the number of game media to be awarded is set in the main RAM 74 so that game media can be awarded in the media awarding process. On the other hand, if the winning is a replay winning, a flag setting process is executed so that a replay setting process is executed in the next start waiting process (FIG. 26).

After executing the winning determination process, a winning result command is sent to the production side MPU 92 (step S1713). The winning result command contains data indicating whether or not a win has been achieved this time, and if a win has been achieved, contains data indicating the type of win.

Next, the response process at the end of play, which is executed in step S912 of the normal process (FIG. 25), will be described with reference to the flowchart in FIG. 39. Note that since the process of step S912 in the normal process (FIG. 25) is executed after the reel control process (step S909), the response process at the end of play is executed after all of the rotations of reels 32L, 32M, and 32R have stopped in one game.

First, CB processing is executed to control the transition and progress of the first CB state ST2 and the second CB state ST3 (step S1801). In the CB processing, if the first CB winning is established, the first CB state flag provided in the main RAM 74 is set to "1" and the first CB winning data stored in the first CB winning data area of the main RAM 74 is cleared. Then, a first CB winning command indicating that the first CB state ST2 has been transitioned to is sent to the production side MPU 92. This causes the game state to become the first CB state ST2. In the first CB state ST2, as already explained, the game is executed only when "3" game media are bet. In the CB processing, if the second CB winning is established, the second CB state flag provided in the main RAM 74 is set to "1" and the second CB winning data stored in the second CB winning data area of the main RAM 74 is cleared. Then, a second CB winning command indicating a transition to the second CB state ST3 is sent to the presentation side MPU 92. This puts the game state into the second CB state ST3. As already explained, in the second CB state ST3, the game is only executed when "2" gaming media has been bet.

In the CB process, if the current game state is the CB state (first CB state ST2 or second CB state ST3), if the first bell is won in the current game, the value of the total award counter provided in the main RAM 74 is incremented by 1. The total award counter is a counter that allows the main MPU 72 to identify the total number of game media awarded in the CB state, and is cleared to "0" when the CB state begins. If the value of the total award counter after incrementing by 1 becomes "30", which is the CB state termination reference number, the CB state flag corresponding to the current CB state is cleared to "0". Then, a CB end command indicating that the current CB state has ended is sent to the production MPU 92.

On the condition that the game is not in the CB state (step S1802: NO), jump to the process corresponding to the current game state (step S1803). Specifically, if the game state is the normal game state ST1, execute the normal process (step S1804), if the game state is the pseudo bonus state ST4, execute the pseudo bonus process (step S1805), if the game state is the AT state ST5, execute the AT process (step S1806), and if the game state is the end preparation state ST6, execute the second control process of the game section (step S1807). In addition, if any of the normal process of step S1804, the pseudo bonus process of step S1805, and the AT process of step S1806 is executed, execute the second control process of the game section (step S1807). In addition, if the game is in the CB state, execute the second control process of the game section (step S1807). The process contents of steps S1804 to S1807 will be explained in detail later.

If the current gaming state is the CB state, a positive judgment is made in step S1802, and the normal processing in step S1804, the pseudo bonus processing in step S1805, and the AT processing in step S1806 are not executed. Therefore, if it is in the CB state, the processing for progressing through the normal gaming state ST1, the processing for progressing through the pseudo bonus state ST4, and the processing for progressing through the AT state ST5 are not executed. On the other hand, even if the current gaming state is the CB state, the second control processing of the gaming section in step S1807 is executed. Therefore, even if it is in the CB state, the processing for progressing through the second section SC2 is executed.

<About game status and game area>
Next, the game states and game intervals will be described. Figure 40 is an explanatory diagram for explaining the game states and game intervals existing in the slot machine 10.

The slot machine 10 has four game states: a normal game state ST1, a first CB state ST2, a second CB state ST3, a pseudo bonus state ST4, an AT state ST5, and a preparation-for-ending state ST6. These game states ST1 to ST6 do not overlap with each other.

The normal gaming state ST1 is a gaming state that is entered by executing the clear process (steps S301 to S307) of the main RAM 74. In addition, when the first CB state ST2 or the second CB state ST3 that occurs in the normal gaming state ST1 ends, or when the end preparation state ST6 ends, the gaming state becomes the normal gaming state ST1. In the normal gaming state ST1, it is possible to play one game regardless of whether the number of bets on gaming media is "3" or "2".

In the normal game state ST1, whether three coins or two coins are bet, the expected net increase in game media in one game (the value obtained by subtracting the "number of game media bet in one game" from the "expected number of game media to be awarded in one game") is less than 1. In addition, in the normal game state ST1, there are a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

The first CB state ST2 is a game state to which the player is shifted when a first CB win occurs when the first CB winning data is stored in the first CB winning data area of the main RAM 74. In the first CB state ST2, one game can be played when the number of bets on gaming media is "3", but one game cannot be played when the number of bets on gaming media is "2". The second CB state ST3 is a game state to which the player is shifted when a second CB win occurs when the second CB winning data is stored in the second CB winning data area of the main RAM 74. In the second CB state ST3, one game can be played when the number of bets on gaming media is "2", but because the bet limit is set to "2", it is not possible to bet "3" gaming media.

The first CB state ST2 and the second CB state ST3 are game states that do not increase the number of game media owned by the player. Furthermore, both the first CB state ST2 and the second CB state ST3 are game states that reduce the number of game media owned by the player at the end of the game state compared to the number of game media owned by the player at the start of the game state.

The pseudo bonus state ST4 is a game state to which a transition is made when the transition condition to the pseudo bonus state ST4 is met in the normal game state ST1. The pseudo bonus state ST4 ends when the remaining number of continued games in the pseudo bonus state ST4 becomes "0" or when the ending condition of the second section SC2 is met. If the pseudo bonus state ST4 ends without the ending condition of the second section SC2 described below being met and the transition condition to the AT state ST5 is not met, a transition to the end preparation state ST6 occurs. Also, if the pseudo bonus state ST4 ends when the ending condition of the second section SC2 described below is met, a transition to the normal game state ST1 occurs.

In the pseudo bonus state ST4, it is possible to play one game regardless of whether the number of bets on the gaming medium is "3" or "2." In the pseudo bonus state ST4, there exist a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

In the pseudo bonus state ST4, if the index value IV is 1 to 6, and the number of bets on gaming media is "3", the stop order of the reels 32L, 32M, and 32R that allows the first bell to be won is announced. In addition, in the pseudo bonus state ST4, if the index value IV is 7 to 9, and the number of bets on gaming media is "3", the stop order of the reels 32L, 32M, and 32R that allows the second bell to be won is announced. When the first bell or the second bell is won, "15" gaming media is awarded. This makes it possible to increase the expected number of gaming media awarded in one game in the pseudo bonus state ST4. In the pseudo bonus state ST4, if three coins are bet, the expected net increase in gaming media in one game is 1 or more, and in the pseudo bonus state ST4, if two coins are bet, the expected net increase in gaming media in one game is less than 1.

The AT state ST5 is a game state to which a transition is made when the transition condition to the AT state ST5 is met in the pseudo bonus state ST4. The AT state ST5 ends when the remaining number of continued games in the AT state ST5 becomes "0" or when the ending condition of the second section SC2 is met. If the AT state ST5 ends without the ending condition of the second section SC2 described below being met, the game state transitions to the end preparation state ST6. Also, if the AT state ST5 ends when the ending condition of the second section SC2 described below is met, the game state transitions to the normal game state ST1.

In the AT state ST5, one game can be played regardless of whether the number of bets on the gaming medium is "3" or "2." In the AT state ST5, there are a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

In the AT state ST5, if the index value IV is 1 to 6, and the number of bets on game media is "3", the stop order of the reels 32L, 32M, and 32R that allows the first bell to be won is announced. In the AT state ST5, if the index value IV is 7 to 9, and the number of bets on game media is "3", the stop order of the reels 32L, 32M, and 32R that allows the second bell to be won is announced. When the first bell or the second bell is won, "15" game media is awarded. This makes it possible to increase the expected number of game media to be awarded in one game in the AT state ST5. In the AT state ST5, when three coins are bet, the expected net increase in game media in one game is 1 or more, and in the AT state ST5, when two coins are bet, the expected net increase in game media in one game is less than 1.

The end preparation state ST6 is a game state to which the player transitions when the pseudo bonus state ST4 ends without the ending conditions of the second section SC2 described below being met and the transition conditions to the AT state ST5 being met. The end preparation state ST6 is also a game state to which the player transitions when the AT state ST5 ends without the ending conditions of the second section SC2 described below being met.

The end preparation state ST6 ends when one game has been played. When the end preparation state ST6 ends, the normal game state ST1 is entered. In the end preparation state ST6, one game can be played whether the number of gaming media bets is "3" or "2". The end preparation state ST6 is a game state in which the expected net increase in gaming media in one game is less than 1 whether three coins or two coins are bet. In addition, the end preparation state ST6 has a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and an internal state in which either the first CB winning data or the second CB winning data is stored in the main RAM 74.

In a configuration in which various game states ST1 to ST6 exist as described above, a game zone is set in addition to these game states ST1 to ST6. A first zone SC1 and a second zone SC2 are set as game zones. In other words, in this slot machine 10, the factors that determine the game situation are the number of game media bets of "2" and "3", the setting values of "1" to "6", various game states ST1 to ST6, and the game zones of the first zone SC1 and the second zone SC2.

The first section SC1 is a section in which an advantageous gaming state (pseudo bonus state ST4 and AT state ST5) is not initiated in which the expected net increase in gaming media in one game (the value obtained by subtracting the "number of gaming media bet in one game" from the "expected number of gaming media awarded in one game") can be 1 or more when the stopping order of reels 32L, 32M, and 32R is notified, which allows the player to win advantageous winnings when different winning combinations are achieved depending on the stopping order of reels 32L, 32M, and 32R, and the advantageous gaming state does not continue. When the clearing process (steps S301 to S307) of the main RAM 74 is executed, the normal gaming state ST1 is entered, and the first section SC1 is entered. Also, when the initialization process of the second section SC2 is executed in the second section SC2, the first section SC1 is entered. The second section SC2 is a section in which the advantageous game state can be started and in which the advantageous game state can be continued.

Figure 41 (a) is an explanatory diagram for explaining the first section SC1 and the second section SC2. As described above, when the clear process (steps S301 to S307) of the main RAM 74 is executed, the first section SC1 is set, and when the initialization process of the second section SC2 is executed, the first section SC2 is set. On the other hand, the second section SC2 is set when a transition opportunity to the second section SC2 occurs based on the lottery process (Figure 34) in the first section SC1. In this case, when a game with a bet number of "3" is executed in the first section SC1, a transition opportunity to the second section SC2 may occur, whereas a transition opportunity to the second section SC2 does not occur even if a game with a bet number of "2" is executed in the first section SC1. Therefore, a player who expects a transition to the second section SC2 in the first section SC1 needs to execute a game with a bet number of "3" instead of executing a game with a bet number of "2".

In the first section SC1, the expected net increase in gaming media in one game is always less than 1, whereas in the second section SC2, the expected net increase in gaming media in one game is not only less than 1, but may also be 1 or greater. Therefore, the second section SC2 is in a more advantageous situation than the first section SC1. Therefore, players will expect to move to the second section SC2 in the first section SC1.

The first section SC1 ends when a transition trigger to the second section SC2 occurs, and transition occurs to the second section SC2. In contrast, the second section SC2 ends when the pseudo bonus state ST4, AT state ST5, or end preparation state ST6 ends and transition occurs to the normal gaming state ST1. When the second section SC2 ends, transition occurs to the first section SC1. In addition, an ending condition is set for the second section SC2 such that either one of the following conditions is met: the total number of games played reaches the upper limit number of games (specifically, 1500 games) as the second section SC2 continues without transition to the first section SC1, or the limited total net increase in the number of gaming media reaches the upper limit net increase in the number of games (specifically, 2400) as the second section SC2 continues without transition to the first section SC1. The limited total net increase in game media refers to the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is calculated by subtracting the total number of game media consumed to play games while the second section SC2 is continuing (0 when no game media is being played) from the total number of game media awarded by games played while the second section SC2 is continuing (0 when no game media is being awarded).

In other words, if the limited total net increase in the number of game media since the start of the second section SC2 reaches the upper limit net increase as a result of the continuation of the second section SC2, the second section SC2 ends and transitions to the first section SC1. Also, if the number of games played since the start of the second section SC2 reaches the upper limit game number as a result of the continuation of the second section SC2, the second section SC2 ends and transitions to the first section SC1. Then, if either of these ending conditions is met, even if the game is in the middle of the pseudo bonus state ST4 or the AT state ST5, the pseudo bonus state ST4 or the AT state ST5 ends in the game in which the ending condition is met, and the second section SC2 ends, transitioning to the first section SC1 and the normal game state ST1. This makes it possible to prevent the second section SC2 from continuing excessively.

As shown in FIG. 40, the normal game state ST1, the first CB state ST2, and the second CB state ST3 can occur in either the first section SC1 or the second section SC2. On the other hand, the pseudo bonus state ST4, the AT state ST5, and the end preparation state ST6 are never occurred in the first section SC1, but only in the second section SC2.

Figure 41 (b) is an explanatory diagram for explaining the contents of each game state ST1 to ST6 in the second section SC2. As already explained, in the normal game state ST1, pseudo bonus state ST4, AT state ST5 and end preparation state ST6, it is possible to execute a game in either a situation where the number of bets on game media is "3" or a situation where it is "2". In the first CB state ST2, it is possible to execute a game only when the number of bets on game media is "3", and in the second CB state ST3, it is possible to execute a game only when the number of bets on game media is "2".

In the normal game state ST1 in the second section SC2, the expected net increase in the game media is less than 1 whether a game with a bet number of "3" is executed or a game with a bet number of "2" is executed. In this case, in the normal game state ST1 in the second section SC2, as described later, a lottery process for transition to the pseudo bonus state ST4 can be executed based on the result of the lottery process (FIG. 34) for the role in each game, but the lottery process for transition is executed in a game with a bet number of "3", but is not executed in a game with a bet number of "2". Also, in the normal game state ST1 in the second section SC2, as described later, the value of the release game number counter provided in the main RAM 74 is decremented by 1 each time one game is executed, and if the value of the release game number counter after the decrement is "0", the transition to the pseudo bonus state ST4 is confirmed, but the decrement of the release game number counter is executed in a game with a bet number of "3", but is not executed in a game with a bet number of "2". Therefore, in the normal game state ST1 in the second section SC2, it is more advantageous for the player to have a game with a bet number of "3" executed than to have a game with a bet number of "2" executed.

In the pseudo bonus state ST4, when a game with a bet number of "3" is executed, the expected net increase in the gaming medium can be 1 or more, whereas when a game with a bet number of "2" is executed, the expected net increase in the gaming medium is less than 1. Therefore, in the pseudo bonus state ST4, it is more advantageous for the player to execute a game with a bet number of "3" than to execute a game with a bet number of "2". In the pseudo bonus state ST4, as described later, a lottery process for transition to the AT state ST5 can be executed based on the result of the lottery process (FIG. 34) for the role in each game, but the lottery process for transition is executed in a game with a bet number of "3", but is not executed in a game with a bet number of "2". Therefore, from this point of view, in the pseudo bonus state ST4, it is more advantageous for the player to execute a game with a bet number of "3" than to execute a game with a bet number of "2".

In the AT state ST5, when a game with a bet number of "3" is executed, the expected net increase value of the gaming medium can be 1 or more, whereas when a game with a bet number of "2" is executed, the expected net increase value of the gaming medium is less than 1. Therefore, in the AT state ST5, it is more advantageous for the player to execute a game with a bet number of "3" than to execute a game with a bet number of "2". In the AT state ST5, as described later, based on the result of the lottery process (FIG. 34) for the role in each game, an add-on lottery process for determining whether or not to increase the number of remaining sets in the AT state ST5, and a lottery process for transition to an add-on period in which the number of remaining sets in the AT state ST5 is likely to increase can be executed, but these add-on lottery processes and transition lottery processes are executed in a game with a bet number of "3", while they are not executed in a game with a bet number of "2". Therefore, from this point of view, it is more advantageous for the player to execute a game with a bet number of "3" in the AT state ST5 than to execute a game with a bet number of "2".

As described above, even if it is advantageous to execute a game with a bet number of "3" in the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2, the number of game media awarded in a game with a bet number of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 is added as the limited total net increase in game media in the second section SC2, and a game with a bet number of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 is added as the total number of games executed by continuing the second section SC2. In other words, even though a game with a bet number of "2" in any of the normal game state ST1, pseudo bonus state ST4, and AT state ST5 in the second section SC2 is disadvantageous to the player, the game contributes to the side that establishes the ending condition of the second section SC2. From this perspective, when the player is in the normal game state ST1, the pseudo bonus state ST4, or the AT state ST5 in the second section SC2, it is more advantageous for the player to have a game with a bet of "3" played than to have a game with a bet of "2" played.

In the second section SC2, the first CB winning may occur and the second CB winning may occur, similar to the first section SC1. If the first CB winning occurs in the second section SC2, the first CB state ST2 occurs in the second section SC2, and the second section SC2 is maintained even when the first CB state ST2 occurs and after the first CB state ST2 ends. Also, if the second CB winning occurs in the second section SC2, the second CB state ST3 occurs in the second section SC2, and the second section SC2 is maintained even when the second CB state ST3 occurs and after the second CB state ST3 ends. As already explained, the first CB state ST2 and the second CB state ST3 are both game states in which the number of game media owned by the player at the end of the game state is less than the number of game media owned by the player at the start of the game state. In other words, the first CB state ST2 and the second CB state ST3 are game states that are disadvantageous to the player. On the other hand, games played in either the first CB state ST2 or the second CB state ST3 in the second section SC2 are added to the total number of games played as the second section SC2 continues. In other words, even though the games played in the first CB state ST2 and the second CB state ST3 are disadvantageous to the player, those games end up contributing to the establishment of the ending condition of the second section SC2. Therefore, if the first CB state ST2 or the second CB state ST3 occurs in the second section SC2, it will be even more disadvantageous to the player.

In the end preparation state ST6, the expected net increase in gaming media is less than 1 whether a game with a bet number of "3" is executed in the second section SC2 or a game with a bet number of "2" is executed, but the second section SC2 ends with the end of the pseudo bonus state ST4 or the AT state ST5, and only one game is executed. Therefore, the game executed in the end preparation state ST6 does not contribute to the limited total net increase in gaming media in the second section SC2, and does not contribute to the total number of games in the second section SC2. However, this is not limited to this, and even a game executed in the end preparation state ST6 may be configured to contribute to the limited total net increase in gaming media in the second section SC2 and also to contribute to the total number of games in the second section SC2.

<CB states ST2 and ST3>
Next, the first CB state ST2 and the second CB state ST3 will be described in detail. Figure 42 (a) is an explanatory diagram for explaining the first CB role (i.e., the index value IV by which the first CB winning data is stored in the main RAM 74) and the second CB role (i.e., the index value IV by which the second CB winning data is stored in the main RAM 74), and Figure 42 (b) is an explanatory diagram for explaining the first CB state ST2 and the second CB state ST3.

As shown in FIG. 42(a), the first CB role can be a winning combination in a game with a bet number of "3", but cannot be a winning combination in a game with a bet number of "2". In a game with a bet number of "3", the first CB role has a winning probability of approximately 1/3.3. However, when the first CB role is in a winning state (i.e., the first CB winning data is stored in the main RAM 74), the second CB role is in a winning state (i.e., the second CB winning data is stored in the main RAM 74), the first CB state ST2, or the second CB state ST3, the first CB role is excluded from the lottery targets in the role lottery process (FIG. 34).

The second CB role can be a winning combination in games with a bet of "2", but cannot be a winning combination in games with a bet of "3". In games with a bet of "2", the probability of winning the second CB role is approximately 1/2.2. However, when the first CB role is in a winning state (i.e., the first CB winning data is stored in the main RAM 74), the second CB role is in a winning state (i.e., the second CB winning data is stored in the main RAM 74), or in the first CB state ST2 or second CB state ST3, the second CB role is excluded from the lottery targets in the role lottery process (Figure 34).

In the winning state of the first CB role, the first CB winning can be achieved in a game with a bet number of "3", but the first CB winning cannot be achieved in a game with a bet number of "2". Therefore, even if a game with a bet number of "2" is played in the winning state of the first CB role and the lottery process for the role (FIG. 34) results in a loss result in which none of the index values IV are won, the first CB winning cannot be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44. Also, even if a game with a bet number of "2" is played in the winning state of the first CB role and the lottery process for the role (FIG. 34) results in an index value IV that may cause a so-called miss, the first CB winning cannot be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44. When a game with a bet number of "3" is played in the winning state of the first CB role and the first CB win is achieved, the first CB state ST2 is entered.

As shown in FIG. 42(b), in the first CB state ST2, it is possible to play a game with a bet number of "3", and it is impossible to play a game with a bet number of 2 or less. In the first CB state ST2, normal replay winning data is stored in the main RAM 74 with a probability of 3/10 in the lottery process for the winning combination in each game (FIG. 34), and when normal replay winning data is stored, if the left stop button 42 is operated at a specified timing, a normal replay winning is achieved regardless of the stopping order of the reels 32L, 32M, and 32R. If the left stop button 42 is not operated at the specified timing, a normal replay winning is not achieved even if normal replay winning data is stored.

In the first CB state ST2, if the winning data for the normal replay is not stored in the main RAM 74 in the lottery process for the winning combination (FIG. 34), or if the winning data for the normal replay is stored in the main RAM 74 but the operation timing of the left stop button 42 is not the specified timing and the normal replay cannot be won, the first bell may be won. In this case, the first bell is won regardless of the stopping order of the reels 32L, 32M, and 32R, but the first bell may not be won depending on the timing of the stop operation of the left stop button 42.

However, this is not limited to the above, and if normal replay winning data is stored in the main RAM 74 in the lottery process for winning combinations (FIG. 34) in the first CB state ST2, a normal replay winning may be achieved without fail regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each of the stop buttons 42 to 44. Also, if normal replay winning data is not stored in the main RAM 74 in the lottery process for winning combinations (FIG. 34) in the first CB state ST2, a first bell winning may be achieved without fail regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each of the stop buttons 42 to 44.

When the first bell wins in the first CB state ST2, "1" gaming medium is awarded. As already explained, in the first CB state ST2, a game can be played only when "3" gaming media are bet. In contrast, the number of gaming media awarded in the game in the first CB state ST2 is "1". The first CB state ST2 ends when "30" gaming media are awarded. Therefore, in the first CB state ST2, it is necessary to generate an event in which "1" gaming medium is awarded in a game played by betting "3" gaming media 30 times. In this case, the number of gaming media owned by the player will decrease by at least 60 from the start to the end of the first CB state ST2. Therefore, the first CB state ST2 is a disadvantageous gaming state for the player.

In addition, in the first CB state ST2, as described above, a normal replay win may occur, but it is also possible that neither a normal replay win nor a first bell win occurs. In this case, if the first CB state ST2 occurs in the second section SC2, the first CB state ST2, which is disadvantageous to the player, will continue for 30 games or more, and the number of games will be added to the total number of games played in the second section SC2.

In the winning state of the second CB role, the second CB winning can be achieved in a game with a bet number of "2", but the second CB winning cannot be achieved in a game with a bet number of "3". Therefore, even if a game with a bet number of "3" is played in the winning state of the second CB role and the lottery process for the role (FIG. 34) results in a loss result in which none of the index values IV are won, the second CB winning cannot be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44. Also, even if a game with a bet number of "3" is played in the winning state of the second CB role and the lottery process for the role (FIG. 34) results in an index value IV that may cause a so-called miss, the second CB winning cannot be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44. When a game with a bet of "2" is played in the winning state of the second CB role and the second CB win is achieved, the second CB state ST3 is entered.

As shown in FIG. 42(b), in the second CB state ST3, it is possible to play a game when the number of bets is "2", and the upper limit number of bets for the gaming medium is "2". In the second CB state ST3, normal replay winning data is stored in the main RAM 74 with a probability of 3/10 in the lottery process for the winning combination in each game (FIG. 34), and when normal replay winning data is stored, if the left stop button 42 is operated at a specified timing, a normal replay win is achieved regardless of the stopping order of the reels 32L, 32M, and 32R. If the left stop button 42 is not operated at the specified timing, a normal replay win is not achieved even if normal replay winning data is stored.

In the second CB state ST3, if the winning data for the normal replay is not stored in the main RAM 74 in the lottery process for the winning combination (FIG. 34), or if the winning data for the normal replay is stored in the main RAM 74 but the operation timing of the left stop button 42 is not the specified timing and the normal replay cannot be won, the first bell may be won. In this case, the first bell is won regardless of the stopping order of the reels 32L, 32M, and 32R, but the first bell may not be won depending on the timing of the stop operation of the left stop button 42.

However, this is not limited to the above, and if normal replay winning data is stored in the main RAM 74 in the lottery process for winning combinations (FIG. 34) in the second CB state ST3, a normal replay winning may be achieved without fail regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each of the stop buttons 42 to 44. Also, if normal replay winning data is not stored in the main RAM 74 in the lottery process for winning combinations (FIG. 34) in the second CB state ST3, a first bell winning may be achieved without fail regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each of the stop buttons 42 to 44.

When the first bell win occurs in the second CB state ST3, "1" gaming medium is awarded. As already explained, in the second CB state ST3, a game can be played only when "2" gaming media are bet. In contrast, the number of gaming media awarded in the game in the second CB state ST3 is "1". The second CB state ST3 ends when "30" gaming media are awarded. Therefore, in the second CB state ST3, it is necessary to generate an event in which "1" gaming medium is awarded in a game executed by betting "2" gaming media 30 times, and in this case, the number of gaming media owned by the player will decrease by at least 30 from the start to the end of the second CB state ST3. Therefore, the second CB state ST3 becomes a disadvantageous gaming state for the player. However, the disadvantageous degree of the second CB state ST3 is lower than that of the first CB state ST2.

In addition, in the second CB state ST3, as described above, a normal replay win may occur, but it is also possible that neither a normal replay win nor a first bell win occurs. In this case, if the second CB state ST3 occurs in the second section SC2, the second CB state ST3, which is disadvantageous to the player, will continue for 30 games or more, and the number of games will be added to the total number of games played in the second section SC2.

In the configuration in which the first CB state ST2 and the second CB state ST3 are set as game states disadvantageous to the player as described above, a game with a bet number of "2" is executed to bring about a winning state of the second CB role and prevent the second CB winning from being established, and then a game with a bet number of "3" is executed, so that as a result of the lottery process (FIG. 34) for the roles in each game, it becomes possible to play without causing a transition to the first CB state ST2 and the second CB state ST3, regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of each stop button 42 to 44. In other words, if a winning state of the second CB role is reached by executing a game with a bet number of "2", the second CB winning will not be established even if the winning state of the second CB role is reached by subsequently executing a game with a bet number of "3". Furthermore, even if a game with the number of bets "3" is executed in the winning state of the second CB role, the first CB role is excluded from the lottery subjects in the role selection process (FIG. 34), so the first CB role does not enter the winning state. Since the first CB role does not enter the winning state, the first CB win is not established, and the game state does not transition to the first CB state ST2. This makes it possible to execute a game with the number of bets "3" while preventing transitions to the first CB state ST2 and the second CB state ST3 from occurring. By executing a game with the number of bets "3", a transition to the second section SC2 may occur as already explained, and a transition to the pseudo bonus state ST4 may occur.

As shown in FIG. 42(a), the probability of winning the second CB role in a game with a bet number of "2" is about 1/2.2, whereas the probability of winning the first CB role in a game with a bet number of "3" is about 1/3.3. In other words, the probability of winning the second CB role is set higher than the probability of winning the first CB role. This makes it possible to reduce the number of games required to win the second CB role when the winning state of the second CB role is reached by playing a game with a bet number of "2" in an amusement hall or the like. On the other hand, even if a game with a bet number of "3" is played before the winning state of the second CB role is reached by mistake, it is possible to make it difficult to win the first CB role because the probability of winning the first CB role is lower than the probability of winning the second CB role.

Note that the configuration is not limited to one in which the probability of winning the second CB role is higher than the probability of winning the first CB role, and may be one in which the probability of winning the first CB role is higher than the probability of winning the second CB role, or one in which the probability of winning the first CB role and the probability of winning the second CB role are the same or approximately the same.

<About the second section SC2>
Next, the second section SC2 will be described. First, the first control process of the game section executed by the main MPU 72 will be described with reference to the flowchart of Fig. 43. The first control process of the game section is executed in step S1312 after the hand lottery process (Fig. 34) has completed the hand winning/losing judgment and before the advantageous lottery process (step S1313) at the start of the game.

First, it is determined whether the second section flag in the main RAM 74 is set to "1" (step S1901). The second section flag is a flag that allows the main MPU 72 to identify whether the gaming section is the second section SC2 or not; when the second section flag is set to "1", it is the second section SC2, and when the value of the second section flag is "0", it is the first section SC1. When the second section flag is set to "1" (step S1901: YES), the processing from step S1902 onwards is not executed. As a result, when it is the second section SC2, the lottery processing for the number of games to be released in step S1906 is not executed.

If the second section flag is not set to "1" (step S1901: NO), it is determined whether the current game state is the first CB state ST2 or the second CB state ST3 (step S1902). If the current game state is the first CB state ST2 or the second CB state ST3 (step S1902: YES), the processing from step S1903 onwards is not executed. As a result, even if it is the first section SC1, if it is the first CB state ST2 or the second CB state ST3, the processing to set it to the second section SC2 in step S1905 and the lottery processing for the number of games to be released in step S1906 are not executed.

If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S1902: NO), the number of bets for the current game is determined to be "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S1903). If the number of bets for the current game is "2" (step S1903: NO), the processing from step S1904 onwards is not executed. As a result, in a game where the number of bets is "2" even if it is the first section SC1, the processing to set it to the second section SC2 in step S1905 and the lottery processing for the number of games to be released in step S1906 are not executed.

If the number of bets for the current game is "3" (step S1903: YES), it is determined whether any index value IV has been won in the current role selection process (Figure 34) (step S1904). If the current role selection process (Figure 34) is a miss (step S1904: NO), the processes from step S1905 onwards are not executed. As a result, even if the first section is SC1, if the role selection process (Figure 34) is a miss, the process of setting the second section SC2 in step S1905 and the lottery process of the number of games to be released in step S1906 are not executed.

If any of the index values IV are selected in the current role selection process (FIG. 34) (step S1904: YES), the second section flag in the main RAM 74 is set to "1", and the number of continued games counter 74c (see FIG. 9) and the total number of wins counter 74d (see FIG. 9) provided in the main RAM 74 are both cleared to "0" (step S1905). Setting the second section flag to "1" results in the second section SC2.

The continued game number counter 74c is a counter that allows the main MPU 72 to determine the number of games that have been played since the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between. When the value of the continued game number counter 74c reaches a value corresponding to the upper limit number of games (specifically, 1500 games) in the second section SC2, the second section SC2 ends at the game that has been reached, even if the pseudo bonus state ST4 or AT state ST5 is in the middle of the state, and the state transitions to the first section SC1 and the normal game state ST1.

The total acquisition counter 74d is a counter for the master MPU 72 to determine the limited total net increase in game media from the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between. As already explained, the limited total net increase in game media is the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined reference value, and the difference is the amount obtained by subtracting the total number of game media consumed to execute games when the second section SC2 is continuing (0 when no game media is being executed) from the total number of game media awarded by games executed when the second section SC2 is continuing (0 when no game media is being awarded). If the value of the total winnings counter 74d reaches a value corresponding to the upper limit of the net increase in number of coins (specifically, 2,400 coins) in the second section SC2, even if the game is in the middle of the pseudo bonus state ST4 or the AT state ST5, the second section SC2 ends in the game in which the value is reached, and the game transitions to the first section SC1, which is the normal game state ST1.

After that, a lottery process for the number of release games is executed (step S1906). The number of release games is a counter for the master MPU 72 to specify the number of games required until the transition to the pseudo bonus state ST4 occurs when the transition to the pseudo bonus state ST4 is not selected. In the lottery process for the number of release games, a lottery table for the number of release games pre-stored in the master ROM 73 is read out, and numerical information is obtained from a lottery counter that is periodically updated in the master RAM 74. The number of release games is then selected by comparing the numerical information obtained from the lottery counter with the lottery table for the number of release games. In this case, any of 50 games, 100 games, 200 games, 300 games, 400 games, 500 games, 600 games, 700 games, and 800 games is selected as the number of release games. In addition, the selection probability of each of these numbers of release games is the same. However, this is not limited to this, and a configuration in which the probability of selecting a number of release games with a large number of games is set high, or a configuration in which the probability of selecting a number of release games with a small number of games is set high may be used. After the lottery process for the number of release games is executed, the number of release games selected in the lottery process for the number of release games is set in a release game number counter provided in the master RAM 74 (step S1907). The release game number counter is a counter for identifying the remaining number of release games in the master MPU 72.

Then, a lighting lottery process for the interval display unit 67 is executed (step S1908). In the lighting lottery process for the interval display unit 67, a lighting lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 are used to determine by lottery whether the interval display unit 67 should be turned on from the beginning when the second interval SC2 is set (i.e., immediately turned on), or whether the interval display unit 67 should be turned on when the pseudo bonus state ST4 is subsequently entered (i.e., waiting to be turned on). In the lottery process for the role in this game (FIG. 34), if the index value IV=1 to 10 is selected, there is a 50% probability that immediate lighting will be selected and a 50% probability that standby lighting will be selected; if the index value IV=11 is selected, there is a 65% probability that immediate lighting will be selected and a 35% probability that standby lighting will be selected; if the index value IV=12 is selected, there is a 62% probability that immediate lighting will be selected and a 38% probability that standby lighting will be selected; if the index value IV=13 is selected, there is an 80% probability that immediate lighting will be selected and a 20% probability that standby lighting will be selected; % probability of waiting for light to be selected, if index value IV=14 is selected, there is a 75% probability of selecting instant light and a 25% probability of waiting for light to be selected, if index value IV=15 is selected, there is a 70% probability of selecting instant light and a 30% probability of waiting for light to be selected, if index value IV=16 is selected, there is a 40% probability of selecting instant light and a 60% probability of waiting for light to be selected, and if index value IV=17 is selected, there is a 30% probability of selecting instant light and a 70% probability of waiting for light to be selected. In this case, the lower the probability of winning in the role selection process (FIG. 34) for an index value IV, the higher the probability of selecting instant light.

If immediate lighting is selected in the lighting lottery process for the section display unit 67 (step S1908) (step S1909: YES), lighting process for the section display unit 67 is executed (step S1910). In the lighting process for the section display unit 67, the section display unit 67 is switched from an off state to a on state. This causes the section display unit 67 to start announcing that it is the second section SC2.

On the other hand, if standby is selected in the lighting lottery process (step S1908) of the section display unit 67 (step S1909: NO), the standby flag in the main RAM 74 is set to "1" (step S1911). The standby flag is a flag that allows the main MPU 72 to identify that the section display unit 67 is waiting to be switched from an off state to a on state in the second section SC2.

Next, the second control process of the play area executed by the main MPU 72 will be described with reference to the flowchart in FIG. 44. The second control process of the play area is executed in step S1807 in the response process at the end of play (FIG. 39). As described above, the response process at the end of play is executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game, and therefore the second control process of the play area is also executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game.

If the second section flag in the main RAM 74 is set to "1" and the current game section is the second section SC2 (step S2001: YES), the state of the flag in the main RAM 74 is checked to determine whether the current game state is the end preparation state ST6 (step S2002). The end preparation state ST6 is a game state entered when the pseudo bonus state ST4 or the AT state ST5 ends without the ending condition of the second section SC2 described below being met, and when the second section SC2 ends when entering the normal game state ST1 thereafter.

If the game is in the end preparation state ST6 (step S2002: YES), it is determined whether the end preparation completion flag provided in the main RAM 74 is set to "1" (step S2003). The end preparation completion flag is a flag for the main MPU 72 to determine whether one game has been played in the end preparation state ST6. In the pseudo bonus processing (step S1805) in the corresponding processing at the time of game end (FIG. 39), if it is determined that the remaining number of continued games in the pseudo bonus state ST4 is 0 games and that the game will transition to the normal game state ST1 after that, a flag is set to set the game to the end preparation state ST6 and the end preparation completion flag is cleared to "0". In addition, in the AT processing (step S1806) in the corresponding processing at the time of game end (FIG. 39), if it is determined that one set will end and the game will transition to the normal game state ST1 in a situation where the remaining number of sets in the AT state ST5 is 0, a flag is set to set the game to the end preparation state ST6 and the end preparation completion flag is cleared to "0".

If the end preparation complete flag is not set to "1" (step S2003: NO), the end preparation complete flag is set to "1" (step S2004), and the processing from step S2005 onwards is executed. If the end preparation complete flag is set to "1" (step S2003: YES), this means that one game has been played in the end preparation state ST6. In this case, processing is executed to end the second section SC2.

Specifically, the initialization process of the second section SC2 is first executed (step S2014). In the initialization process of the second section SC2, the second section flag of the main RAM 74 is cleared to "0". This causes the game section to become the first section SC1. In addition, in the initialization process of the second section SC2, even if the game is in the AT state ST5, the game state is shifted to the normal game state ST1 by clearing various data (including the AT state flag) indicating that the game is in the AT state ST5, including a counter for storing the remaining number of games to be continued in the AT state ST5. Note that even if the game is in the middle of the first CB state ST2 and the second CB state ST3, the initialization process of the second section SC2 is executed, and the second section SC2 is terminated, but the first CB state ST2 and the second CB state ST3 are not terminated and are continued as they are.

After that, if the section display unit 67 is in a lit state, the section display unit 67 is switched from a lit state to an off state (step S2015). This ends the notification on the section display unit 67 that it is the second section SC2. Then, a second section initialization command indicating that the second section SC2 has been initialized is sent to the production side MPU 92 (step S2016). This causes the production side MPU 92 to execute a performance corresponding to the end of the second section SC2.

If the game is not in the end preparation state ST6 (step S2002: NO), or if the processing of step S2004 has been executed, the value of the continued game number counter 74c in the master RAM 74 is incremented by 1 (step S2005). As already explained, the continued game number counter 74c is a counter that allows the master MPU 72 to determine the number of games that have been played since the start of the second section SC2 when the second section SC2 is continued without the first section SC1 in between.

Then, it is determined whether the value of the continued game number counter 74c after adding 1 is equal to or greater than 1500, which is the upper limit number of games (step S2006). If the value of the continued game number counter 74c is equal to or greater than 1500, this means that the ending condition for the second section SC2 has been met. In this case, a positive determination is made in step S2006, and processing is executed in steps S2014 to S2016 to end the second section SC2. The processing contents of steps S2014 to S2016 have already been explained. As a result, the second section SC2 ends and the first section SC1 is entered, and if the AT state ST5 is in the middle of the AT state ST5, the AT state ST5 is forcibly ended and the normal game state ST1 is entered.

If the value of the continued game number counter 74c is less than 1500 (step S2006: NO), it is determined whether any of the first chance replay win, second chance replay win, and normal replay win has been achieved in the current game (step S2007). In this case, whether the number of bets in the current game is "2" or "3", it is subject to the determination in step S2007, and also whether the current game is in any of the game states of the normal game state ST1, the first CB state ST2, the second CB state ST3, the pseudo bonus state ST4, and the AT state ST5.

If no replay win is established (step S2007: NO), the number of bets for the current game is subtracted from the total winnings counter 74d of the main RAM 74 (step S2008). In this case, the number of bets for the current game is determined from the value of the bet number history counter 74f, not the value of the bet number setting counter 74a. As already explained, in the normal process (FIG. 25), the value of the bet number setting counter 74a is set in the bet number history counter 74f at the timing after the rotation of all reels 32L, 32M, 32R in one game is completed and before the corresponding process at the end of the game (step S912) is started. Therefore, the bet number for the current game is set in the bet number history counter 74f at the timing when the second control process (FIG. 44) of the game section is started. In addition, even if a replay win was made in the previous game and the current game corresponds to a replay due to the replay win, the number of bets in the current game (i.e., the value of the bet number history counter 74f) is subtracted from the total win number counter 74d.

As already explained, the total acquisition counter 74d is a counter for the master MPU 72 to determine the limited total net increase in game media from the start of the second section SC2 when the second section SC2 continues without the first section SC1 in between. As already explained, the limited total net increase in game media is the increase in the predetermined difference from the predetermined reference value, where the minimum value of the predetermined difference is the predetermined difference obtained by subtracting the total number of game media consumed to execute games while the second section SC2 is continuing (0 when no game media is being executed) from the total number of game media awarded by games executed while the second section SC2 is continuing (0 when no game media is being awarded).

After that, it is determined whether any of the minor winning combinations that result in the awarding of gaming media in the current game (1st to 9th compensation winning combinations, 1st bell winning combination, 2nd bell winning combination, 1st watermelon winning combination, 2nd watermelon winning combination, and cherry winning combination) has been achieved (step S2009). In this case, whether the number of bets in the current game is "2" or "3", it is subject to the determination in step S2009, and also whether the current game is in any of the game states of normal game state ST1, 1st CB state ST2, 2nd CB state ST3, pseudo bonus state ST4, and AT state ST5, it is subject to the determination in step S2009.

If a positive judgment is made in step S2009, the number of game media awarded in the current game is added to the total acquisition number counter 74d of the main RAM 74 (step S2010). In this case, the number of game media awarded in the current game is determined from the value of the awarded number history counter, not the value of the medium award counter. As already explained, in normal processing (FIG. 25), the value of the medium award counter is set in the awarded number history counter after the rotation of all reels 32L, 32M, and 32R in one game has ended and the medium award processing (step S910) has ended, but before the corresponding processing at the end of the game (step S912) is started. Therefore, the number of game media awarded in the current game is set in the awarded number history counter at the time when the second control processing (FIG. 44) of the play section is started.

If a negative judgment is made in step S2009, or if the processing of step S2010 is executed, it is judged whether the value of the total acquisition number counter 74d in the main RAM 74 is equal to or greater than 0 (step S2011). If the value of the total acquisition number counter 74d is less than 0 (step S2011: NO), the total acquisition number counter 74d is cleared to "0" (step S2012).

As described above, in step S2008, the bet number for the current game is subtracted from the total winnings counter 74d. For example, if no small wins are achieved in the game in the normal game state ST1 immediately after the transition to the second section SC2, the value of the total winnings counter 74d will be less than 0. In this case, by making a negative judgment in step S2011, the total winnings counter 74d is cleared to "0" in step S2012. As a result, when the value obtained by subtracting the "total number of game media consumed to execute games in the state in which the second section SC2 is continuing ("0" when games are not being executed)" from the "total number of game media awarded by games executed in the state in which the second section SC2 is continuing ("0" when no game media is awarded)" is set as the predetermined difference number, the minimum value of the predetermined difference number is set as the predetermined reference value, and the limited total net increase in game media, which is the increase in the predetermined difference number from the predetermined reference value, can be measured using the total winnings counter 74d.

If a positive judgment is made in step S2007, if a positive judgment is made in step S2011, or if the processing of step S2012 is executed, it is judged whether the value of the total winning number counter 74d exceeds the upper limit net increase number of "2400" (step S2013). If the value of the total winning number counter 74d exceeds "2400", it means that the ending condition of the second section SC2 is established. In this case, a positive judgment is made in step S2013, and the processing to end the second section SC2 in steps S2014 to S2016 is executed. The processing contents of steps S2014 to S2016 have already been explained. As a result, the second section SC2 ends and becomes the first section SC1, and if it is in the middle of the AT state ST5, the AT state ST5 is forcibly ended and the normal game state ST1 is entered.

If any replay win is achieved, a positive determination is made in step S2007, and the processing of steps S2008 to S2012 is not executed. In a game in which a replay win is achieved, the game media owned by the player at the start of the game are used to set a bet, but as a benefit from the replay win, the player can replay a new game with the same number of bets as the number of bets in the game in which the replay win was achieved. In other words, the number of game media owned by the player does not change in a game in which a replay win is achieved. In this case, by not executing the processing of steps S2008 to S2012 in a game in which a replay win is achieved, it is possible to omit the execution of the processing for changing the value of the total winnings counter 74d in a game in which the number of game media owned by the player does not change, and it is possible to avoid the execution of unnecessary processing.

On the other hand, even in a game in which a replay win has been achieved, in step S2013, it is determined whether the value of the total winnings counter 74d exceeds the upper limit net increase of coins, which is "2400". As a result, even if the value of the total winnings counter 74d has already exceeded the upper limit net increase of coins, which is "2400", in a game prior to the game in which a replay win has been achieved, but the initialization process for the second section SC2 has not been performed due to noise or other reasons, it is possible to determine that the value of the total winnings counter 74d exceeds the upper limit net increase of coins, which is "2400", in the game in which a replay win has been achieved thereafter, and it is possible to perform the initialization process for the second section SC2.

If a negative determination is made in step S2013, the ending handling process is executed (step S2017). Figure 45 is a flowchart showing the ending handling process.

First, it is determined whether the first ending flag stored in the master RAM 74 is set to "1" (step S2101). The first ending flag is a flag that the master MPU 72 uses to determine whether the number of games played in the second section SC2, which is measured using the continued game counter 74c, is likely to reach the upper limit number of games.

If the first ending flag is not set to "1" (step S2101: NO), it is determined whether the sum of the value of the continued game number counter 74c of the main RAM 74, the value of the AT continuation counter provided in the main RAM 74, the value of the set number counter provided in the main RAM 74, and the value of the initial continued game number (50 games) in one set of the AT state ST5 is equal to or greater than the upper limit game number of the second section SC2 (step S2102). The AT continuation counter is a counter for the main MPU 72 to specify the remaining number of continued games in one set in the AT state ST5. The initial number of continued games in one set of the AT state ST5 is 50 games, and the remaining number of continued games can be increased by the establishment of an additional condition in the middle of the one set. The set number counter is a counter for the main MPU 72 to specify the remaining number of sets in the AT state ST5. As already explained, the upper limit game number of the second section SC2 is set to 1500 games. Note that the upper limit of the number of games in the second section SC2 is not limited to 1500 games, and may be less than 1500 games or more than 1500 games.

If a positive judgment is made in step S2102, the first ending flag is set to "1" (step S2103). When the first ending flag is set to "1", the remaining number of continued games and the remaining number of sets are not added in the AT state ST5, as will be described in detail later. This makes it possible to prevent the remaining number of continued games and the remaining number of sets in the AT state ST5 from being further added in a situation where the ending condition of the second section SC2 is met.

Then, a first ending command is sent to the production side MPU 92 (step S2104). The first ending command includes information on the number of games required until the ending condition of the second section SC2 is met, i.e., information corresponding to the difference between the value of the continued game number counter 74c and the upper limit game number of the second section SC2.

By receiving the first ending command, the production side MPU 92 is able to grasp that the first ending flag is set to "1" in the main side MPU 72. If the production side MPU 92 receives the first ending command when the production has not yet started in the execution mode corresponding to the ending period, it causes the execution mode of the performance in the upper lamp 61, speaker 62 and image display device 63 to become the execution mode corresponding to the ending period. Note that the situation in which the first ending flag is set to "1" basically occurs in the AT state ST5, but can also occur in the first CB state ST2 or the second CB state ST3.

If a positive judgment is made in step S2101, if a negative judgment is made in step S2102, or if the processing of step S2104 is executed, it is judged whether or not the second ending flag provided in the main RAM 74 is set to "1" (step S2105). The second ending flag is a flag for the main MPU 72 to identify that there is a high possibility that the limited total net increase in the number of game media measured using the total acquisition counter 74d will reach the upper limit net increase in the number of game media.

If the second ending flag is not set to "1" (step S2105: NO), the sum of the AT continuation counter value, the set count counter value, and the initial number of continued games in one set in the AT state ST5 (50 games) is multiplied by the expected value of the game media in the AT state ST5, and the sum of the total acquisition counter 74d is added to determine whether the result is equal to or greater than the upper limit net increase in the second section SC2 (step S2106). The expected value of the game media in one game in the pseudo bonus state ST4 and the AT state ST5 is about 5 pieces. As already explained, the upper limit net increase in the second section SC2 is set to 2400 pieces. Note that the upper limit net increase in the second section SC2 is not limited to 2400 pieces, and may be less than 2400 pieces or more than 2400 pieces.

If a positive judgment is made in step S2106, the second ending flag is set to "1" (step S2107). When the second ending flag is set to "1", the remaining number of continued games and the remaining number of sets are not added in the AT state ST5, as will be described in detail later. This makes it possible to prevent the remaining number of continued games and the remaining number of sets in the AT state ST5 from being further added in a situation where the ending condition of the second section SC2 is met.

Then, a second ending command is sent to the production side MPU 92 (step S2108). The second ending command includes information on the limited total net increase in the number of game media required until the ending condition of the second section SC2 is met, i.e., information corresponding to the difference between the value of the total acquisition counter 74d and the upper limit net increase in the number of game media in the second section SC2.

By receiving the second ending command, the presentation side MPU 92 is able to grasp that the second ending flag is set to "1" in the main side MPU 72. If the presentation side MPU 92 receives the second ending command when the presentation has not yet started in the execution mode corresponding to the ending period, it causes the execution mode of the presentation in the upper lamp 61, speaker 62 and image display device 63 to become the execution mode corresponding to the ending period. Note that the situation in which the second ending flag is set to "1" occurs in the AT state ST5, but does not occur in other game states.

<Regarding normal gaming state ST1>
Next, the processing contents in the normal game state ST1 will be described. Fig. 46 is a flow chart showing the advantageous lottery processing at the start of the game executed by the main MPU 72. The advantageous lottery processing at the start of the game is executed in step S1313, which is a process executed after the winning/losing judgment of the winning combination and the first control process (step S1312) of the game area are completed in the lottery process for winning combinations (Fig. 34) and before the stop order notification control process (step S1314).

First, it is determined whether the second section flag in the main RAM 74 is set to "1" (step S2201). As already explained, the second section flag is a flag that allows the main MPU 72 to identify whether the gaming section is the second section SC2 or not; when the second section flag is set to "1", it is the second section SC2, and when the value of the second section flag is "0", it is the first section SC1. If the second section flag is not set to "1" (step S2201: NO), the processing from step S2202 onwards is not executed. As a result, if it is the first section SC1, the processing from step S2207 onwards to transition the gaming state to the pseudo bonus state ST4 is not executed.

If the second section flag is set to "1" (step S2201: YES), and if the current game state is the pseudo bonus state ST4 or the AT state ST5 (step S2202: YES), the processing for the advantageous state at the start of the game is executed (step S2203). The processing for the advantageous state at the start of the game will be explained later.

If the second section flag is set to "1" (step S2201: YES) and the game state is neither the pseudo bonus state ST4 nor the AT state ST5 (step S2202: NO), it is determined whether the current game state is the first CB state ST2 or the second CB state ST3 (step S2204). If the current game state is the first CB state ST2 or the second CB state ST3 (step S2204: YES), the processing from step S2205 onwards is not executed. As a result, even if it is in the second section SC2, if it is the first CB state ST2 or the second CB state ST3, the processing from step S2207 onwards to transition the game state to the pseudo bonus state ST4 is not executed.

If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S2204: NO), the number of bets for the current game is determined to be "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S2205). If the number of bets for the current game is "2" (step S2205: NO), the processing from step S2206 onwards is not executed. As a result, in a game where the number of bets is "2" even if it is in the second section SC2, the processing from step S2207 onwards to transition the game state to the pseudo bonus state ST4 is not executed.

If the number of bets on the current game is "3" (step S2205: YES), it is determined whether the second transition confirmation flag provided in the main RAM 74 is set to "1" (step S2206). The second transition confirmation flag is a flag that the main MPU 72 uses to determine that a transition to the pseudo bonus state ST4 has already been won in the transition lottery process (step S2215) described below. If the second transition confirmation flag is set to "1" (step S2206: YES), the processing from step S2207 onwards is not executed. As a result, in a situation where the transition to the pseudo bonus state ST4 has already been confirmed, the processing from step S2207 onwards to transition the game state to the pseudo bonus state ST4 is not executed.

If the second transition confirmation flag is not set to "1" (step S2206: NO), it is determined whether or not winning data corresponding to a direct hit is stored in the host RAM 74 (step S2207). The winning data corresponding to a direct hit is cherry winning data. That is, if the lottery process for the role in the current game (FIG. 34) shows that the index value IV=13 is a winning combination, a positive determination is made in step S2207. If a positive determination is made in step S2207, a direct hit lottery process is executed (step S2208). In the direct hit lottery process, a direct hit lottery table provided in the host ROM 73 and a lottery counter that is periodically updated in the host RAM 74 are used to determine by lottery whether or not to transition to the pseudo bonus state ST4 at the end of the current game. The probability of a direct hit winning in the direct hit lottery process is arbitrary, but in this slot machine 10, the probability of a direct hit winning is 25%.

If a direct hit lottery process results in a direct hit win (step S2209: YES), the first transition confirmation flag provided in the main RAM 74 is set to "1" (step S2210). The first transition confirmation flag is a flag for the main MPU 72 to identify that a direct hit win has occurred. After that, a freeze counter setting process is executed (step S2211). In this setting process, information on the freeze period corresponding to the direct hit win is set in the freeze counter provided in the main RAM 74. The freeze counter is a counter for the main MPU 72 to identify that the freeze period has been set, and is a counter for the main MPU 72 to identify the remaining period of the freeze period.

The freeze period is a period during which the player's operation on the rotation of the reels 32L, 32M, and 32R, which will be executed based on the result of the lottery process for the winning combination (FIG. 34), is disabled. As already explained, in the normal process (FIG. 25), after the lottery process for the winning combination (step S906) is executed and before the reel control process (step S909) is started, it is determined whether the value of the freeze counter is 1 or more (step S908), and if the value of the freeze counter is 1 or more, the process waits in step S908. The value of the freeze counter is subtracted in the timer subtraction process (step S506) each time the timer interrupt process (FIG. 19) is started. In other words, in this slot machine 10, the freeze period is a period during which the start of the rotation of the reels 32L, 32M, and 32R is forcibly waited for the operation of the start lever 41 to start one game. However, it is not limited to this, and the freeze period may be the period during which operation of the stop buttons 42 to 44 is disabled after the reels 32L, 32M, and 32R start to spin, or the period during which operation of the stop buttons 42 to 44 is disabled after the reels 32L, 32M, and 32R start to spin, during which stop control corresponding to the result of the lottery process for the winning combination (FIG. 34) is executed. The freeze period is specifically set to 30 seconds, but is arbitrary.

Then, the direct hit freeze occurrence flag stored in the main RAM 74 is set to "1" (step S2212). The direct hit freeze occurrence flag is a flag that allows the main MPU 72 to identify that a freeze period has been set as a result of a direct hit win. In addition, a direct hit freeze command is sent to the presentation MPU 92 (step S2213). When the presentation MPU 92 receives the direct hit freeze command, it changes the execution mode of the presentation on the upper lamp 61, speaker 62, and image display device 63 to an execution mode that corresponds to a direct hit win. By checking this presentation, the player can understand that a transition to pseudo bonus state ST4 will occur as a result of a direct hit win.

If a negative judgment is made in step S2207 or if a negative judgment is made in step S2209, it is judged whether or not transition-compatible winning data is stored in the main RAM 74 (step S2214). The transition-compatible winning data is any one of the first watermelon winning data, the second watermelon winning data, the cherry winning data, the first chance replay winning data, and the second chance replay winning data. In other words, if the lottery process for the role in the current game (FIG. 34) results in a win with index value IV=11 to 15, a positive judgment is made in step S2214. If a positive judgment is made in step S2214, a transition lottery process is executed (step S2215).

In the transition lottery process, a transition lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 are used to determine by lottery whether or not to transition to the pseudo bonus state ST4. In the lottery process for the role in this game (FIG. 34), if the first watermelon winning data is stored in the main RAM 74 (if the index value IV=11 is won), there is a 20% probability of winning the transition to the pseudo bonus state ST4; if the second watermelon winning data is stored in the main RAM 74 (if the index value IV=12 is won), there is a 10% probability of winning the transition to the pseudo bonus state ST4; if the cherry winning data is stored in the main RAM 74 (if the index value IV=13 is won), there is a 40% probability of winning the transition to the pseudo bonus state ST4; if the first chance replay winning data is stored in the main RAM 74 (if the index value IV=14 is won), there is a 30% probability of winning the transition to the pseudo bonus state ST4; and if the second chance replay winning data is stored in the main RAM 74 (if the index value IV=15 is won), there is a 20% probability of winning the transition to the pseudo bonus state ST4. In this case, the lower the probability of winning the role selection process (FIG. 34) for an index value IV, the higher the probability of winning the transition to the pseudo bonus state ST4. This makes it possible to increase the advantage of winning an index value IV with a low probability of winning in the role selection process (FIG. 34).

If the transition to the pseudo bonus state ST4 is selected in the transition lottery process (step S2216: YES), the second transition confirmation flag in the master RAM 74 is set to "1" (step S2217). As already explained, the second transition confirmation flag is a flag for the master MPU 72 to identify that the transition to the pseudo bonus state ST4 has already been selected in the transition lottery process (step S2215). In addition, a value corresponding to the number of transition waiting games (specifically, 5 games) is set to the transition waiting counter provided in the master RAM 74 (step S2118). The transition waiting counter is a counter for the master MPU 72 to identify that the number of transition waiting games (specifically, 5 games) has been consumed since the second transition confirmation flag was set to "1". By selecting the transition lottery process (step S2215), not only is the second transition confirmation flag set to "1", but a value corresponding to the number of transition waiting games is set to the transition waiting counter. When the second transition confirmation flag is set to "1", the value of the transition waiting counter is decremented by 1 each time one game is played. When the second transition confirmation flag is set to "1", the value of the transition waiting counter becomes "0", and the game state transitions to the pseudo bonus state ST4. Therefore, a transition to the pseudo bonus state ST4 occurs when the transition waiting number of games is played after a transition win has been made in the transition lottery process (step S2215).

Next, the normal processing executed by the main MPU 72 will be described with reference to the flowchart in FIG. 47. The normal processing is executed in step S1804 in the response processing at the end of play (FIG. 39). As described above, the response processing at the end of play is executed after all reels 32L, 32M, and 32R have stopped spinning in one game, so the normal processing is also executed after all reels 32L, 32M, and 32R have stopped spinning in one game. Note that, as already explained, in the response processing at the end of play (FIG. 39), if the first CB state ST2 or the second CB state ST3 is selected, a positive determination is made in step S1802 and the normal processing (step S1804) is not executed.

If the second section flag in the main RAM 74 is set to "1" and the current play section is the second section SC2 (step S2301: YES), it is determined whether the first transition confirmation flag in the main RAM 74 is set to "1" (step S2302). If a direct hit win has occurred in the direct hit lottery process (step S2208) executed at the start of the current game, the first transition confirmation flag is set to "1".

If the first transition confirmation flag is set to "1" (step S2302: YES), the first start setting process is executed (step S2303). In the first start setting process, the pseudo bonus state flag provided in the main RAM 74 is set to "1". In addition, in the first start setting process, a value corresponding to 100 games is set in the pseudo bonus continuation counter provided in the main RAM 74 as the initial number of continued games in the pseudo bonus state ST4. In addition, in the first start setting process, the AT transition confirmation flag indicating that it is confirmed that the transition to the AT state ST5 will occur after the end of the pseudo bonus state ST4 is set to "1". In other words, if a direct hit is won in the direct hit lottery process (step S2208), not only does a transition to the pseudo bonus state ST4 occur, but it is also confirmed that the transition to the AT state ST5 will occur after the end of the pseudo bonus state ST4. The pseudo bonus state flag is a flag that allows the main MPU 72 to determine whether the game state is in the pseudo bonus state ST4, and the pseudo bonus continuation counter is a counter that allows the main MPU 72 to determine the remaining number of continued games in the pseudo bonus state ST4. The AT transition confirmation flag is a flag that allows the main MPU 72 to determine that the AT state ST5 will occur after the pseudo bonus state ST4 ends. After that, the first output start flag provided in the main RAM 74 is set to "1" (step S2304). The first output start flag is a flag that allows the main MPU 72 to determine that a situation exists in which an external output corresponding to the start of the pseudo bonus state ST4 should be executed.

If the first transition confirmation flag is not set to "1" (step S2302: NO), the bet number for the current game is determined to be "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S2305). If the bet number for the current game is "2" (step S2305: NO), the processing from step S2306 onwards is not executed. As already explained, in the processing from step S2306 onwards, the processing is executed to subtract the number of games required to transition to the pseudo bonus state ST4 as one game is played, and if the transition condition to the pseudo bonus state ST4 is established as the game is played, the processing is executed to transition to the pseudo bonus state ST4. In this case, if a game with the bet number of "2" is played, the processing from step S2306 onwards is not executed, so that even if a game with the bet number of "2" is played, it is possible to prevent this from being a factor in approaching the transition to the pseudo bonus state ST4.

If the number of bets on the current game is "3" (step S2305: YES), it is determined whether the second transition confirmation flag in the master RAM 74 is set to "1" (step S2306). As already explained, the second transition confirmation flag is a flag that allows the master MPU 72 to determine whether or not a transition has been won in the transition lottery process (step S2215).

If the second transition confirmation flag is set to "1" (step S2306: YES), the value of the transition waiting counter in the master RAM 74 is decremented by 1 (step S2307). As already explained, the transition waiting counter is a counter for the master MPU 72 to determine that the number of transition waiting games (specifically, 5 games) has been played since the second transition confirmation flag was set to "1". If the value of the transition waiting counter after decrementing by 1 is "0" (step S2308: YES), the second start setting process is executed (step S2309). As will be described in detail later, the second start setting process executes a process for transitioning to the pseudo bonus state ST4. After that, the first output start flag provided in the master RAM 74 is set to "1" (step S2310). The first output start flag is a flag for the master MPU 72 to determine that it is a situation in which an external output corresponding to the start of the pseudo bonus state ST4 should be executed.

If the second transition confirmation flag is not set to "1" (step S2306: NO), the value of the release game number counter in the main RAM 74 is subtracted by 1 (step S2311). The release game number counter is a counter for the main MPU 72 to identify the remaining release game number, which is the number of games required to transition to the pseudo bonus state ST4 in a situation where neither the first nor second transition confirmation flag in the main RAM 74 is set to "1". When the game zone transitions from the first zone SC1 to the second zone SC2, the release game number is set to the release game number counter. If the value of the release game number counter after subtracting 1 is "0" (step S2312: YES), the second start setting process is executed (step S2309). Details will be described later, but in the second start setting process, a process for transitioning to the pseudo bonus state ST4 is executed. After that, the first output start flag provided in the main RAM 74 is set to "1" (step S2310). The first output start flag is a flag that allows the main MPU 72 to identify a situation in which an external output corresponding to the start of the pseudo bonus state ST4 should be executed.

When the process of step S2310 is executed, it is determined whether the standby flag for lighting in the main RAM 74 is set to "1" (step S2313). As already explained, the standby flag is a flag for the main MPU 72 to identify that the section display unit 67 is waiting to be switched from an off state to an on state in the second section SC2. When the standby flag for lighting is set to "1" (step S2313: YES), lighting process of the section display unit 67 is executed (step S2314). In the lighting process of the section display unit 67, the section display unit 67 is switched from an off state to an on state. This causes the section display unit 67 to start announcing that it is the second section SC2. When the process of step S2314 is executed, the standby flag for lighting is cleared to "0".

When a transition to pseudo bonus state ST4 occurs while the lighting standby flag is set to "1" as described above, the section display unit 67 is switched from an unlit state to a lit state. The pseudo bonus state ST4 is a gaming state in which the expected net increase in gaming media in one game (the value obtained by subtracting the "number of gaming media bet in one game" from the "expected number of gaming media to be awarded in one game") can be 1 or more. In other words, the section display unit 67 can be maintained in an unlit state even when the second section SC2 is entered, but is reliably switched to a lit state when the gaming state transitions to a gaming state in which the expected net increase in gaming media can be 1 or more. This makes it possible to notify the manager of the gaming hall that a gaming state in which the expected net increase in gaming media can be 1 or more is in question.

<Regarding the second initiation setting process>
Next, the second initiation setting process executed in step S2309 of the normal process (FIG. 47) will be described.

In the second start setting process, the transition to the current pseudo bonus state ST4 triggers an AT transition lottery process at the start. If the AT transition lottery process at the start results in an AT transition win, the game will transition to the AT state ST5 after the current pseudo bonus state ST4 ends. In addition, in the second start setting process, the initial number of continuing games in the pseudo bonus state ST4 to be transitioned to this time is determined by lottery. In addition, in the pseudo bonus state ST4, the AT transition lottery process is executed when a transition lottery trigger occurs in each game, and if the AT transition lottery process results in an AT transition win, the game will transition to the AT state ST5 after the current pseudo bonus state ST4 ends. In this case, in the second start setting process, the probability of winning the AT transition lottery process in the AT transition lottery process in the pseudo bonus state ST4 to be transitioned to this time is determined by lottery.

Figure 48 (a) is an explanatory diagram for explaining the selection probability of the game number mode that determines the initial number of continuing games in pseudo bonus state ST4, and Figure 48 (b) is an explanatory diagram for explaining the selection probability of the winning rate mode that determines the probability of winning the AT transition in the AT transition lottery process for each game in pseudo bonus state ST4.

As shown in FIG. 48(a), multiple types of game number modes are set, specifically, a first game number mode in which the initial number of continuous games in the pseudo bonus state ST4 is 20 games, a second game number mode in which it is 30 games, a third game number mode in which it is 40 games, a fourth game number mode in which it is 50 games, and a fifth game number mode in which it is 60 games are set. When the setting value of the object to be used is "1", the first to fourth game number modes are selectable, and the fifth game number mode is not selectable. In addition, the selection probability of each of the first to fourth game number modes is the same at 25%. When the setting value of the object to be used is "2", the first to fourth game number modes are selectable, and the fifth game number mode is not selectable. In addition, the selection probability of each of the third game number mode and the fourth game number mode is higher than the selection probability of each of the first game number mode and the second game number mode. When the setting value of the object to be used is "3", the first to fourth game number modes are selectable, and the fifth game number mode is not selectable. Also, a mode with a larger initial number of continuous games has a higher selection probability than a mode with a smaller number of games. When the setting value of the object to be used is "4", the first to fourth game number modes are selectable, and the fifth game number mode is not selectable. Also, the third game number mode and the fourth game number mode are each selected more likely than the first game number mode and the second game number mode. When the setting value of the object to be used is "5", the first to fifth game number modes are selectable. Also, the third game number mode and the fourth game number mode are selected most likely, the first game number mode and the second game number mode are selected next, and the fifth game number mode is selected least likely. When the setting value of the object to be used is "6", the first to fifth game number modes are selectable. Also, the selection probability of each of the first to fifth game number modes is the same at 20%.

With the above configuration, the expected value of the initial number of continuing games in pseudo bonus state ST4 increases as the setting value increases. This makes it possible to create advantages and disadvantages depending on the setting value for the initial number of continuing games in pseudo bonus state ST4. Furthermore, when compared with the same game number mode, the selection probability may differ depending on the setting value. Furthermore, the fifth game number mode is not selectable if the setting value is 4 or less, but is selectable if the setting value is 5 or more.

As shown in FIG. 48(b), multiple types of winning rate modes are set. Specifically, the first winning rate mode has an expected value of about 20% of the probability of winning the AT transition in the current pseudo bonus state ST4, the second winning rate mode has an expected value of about 30%, the third winning rate mode has an expected value of about 40%, the fourth winning rate mode has an expected value of about 60%, and the fifth winning rate mode has an expected value of about 75%. When the setting value of the target to be used is "1", the first to fifth winning rate modes are available for selection. Also, the selection probability of each of the first to fifth winning rate modes is the same at 20%. When the setting value of the target to be used is "2", the first to fifth winning rate modes are available for selection. Also, the selection probability of the third winning rate mode is the highest, the selection probability of the fourth winning rate mode and the fifth winning rate mode is the next highest, and the selection probability of the first winning rate mode and the second winning rate mode is the lowest. When the setting value of the target to be used is "3", the first to fifth winning rate modes are available for selection. Also, the fourth winning rate mode has the highest probability of being selected, the third and fifth winning rate modes have the next highest probability of being selected, and the first and second winning rate modes have the lowest probability of being selected. When the setting value of the target to be used is "4", the first to fifth winning rate modes are the selection targets. Also, the fifth winning rate mode has the highest probability of being selected, the fourth winning rate mode has the next highest probability of being selected, and the first, second and third winning rate modes have the lowest probability of being selected. When the setting value of the target to be used is "5", the first to fifth winning rate modes are the selection targets. Also, the fifth winning rate mode has the highest probability of being selected, the third and fourth winning rate modes have the next highest probability of being selected, and the first and second winning rate modes have the lowest probability of being selected. When the setting value of the target to be used is "6", the second to fifth winning rate modes are the selection targets, and the first winning rate mode is not the selection target. Also, the selection probabilities of each of the second to fifth game number modes are the same at 25%.

With the above configuration, the expected probability of winning the AT transition in the pseudo bonus state ST4 increases as the setting value increases. This makes it possible to create advantages and disadvantages in the probability of winning the AT transition in the pseudo bonus state ST4 depending on the setting value. Furthermore, when compared with the same winning rate mode, the selection probability may differ depending on the setting value. Furthermore, the first winning rate mode is not selectable if the setting value is "6", but is selectable if the setting value is 5 or less.

In the second start setting process, as described above, the AT transition lottery process at the start, the lottery process for the number of games mode, and the lottery process for the winning rate mode are executed. In these lottery processes, a random number is obtained from the second random number circuit 76 of the main MPU 72, and the lottery is executed using the obtained random number. Figure 49 (a) is an explanatory diagram for explaining the latch area 111 for latching the second random number updated in the second random number circuit 76.

The latch area 111 is provided in the second random number circuit 76. As already explained, the second random number circuit 76 sequentially updates the second random number within a predetermined numerical range based on the clock signal (specifically, 0.1 nanosecond period) output from the clock circuit. When the second random number updated in the second random number circuit 76 is used by the main MPU 72, a latch signal is sent from the main MPU 72 to the second random number circuit 76. When the second random number circuit 76 receives the latch signal, it stores the second random number at that time in the latch area 111. Since the second random number updated in the second random number circuit 76 has a data capacity of 2 bytes, the latch area 111 also has a data capacity of 2 bytes accordingly. The upper byte of the second random number is stored in the upper area 111a of the latch area 111, and the lower byte of the second random number is stored in the lower area 111b of the latch area 111.

When the start-time AT transition lottery process is executed in the second start setting process, the second random number stored in the latch area 111 is used as is based on the latch signal sent from the main MPU 72 to the second random number circuit 76. In other words, the random number used in the start-time AT transition lottery process has a data capacity of 2 bytes, and the numerical range of the random number is 0 to 65535. For example, if the second random number stored in the latch area 111 is "10110011" or "10110101" in binary as shown in FIG. 49(b), this numerical value is used as the random number in the start-time AT transition lottery process.

When the lottery process for the number of games mode is executed in the second start setting process, only the upper byte stored in the upper area 111a of the second random number stored in the latch area 111 based on the latch signal sent from the main MPU 72 to the second random number circuit 76 is used. In other words, the random number used in the lottery process for the number of games mode has a data capacity of 1 byte, and the numerical range of the random number is 0 to 255. For example, if the second random number stored in the latch area 111 is "10110011" and "10110101" in binary as shown in FIG. 49(b), the upper byte "10110011" is used as the random number in the lottery process for the number of games mode as shown in FIG. 49(c).

When the lottery process of the winning rate mode is executed in the second start setting process, only the lowest 7 bits of the upper byte stored in the upper area 111a of the second random number stored in the latch area 111 based on the latch signal sent from the main MPU 72 to the second random number circuit 76 are used. In other words, the random number used in the lottery process of the winning rate mode has a data capacity of 7 bits, and the numerical range of the random number is 0 to 127.

When obtaining the 7-bit random number, first, a second random number is stored in the latch area 111 based on a latch signal sent from the main MPU 72 to the second random number circuit 76. After that, the upper byte random number stored in the upper area 111a of the latch area 111 is obtained in a register of the main MPU 72. Then, the most significant bit of the upper byte random number is cleared to "0". This makes it possible to obtain a 7-bit random number using the 2-byte second random number latched in the second random number circuit 76.

For example, if the second random number stored in the latch area 111 is "10110011" or "10110101" in binary as shown in FIG. 49(b), the upper byte "10110011" is acquired in the register of the master MPU 72 as shown in FIG. 49(c). Then, the most significant bit of the acquired 1-byte information is cleared to "0", so that the random number information stored in the register of the master MPU 72 becomes "00110011" as shown in FIG. 49(d). This random number information is used in the lottery process in the winning rate mode. In this case, the random number information is treated as 1-byte information "00110011", but since the most significant bit is forcibly cleared to "0", it is the lower 7 bits excluding the most significant bit that actually contribute to generating the numerical range of the random number.

Here, a configuration is also possible in which the random number information is stored as 7-bit information. However, in this case, it becomes impossible to handle the random number information as byte-based information, making handling of the information complicated. In contrast, even if it actually takes 7 bits to generate the numerical range of the random number, since the random number information is 1 byte, it becomes possible to handle the random number information as byte-based information. Also, even if the random number information is configured as 1 byte in this way, the most significant bit is cleared to "0", so it becomes possible to prevent the numerical range of the random number from exceeding the range of 0 to 127, which corresponds to 7 bits.

As described above, by using the 2-byte second random number updated in the second random number circuit 76, it is possible to obtain multiple types of random numbers with different numerical ranges. This makes it possible to reduce the number of random number circuits and simplify the hardware configuration compared to a configuration in which different random number circuits are individually provided to correspond to each of the different numerical ranges.

Figure 50 is a flowchart showing the second start setting process executed in step S2309 of the normal process (Figure 47).

First, a second random number is obtained (step S2401). Specifically, a latch signal is sent to the second random number circuit 76, causing information about the second random number after the most recent update in the second random number circuit 76 to be stored in the latch area 111. Then, when the second random number is stored in the latch area 111, the second random number is obtained in a register of the master MPU 72.

Then, the start-time AT transition lottery table is read from the main ROM 73 (step S2402). In the start-time AT transition lottery table, a numerical value included in the numerical range of the second random number from 0 to 65535 is set to either an AT transition winning or a transition losing numerical range. Specifically, the probability of an AT transition winning is set to 10%.

After that, the start-time AT transition lottery process is executed (step S2403). In the start-time AT transition lottery process, the second random number acquired in step S2401 is compared with the start-time AT transition lottery table read in step S2402. As a result, if the AT transition is won (step S2404: YES), the AT transition confirmation flag in the main RAM 74 is set to "1" (step S2405). As already explained, the AT transition confirmation flag is a flag that the main MPU 72 uses to determine that the AT state ST5 will occur after the pseudo bonus state ST4 ends.

If a negative judgment is made in step S2404 or if the processing of step S2405 is executed, the upper byte of the second random number is obtained from the second random number circuit 76 (step S2406). Specifically, a latch signal is sent to the second random number circuit 76 to store the second random number information after the most recent update in the second random number circuit 76 in the latch area 111. Then, the upper byte information stored in the upper area 111a of the latch area 111 is obtained in a register of the main MPU 72.

Here, in this second start setting process, a latch signal is sent in step S2401 so that the second random number is latched in the second random number circuit 76, and a latch signal is sent in step S2406 so that the second random number is latched in the second random number circuit 76. In this case, the second random number is sequentially updated in the second random number circuit 76 based on the clock signal output from the clock circuit, and this update period is 0.1 nanoseconds. The period from when the process of step S2401 is executed to when the process of step S2406 is executed is longer than the period required for the second random number, which is updated every 0.1 nanoseconds as described above, to complete one cycle in the numerical range of 0 to 65535. In addition, the period from when the process of step S2401 is executed to when the process of step S2406 is executed varies within a predetermined period range in each of the cases where the process of step S2405 is executed and where the process of step S2405 is not executed, and this variation is large in relation to the update period of the second random number. Therefore, even if a latch signal is sent to the second random number circuit 76 in each of steps S2401 and S2406 during one processing round of the second start setting process (FIG. 50), no regularity is created between the second random number stored in the latch area 111 by sending the latch signal in step S2401 and the second random number stored in the latch area 111 by sending the latch signal in step S2406.

Then, the lottery number counter 74k in the master RAM 74 is set to "1" (step S2407). As already explained, the lottery number counter 74k is used to identify which index value IV is the subject of the lottery in the lottery process for the role (FIG. 34), but in the lottery process for the game count mode, it is used by the master MPU 72 to identify which of the first to fifth game count modes is the subject of the lottery process. In the lottery process for the number of games mode, if the value of the lottery number counter 74k is "1", the second number of games mode is the selection target of the lottery process, if the value of the lottery number counter 74k is "2", the third number of games mode is the selection target of the lottery process, if the value of the lottery number counter 74k is "3", the fourth number of games mode is the selection target of the lottery process, and if the value of the lottery number counter 74k is "4", the fifth number of games mode is the selection target of the lottery process. If the value of the lottery number counter 74k is not 1 to 4, the first number of games mode is selected.

Then, the start address for the game count mode lottery is set in an address reference register in the master MPU 72 (step S2408). The start address is the start address of the game count mode lottery table 112 provided in the master ROM 73. Figure 51 (a) is an explanatory diagram for explaining the game count mode lottery table 112.

In the game count mode lottery table 112, a plurality of address information D(1)-D(24) are set, and a judgment value LV is set in one-to-one correspondence with the plurality of address information D(1)-D(24). Each address information D(1)-D(24) has a data capacity of 1 byte and is a consecutive number. The first range of address information D(1)-D(4) corresponds to a set value of "1", the second range of address information D(5)-D(8) corresponds to a set value of "2", the third range of address information D(9)-D(12) corresponds to a set value of "3", the fourth range of address information D(13)-D(16) corresponds to a set value of "4", the fifth range of address information D(17)-D(20) corresponds to a set value of "5", and the sixth range of address information D(21)-D(24) corresponds to a set value of "6". In other words, if the set value is n (n is an integer between 1 and 6), the set value of n corresponds to the range of address information D((n-1) x 4 + 1) to D((n-1) x 4 + 4).

In addition, within the range of address information corresponding to each setting value, the first address information D(1), D(5), D(9), D(13), D(17), and D(21) are associated with the determination value LV of the second game number mode, the second address information D(2), D(6), D(10), D(14), D(18), and D(22) are associated with the determination value LV of the third game number mode, the third address information D(3), D(7), D(11), D(15), D(19), and D(23) are associated with the determination value LV of the fourth game number mode, and the last address information D(4), D(8), D(12), D(16), D(20), and D(24) are associated with the determination value LV of the fifth game number mode. In other words, if the set value is n (n is an integer between 1 and 6), the determination value LV for the mth game count mode (m is an integer between 2 and 4) is associated with the address information D ((n-1) x 4 + (m-1)).

In a configuration in which the probability of selecting each game number mode differs depending on the setting value being used, the game number mode selection table 112 is set with a range of address information D(0) to D(24) depending on each setting value, and furthermore, within the range of address information D(0) to D(24) for each setting value, the allocation order of the second to fifth game number modes is common to each setting value. As a result, in a configuration in which the number of tables is reduced by providing one game number mode selection table 112 corresponding to all setting values rather than providing a different table for each setting value, when the judgment value LV corresponding to the combination of the setting value being used and the game number mode being selected is read from the game number mode selection table 112, the judgment value LV can be read according to certain rules.

For example, the determination value LV set in the address information D(1) is "64", and the range of random numbers in the lottery process for the game count mode is 0 to 255, so the probability of selecting the second game count mode when the set value is "1" is 25% as shown in FIG. 48(a). For example, the determination value LV set in the address information D(8) is "0", so the probability of selecting the fifth game count mode when the set value is "2" is 0% as shown in FIG. 48(a). As already explained, if the lottery process for the game count mode fails, the first game count mode will be selected regardless of the set value, so the determination value LV corresponding to the first game count mode is not set in the game count mode lottery table 112.

Returning to the explanation of the second start setting process (Figure 50), as already explained in step S2408, the start address of the game count mode selection table 112 is set in a register for address reference in the master MPU 72. In this case, the game count mode selection table 112 is read from the master ROM 73 to the master RAM 74.

Then, the LV acquisition process is executed (step S2409). Figure 52 is a flowchart showing the LV acquisition process.

First, the setting value information to be used is read from the setting value storage area of the main RAM 74, and the read setting value information is set in the B register provided in the main MPU 72 (step S2501). After that, the information of the lottery number counter 74k in the main RAM 74 is read, and the read information is set in the C register provided in the main MPU 72 (step S2502). Then, the offset value of the address information is calculated by executing the calculation (B-1) x 4 + C (step S2503).

Then, the offset value of the address information calculated in step S2503 is added to the start address set in step S2408 of the second start setting process (FIG. 50) (step S2504). Then, the judgment value LV corresponding to the target address of the addition result in step S2504 is read from the game count mode selection table 112 (step S2505). As a result, the judgment value LV corresponding to the combination of the setting value to be used and the game count mode to be selected is read from the game count mode selection table 112.

Returning to the explanation of the second start setting process (FIG. 50), after the judgment value LV is acquired in step S2409, the lottery value JV used to determine the success or failure of the game number mode to be selected is set (step S2410). In this process, the judgment value LV acquired in step S2409 is added to the current lottery value JV to set a new lottery value JV. In the first process of step S2410 after the processes of steps S2406 to S2408 are executed, the value of the 1-byte random number information (any of 0 to 255) acquired in step S2406 is set as the current lottery value JV, and the judgment value LV acquired in step S2409 is added to this 1-byte random number information to set a new lottery value JV. Note that if the judgment value LV acquired in step S2409 is "0", the lottery value JV does not change even if the process of step S2410 is executed. In other words, if the judgment value LV is "0" in the first setting process, the 1-byte random number information (any value between 0 and 255) becomes the lottery value JV as is, and if the judgment value LV is "0" in the second or subsequent setting processes, the lottery value JV from the previous setting process becomes the lottery value JV this time.

Then, a win/loss judgment is performed for the game number mode corresponding to the current value of the lottery number counter 74k (step S2411). In this win/loss judgment, it is judged whether the lottery value JV exceeds "255". If it does not exceed "255" (step S2411: NO), it means that the game number mode corresponding to the current value of the lottery number counter 74k has been missed. In this case, after adding 1 to the value of the lottery number counter 74k in the main RAM 74 (step S2412), it is judged whether the game number mode to be judged for win/loss still exists (step S2413). Specifically, if the value of the lottery number counter 74k to which 1 has been added is not "5" (step S2413: NO), the process returns to step S2409 and the win/loss judgment of the game number mode is continued. At this time, in the LV acquisition process in step S2409 (FIG. 52), the set value set as the target to be used is the same value, but the value of the lottery number counter 74k is a value that is added by 1 to the value at the time of the previous execution of this acquisition process. Therefore, in step S2503 of the LV acquisition process (FIG. 52), the offset value of the address information acquired in the previous main acquisition process is increased by 1 to calculate the offset value of the current address information, and the judgment value LV corresponding to the address information D(0) to D(24) that is one address after the address information D(0) to D(24) that was the reference target in the previous main acquisition process is acquired. Then, using the newly acquired judgment value LV, a new lottery value JV is calculated in step S2410, and it is determined whether the calculated lottery value JV exceeds "255" to determine whether the game number mode corresponding to the current value of the lottery number counter 74k is correct.

If the lottery value JV exceeds "255" (step S2411: YES), this means that the game number mode corresponding to the current value of the lottery number counter 74k has been won. Also, if the lottery value JV does not exceed "255" (step S2411: NO) and the value of the lottery number counter 74k after adding 1 is "5" (step S2413: YES), this means that none of the second to fifth game number modes have been won, and in this case, this means that the first game number mode has been won. In these cases, a game number storage process is executed (step S2414).

In the game number storage process, if a positive judgment is made in step S2413, this means that the current game number mode is the first game number mode, and therefore the pseudo bonus continuation counter in the main RAM 74 is set to a value corresponding to 20 games, which is the minimum number of games, as the initial continuation game number for the pseudo bonus state ST4. Also, in the game number storage process, if a positive judgment is made in step S2411, this means that the current game number mode is the game number mode corresponding to the current value of the lottery number counter 74k, and therefore the value of the initial continuation game number for the pseudo bonus state ST4 corresponding to that game number mode is set to the pseudo bonus continuation counter in the main RAM 74. Specifically, if the value of the lottery number counter 74k is "1", the pseudo bonus continuation counter is set to a value of 30 games corresponding to the second game number mode, if the value of the lottery number counter 74k is "2", the pseudo bonus continuation counter is set to a value of 40 games corresponding to the third game number mode, if the value of the lottery number counter 74k is "3", the pseudo bonus continuation counter is set to a value of 50 games corresponding to the fourth game number mode, and if the value of the lottery number counter 74k is "4", the pseudo bonus continuation counter is set to a value of 60 games corresponding to the fifth game number mode. As already explained, the pseudo bonus continuation counter is a counter that allows the main MPU 72 to determine the remaining number of continued games in the pseudo bonus state ST4.

When the process of step S2414 is executed, the upper byte of the second random number is obtained from the second random number circuit 76 (step S2415). Specifically, a latch signal is sent to the second random number circuit 76, causing the second random number information after the most recent update in the second random number circuit 76 to be stored in the latch area 111. Then, the upper byte information stored in the upper area 111a of the latch area 111 is obtained in a register of the main MPU 72. Then, the most significant bit of the obtained upper byte information is cleared to "0" (step S2416). This makes it possible to obtain a 7-bit random number.

Here, in this second start setting process, a latch signal is sent in step S2406 so that the second random number is latched in the second random number circuit 76, and a latch signal is sent in step S2415 so that the second random number is latched in the second random number circuit 76. In this case, the second random number is sequentially updated in the second random number circuit 76 based on the clock signal output from the clock circuit, and this update period is 0.1 nanoseconds. The period from when the process of step S2406 is executed to when the process of step S2415 is executed is longer than the period required for the second random number, which is updated every 0.1 nanoseconds as described above, to complete one cycle in the numerical range of 0 to 65535. In addition, the period from when the process of step S2406 is executed to when the process of step S2415 is executed varies within a predetermined period range, and this variation is large in relation to the update period of the second random number. Therefore, even if a latch signal is sent to the second random number circuit 76 in each of steps S2406 and S2415 during one processing round of the second start setting process (FIG. 50), no regularity is created between the second random number stored in the latch area 111 by sending the latch signal in step S2406 and the second random number stored in the latch area 111 by sending the latch signal in step S2415.

Then, the lottery number counter 74k in the master RAM 74 is set to "1" (step S2417). As already explained, the lottery number counter 74k is used to identify which index value IV is the subject of the lottery in the lottery process for the role (FIG. 34), and is used to identify which game number mode is the subject of the lottery in the lottery process for the game number mode, but in the lottery process for the winning rate mode, it is used by the master MPU 72 to identify which winning rate mode is the subject of the lottery in the lottery process. In the lottery process of the winning rate mode, if the value of the lottery number counter 74k is "1", the second winning rate mode is the target of the lottery process, if the value of the lottery number counter 74k is "2", the third winning rate mode is the target of the lottery process, if the value of the lottery number counter 74k is "3", the fourth winning rate mode is the target of the lottery process, and if the value of the lottery number counter 74k is "4", the fifth winning rate mode is the target of the lottery process. If the value of the lottery number counter 74k is not 1 to 4, the first winning rate mode is selected.

Then, the start address for the winning rate mode lottery is set in a register for address reference in the master MPU 72 (step S2418). The start address is the start address of the winning rate mode lottery table 113 provided in the master ROM 73. Figure 51 (b) is an explanatory diagram for explaining the winning rate mode lottery table 113.

In the winning rate mode lottery table 113, a plurality of address information E(1)-E(24) are set, and a judgment value LV is set in one-to-one correspondence with the plurality of address information E(1)-E(24). Each address information E(1)-E(24) has a data capacity of 1 byte and is a consecutive number. The first range of address information E(1)-E(4) corresponds to a set value of "1", the second range of address information E(5)-E(8) corresponds to a set value of "2", the third range of address information E(9)-E(12) corresponds to a set value of "3", the fourth range of address information E(13)-E(16) corresponds to a set value of "4", the fifth range of address information E(17)-E(20) corresponds to a set value of "5", and the sixth range of address information E(21)-E(24) corresponds to a set value of "6". In other words, if the set value is n (n is an integer between 1 and 6), the set value of n corresponds to the range of address information E((n-1) x 4 + 1) to E((n-1) x 4 + 4).

In addition, within the range of address information corresponding to each set value, the first address information E(1), E(5), E(9), E(13), E(17), and E(21) are associated with the judgment value LV of the second winning rate mode, the second address information E(2), E(6), E(10), E(14), E(18), and E(22) are associated with the judgment value LV of the third winning rate mode, the third address information E(3), E(7), E(11), E(15), E(19), and E(23) are associated with the judgment value LV of the fourth winning rate mode, and the last address information E(4), E(8), E(12), E(16), E(20), and E(24) are associated with the judgment value LV of the fifth winning rate mode. In other words, if the set value is n (n is an integer between 1 and 6), the determination value LV for the mth winning rate mode (m is an integer between 2 and 4) is associated with the address information E((n-1) x 4 + (m-1)).

In a configuration in which the probability of selecting each winning rate mode differs depending on the setting value being used, the winning rate mode selection table 113 has a range of address information E(0) to E(24) set according to each setting value, and furthermore, within the range of address information E(0) to E(24) for each setting value, the allocation order of the second to fifth winning rate modes is common to each setting value. As a result, in a configuration in which the number of tables is reduced by providing one winning rate mode selection table 113 corresponding to all setting values rather than providing a different table for each setting value, when the judgment value LV corresponding to the combination of the setting value being used and the winning rate mode being selected is read from the winning rate mode selection table 113, the judgment value LV can be read according to certain rules.

For example, the LV judgment value set in address information E(1) is "25", and the range of random numbers in the lottery process for the game count mode is 0 to 127, so the probability of selecting the second game count mode when the setting value is "1" is approximately 20%, as shown in FIG. 48(b). Also, as already explained, if the lottery process for the winning rate mode results in a miss, the first winning rate mode will be selected if the setting value is "1" to "5", and since the first winning rate mode is not included in the lottery targets for the setting value of "6", the winning rate mode lottery table 113 does not have a LV judgment value corresponding to the first winning rate mode.

Returning to the explanation of the second start setting process (Figure 50), as already explained in step S2418, the start address of the winning rate mode selection table 113 is set in a register for address reference in the master MPU 72. In this case, the winning rate mode selection table 113 is read from the master ROM 73 to the master RAM 74.

Then, the LV acquisition process is executed (step S2419). Figure 52 is a flowchart showing the LV acquisition process.

First, the setting value information to be used is read from the setting value storage area of the main RAM 74, and the read setting value information is set in the B register provided in the main MPU 72 (step S2501). After that, the information of the lottery number counter 74k in the main RAM 74 is read, and the read information is set in the C register provided in the main MPU 72 (step S2502). Then, the offset value of the address information is calculated by executing the calculation (B-1) x 4 + C (step S2503).

Then, the offset value of the address information calculated in step S2503 is added to the start address set in step S2418 of the second start setting process (FIG. 50) (step S2504). Then, the judgment value LV corresponding to the target address of the addition result in step S2504 is read from the winning rate mode selection table 113 (step S2505). As a result, the judgment value LV corresponding to the combination of the setting value to be used and the winning rate mode to be selected is read from the winning rate mode selection table 113.

Returning to the explanation of the second start setting process (FIG. 50), after the judgment value LV is acquired in step S2419, the lottery value JV used to judge the success or failure of the winning rate mode that is the subject of the lottery is set (step S2420). In this process, the judgment value LV acquired in step S2419 is added to the current lottery value JV to set a new lottery value JV. In the first process of step S2420 after the processes of steps S2415 to S2418 are executed, the value of the 7-bit random number information (any of 0 to 127) acquired in steps S2415 and S2416 is set as the current lottery value JV, and the judgment value LV acquired in step S2419 is added to this 7-bit random number information to set a new lottery value JV. Note that if the judgment value LV acquired in step S2419 is "0", the lottery value JV does not change even if the process of step S2420 is executed. In other words, if the judgment value LV is "0" in the first setting process, the 7-bit random number information (any value between 0 and 127) becomes the lottery value JV as is, and if the judgment value LV is "0" in the second or subsequent setting processes, the lottery value JV from the previous setting process becomes the lottery value JV this time.

Then, a win/loss judgment is performed for the winning rate mode corresponding to the current value of the lottery number counter 74k (step S2421). In this win/loss judgment, it is judged whether the lottery value JV exceeds "127". If it does not exceed "127" (step S2421: NO), it means that the winning rate mode corresponding to the current value of the lottery number counter 74k has been missed. In this case, after adding 1 to the value of the lottery number counter 74k in the main RAM 74 (step S2422), it is judged whether the winning rate mode to be judged for win/loss still exists (step S2423). Specifically, if the value of the lottery number counter 74k to which 1 has been added is not "5" (step S2423: NO), the process returns to step S2419 and the win/loss judgment of the winning rate mode is continued. At this time, in the LV acquisition process in step S2419 (FIG. 52), the set value set as the target to be used is the same value, but the value of the lottery number counter 74k is a value that is added by 1 to the value at the time of the previous execution of this acquisition process. Therefore, in step S2503 of the LV acquisition process (FIG. 52), the offset value of the address information acquired in the previous main acquisition process is increased by 1 to calculate the offset value of the current address information, and the judgment value LV corresponding to the address information E(0)-E(24) that is one address after the address information E(0)-E(24) that was the reference target in the previous main acquisition process is acquired. Then, using the newly acquired judgment value LV, a new lottery value JV is calculated in step S2420, and it is determined whether the calculated lottery value JV exceeds "127" to determine whether the winning rate mode corresponding to the current value of the lottery number counter 74k is successful.

If the lottery value JV exceeds "127" (step S2421: YES), it means that the winning rate mode corresponding to the current value of the lottery number counter 74k has been won. Also, if the lottery value JV does not exceed "127" (step S2421: NO) and the value of the lottery number counter 74k after adding 1 is "5" (step S2423: YES), it means that none of the second to fifth winning rate modes have been won, and in this case, it means that the first winning rate mode has been won. In these cases, the storage process for the winning rate mode is executed (step S2424).

In the storage process of the winning rate mode, if a positive judgment is made in step S2423, this means that the current winning rate mode is the first winning rate mode, and therefore information corresponding to the first winning rate mode is stored in the main RAM 74. In addition, in the storage process of the winning rate mode, if a positive judgment is made in step S2421, this means that the current winning rate mode is the winning rate mode corresponding to the current value of the lottery number counter 74k, and therefore information corresponding to that winning rate mode is stored in the main RAM 74. Specifically, if the value of the lottery number counter 74k is "1", information corresponding to the second winning rate mode is stored in the main RAM 74, if the value of the lottery number counter 74k is "2", information corresponding to the third winning rate mode is stored in the main RAM 74, if the value of the lottery number counter 74k is "3", information corresponding to the fourth winning rate mode is stored in the main RAM 74, and if the value of the lottery number counter 74k is "4", information corresponding to the fifth winning rate mode is stored in the main RAM 74.

After executing the processing of step S2424, the pseudo bonus state flag in the master RAM 74 is set to "1" (step S2425). As already explained, the pseudo bonus state flag is a flag that allows the master MPU 72 to determine whether the game state is in the pseudo bonus state ST4 or not.

<About the freeze setting process when transferring bonuses>
Next, the freeze setting process at the time of transition to the bonus executed in step S907 of the normal process (FIG. 25) will be described.

In a configuration in which the game state transitions to the pseudo bonus state ST4 when the transition condition is satisfied in the normal game state ST1, a freeze period basically occurs at the start of the first game executed in the pseudo bonus state ST4. As already explained, the freeze period is a period during which the player's operation of the rotation of the reels 32L, 32M, and 32R, in which reel control corresponding to the result of the lottery process for winning combinations (FIG. 34) is executed, is disabled, and in this slot machine 10, it is a period during which the start of rotation of the reels 32L, 32M, and 32R is forcibly suspended in response to the operation of the start lever 41 to start one game. The freeze period set at the start of the pseudo bonus state ST4 differs depending on the type of game number mode and win rate mode determined when transitioning to the pseudo bonus state ST4.

Specifically, when the number of games mode is any of the first to third number of games mode, it corresponds to the first combination regardless of the winning rate mode, and further when the winning rate mode is any of the first to third winning rate modes, it corresponds to the first combination regardless of the number of games mode. When it corresponds to the first combination, 10 seconds are set as the freeze period at the start of the pseudo bonus state ST4. When the number of games mode is the fourth number of games mode and the winning rate mode is the fourth winning rate mode or the fifth winning rate mode, it corresponds to the second combination, and further when the winning rate mode is the fourth winning rate mode and the number of games mode is the fourth number of games mode or the fifth number of games mode, it corresponds to the second combination. When it corresponds to the second combination, 20 seconds are set as the freeze period at the start of the pseudo bonus state ST4. When the number of games mode is the fifth number of games mode and the winning rate mode is the fifth winning rate mode, it corresponds to the third combination. When it corresponds to the third combination, 30 seconds are set as the freeze period at the start of the pseudo bonus state ST4.

As described above, at the start of the pseudo bonus state ST4, a freeze period is basically set corresponding to the combination of the number of games mode and the winning rate mode. However, in the normal game state ST1, when a direct hit is won in the direct hit lottery process (step S2208) and the first start setting process (step S2303) is executed, and a transition to the pseudo bonus state ST4 occurs as a result of the execution of the first start setting process, a freeze period of 30 seconds is set at a stage before the rotation of the reels 32L, 32M, and 32R begins in the game in which the direct hit lottery process (step S2208) is won. Since the game in which this freeze period is set is the game one game before the game first executed in the pseudo bonus state ST4, if a further freeze period is set in the game first executed in the pseudo bonus state ST4, it may become bothersome for the player. In contrast, in this slot machine 10, in the pseudo bonus state ST4, which is entered as a result of a direct hit win in the direct hit lottery process (step S2208), a freeze period is not set at the start of the first game.

The processing configuration for realizing this configuration is described below. Figure 53 is a flowchart showing the freeze setting process at the time of bonus transfer executed by the main MPU 72.

If the current game is the first game executed in the pseudo bonus state ST4 (step S2601: YES), it is determined whether the direct hit freeze occurrence flag in the main RAM 74 is set to "1" (step S2602). As already explained, the direct hit freeze occurrence flag is set to "1" in step S2212 if a direct hit is won in the direct hit lottery process (step S2208) in the advantageous lottery process (FIG. 46) at the start of the game. If the direct hit freeze occurrence flag is set to "1" (step S2602: YES), the direct hit freeze occurrence flag is cleared to "0" (step S2603), and the freeze setting process at the time of transition to the main bonus is terminated without executing the process for setting the freeze period from step S2604 onwards.

If a direct hit is selected in the direct hit lottery process (step S2208), a freeze counter setting process is executed in step S2211 in the advantageous lottery process (FIG. 46) at the start of the game, and information corresponding to a 30-second freeze period is set in the freeze counter of the main RAM 74. Furthermore, in normal processing (FIG. 25), if the value of the freeze counter is 1 or more in step S908 executed thereafter, the process waits in step S908 to wait for the start of rotation of the reels 32L, 32M, and 32R. The value of the freeze counter is subtracted in the timer subtraction process (step S506) each time the timer interrupt process (FIG. 19) is started. With this configuration, if a direct hit is selected in the direct hit lottery process (step S2208), the start of rotation of the reels 32L, 32M, and 32R in the game in which the direct hit is selected is waited for a 30-second freeze period. Then, at the end of the game in which the freeze period occurred, a transition to pseudo bonus state ST4 occurs, and the game following that game becomes the first game to be executed in pseudo bonus state ST4. In such circumstances, if the direct hit freeze occurrence flag is set to "1", the process for setting the freeze period from step S2604 onwards is not executed, so that it is possible to prevent a further freeze period at the start of pseudo bonus state ST4 from occurring in the game following the game in which the freeze period occurred due to a direct hit win.

If the direct freeze occurrence flag is not set to "1" (step S2602: NO), it is determined whether or not the combination of the game count mode and the winning rate mode in the current pseudo bonus state ST4 is the first combination (step S2604). As already explained, if the game count mode is any of the first to third game count modes, it corresponds to the first combination regardless of the winning rate mode, and if the winning rate mode is any of the first to third winning rate modes, it corresponds to the first combination regardless of the game count mode. If it is the first combination (step S2604: YES), the first freeze setting process is executed (step S2605). In the first freeze setting process, information corresponding to 10 seconds, which corresponds to the first freeze period, is set in the freeze counter of the main RAM 74. As a result, in the normal process (FIG. 25) after the freeze setting process at the time of the bonus transition is completed, a positive determination is made in step S908 and the process waits until the first freeze period has elapsed. Therefore, the start of rotation of reels 32L, 32M, and 32R in this game will be delayed for the first freeze period.

Then, a first freeze command is sent to the presentation side MPU 92 (step S2606). When the presentation side MPU 92 receives the first freeze command, it causes the presentation execution mode on the upper lamp 61, speaker 62, and image display device 63 to correspond to the first freeze period. By checking the presentation, the player can understand that a pseudo bonus state ST4 has occurred, in which the combination of the number of games mode and the winning rate mode is the first combination.

If the combination of the game number mode and the winning rate mode in the current pseudo bonus state ST4 is not the first combination (step S2604: NO), it is determined whether or not the combination of the game number mode and the winning rate mode in the current pseudo bonus state ST4 is the second combination (step S2607). As already explained, if the game number mode is the fourth game number mode and the winning rate mode is the fourth winning rate mode or the fifth winning rate mode, it corresponds to the second combination, and if the winning rate mode is the fourth winning rate mode and the game number mode is the fourth game number mode or the fifth game number mode, it corresponds to the second combination. If it is the second combination (step S2607: YES), the second freeze setting process is executed (step S2608). In the second freeze setting process, information corresponding to 20 seconds, which corresponds to the second freeze period, is set in the freeze counter of the main RAM 74. As a result, in the normal process (FIG. 25) after the freeze setting process at the time of the present bonus transition is completed, a positive determination is made in step S908 and the process waits until the second freeze period has elapsed. Therefore, the start of rotation of reels 32L, 32M, and 32R in the current game will be delayed for the second freeze period.

Then, a second freeze command is sent to the presentation side MPU 92 (step S2609). When the presentation side MPU 92 receives the second freeze command, it causes the presentation execution mode on the upper lamp 61, speaker 62, and image display device 63 to correspond to the second freeze period. By checking the presentation, the player can understand that a pseudo bonus state ST4 has occurred, in which the combination of the game count mode and the win rate mode is the second combination.

If the combination of the game count mode and the winning rate mode in the current pseudo bonus state ST4 is not the second combination (step S2607: NO), it means that the combination of the game count mode and the winning rate mode in the current pseudo bonus state ST4 is the third combination. As already explained, if the game count mode is the fifth game count mode and the winning rate mode is the fifth winning rate mode, it corresponds to the third combination. If it is the third combination (step S2607: NO), the third freeze setting process is executed (step S2610). In the third freeze setting process, information corresponding to 30 seconds, which corresponds to the third freeze period, is set in the freeze counter of the main RAM 74. As a result, in the normal process (FIG. 25) after the freeze setting process at the time of the transition to the main bonus is completed, a positive determination is made in step S908 and the process waits until the third freeze period has elapsed. Therefore, the start of rotation of the reels 32L, 32M, and 32R in the current game is waited for the third freeze period.

Then, a third freeze command is sent to the presentation side MPU 92 (step S2611). When the presentation side MPU 92 receives the third freeze command, it causes the presentation execution mode on the upper lamp 61, speaker 62, and image display device 63 to correspond to the third freeze period. By checking the presentation, the player can understand that a pseudo bonus state ST4 has occurred, in which the combination of the number of games mode and the winning rate mode is the third combination.

Next, the manner in which the freeze period is set will be described with reference to the time chart in Figure 54. Figure 54(a) shows the execution period of one game, Figure 54(b) shows the period in the normal game state ST1, Figure 54(c) shows the period in the pseudo bonus state ST4, Figure 54(d) shows the situation in the freeze period, and Figure 54(e) shows the timing when a direct hit occurs in the direct hit lottery process (step S2208).

First, we will explain the case where a transition to pseudo bonus state ST4 occurs without a direct hit being won in the direct hit lottery process (step S2208).

As shown in FIG. 54(b), in a situation where the normal gaming state ST1 is in progress, games are executed from timing t1 to timing t2 and from timing t3 to timing t4 as shown in FIG. 54(a). Then, when the value of the transition waiting counter or release game number counter in the main RAM 74 becomes "0" in the game executed from timing t3 to timing t4, the second start setting process (FIG. 50) is executed to transition the gaming state to the pseudo bonus state ST4. Therefore, at timing t4, the normal gaming state ST1 ends and the pseudo bonus state ST4 begins as shown in FIG. 54(b) and FIG. 54(c).

After that, at the timing of t5, the first game in the pseudo bonus state ST4 is started as shown in FIG. 54(a). The pseudo bonus state ST4 this time is not triggered by a direct hit win in the direct hit lottery process (step S2208), but by a transition win in the transition lottery process (step S2215) or by the execution of a game for the release game number. Therefore, as shown in FIG. 54(d), a freeze period is set from the timing of t5, which is the timing when the game is started, to the timing of t6. As already explained, this freeze period is 10 seconds, 20 seconds, or 30 seconds depending on the type of combination of the game number mode and the win rate mode in the pseudo bonus state ST4 this time. Until the freeze period has elapsed, by making a positive judgment in step S908 in the normal process (FIG. 25), the start of rotation of the reels 32L, 32M, and 32R is awaited even after the execution of the role lottery process (FIG. 34). Then, at time t6, the freeze period elapses, and reels 32L, 32M, and 32R begin to rotate. After that, at time t7, the current game ends as shown in FIG. 54(a), and a new game in pseudo bonus state ST4 is played from time t8 to time t9.

The occurrence of the freeze period as described above allows the player to clearly recognize that the pseudo bonus state ST4 has begun. During the freeze period, the performance corresponding to the freeze period is executed by the upper lamp 61, speaker 62, and image display device 63. This makes it possible to increase the player's sense of satisfaction regarding the beginning of the pseudo bonus state ST4.

Next, we will explain the case where a transition to pseudo bonus state ST4 occurs due to a direct hit win in the direct hit lottery process (step S2208).

In the normal game state ST1 as shown in FIG. 54(b), the game is executed from t10 to t11 and from t12 to t14 as shown in FIG. 54(a). In this case, at t12, a direct hit is won in the direct hit lottery process (step S2208) as shown in FIG. 54(e). Therefore, as shown in FIG. 54(d), a freeze period is set from t12 to t13. The freeze period triggered by a direct hit is fixed at 30 seconds as already explained. Until the freeze period has elapsed, the start of rotation of the reels 32L, 32M, and 32R is awaited even after the lottery process (FIG. 34) has been executed by making a positive determination in step S908 in the normal process (FIG. 25). Then, the freeze period elapses at t13, and the rotation of the reels 32L, 32M, and 32R is started.

By generating a freeze period in this way, it is possible for the player to clearly recognize that an opportunity to transition to pseudo bonus state ST4 has occurred. Furthermore, during the freeze period, a presentation corresponding to the freeze period is executed by the upper lamp 61, speaker 62, and image display device 63. This makes it possible to increase the player's sense of satisfaction at the occurrence of an opportunity to transition to pseudo bonus state ST4.

Then, at timing t14, as shown in FIG. 54(a), the current game ends. In this case, the first start setting process (step S2303) is executed, and the normal game state ST1 ends and the pseudo bonus state ST4 begins, as shown in FIG. 54(b) and FIG. 54(c). Note that since the pseudo bonus state ST4 is triggered by a direct hit win, once the pseudo bonus state ST4 ends, the game will definitely transition to the AT state ST5.

After that, at timing t15, the first game in pseudo bonus state ST4 starts as shown in FIG. 54(a). The current pseudo bonus state ST4 is triggered by a direct win in the direct hit lottery process (step S2208), and a freeze period triggered by the direct win has already occurred. Therefore, a freeze period triggered by the start of the first game in pseudo bonus state ST4 does not occur. This makes it possible to prevent excessive freeze periods from occurring. After that, at timing t16, the current game ends as shown in FIG. 54(a), and a new game in pseudo bonus state ST4 is played from timing t17 to timing t18.

<About the pseudo bonus state ST4>
Next, the processing contents in the pseudo bonus state ST4 and the AT state ST5 will be described. FIG. 55 is a flow chart showing the processing for advantageous state at the start of the game executed by the main MPU 72. As already explained, the advantageous lottery processing at the start of the game (FIG. 46) is executed in step S1313, which is the processing executed after the role lottery processing (FIG. 34) has completed the role win/loss judgment and the first control processing (step S1312) of the play area has been executed, and before the stop order notification control processing (step S1314). And, the processing for advantageous state at the start of the game is executed in step S2203 in the advantageous lottery processing at the start of the game (FIG. 46).

First, it is determined whether the number of bets for the current game is "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S2701). If the number of bets for the current game is "2" (step S2701: NO), the processing from step S2702 onwards is not executed. As a result, in a game where the number of bets is "2" even if the game is in the pseudo bonus state ST4 or AT state ST5, the processing from step S2702 onwards is not executed.

If the number of bets for the current game is "3" (step S2701: YES), it is determined whether the current game state is the first CB state ST2 or the second CB state ST3 (step S2702). If the current game state is the first CB state ST2 or the second CB state ST3 (step S2702: YES), the processing from step S2703 onwards is not executed. As a result, even if the pseudo bonus state flag or the AT state flag in the main RAM 74 is set to "1", if the state is the first CB state ST2 or the second CB state ST3, the processing from step S2703 onwards is not executed.

If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S2702: NO), it is determined whether the pseudo bonus state flag in the main RAM 74 is set to "1" to determine whether the current game state is the pseudo bonus state ST4 (step S2703). If the current game state is not the pseudo bonus state ST4 (step S2703: NO), this means that the current game state is the AT state ST5, so AT state processing at the start of the game is executed (step S2704). The AT state processing at the start of the game will be described later.

If the current game state is the pseudo bonus state ST4 (step S2703: YES), it is determined whether the AT transition confirmation flag provided in the main RAM 74 is set to "1" (step S2705). The AT transition confirmation flag is a flag that the main MPU 72 uses to determine whether the transition conditions to the AT state ST5 have already been met in the pseudo bonus state ST4. If the AT transition confirmation flag has already been set to "1" (step S2705: YES), this means that the transition conditions to the AT state ST5 have already been met in the current pseudo bonus state ST4, and therefore no processing is performed to determine whether to transition to the AT state ST5 in steps S2706 and after.

If the AT transition confirmation flag is not set to "1" (step S2705: NO), it is determined whether or not transition-compatible winning data is stored in the main RAM 74 (step S2706). The transition-compatible winning data is any one of the following: first watermelon winning data, second watermelon winning data, cherry winning data, first chance replay winning data, and second chance replay winning data. In other words, if the lottery process for the role in this game (Figure 34) results in a win with index value IV = 11 to 15, a positive determination is made in step S2706. If a positive determination is made in step S2706, an AT transition lottery process is executed (step S2707).

In the AT transition lottery process, an AT transition lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 are used to determine by lottery whether or not to transition to the AT state ST5 after the end of the current pseudo bonus state ST4. In the lottery process of the role in this game (FIG. 34), if the first watermelon winning data is stored in the main RAM 74 (if the index value IV=11 is won), the probability of AT shift winning is 20%, if the second watermelon winning data is stored in the main RAM 74 (if the index value IV=12 is won), the probability of AT shift winning is 10%, if the cherry winning data is stored in the main RAM 74 (if the index value IV=13 is won), the probability of AT shift winning is 40%, if the first chance replay winning data is stored in the main RAM 74 (if the index value IV=14 is won), the probability of AT shift winning is 30%, and if the second chance replay winning data is stored in the main RAM 74 (if the index value IV=15 is won), the probability of AT shift winning is 20%. In this case, the lower the probability of winning in the lottery process of the role (FIG. 34), the higher the probability of AT shift winning. This makes it possible to increase the advantage of winning an index value IV, which has a low probability of winning, during the role selection process (Figure 34).

If the AT transition is won (step S2708: YES), the AT transition confirmation flag in the main RAM 74 is set to "1" (step S2709). After that, an AT transition winning command indicating that the AT transition has been won is sent to the performance side MPU 92 (step S2710). When the performance side MPU 92 receives the AT transition winning command, it causes the upper lamp 61, speaker 62, and image display device 63 to display a performance indicating that the AT transition has been won.

Next, the pseudo bonus processing executed by the main MPU 72 will be described with reference to the flowchart in FIG. 56. The pseudo bonus processing is executed in step S1805 of the response processing at the end of play (FIG. 39). As described above, the response processing at the end of play is executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game, so the pseudo bonus processing is also executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game.

First, it is determined whether the number of bets for the current game is "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S2801). If the number of bets for the current game is "2" (step S2801: NO), the processing from step S2802 onwards is not executed. As a result, even if a game with the number of bets of "2" is executed in the pseudo bonus state ST4, the number of remaining continued games in the pseudo bonus state ST4 is not subtracted.

Note that when in the CB state (first CB state ST2 or second CB state ST3), the pseudo bonus process (Figure 56) itself is not executed, so even if the CB state is started in the middle of the pseudo bonus state ST4, the number of games played in the CB state is not treated as the number of games played in the pseudo bonus state ST4. Therefore, even if the CB state is transitioned to in the middle of the pseudo bonus state ST4, after the CB state ends, the pseudo bonus state ST4 will resume from the state of the remaining number of continued games immediately before transitioning to the CB state.

If the number of bets on the current game is "3" (step S2801: YES), the value of the pseudo bonus continuation counter in the main RAM 74 is decremented by 1 (step S2802). After that, it is determined whether the value of the pseudo bonus continuation counter is "0" (step S2803). If the value of the pseudo bonus continuation counter is "0" (step S2803: YES), it is determined whether the AT transition confirmation flag in the main RAM 74 is set to "1" (step S2804).

If the AT transition confirmation flag is set to "1" (step S2804: YES), a lottery process for the number of sets is executed (step S2805). In the lottery process for the number of sets, the initial number of sets in the AT state ST5 is determined by lottery using a set number table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74. As already explained, the initial number of continuing games in one set in the AT state ST5 is 50 games, and the remaining number of continuing games can be increased by the establishment of an additional condition in the middle of one set. When one set ends and the remaining number of sets is "0", the AT state ST5 ends.

In the lottery process for the number of sets, if the transition trigger for the currently ended pseudo bonus state ST4 was a direct hit win or if the win rate mode of the currently ended pseudo bonus state ST4 was the fifth win rate mode, an initial set number of 1 is selected with a 20% probability, an initial set number of 2 is selected with a 30% probability, and an initial set number of 3 is selected with a 50% probability. Also, if the win rate mode of the currently ended pseudo bonus state ST4 was the fourth win rate mode or the third win rate mode, an initial set number of 1 is selected with a 30% probability, an initial set number of 2 is selected with a 50% probability, and an initial set number of 3 is selected with a 20% probability. Furthermore, if the winning rate mode of the currently ended pseudo bonus state ST4 was the second winning rate mode or the first winning rate mode, an initial set number of times is selected with a 50% probability, an initial set number of times is selected with a 30% probability, and an initial set number of times is selected with a 20% probability.

Then, a process for storing the number of sets is executed (step S2806). In the process for storing the number of sets, information on the initial number of sets selected in the lottery process for the number of sets is set in the set number counter in the main RAM 74. As already explained, the set number counter is a counter for identifying the remaining number of sets in the AT state ST5 by the main MPU 72.

Then, the AT continuation counter in the main RAM 74 is set to "50" as information on the initial number of continued games (step S2807). As already explained, the AT continuation counter is a counter that allows the main MPU 72 to determine the remaining number of continued games in one set in the AT state ST5. In addition, the AT state flag provided in the main RAM 74 is set to "1" (step S2808). The AT state flag is a flag that allows the main MPU 72 to determine whether the game state is in the AT state ST5 or not. Then, an AT transition command indicating that a transition to the AT state ST5 will occur is sent to the presentation side MPU 92 (step S2809). When the presentation side MPU 92 receives the AT transition command, it causes the upper lamp 61, speaker 62, and image display device 63 to execute a presentation indicating that a transition to the AT state ST5 will occur.

Then, the second output start flag stored in the main RAM 74 is set to "1" (step S2810). The second output start flag is a flag that allows the main MPU 72 to identify a situation in which an external output corresponding to the start of AT state ST5 should be executed.

On the other hand, if the AT transition confirmation flag is not set to "1" (step S2804: NO), a process for setting the end preparation state ST6 is executed (step S2811). In this setting process, the end preparation state flag provided in the main RAM 74 is set to "1". The end preparation state flag is a flag that the main MPU 72 uses to identify that the game is in the end preparation state ST6, and setting the end preparation state flag to "1" changes the game state to the end preparation state ST6. In addition, the end preparation complete flag in the main RAM 74 is cleared to "0" (step S2812). As already explained, the end preparation complete flag is a flag that the main MPU 72 uses to identify whether or not one game has been played in the end preparation state ST6.

As already explained, in the end preparation state ST6, if a positive judgment is made in step S2002 in the second control process for the game section (FIG. 44) and the end preparation complete flag is not set to "1" (step S2003: NO), the end preparation complete flag is set to "1" and then processing is executed to determine whether the ending condition for the second section SC2 has been met, and the second control process for the game section in the current game (FIG. 44) is terminated. On the other hand, if the end preparation complete flag is set to "1" (step S2003: YES), processing is executed to terminate the second section SC2 and transition to the first section SC1 (steps S2014 to S2016). As a result, the second section SC2 ends when the game following the game in which the pseudo bonus state ST4 ended ends.

After executing step S2812 in the pseudo bonus process (FIG. 56), a bonus end command indicating that the pseudo bonus state ST4 has ended is sent to the presentation side MPU 92 (step S2813). When the presentation side MPU 92 receives the bonus end command, it turns off the upper lamp 61. This off state continues until a new game is started. When the presentation side MPU 92 receives the bonus end command, it causes the speaker 62 and image display device 63 to execute a presentation indicating that the pseudo bonus state ST4 has ended. After that, it sets the external output end flag provided in the main RAM 74 to "1" (step S2814). The external output end flag is a flag that allows the main side MPU 72 to identify that the current situation is one in which the external output should be set to a state corresponding to the end of the pseudo bonus state ST4 or the AT state ST5 and the transition to the normal game state ST1.

When the processing of step S2810 or the processing of step S2814 is executed, a clear process at the end of the bonus is executed (step S2815). In the clear process at the end of the bonus, a process is executed to clear an area of the main RAM 74 in response to the end of the pseudo bonus state ST4.

Figure 57 is a flowchart showing the clearing process when the bonus ends.

First, "k" is set as the start address for the clearing process in the address to be cleared provided in the register of the master MPU 72 (step S2901). Here, the contents of the memory areas of the master RAM 74 will be explained again with reference to FIG. 16. As shown in FIG. 16, an address is set in each memory area of the master RAM 74. The addresses are set as consecutive number information. Specifically, the address "0000" is set as the initial address, the address "0001" is set as the next sequential address, the address "0002" is set as the next sequential address, and the addresses are set so that they are consecutive thereafter.

The second CB winning data area, which is an area for storing the second CB winning data, is set as the memory area corresponding to the starting address "0000", the first CB winning data area, which is an area for storing the first CB winning data, is set as the memory area corresponding to the next turn "0001", the setting value memory area, which is an area for storing the setting value to be used, is set as the memory area corresponding to the next turn "0002", the continued game count counter 74c is set as the memory area corresponding to the next turn "0003", the total win count counter 74d is set as the memory area corresponding to the next turn "0004", the credit counter 74b is set as the memory area corresponding to the next turn "0005", and the door status area 74e is set as the memory area corresponding to the next turn "0006". In addition, various storage areas are set in the storage areas corresponding to "0007" to "k-3", such as a second section flag, a set counter, an AT continuation counter, an AT state flag, a second output start flag, a finish preparation state flag, a finish preparation completion flag, an external output end flag, and a storage area in which information indicating whether a replay win has been established is stored. In addition, a bet number history counter 74f is set as a storage area corresponding to "k-2", a given number history counter is set as a storage area corresponding to the next order "k-1", a pseudo bonus state flag is set as a storage area corresponding to the next order "k", a pseudo bonus continuation counter is set as a storage area corresponding to the next order "k+1", a bet number setting counter 74a is set as a storage area corresponding to the next order "k+2", and a medium given counter is set as a storage area corresponding to the next order "k+3". In addition, as storage areas for addresses from "k+4" onwards, for example, an information abnormality flag 74g, an area for storing information on the number of games mode, and an area for storing information on the winning rate mode are included.

After "k" is set as the address to be cleared in the master MPU 72 in step S2901, the memory area of the master RAM 74 corresponding to the address set as the address to be cleared is cleared to "0" to perform initialization (step S2902). Then, the update process of the address to be cleared is performed (step S2903). In the update process, the value of the address to be cleared is incremented by 1, so that the address set as the address to be cleared is changed to the next address in the order of addresses in the master RAM 74. Then, it is determined whether the address after the update exceeds the end address, which is the last address in the order, in the master RAM 74 (step S2904). If a negative determination is made in step S2904, the memory area of the address after the update is cleared to "0" to perform initialization (step S2902), and the processes of steps S2903 and S2904 are performed again. If a positive determination is made in step S2904, this means that the clear process of the master RAM 74 at the end of the pseudo bonus state ST4 has ended. In this case, the clear process at the end of the bonus is ended.

When the pseudo bonus state ST4 ends by executing the clearing process at the end of the bonus as described above, the memory areas corresponding to addresses "0000" to "k-1" in the main RAM 74 are not cleared to "0". The memory area corresponding to "0000" is set as the second CB winning data area as described above, and the memory area corresponding to "0001" is set as the first CB winning data area as described above. Because these memory areas are excluded from the targets for executing the clearing process at the end of the bonus, the first CB winning data will not be erased even if the pseudo bonus state ST4 ends when the first CB winning data is stored in the main RAM 74, and the second CB winning data will not be erased even if the pseudo bonus state ST4 ends when the second CB winning data is stored in the main RAM 74.

The memory area corresponding to "0002" is set as a set value memory area as described above. Since the memory area is excluded from the execution of the clear process at the end of the bonus, the set value to be used will not be erased even if the pseudo bonus state ST4 ends. The memory area corresponding to "0003" is set as a continued game counter 74c as described above, and the memory area corresponding to "0004" is set as a total acquisition counter 74d as described above. Since these memory areas are excluded from the execution of the clear process at the end of the bonus, information for identifying the trigger for the establishment of the ending condition of the second section SC2 will not be erased even if the pseudo bonus state ST4 ends. The memory area corresponding to "0005" is set as a credit counter 74b as described above. Since the memory area is excluded from the execution of the clear process at the end of the bonus, the information of the credited virtual medals will not be erased even if the pseudo bonus state ST4 ends. The memory area corresponding to "0006" is set as a door state area 74e as described above. Since the memory area is excluded from the execution target of the clearing process at the end of the bonus, the information on the monitoring state of the front door 12 is not erased even when the pseudo bonus state ST4 ends. The second section flag is set in the memory area corresponding to "0007" to "k-3". Since the second section flag is excluded from the execution target of the clearing process at the end of the bonus, it is possible to prevent the second section SC2 from ending when the pseudo bonus state ST4 ends and transitions to the AT state ST5. In addition, the memory areas corresponding to "0007" to "k-3" include a set number counter, an AT continuation counter, an AT state flag, a second output start flag, a state flag for preparing for ending, a flag for preparing for ending, and an external output end flag. Since these memory areas are excluded from the execution target of the clearing process at the end of the bonus, it is possible to prevent the information referenced after the pseudo bonus state ST4 ends from being erased when the pseudo bonus state ST4 ends. In addition, the memory areas corresponding to "0007" to "k-3" include a memory area in which information indicating whether or not a replay win has been established is stored. By excluding the memory area from the target for the clear process at the end of the bonus, if a replay win is made in the final game of the pseudo bonus state ST4, it is possible to prevent the profit from replay resulting from the replay win from being erased when the pseudo bonus state ST4 ends.

As described above, the bet number history counter 74f is set in the memory area corresponding to "k-2". The bet number history counter 74f is set with the value of the bet number setting counter 74a in step S911 in the normal processing (Figure 25), so that the bet number for the current game is stored in the bet number history counter 74f at the timing when the pseudo bonus processing (Figure 56) is executed. The clear processing at the end of the bonus (Figure 57) is executed in the pseudo bonus processing (Figure 56), and the pseudo bonus processing (Figure 56) is executed in the corresponding processing at the end of play (Figure 39). In the corresponding processing at the end of play (Figure 39), the second control processing (Figure 44) for the play section is executed after the pseudo bonus processing (Figure 56) is completed. As already explained, in the second control process (FIG. 44) of the game section, a process (steps S2007 to S2012) is executed to update the value of the total winnings counter 74d in accordance with the content of the current game in order to determine whether the ending condition of the second section SC2 is established. In step S2008 of the update process, a process is executed to subtract the number of bets for the current game from the value of the total winnings counter 74d. In this subtraction, the value of the bet number history counter 74f is subtracted from the value of the total winnings counter 74d. In this situation, since the bet number history counter 74f is excluded from the target of the clear process at the end of the bonus, even if the process of subtracting the number of bets for the current game from the value of the total winnings counter 74d is executed in the second control process (FIG. 44) of the game section after the clear process at the end of the bonus, the subtraction process can be performed appropriately.

The memory area corresponding to "k-1" has the number of awarded media history counter set as described above. The number of awarded media history counter is set with the value of the medium awarded counter in step S911 in the normal processing (Figure 25), so that the number of awarded media history counter stores the number of gaming media awarded in the current game at the timing when the pseudo bonus processing (Figure 56) is executed. The clear processing at the end of the bonus (Figure 57) is executed in the pseudo bonus processing (Figure 56), and the pseudo bonus processing (Figure 56) is executed in the corresponding processing at the end of the game (Figure 39), but in the corresponding processing at the end of the game (Figure 39), the second control processing (Figure 44) of the game section is executed after the pseudo bonus processing (Figure 56) is completed. In the second control process (FIG. 44) of the game section, as already explained, a process (steps S2007 to S2012) is executed to update the value of the total acquisition counter 74d in accordance with the content of the current game in order to determine whether the ending condition of the second section SC2 is established or not. In step S2010 of the update process, a process is executed to add the number of game media awarded in the current game to the value of the total acquisition counter 74d. In this addition, the value of the awarded number history counter is added to the value of the total acquisition counter 74d. In this situation, since the awarded number history counter is excluded from the execution target of the clear process at the end of the bonus, even if the process of adding the number of game media awarded in the current game to the value of the total acquisition counter 74d is executed in the second control process (FIG. 44) of the game section after the clear process at the end of the bonus is executed, the addition process can be performed appropriately.

On the other hand, when the pseudo bonus state ST4 ends, the memory areas corresponding to addresses "k" and after in the main RAM 74 are cleared to "0" and initialized. The memory area corresponding to "k" has the pseudo bonus state flag set as described above, and the memory area corresponding to "k+1" has the pseudo bonus continuation counter set as described above. In addition, the memory areas for addresses "k+4" and after include an area for storing information on the number of games mode and an area for storing information on the win rate mode. By including these memory areas as targets for the clearing process to be executed when the bonus ends, it becomes possible for the memory areas used in the pseudo bonus state ST4 to be cleared to "0" and initialized when the pseudo bonus state ST4 ends.

The memory area corresponding to "k+2" is set with the bet number setting counter 74a as described above, and the memory area corresponding to "k+3" is set with the medium giving counter as described above. As already explained, the bet number for one game is set in the bet number setting counter 74a, and the display content of the bet display unit 64 is the display content corresponding to the information stored in the bet number setting counter 74a. When the value of the bet number setting counter 74a is "0", all three light emitting parts of the bet display unit 64 are turned off. Also, as already explained, the number of game media given in one game is set in the medium giving counter, and the display content of the dual-purpose display unit 66 is the display content corresponding to the information stored in the medium giving counter in a situation where the notification of the stop order of the reels 32L, 32M, and 32R is not executed. When the value of the medium giving counter is "0" in a situation where the notification of the stop order of the reels 32L, 32M, and 32R is not executed, all the light emitting parts of the dual-purpose display unit 66 are turned off. In this configuration, the bet number setting counter 74a and the medium awarding counter are included in the targets of the clear process at the end of the bonus, so that the bet display unit 64 and the dual-purpose display unit 66 can be turned off when the pseudo bonus state ST4 ends. The bet display unit 64 remains turned off until the bet number setting counter 74a is set to a value of 1 or more, and the dual-purpose display unit 66 remains turned off until a new notification of the stop order of the reels 32L, 32M, and 32R is started or until the medium awarding counter is set to a value of 1 or more.

The timing of execution of various processes when the pseudo bonus state ST4 ends will be explained with reference to the time chart in Figure 58. Figure 58(a) shows the execution period of one game, Figure 58(b) shows the period in which the pseudo bonus state ST4 is in effect, Figure 58(c) shows the timing at which the history storage process (step S911) of the normal process (Figure 25) is executed, Figure 58(d) shows the timing at which the bet display unit 64 and the dual-purpose display unit 66 are completely turned off, and Figure 58(e) shows the timing at which the second control process (Figure 44) for the play area is executed.

In the pseudo bonus state ST4 as shown in FIG. 58(b), a new game is started at timing t1 as shown in FIG. 58(a). This game is the final game of the pseudo bonus state ST4. Then, at timing t2, which is the timing after the rotation of all reels 32L, 32M, and 32R in the current game has stopped and the medium granting process (step S910) of the normal process (FIG. 25) has ended, the history storage process (step S911) of the normal process (FIG. 25) is executed as shown in FIG. 58(c). As a result, the value of the bet number setting counter 74a of the master RAM 74 is set to the bet number history counter 74f of the master RAM 74, and the value of the medium granting counter of the master RAM 74 is set to the grant number history counter of the master RAM 74.

After that, at the timing of t3, the clear process (FIG. 57) at the end of the bonus in the pseudo bonus process (FIG. 56) is executed, and the pseudo bonus state flag in the main RAM 74 is cleared to "0". Therefore, the pseudo bonus state ST4 ends at the timing of t3, as shown in FIG. 58(b). Furthermore, in the clear process (FIG. 57) at the end of the bonus, the bet number setting counter 74a in the main RAM 74 is cleared to "0", and the medium award counter in the main RAM 74 is cleared to "0". Therefore, at the timing of t3, the bet display unit 64 and the dual-purpose display unit 66 are turned off, as shown in FIG. 58(d). Note that if the dual-purpose display unit 66 was already turned off, it will remain turned off.

In this way, when the pseudo bonus state ST4 ends, the bet display unit 64 and the combined display unit 66 turn off, making it easier for the player to recognize that the pseudo bonus state ST4 has ended. In addition, by checking whether the bet display unit 64 and the combined display unit 66 have turned off, the manager of the gaming hall can check whether a presentation indicating that the pseudo bonus state ST4 has ended and a transition to the AT state ST5 is occurring is legitimate when it is being executed on the image display device 63, which is display-controlled by the presentation side MPU 92.

After that, the second control process (FIG. 44) of the game section is executed at the timing of t4 as shown in FIG. 58(e). As described above, the history storage process (step S911) is executed at the timing of t2, which is the timing before the timing of t3 when the clear process (FIG. 57) is executed at the end of the bonus, so that the value of the bet number setting counter 74a of the main RAM 74 is set in the bet number history counter 74f of the main RAM 74, and the value of the medium grant counter of the main RAM 74 is set in the grant number history counter of the main RAM 74. Then, in the second control process (FIG. 44), a process is executed to update the value of the total acquisition number counter 74d using the information stored in the bet number history counter 74f and the grant number history counter. As a result, even if the configuration is such that the clear process (FIG. 57) is executed at the end of the bonus as described above, it is possible to appropriately update the value of the total acquisition number counter 74d. After that, as shown in FIG. 58(a), the current game ends at the timing of t5, and a new game starts at the timing of t6.

<About AT state ST5>
Next, the processing contents executed in the AT state ST5 will be described. Fig. 59 is a flowchart showing the processing for the AT state at the start of the game executed by the main MPU 72. As already explained, the processing for the AT state at the start of the game is executed in step S2704 in the processing for the advantageous state at the start of the game (Fig. 55).

First, it is determined whether or not either the first ending flag or the second ending flag of the master RAM 74 is set to "1" (step S3001). As already explained, the first ending flag is a flag for the master MPU 72 to identify that the number of games played in the second section SC2, measured using the continued game number counter 74c, has reached the upper limit number of games. As already explained, the second ending flag is a flag for the master MPU 72 to identify that the limited total net increase in the number of game media, measured using the total acquisition number counter 74d, is likely to reach the upper limit net increase. If either the first ending flag or the second ending flag is set to "1" (step S3001: YES), the processing from step S3002 onwards is not executed. As a result, in a situation where the number of games played in the second section SC2 has reached the upper limit number of games, or in a situation where the limited total net increase in the number of game media is likely to reach the upper limit net increase, the processing for adding the number of continued games or the number of sets in the AT state ST5 from step S3002 onwards is not executed.

If neither the first ending flag nor the second ending flag is set to "1" (step S3001: NO), the system determines whether the current state is the add-on period in the AT state ST5 by determining whether the value of the add-on period counter provided in the main RAM 74 is 1 or greater (step S3002). The add-on period counter is a counter that allows the main MPU 72 to determine whether the current state is the add-on period and the remaining number of games to be played during the add-on period.

If the value of the add-on period counter is "0" and it is not the add-on period (step S3002: NO), it is determined whether or not transition-compatible winning data is stored in the main RAM 74 (step S3003). The transition-compatible winning data is any one of the following: first watermelon winning data, second watermelon winning data, cherry winning data, first chance replay winning data, and second chance replay winning data. In other words, if the lottery process for the role in this game (Figure 34) results in a win with index value IV = 11 to 15, a positive determination is made in step S3003. If a positive determination is made in step S3003, a transition lottery process for the add-on period is executed (step S3004).

In the lottery process for transition to the top-up period, a lottery is used to determine by lottery whether or not to transition to an add-on period in which the remaining number of sets in AT state ST5 is more likely to be added on, using an add-on period transition lottery table provided in main ROM 73 and a lottery counter that is periodically updated in main RAM 74. In the lottery process for the roles in this game (FIG. 34), if the first watermelon winning data is stored in the main RAM 74 (if the index value IV=11 is won), there is a 10% chance of winning the transition to the added-on period; if the second watermelon winning data is stored in the main RAM 74 (if the index value IV=12 is won), there is a 5% chance of winning the transition to the added-on period; if the cherry winning data is stored in the main RAM 74 (if the index value IV=13 is won), there is a 20% chance of winning the transition to the added-on period; if the first chance replay winning data is stored in the main RAM 74 (if the index value IV=14 is won), there is a 15% chance of winning the transition to the added-on period; and if the second chance replay winning data is stored in the main RAM 74 (if the index value IV=15 is won), there is a 10% chance of winning the transition to the added-on period. In this case, the lower the probability of winning in the lottery process for the winning combination (FIG. 34), the higher the probability of winning during the transition period of the added-on period. This makes it possible to increase the advantage of winning an index value IV with a low probability of winning in the lottery process for the winning combination (FIG. 34).

If the transition to the added-on period is selected (step S3005: YES), an addition process for the number of continued games is executed (step S3006). In the addition process for the number of continued games, the number of games equal to or greater than the number of continued games for which the added-on period will continue is added to the value of the AT continuation counter in the main RAM 74. Specifically, the added-on period will continue for 10 games, and in step S3006, 20 games, which is the number of games equal to or greater than the 10 games, are added to the value of the AT continuation counter in the main RAM 74. This makes it possible to prevent the remaining number of continued games in the AT state ST5 from becoming "0" in the middle of the added-on period.

Then, a first addition command is sent to the presentation side MPU 92 (step S3007). The first addition command is a command for making the presentation side MPU 92 recognize that an addition of the number of games has occurred when transitioning to the addition period. The first addition command also contains information on the number of games that was the subject of the current addition, 20 games. When the presentation side MPU 92 receives the first addition command, it causes the upper lamp 61, speaker 62, and image display device 63 to execute a presentation indicating that an addition of the number of games has occurred when transitioning to the addition period. Then, it sets the addition winning flag provided in the main side RAM 74 to "1" (step S3008). The addition winning flag is a flag for the main side MPU 72 to identify that a win has been made for the transition to the addition period in the transition lottery process for the addition period (step S3004).

If the transition lottery process for the top-up period (step S3004) does not result in a win for the transition to the top-up period (step S3005: NO), the first top-up lottery process is executed (step S3009). In the first top-up lottery process, a lottery is used to determine whether or not to generate a top-up that will increase the remaining number of sets in the AT state ST5, using the first top-up lottery table provided in the main ROM 73 and the lottery counter that is regularly updated in the main RAM 74. If the first watermelon winning data is stored in the main RAM 74 (if the index value IV = 11 is won), one set of top-up is selected with a 10% probability, two sets of top-up is selected with a 10% probability, and there is an 80% probability of a miss. If the second watermelon winning data is stored in the main RAM 74 (if the index value IV = 12 is won), one set of top-up is selected with a 5% probability, two sets of top-up is selected with a 5% probability, and there is a 90% probability of a miss. When cherry winning data is stored in the main RAM 74 (when the index value IV=13 is won), one set of added bonuses is selected with a probability of 20%, two sets of added bonuses are selected with a probability of 20%, and a miss is generated with a probability of 60%. When first chance replay winning data is stored in the main RAM 74 (when the index value IV=14 is won), one set of added bonuses is selected with a probability of 15%, two sets of added bonuses are selected with a probability of 15%, and a miss is generated with a probability of 70%. When second chance replay winning data is stored in the main RAM 74 (when the index value IV=15 is won), one set of added bonuses is selected with a probability of 10%, two sets of added bonuses are selected with a probability of 10%, and a miss is generated with a probability of 80%. In this case, the lower the index value IV is in the winning probability in the role selection process (FIG. 34), the higher the probability of added bonuses being selected. In addition, the lower the probability of winning in the lottery process for the winning combination (FIG. 34) for an index value IV, the higher the expected number of sets to be added. This makes it possible to increase the advantage of winning an index value IV with a low probability of winning in the lottery process for the winning combination (FIG. 34).

If either one set of addition or two sets of addition is selected in the first add-on lottery process (step S3009) and an addition win is obtained (step S3010: YES), an addition process for the number of sets is executed (step S3011). In the addition process for the number of sets, the number of sets selected in the first add-on lottery process (step S3009) is added to the set number counter in the main RAM 74. Then, a second addition command is sent to the production side MPU 92 (step S3012). The second addition command is a command for making the production side MPU 92 recognize that an addition win has been obtained in the first add-on lottery process (step S3009) and the number of added sets selected in the first add-on lottery process (step S3009), and the second addition command includes information corresponding to the number of added sets selected in the first add-on lottery process (step S3009). When the performance side MPU 92 receives the second addition command, it causes the upper lamp 61, speaker 62, and image display device 63 to execute a performance indicating that an increase in the number of sets has occurred.

If the value of the top-up period counter in the main RAM 74 is 1 or more and is in the top-up period (step S3002: YES), a second top-up lottery process is executed (step S3013). In the second top-up lottery process, the number of sets to be added to the remaining number of sets in the AT state ST5 is determined by lottery using a second top-up lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74.

In the second add-on lottery process (step S3013), if an index value IV other than index value IV=11 to 15 is selected, one add-on set is selected with an 80% probability, two add-on sets are selected with a 10% probability, and three add-on sets are selected with a 10% probability. If the first watermelon winning data is stored in the main RAM 74 (if an index value IV=11 is selected), one add-on set is selected with a 50% probability, two add-on sets are selected with a 25% probability, and three add-on sets are selected with a 25% probability. If the second watermelon winning data is stored in the main RAM 74 (if an index value IV=12 is selected), one add-on set is selected with a 60% probability, two add-on sets are selected with a 20% probability, and three add-on sets are selected with a 20% probability. When cherry winning data is stored in the main RAM 74 (when the index value IV=13 is won), one set of added bonus is selected with a probability of 20%, two sets of added bonus is selected with a probability of 40%, and three sets of added bonus is selected with a probability of 40%. When first chance replay winning data is stored in the main RAM 74 (when the index value IV=14 is won), one set of added bonus is selected with a probability of 30%, two sets of added bonus is selected with a probability of 35%, and three sets of added bonus is selected with a probability of 35%. When second chance replay winning data is stored in the main RAM 74 (when the index value IV=15 is won), one set of added bonus is selected with a probability of 50%, two sets of added bonus is selected with a probability of 25%, and three sets of added bonus is selected with a probability of 25%. In this case, the lower the probability of winning in the role lottery process (FIG. 34), the higher the expected number of sets to be added. This makes it possible to increase the advantage of winning an index value IV, which has a low probability of winning, during the role selection process (Figure 34).

Then, an addition process for the number of sets is executed (step S3014). In the addition process for the number of sets, the number of sets selected in the second add-on lottery process (step S3013) is added to the set number counter in the main RAM 74. Then, a third addition command is sent to the production side MPU 92 (step S3015). The third addition command is a command for causing the production side MPU 92 to recognize the number of sets selected in the second add-on lottery process (step S3013), and the third addition command includes information corresponding to the added number of sets selected in the second add-on lottery process (step S3013). When the production side MPU 92 receives the third addition command, it causes the upper lamp 61, speaker 62, and image display device 63 to perform a performance indicating that the number of sets has been added.

Figure 60 is a flowchart showing the AT processing executed by the main MPU 72. The AT processing is executed in step S1806 in the response processing at the end of play (Figure 39). As described above, the response processing at the end of play is executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game, so the AT processing is also executed after all of the reels 32L, 32M, and 32R have stopped spinning in one game.

First, it is determined whether the number of bets for the current game is "3" by determining whether the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S3101). If the number of bets for the current game is "2" (step S3101: NO), the processing from step S3102 onwards is not executed. As a result, even if a game with the number of bets of "2" is executed in the AT state ST5, the remaining number of continued games in the AT state ST5 is not subtracted, and furthermore, the remaining number of continued games in the added period in the AT state ST5 is not subtracted.

Note that when in the CB state (first CB state ST2 or second CB state ST3), the AT processing (Figure 60) itself is not executed, so even if the CB state is started in the middle of the AT state ST5, the number of games executed in the CB state is not treated as the number of games played in the AT state ST5. Therefore, even if the AT state is transitioned to the CB state in the middle of the AT state ST5, after the CB state ends, the AT state ST5 will resume from the state of the remaining number of continued games immediately before transitioning to the CB state.

If the number of bets for the current game is "3" (step S3101: YES), the value of the AT continuation counter in the main RAM 74 is decremented by 1 (step S3102). After that, it is determined whether the value of the top-up period counter in the main RAM 74 is 1 or greater, thereby determining whether the current time is the top-up period (step S3103).

If the value of the added-on period counter is "0" and it is not the added-on period (step S3103: NO), it is determined whether the added-on winning flag in the main RAM 74 is set to "1" (step S3104). If the added-on period transition lottery process (step S3004) at the start of the current game results in a win for the transition to the added-on period, the added-on winning flag is set to "1".

If the add-on winning flag is set to "1" (step S3104: YES), the setting process for the add-on period is executed (step S3105). In the setting process for the add-on period, the add-on period counter in the main RAM 74 is set to a value corresponding to 10 games, which is the initial number of continuing games for the add-on period. After that, the add-on winning flag is cleared to "0" (step S3106), and then a start command for the add-on period is sent to the presentation side MPU 92 (step S3107). The start command for the add-on period is a command for making the presentation side MPU 92 recognize that the add-on period has started. When the presentation side MPU 92 receives the start command for the add-on period, it causes the upper lamp 61, speaker 62, and image display device 63 to execute a presentation indicating that the add-on period has started and a presentation indicating that the add-on period is in progress.

If the value of the added-on period counter is 1 or more and is in the added-on period (step S3103: YES), the value of the added-on period counter is decremented by 1 (step S3108). Then, if the value of the added-on period counter after decrementing by 1 becomes "0" (step S3109: YES), an end command for the added-on period is sent to the production side MPU 92 (step S3110). The end command for the added-on period is a command for making the production side MPU 92 recognize that the added-on period has ended. When the production side MPU 92 receives the end command for the added-on period, it causes the upper lamp 61, speaker 62, and image display device 63 to execute a performance indicating that the added-on period has ended.

If a negative judgment is made in step S3104, if the processing of step S3107 is executed, if a negative judgment is made in step S3109, or if the processing of step S3110 is executed, it is determined whether the value of the AT continuation counter in the main RAM 74 is "0" (step S3111). If the value of the AT continuation counter is "0" (step S3111: YES), the value of the set number counter in the main RAM 74 is decremented by 1 (step S3112). Then, it is determined whether the value of the set number counter after the decrement is "0" (step S3113).

If the value of the set count counter is 1 or more (step S3113: NO), a process is executed to start a new set in AT state ST5. Specifically, first, the AT continuation counter in the main RAM 74 is set to "50" as the initial number of continuing games for the new set (step S3114). Then, an AT continuation command is sent to the presentation side MPU 92 (step S3115). The AT continuation command is a command for making the presentation side MPU 92 recognize that a new set in AT state ST5 has started. When the presentation side MPU 92 receives the AT continuation command, it causes the upper lamp 61, speaker 62, and image display device 63 to display a presentation indicating that a new set in AT state ST5 has started.

Then, the third output start flag stored in the main RAM 74 is set to "1" (step S3116). The third output start flag is a flag for the main MPU 72 to identify a situation in which an external output corresponding to the start of a new set of the AT state ST5 should be executed.

If the value of the set count counter is "0" (step S3113: YES), a process for setting the end preparation state ST6 is executed (step S3117). In this process, the end preparation state flag in the main RAM 74 is set to "1". The end preparation state flag is a flag that the main MPU 72 uses to identify the end preparation state ST6, and setting the end preparation state flag to "1" changes the game state to the end preparation state ST6. In addition, the end preparation complete flag in the main RAM 74 is cleared to "0" (step S3118). As already explained, the end preparation complete flag is a flag that the main MPU 72 uses to identify whether or not one game has been played in the end preparation state ST6.

As already explained, in the end preparation state ST6, if a positive judgment is made in step S2002 in the second control process for the game section (FIG. 44) and the end preparation complete flag is not set to "1" (step S2003: NO), the end preparation complete flag is set to "1" and then processing is executed to determine whether the ending condition for the second section SC2 is met, and the second control process for the game section in the current game (FIG. 44) is terminated. On the other hand, if the end preparation complete flag is set to "1" (step S2003: YES), processing is executed to terminate the second section SC2 and transition to the first section SC1 (steps S2014 to S2016). As a result, the second section SC2 ends when the game following the game in which the AT state ST5 has ended ends.

After executing the process of step S3118 in the AT process (FIG. 60), the AT state flag in the main RAM 74 is cleared to "0" (step S3119). This ends the AT state ST5, and the game state becomes the normal game state ST1. In addition, an AT end command indicating that the AT state ST5 has ended is sent to the presentation side MPU 92 (step S3120). When the presentation side MPU 92 receives the AT end command, it causes the upper lamp 61, speaker 62, and image display device 63 to perform a presentation indicating that the AT state ST5 has ended. After that, it sets the external output end flag in the main RAM 74 to "1" (step S3121). The external output end flag is a flag for the main MPU 72 to identify that the current situation is an external output state that corresponds to the end of the pseudo bonus state ST4 or the AT state ST5 and the transition to the normal game state ST1.

<External output setting process>
Next, the external output setting process executed in step S913 of the normal process (FIG. 25) will be described. The external output setting process is executed after the rotation of all the reels 32L, 32M, and 32R has stopped and the process for changing the game state in the game end response process (FIG. 39) has been completed.

In the external output setting process, a process is executed to output an external signal to the gaming hall's management computer through each output terminal provided on the external output terminal board 78. The external output terminal board 78 is provided with a first output terminal and a second output terminal.

The first output terminal and the main MPU 72 are electrically connected through a first signal path, and when a first external signal of HI level is sent from the main MPU 72 through the first signal path, the first external signal of HI level is sent to the management computer of the game hall through the first output terminal. Details will be described later, but in the pseudo bonus state ST4, the first external signal becomes HI level, and also when one set of the AT state ST5 continues, the first external signal becomes HI level, and otherwise the first external signal becomes LOW level. The management computer of the game hall determines that the slot machine 10 is in the pseudo bonus state ST4 or the AT state ST5 by determining that the first external signal output from the slot machine 10 is at HI level, and can determine the total number of times that the pseudo bonus state ST4 has occurred and the number of times that the set of the AT state ST5 has occurred in the slot machine 10 by measuring the number of times that the output state of the first external signal has switched from LOW level to HI level.

The second output terminal and the main MPU 72 are electrically connected through a second signal path, and when a second external signal of HI level is sent from the main MPU 72 through the second signal path, the second external signal of HI level is sent to the management computer of the game hall through the second output terminal. Details will be described later, but when a transition from the pseudo bonus state ST4 to the AT state ST5 occurs, the second external signal becomes HI level, and otherwise the second external signal becomes LOW level. The management computer of the game hall determines that the slot machine 10 has transitioned from the pseudo bonus state ST4 to the AT state ST5 by determining that the second external signal output from the slot machine 10 is HI level, and can determine the number of times that the slot machine 10 has transitioned from the pseudo bonus state ST4 to the AT state ST5 by measuring the number of times the output state of the second external signal has switched from LOW level to HI level.

Figure 61 is a flowchart showing the external output setting process.

First, it is determined whether the first output start flag in the main RAM 74 is set to "1" (step S3201). As already explained, the first output start flag is set to "1" when the game state transitions from the normal game state ST1 to the pseudo bonus state ST4. If the first output start flag is set to "1" (step S3201: YES), the first output start flag is cleared to "0" (step S3202). Then, the output timing counter provided in the main RAM 74 is set to "1" (step S3203). The output timing counter is a counter for the main MPU 72 to specify whether or not the first external signal needs to be changed from a LOW level to a HI level, and is also a counter for the main MPU 72 to specify the timing for changing the first external signal from a LOW level to a HI level. Details will be described later, but by setting the output timing counter to "1", the first external signal is switched from a LOW level to a HI level at the end of the current game.

In the external output setting process, it is determined whether the second output start flag in the main RAM 74 is set to "1" (step S3204). As already explained, the second output start flag is set to "1" when the game state transitions from the pseudo bonus state ST4 to the AT state ST5. If the second output start flag is set to "1" (step S3204: YES), the second output start flag is cleared to "0" (step S3205). Then, the output timing counter in the main RAM 74 is set to "2" (step S3206). As will be described in detail later, by setting the output timing counter to "2", the first external signal is switched from HI level to LOW level at the end of the current game, and further the first external signal is switched from LOW level to HI level at the end of the next game.

Then, the second external signal is set to ON (step S3207). In this ON setting process, the output state of the second external signal is switched from LOW level to HIGH level. This causes a HIGH level second external signal to be sent from the main MPU 72 to the second output terminal via the second signal path, and the HI level second external signal is output to the amusement hall's management computer via the second output terminal.

In the external output setting process, it is determined whether the third output start flag in the main RAM 74 is set to "1" (step S3208). As already explained, the third output start flag is set to "1" when a new set of AT state ST5 is started. If the third output start flag is set to "1" (step S3208: YES), the third output start flag is cleared to "0" (step S3209). Then, the output timing counter in the main RAM 74 is set to "2" (step S3210). As will be described in detail later, by setting the output timing counter to "2", the first external signal is switched from HI level to LOW level at the end of the current game, and further the first external signal is switched from LOW level to HI level at the end of the next game.

In the external output setting process, steps S3201 to S3210 are executed, and then external output processing is executed (step S3211). Figure 62 is a flowchart showing external output processing.

If the value of the output timing counter in the main RAM 74 is 1 or more (step S3301: YES), the value of the output timing counter is decremented by 1 (step S3302). Then, it is determined whether the value of the output timing counter after decrementing by 1 is "1" (step S3303). The value of the output timing counter after decrementing by 1 is "1" when the output timing counter is set to "2" in step S3206 of the external output setting process (FIG. 61) when a transition from the pseudo bonus state ST4 to the AT state ST5 occurs, or when the output timing counter is set to "2" in step S3210 of the external output setting process (FIG. 61) when a new set of the AT state ST5 is started.

If the value of the output timing counter after subtracting 1 is "1" (step S3303: YES), the first external signal is set to OFF (step S3304), and then the external output process is terminated. In the OFF setting process, the output state of the first external signal is switched from HI level to LOW level. As a result, a LOW level first external signal is sent from the main MPU 72 to the first output terminal via the first signal path, and a LOW level first external signal is output to the amusement hall's management computer via the first output terminal.

If the value of the output timing counter after subtracting 1 is not "1", it means that the value of the output timing counter is "0". This is because the output timing counter is set to "1" or "2" in the external output setting process (Figure 61). When the value of the output timing counter after subtracting 1 is "0", this corresponds to the case where a transition from the normal game state ST1 to the pseudo bonus state ST4 has occurred in the current game, and the output timing counter has been set to "1" in the current processing of the external output setting process (Figure 61). In addition, this also applies when the output timing counter is set to "2" in the previous processing of the external output setting process (FIG. 61) due to a transition from the pseudo bonus state ST4 to the AT state ST5 in the previous game, or when a new set of the AT state ST5 is started in the previous game and the output timing counter is set to "2" in the previous processing of the external output setting process (FIG. 61), and the first game is played in the AT state ST5 transitioned from the pseudo bonus state ST4, or the first game is played in the new set of the AT state ST5.

If the value of the output timing counter is "0" (step S3303: NO), an OFF setting process for the second external signal is executed (step S3305). In this OFF setting process, the output state of the second external signal is switched from HI level to LOW level. As a result, a LOW level second external signal is sent from the main MPU 72 to the second output terminal via the second signal path, and a LOW level second external signal is output to the amusement hall's management computer via the second output terminal. Note that if the output state of the second external signal is already LOW level, the LOW level state is maintained.

After that, the first external signal is set to ON (step S3306), and then this external output process is terminated. In this ON setting process, the output state of the first external signal is switched from LOW level to HIGH level. This causes a HIGH level first external signal to be sent from the main MPU 72 to the first output terminal via the first signal path, and the HIGH level first external signal is output externally to the amusement hall's management computer via the first output terminal.

In the external output process, if it is determined in step S3301 that the value of the output timing counter is "0", it is determined whether the external output end flag in the main RAM 74 is set to "1" (step S3307). As already explained, the external output end flag is set to "1" when the pseudo bonus state ST4 or the AT state ST5 ends and transitions to the normal game state ST1 occurs. If the external output end flag is set to "1" (step S3307: YES), the external output end flag is cleared to "0" (step S3308). Then, after executing the OFF setting process of the first external signal (step S3309), this external output process is terminated. In the OFF setting process, the output state of the first external signal is switched from HI level to LOW level. As a result, a first external signal of LOW level is sent from the main MPU 72 to the first output terminal via the first signal path, and the first external signal of LOW level is output externally to the management computer of the amusement hall via the first output terminal.

Next, the manner in which the output modes of the first external signal and the second external signal are appropriately changed will be described with reference to the time chart in FIG. 63. FIG. 63(a) shows the execution period of one game, FIG. 63(b) shows the period in the normal game state ST1, FIG. 63(c) shows the period in the pseudo bonus state ST4, FIG. 63(d) shows the period in the AT state ST5, FIG. 63(e) shows the timing when a new set starts in the AT state ST5, FIG. 63(f) shows the timing when one set ends in the AT state ST5, FIG. 63(g) shows the output state of the first external signal, and FIG. 63(h) shows the output state of the second external signal.

In a situation where the game is in the normal game state ST1 as shown in FIG. 63(b), a new game is started at the timing of t1 as shown in FIG. 63(a). This game is a game that triggers a transition from the normal game state ST1 to the pseudo bonus state ST4. Therefore, at the end of this game, the game state transitions from the normal game state ST1 to the pseudo bonus state ST4 as shown in FIG. 63(b) and FIG. 63(c). In addition, since "1" is set to the output timing counter of the main RAM 74 in step S3203 of the external output setting process (FIG. 61) in this game, the value of the output timing counter is decremented by 1 in step S3302 in the external output process (FIG. 62), and the value of the output timing counter after the decrement becomes "0", so that the ON setting process (step S3306) of the first external signal is executed. Therefore, at the timing of t2, the state of the external output of the first external signal is switched from LOW level to HI level as shown in FIG. 63(g).

After that, in a situation where the pseudo bonus state ST4 continues as shown in FIG. 63(c), multiple games are repeatedly executed including the timing of t3 to the timing of t4 and the timing of t5 to the timing of t6 as shown in FIG. 63(a). Then, the game from the timing of t5 to the timing of t6 becomes the last game in the pseudo bonus state ST4. Since the transition condition to the AT state ST5 is established in the pseudo bonus state ST4, the game state transitions from the pseudo bonus state ST4 to the AT state ST5 at the timing of t6 as shown in FIG. 63(c) and FIG. 63(d). In addition, since "2" is set to the output timing counter of the main RAM 74 in step S3206 of the external output setting process (FIG. 61) in the game, in step S3302 in the external output process (FIG. 62), the value of the output timing counter is decremented by 1, and since the value of the output timing counter after the decrement is "1", the OFF setting process (step S3304) of the first external signal is executed. Therefore, at the timing t6, the external output state of the first external signal is switched from HI to LOW as shown in Figure 63(g). Also, since the ON setting process of the second external signal is executed in step S3207 of the external output setting process (Figure 61) in the game, at the timing t6, the external output state of the second external signal is switched from LOW to HI as shown in Figure 63(h).

Then, as shown in FIG. 63(a), at the timing of t7, the first game in the AT state ST5 started this time is started. In this case, at the timing of t7, a new set of AT state ST5 is started as shown in FIG. 63(e). Then, as shown in FIG. 63(a), the first game ends at the timing of t8. In this case, when the external output setting process (FIG. 61) at the end of the game is started, the value of the output timing counter of the main RAM 74 is "1". Therefore, in the external output process (FIG. 62), the value of the output timing counter is decremented by 1 in step S3302, and the value of the output timing counter after the decrement becomes "0", so that the second external signal OFF setting process (step S3305) and the first external signal ON setting process (step S3306) are executed. Therefore, at timing t8, the state of the external output of the second external signal is switched from HI level to LOW level as shown in FIG. 63(h), and the state of the external output of the first external signal is switched from LOW level to HI level as shown in FIG. 63(g).

In other words, when a transition from the pseudo bonus state ST4 to the AT state ST5 occurs, first, at the end of the final game in the pseudo bonus state ST4, the output state of the first external signal is switched from the previous HI level to the LOW level, and the output state of the second external signal is switched from the previous LOW level to the HI level. Then, when the first game in the AT state ST5 is started and the game ends, the output state of the second external signal is switched from the previous HI level to the LOW level, and the output state of the first external signal is switched from the previous LOW level to the HI level. By determining that an output period of the first external signal at a HI level has occurred, sandwiched between an output period of the second external signal at a HI level, the management computer of the game hall can determine that the pseudo bonus state ST4 has ended and the AT state ST5 has started anew in the slot machine 10.

In addition, from the end of the final game in the pseudo bonus state ST4 to the end of the first game in the AT state ST5, the first external signal is maintained at a LOW level and the second external signal is maintained at a HI level. This makes it possible to set the period during which the first external signal is maintained at a LOW level and the period during which the second external signal is maintained at a HI level to a period longer than the shortest period required to execute one game. This makes it possible to reduce the possibility that the gaming hall's management computer will overlook the occurrence of a period during which the first external signal is output at a HI level, sandwiched between a period during which the second external signal is output at a HI level.

After that, as shown in FIG. 63(a), at the timing of t9, the final game of the current set in the AT state ST5 starts. Then, at the timing of t10, as shown in FIG. 63(a) and FIG. 63(f), the final game of the current set ends. In this case, in the external output setting process (FIG. 62), the output timing counter of the main RAM 74 is set to "2" in step S3210, so in the external output process (FIG. 62), the value of the output timing counter is decremented by 1 in step S3302, and since the value of the output timing counter after the decrement is "1", the OFF setting process (step S3304) of the first external signal is executed. Therefore, at the timing of t10, the state of the external output of the first external signal is switched from HI level to LOW level as shown in FIG. 63(g).

Then, as shown in FIG. 63(a) and FIG. 63(e), the first game of a new set in AT state ST5 starts at timing t11. Then, as shown in FIG. 63(a), the first game ends at timing t12. In this case, when the external output setting process (FIG. 61) at the end of the game starts, the value of the output timing counter in the main RAM 74 is "1". Therefore, in the external output process (FIG. 62), the value of the output timing counter is decremented by 1 in step S3302, and the value of the output timing counter after the decrement becomes "0", so the ON setting process (step S3306) of the first external signal is executed. Therefore, at timing t12, the state of the external output of the first external signal is switched from LOW level to HI level as shown in FIG. 63(g).

In other words, when one set of the AT state ST5 ends and a new set begins, the output state of the first external signal is switched from the previous HI level to the LOW level at the end of the final game of the ending set. In this case, the output state of the second external signal is maintained at the LOW level. Then, when the first game of a new set in the AT state ST5 begins and ends, the output state of the first external signal is switched from the previous LOW level to the HI level. In this situation where the second external signal is maintained at the LOW level, the gaming hall's management computer can determine that a new set of the AT state ST5 has begun in the slot machine 10 by grasping that the first external signal has been switched from the HI level to the LOW level once, and then switched from the LOW level to the HI level again.

The first external signal is maintained at a LOW level from the end of the final game of one set in the AT state ST5 to the end of the first game in a new set in the AT state ST5. This makes it possible to set the period during which the first external signal is maintained at a LOW level to a period equal to or longer than the shortest period required to execute one game. This reduces the possibility that the gaming hall's management computer will miss the fact that the first external signal is switched from a HI level to a LOW level once and then switched back from a LOW level to a HIGH level again while the second external signal is maintained at a LOW level.

After that, at times t13 to t16, similar to the times t9 to t12 described above, when one set in the AT state ST5 ends and a new set of the AT state ST5 starts, while the second external signal is maintained at a LOW level, the first external signal is switched from a HI level to a LOW level once, and then switched from a LOW level to a HIGH level again.

After that, as shown in FIG. 63(a), at the timing of t17, the final game of the current set in the AT state ST5 is started. Then, as shown in FIG. 63(a) and FIG. 63(f), at the timing of t18, the final game of the current set is ended. When the set is ended, the number of remaining sets in the AT state ST5 is "0". Therefore, as shown in FIG. 63(b) and FIG. 63(d), the AT state ST5 ends at the timing of t18, and the game state becomes the normal game state ST1. When the AT state ST5 ends, the external output end flag of the main RAM 74 is set to "1", so that the external output process (FIG. 62) executes the OFF setting process of the first external signal (step S3309). Therefore, at the timing of t18, the state of the external output of the first external signal is switched from the HI level to the LOW level as shown in FIG. 63(g). This enables the management computer of the game hall to determine that one set of the AT state ST5 has ended in the slot machine 10. After that, as shown in FIG. 63(a), the first game in normal gaming state ST1 is played from timing t19 to timing t20.

The present embodiment described above provides the following excellent advantages:

In a configuration in which the main MPU 72 executes power failure processing based on the fact that the output level of the power failure signal has become LOW, when the supply of operating power to the main MPU 72 is started, the processing is put on hold until it is confirmed that the output level of the power failure signal is HIGH. This makes it possible to prevent processing from proceeding even if the reception status of the power failure signal is not stable when the supply of operating power is started. Therefore, it is possible to prevent a situation in which processing is not executed at an unexpected timing due to the output level of the power failure signal becoming LOW due to the reception status of the power failure signal being unstable when processing is progressing when the supply of operating power is started. Therefore, it is possible to preferably execute processing when the supply of operating power is started.

In a configuration in which power failure processing is executed based on the determination in the timer interrupt processing (FIG. 19) that the output level of the power failure signal is at a LOW level, when the supply of operating power begins and before the execution of the timer interrupt processing (FIG. 19) is permitted, the processing is put on hold until the main processing (FIG. 10) determines that the output level of the power failure signal is at a HIGH level. This makes it possible to prevent the timer interrupt processing (FIG. 19) from determining whether the output level of the power failure signal is at a LOW level before the reception of the power failure signal has stabilized.

In addition, in this state where processing is waiting to proceed, it is confirmed whether the output level of the power failure signal has become HI level during processing in the state where processing is waiting to proceed, and the state where processing is waiting to proceed is released based on confirmation that the output level of the power failure signal has become HI level. As a result, even if the configuration does not execute timer interrupt processing (FIG. 19) while processing is waiting to proceed, it is possible to determine whether the reception status of the power failure signal has stabilized, and it is possible to allow processing to proceed when the reception status of the power failure signal is stable.

After the information abnormality flag 74g, which is a flag for the main MPU 72 to determine whether an information abnormality has occurred in the main RAM 74, is set to "1", an abnormality detection process is executed to perform various determinations as to whether an information abnormality has occurred in the main RAM 74. If the abnormality detection process determines that an information abnormality has occurred in the main RAM 74, the information abnormality flag 74g is maintained in a state in which it is set to "1", and if the abnormality detection process determines that no information abnormality has occurred in the main RAM 74, the information abnormality flag 74g is cleared to "0". If the information abnormality flag 74g is maintained in a state in which it is set to "1", an operation prohibition process is executed, and if the value of the information abnormality flag 74g is "0", a process is started to proceed with the game without executing the operation prohibition process. In this way, by first setting the information abnormality flag 74g to "1" and then clearing the information abnormality flag 74g to "0" if it is determined that no information abnormality has occurred in the main RAM 74, it is possible to execute the operation prohibition process if various determinations as to whether or not an information abnormality has occurred in the main RAM 74 are not made due to the occurrence of electrical noise, even though an information abnormality has actually occurred.

In a configuration in which the information abnormality in the main RAM 74 is set to "1" for the power outage flag, the checksum does not match, and the setting value is abnormal, and operation prohibition processing is executed even if any of these information abnormalities occur, the information abnormality flag 74g is set to "1" before the process of determining whether or not each of these information abnormalities has occurred is executed, and the information abnormality flag 74g is cleared to "0" based on the determination that none of the above information abnormalities have occurred. This makes it possible to reduce the required storage capacity compared to a configuration in which an information abnormality flag 74g is provided corresponding to each of the above information abnormalities.

In a configuration in which the setting change process (FIG. 15) is executed if a setting change operation is being performed when the supply of operating power is started, even if the information anomaly flag 74g is set to "1", execution of the setting change process is prioritized over execution of the operation prohibition process if a setting change operation is being performed. This makes it possible to prioritize execution of the setting change process (FIG. 15) in response to the occurrence of a setting change operation.

In the setting change process (Figure 15), a process of clearing the main RAM 74 is executed. When this clear process is executed, the information abnormality flag 74g is also cleared to "0". This makes it possible to ensure that even if the information abnormality flag 74g is set to "1" before the setting change process (Figure 15) is executed, the information abnormality flag 74g is not set to "1" after the setting change process (Figure 15) is executed.

In a configuration in which execution of the setting change process (FIG. 15) is prioritized even when the information abnormality flag 74g is set to "1", when the setting change process (FIG. 15) is executed, if the information abnormality flag 74g is set to "1", the number of memory areas of the main RAM 74 that are the target of the clear process will be greater than when the information abnormality flag 74g is not set to "1". More specifically, when the information abnormality flag 74g is not set to "1", some memory areas of the main RAM 74 are not the target of the clear process, whereas when the information abnormality flag 74g is set to "1", all memory areas of the main RAM 74 are the target of the clear process. This makes it possible to carefully clear the main RAM 74 in the setting change process (FIG. 15) when an information abnormality occurs in the main RAM 74.

All memory areas of the main RAM 74 are subject to the clear process not only when the information abnormality flag 74g is set to "1" but also when the supply of operating power is started and the reset button 56 is turned ON in addition to the setting change operation. This makes it possible to execute the clear process on all memory areas of the main RAM 74 when the supply of operating power is started and the administrator of the game hall not only changes the setting but also presses the reset button 56.

In the setting change execution process (FIG. 18), the processes of steps S402 and S406 are executed, so that an interrupt waiting period, which is a period for waiting for the progress of the process until the timer interrupt process (FIG. 19) is newly executed, occurs twice from the start of the setting change execution process (FIG. 18) until the start of the first determination process of whether the pressing operation of the reset button 56 has started. By setting these interrupt waiting periods, even if the supply of operating power to the main MPU 72 is started when the reset button 56 is pressed and the setting change execution process (FIG. 18) is started in a situation where the pressing operation of the reset button 56 is maintained, the contents of the information in the previous reset memory area 74i and the current reset memory area 74h indicate that the pressing operation of the reset button 56 is continuing from the start of the setting change execution process (FIG. 18) until the start of the first determination process of whether the pressing operation of the reset button 56 has started. Therefore, in step S409, it is not determined that the pressing operation of the reset button 56 has started. This makes it possible to prevent the setting value that is the selection target from being changed by maintaining the reset button 56 pressed when the supply of operating power is started while the reset button 56 is pressed.

Whether the reset button 56 has been pressed is grasped by the sensor monitoring process (FIG. 20), and the results of the multiple grasps are stored in the current reset state storage area 74h and the previous reset state storage area 74i. Then, when the contents of the information stored in the current reset state storage area 74h and the previous reset state storage area 74i correspond to the start of the operation of the reset button 56, the setting value of the selection target is changed. This makes it possible to update the setting value of the selection target once for one pressing operation of the reset button 56. In this case, before the process for identifying whether the reset button 56 has been pressed in the setting change process (FIG. 15) is first executed, information corresponding to the operation state of the reset button 56 is set in each of the current reset state storage area 74h and the previous reset state storage area 74i, so that when the setting change process (FIG. 15) is started in a situation where the operation of the reset button 56 is continuing, the setting value that is the selection target is not updated by the operation of the reset button 56. In other words, with a simple configuration that ensures that the sensor monitoring process (FIG. 20) in the timer interrupt process (FIG. 19) is executed before the process for determining whether or not the reset button 56 has been pressed is executed for the first time in the setting change process (FIG. 15), it is possible to prevent the setting value that is the selection target from being updated by pressing the reset button 56 if the setting change process (FIG. 15) is started while the reset button 56 is still being pressed.

In a configuration in which a clear process is performed on the storage area of the main RAM 74 when the setting change process (FIG. 15) is performed to change the setting value to be used, reset state information that is neither open nor closed is stored in the door state area 74e when the setting change execution process (FIG. 18) is completed. As a result, if the front door 12 is in an open state when the setting change execution process (FIG. 18) is completed, the setting change notification ends and then the door open notification starts. Also, if the front door 12 is in a closed state when the setting change execution process (FIG. 18) is completed, the setting change notification ends and then the door closed notification starts. Therefore, when the setting change execution process (FIG. 18) is completed, it is possible to execute either the door open notification or the door closed notification following the setting change notification. Therefore, it is possible to reliably notify that the front door 12 is in an open state or that the front door 12 is in a closed state.

When the memory area of the main RAM 74 is cleared during the setting change process (Figure 15), reset state information different from the closed information is set in the door status area 74e. As a result, even if an act of fraudulently executing the setting change process (Figure 15) while maintaining the front door 12 in a closed state is performed, in this case even if the front door 12 is maintained in a closed state, the memory area of the main RAM 74 is cleared and reset state information is set in the door status area 74e, and then it is determined that the front door 12 is in a closed state, and a notification that the front door 12 is in a closed state is issued. This makes it possible to deal with such fraudulent acts.

The bet number stored in the bet number setting counter 74a is displayed on the bet display unit 64, so the player can know the bet number by checking the bet display unit 64. In this case, after the reels 32L, 32M, and 32R have all stopped spinning in the final game in the pseudo bonus state ST4 and before the second control process (FIG. 44) of the play area is executed, the bonus end clear process (FIG. 57) is executed, and the bet number information stored in the bet number setting counter 74a is erased. By erasing the bet number information in the bet number setting counter 74a, the bet display unit 64 is turned off. This makes it possible to notify that the final game in the pseudo bonus state ST4 has ended, and makes it possible to make the notification early when the reels 32L, 32M, and 32R have all stopped spinning in the final game.

In addition, in the final game of the pseudo bonus state ST4, before the information on the number of bets in the bet number setting counter 74a is erased, the information on the number of bets in the bet number setting counter 74a is stored in the bet number history counter 74f, and in the second control process (FIG. 44) of the play section, a process is executed to update the value of the total winning number counter 74d using the information on the number of bets stored in the bet number history counter 74f. This makes it possible to update the value of the total winning number counter 74d using the information on the number of bets after all of the reels 32L, 32M, and 32R have stopped spinning, while making it possible to turn off the bet display unit 64 early when all of the reels 32L, 32M, and 32R have stopped spinning as described above.

The dual-purpose display unit 66 displays the number of game media awarded stored in the media award counter of the main RAM 74, so the player can know the number of game media awarded by checking the dual-purpose display unit 66. In this case, after the rotation of the reels 32L, 32M, and 32R has all stopped in the final game in the pseudo bonus state ST4 and before the second control process (FIG. 44) of the play area is executed, the bonus end clear process (FIG. 57) is executed, and the awarded number information stored in the media award counter is erased. By erasing the awarded number information of the media award counter, the dual-purpose display unit 66 is turned off. This makes it possible to notify that the final game of the pseudo bonus state ST4 has ended, and makes it possible to make the notification early when the rotation of the reels 32L, 32M, and 32R in the final game has all stopped.

In addition, in the final game of the pseudo bonus state ST4, before the information on the number of awards on the medium award counter is erased, the information on the number of awards on the medium award counter is stored in the award number history counter of the main RAM 74, and in the second control process of the game section (FIG. 44), a process is executed to update the value of the total winning number counter 74d using the information on the number of awards stored in the award number history counter. This makes it possible to update the value of the total winning number counter 74d using the information on the number of awards after all of the rotation of the reels 32L, 32M, and 32R has stopped, while also making it possible to turn off the dual-purpose display unit 66 early when all of the rotation of the reels 32L, 32M, and 32R has stopped as described above.

If a transition to the pseudo bonus state ST4 occurs without a direct hit winning in the direct hit lottery process (step S2208), a freeze period occurs in the first game of the pseudo bonus state ST4, and the start of rotation of the reels 32L, 32M, and 32R is awaited. This makes it possible for the player to clearly recognize that the pseudo bonus state ST4 has started. Also, if a direct hit win occurs in the direct hit lottery process (step S2208), a freeze period occurs in that game, and the start of rotation of the reels 32L, 32M, and 32R is awaited. This makes it possible for the player to clearly recognize that a transition to the pseudo bonus state ST4 has been confirmed due to a direct hit winning in the direct hit lottery process (step S2208). In this case, if a direct hit win occurs in the direct hit lottery process (step S2208), a freeze period is set in that game, but a freeze period is not set in the first game of the pseudo bonus state ST4. This makes it possible to prevent the freeze period from being repeated in a short period of time.

The number of games mode to be executed among the first to fifth number of games modes is determined by lottery. The probability of the first to fifth number of games modes being selected by lottery may differ for each type of number of games mode and may also differ depending on the setting value to be used. In this case, the number of games mode lottery table 112 is set with a number of judgment values LV corresponding to the product of the number of types of number of games modes that can be selected by lottery and the number of types of setting values that can be set to be used. This makes it possible to make the number of games mode lottery table 112 common to all combinations of the number of games modes that can be selected by lottery and the setting values that can be set to be used. In addition, since the judgment value LV for the number of types of setting values is set for any number of games mode that can be selected by lottery, it is possible to standardize the process when reading out the judgment value LV corresponding to the combination of the number of games mode set to be selected and the setting value to be used from the number of games mode lottery table 112.

Even if the fifth game number mode is configured not to be a winning combination depending on the type of setting value to be used, the game number mode lottery table 112 has the judgment value LV corresponding to that combination set to "0", which is numerical information corresponding to a non-winning combination. As a result, even in the fifth game number mode in which there is a setting value that is definitely a non-winning combination, there will be a number of judgment values LV corresponding to the number of types of setting values. Therefore, for any game number mode that can be selected, a number of judgment values LV corresponding to the number of types of setting values is set, and it is possible to standardize the process when reading out the judgment value LV corresponding to the combination of the game number mode set to be selected and the setting value to be used from the game number mode lottery table 112.

In the game count mode lottery table 112, the judgment value LV of the number corresponding to the number of types of setting values corresponding to one type of game count mode is set so that the address information D(0) to D(24) in the data is consecutive. As a result, the game count mode lottery table 112 has a number of judgment value LVs corresponding to the number of types of setting values for each type of game count mode collectively set, making it easier to obtain the judgment value LV corresponding to the setting value set as the target for use from the judgment value LVs corresponding to the game count mode that is the subject of the lottery.

In the game count mode lottery table 112, the order of the address information D(0) to D(24) in the data for the judgment value LV corresponding to the number of types of setting values aggregated for each type of game count mode is a fixed order according to the type of corresponding setting value. As a result, the order of the address information D(0) to D(24) in the data in which the judgment value LV corresponding to the setting value to be used among the judgment value LV corresponding to the game count mode to be lottery is set is uniquely determined according to the type of the setting value. Therefore, it becomes easier to obtain the judgment value LV corresponding to the setting value to be used among the judgment value LV corresponding to the game count mode to be lottery.

By executing an address derivation calculation process (step S2503 in the LV acquisition process (FIG. 52)) using numerical information corresponding to the arrangement order in the game count mode lottery table 112 of the game count mode to be selected and numerical information corresponding to the arrangement order in the game count mode lottery table 112 of the currently used setting value, address information D(0) to D(24) on the data in which the judgment value LV corresponding to the combination of the game count mode to be selected and the setting value to be used in the game count mode lottery table 112 is set is acquired. This makes it possible to reduce the processing load when acquiring the judgment value LV corresponding to the combination of the game count mode to be selected and the setting value to be used.

In a configuration in which the 2-byte second random number is updated by the second random number circuit 76 each time an update trigger occurs, there are cases in which the 2-byte second random number is used to execute the AT transition lottery process at the start (step S2403), cases in which a 1-byte random number, which is less than 2 bytes of the second random number, is used to execute the game count mode lottery process (steps S2407 to S2413), and cases in which a 7-bit random number, which is less than 2 bytes of the second random number, is used to execute the win rate mode lottery process (steps S2417 to S2423). This makes it possible to increase the number of lottery processes while suppressing an increase in the number of random number circuits.

In a configuration in which a 2-byte second random number is read from the latch area 111 when the start-time AT transition lottery process (step S2403) is executed using a 2-byte second random number, even when the lottery process is executed using a 1-byte random number or a 7-bit random number using the second random number, the 2-byte second random number is read from the latch area 111, and a 1-byte random number or a 7-bit random number is derived from the read second random number. This makes it possible to derive random numbers of different data capacities while keeping the configuration for reading random numbers from the second random number circuit 76 common.

When acquiring a 7-bit random number, first, a second random number is stored in the latch area 111 based on a latch signal sent from the main MPU 72 to the second random number circuit 76. After that, the upper byte random number stored in the upper area 111a of the latch area 111 is acquired by a register of the main MPU 72. Then, the most significant bit of the upper byte random number is cleared to "0". This makes it possible to acquire a 7-bit random number using the 2-byte second random number latched in the second random number circuit 76, and also makes it possible to simplify the processing configuration for acquiring the 7-bit random number.

Even if a 7-bit random number is used, the random number is treated as 1 byte of data. This makes it possible to treat a 7-bit random number as byte-based data.

At step S2401, a latch signal is sent so that the second random number is latched in the second random number circuit 76, and at step S2406, a latch signal is sent so that the second random number is latched in the second random number circuit 76. In this case, the second random number is sequentially updated in the second random number circuit 76 based on the clock signal output from the clock circuit, and this update period is 0.1 nanoseconds. The period from when the process of step S2401 is executed to when the process of step S2406 is executed is longer than the period required for the second random number, which is updated every 0.1 nanoseconds as described above, to complete one cycle in the numerical range of 0 to 65535. In addition, the period from when the process of step S2401 is executed to when the process of step S2406 is executed varies within a predetermined period range in each of the cases where the process of step S2405 is executed and where the process of step S2405 is not executed, and this variation is large in relation to the update period of the second random number. Therefore, even if a latch signal is sent to the second random number circuit 76 in each of steps S2401 and S2406 during one processing round of the second start setting process (FIG. 50), no regularity is created between the second random number stored in the latch area 111 by sending the latch signal in step S2401 and the second random number stored in the latch area 111 by sending the latch signal in step S2406.

At step S2406, a latch signal is sent so that the second random number is latched in the second random number circuit 76, and at step S2415, a latch signal is sent so that the second random number is latched in the second random number circuit 76. In this case, the second random number is sequentially updated in the second random number circuit 76 based on the clock signal output from the clock circuit, and this update period is 0.1 nanoseconds. The period from when the process of step S2406 is executed to when the process of step S2415 is executed is longer than the period required for the second random number, which is updated every 0.1 nanoseconds as described above, to complete one cycle in the numerical range of 0 to 65535. In addition, the period from when the process of step S2406 is executed to when the process of step S2415 is executed varies within a predetermined period range, and this variation is large in relation to the update period of the second random number. Therefore, even if a latch signal is sent to the second random number circuit 76 in each of steps S2406 and S2415 during one processing round of the second start setting process (FIG. 50), no regularity is created between the second random number stored in the latch area 111 by sending the latch signal in step S2406 and the second random number stored in the latch area 111 by sending the latch signal in step S2415.

When transitioning from pseudo bonus state ST4 to AT state ST5, or when the AT state ST5 remains set, the configuration is such that the external output of the first external signal is stopped once and then restarted. The output timing counter of the main RAM 74 is first set to "2", and if the output level of the first external signal then becomes LOW, the value of the output timing counter is decremented by 1, and if the value of the output timing counter is "1", the value of the output timing counter is decremented by 1 and the output level of the first external signal becomes HI. This makes it possible to stop the external output of the first external signal once and then restart the external output of the first external signal simply by sequentially updating the value of the output timing counter. This makes it possible to perform the process for externally outputting the first external signal in an optimal manner.

When the pseudo bonus state ST4 is initiated, the output level of the first external signal is set to a HI level when the output level of the first external signal is a LOW level. In this case, the output timing counter of the main RAM 74 is set to "1", and when the value of the output timing counter is "1", the value of the output timing counter is decremented by 1 as described above and the output level of the first external signal is set to a HI level. This makes it possible to use the output timing counter to control the output of the first external signal in both cases where the output level of the first external signal is set to a LOW level once and then set to a HI level again, and where the output level of the first external signal is simply set to a HI level.

When the value of the output timing counter of the main RAM 74 is "0", the output level of the first external signal is not changed based on the value of the output timing counter. This makes it possible to create a situation in which the output level of the first external signal is not changed based on the value of the output timing counter.

When the game state is in the CB state, the value of the judgment value counter 74j is set to "1", and when the game state is in the non-CB state and the CB winning data is stored in the main RAM 74, "2" is added to the value of the judgment value counter 74j. Also, when the game state is in the non-CB state, if the number of bets on the game is "2", "2" is added to the value of the judgment value counter 74j, and if the number of bets on the game is "3", "3" is added to the value of the judgment value counter 74j. Therefore, when the game state is in the CB state, the value of the judgment value counter 74j is "1", when the game state is in the non-internal 2-coin bet state, the value of the judgment value counter 74j is "2", when the game state is in the non-internal 3-coin bet state, the value of the judgment value counter 74j is "3", when the game state is in the internal 2-coin bet state, the value of the judgment value counter 74j is "4", and when the game state is in the internal 3-coin bet state, the value of the judgment value counter 74j is "5". This makes it possible to determine whether the current game state is a CB state, a 2-coin bet state while not inside, a 3-coin bet state while not inside, a 2-coin bet state while inside, or a 3-coin bet state while inside by checking the value of the judgment value counter 74j.

When the game state is the CB state, the judgment value counter 74j is set to "1", but the value corresponding to the number of bets is not added to the judgment value counter 74j. This makes it possible to prevent multiple values of the judgment value counter 74j from existing for that situation in a configuration in which the number of bets does not affect the execution content of the lottery process for the role (Figure 34) when the game state is the CB state.

In a configuration in which the type of index value IV to which a point value PV that is 1 or greater is set may differ depending on the game state, rather than varying the numerical range of the index value IV depending on each game state, the index value IV is set to a certain range and the type of winning data associated with each index value IV is the same, while the type of index value IV to which a point value PV that is 1 or greater within that certain range is set is different. This makes it possible to simplify the data format, since there is no need to change the numerical range of the index value IV for each game state, or to change the correspondence between the index value IV and the winning data for each game state.

Data groups 101a-101q for IV=1-17 are provided in one-to-one correspondence with the index values IV=1-17, and data for acquiring the point value PV (including "0") in each game state is set in each of the data groups 101a-101q for IV=1-17. This makes it possible to simplify the data structure, as there is no need to prepare a separate lottery table for each game state.

A judgment value corresponding to each game state is calculated, and if that judgment value corresponds to a bit set to "1" in game state data 102a-104a set in each of data groups 101a-101q for IV=1-17, the point value PV corresponding to the bit set to "1" is obtained from point value data 102c-104c of data groups 101a-101q for IV=1-17. This makes it possible to obtain the point value PV corresponding to each game state, even if data groups 101a-101q for IV=1-17 are set to be common to each game state.

When a judgment value corresponding to each game state is calculated, and a bit set to "0" in game state data 102a-104a set in data groups 101a-101q for IV=1-17 corresponds to that judgment value, the point value PV of "0", which is numerical information corresponding to a non-win, is not set in point value data 102c-104c of data groups 101a-101q for IV=1-17, and is derived separately in the process. This eliminates the need to set numerical information corresponding to a non-win in point value data 102c-104c, making it possible to reduce the data capacity of data groups 101a-101q for IV=1-17.

Second Embodiment
In this embodiment, the hardware configuration of the main MPU 72 and the manner in which processing is executed are different from those in the first embodiment. The following describes the configurations that are different from those in the first embodiment. Note that descriptions of the same configurations as those in the first embodiment will basically be omitted.

Figure 64 is an explanatory diagram for explaining the electrical configuration of the main MPU 72.

The main MPU 72 is provided with a jump status flag 121, a CLR execution circuit 122, and a DEC execution circuit 123. The jump status flag 121 is referenced when a specific memory area is cleared to "0" in the CLR execution circuit 122, and when determining whether the information in the specific memory area before the "0" was cleared is "0" during execution of processing by the program of the main MPU 72. The jump status flag 121 is also referenced when a specific memory area value is decremented by 1 in the DEC execution circuit 123, and when determining whether the information in the specific memory area after the decrement is "0" during execution of processing by the program of the main MPU 72.

The CLR execution circuit 122 is a dedicated circuit for clearing a specific memory area to "0". The specific memory area is not a fixed area, but is changed as appropriate according to the execution content of the process by the program of the main MPU 72. Figures 65(a) and 65(b) are explanatory diagrams for explaining the state of the jump status flag 121 when the specific memory area is cleared to "0" by the CLR execution circuit 122. When the specific memory area is cleared to "0" by the CLR execution circuit 122, first, as shown in Figures 65(a1) and 65(b1), the information of the specific memory area is stored in the pre-CLR storage buffer 122a provided in the CLR execution circuit 122. The pre-CLR storage buffer 122a has a data capacity of 1 byte. In addition, the area that can be the specific memory area has a data capacity of 8 bits or less, but also includes a flag with a data capacity of 1 bit. When a flag with a data capacity of 1 bit is the specific memory area, the information of the flag is stored in the least significant bit of the pre-CLR storage buffer 122a.

Each bit of the pre-CLR storage buffer 122a is connected to a NOR circuit 122b, and the information stored in each bit is subjected to a logical operation using NOR in the NOR circuit 122b. The result of the operation is then stored in the jump status flag 121. Specifically, if the information in a specified storage area before the "0" clear is executed is all "0" as shown in FIG. 65(a1), a logical operation using NOR is executed and "1" is stored in the jump status flag 121. Also, if the information in a specified storage area before the "0" clear is executed is "00000001" as shown in FIG. 65(b1), a logical operation using NOR is executed and "0" is stored in the jump status flag 121.

The information stored in the pre-CLR storage buffer 122a is cleared to "0" by the CLR execution circuit 122, and the result is overwritten in a specified storage area as shown in Figures 65(a2) and 65(b2). As a result, the specified storage area is cleared to "0". Note that if the specified storage area is a 1-bit data capacity flag, the 1-bit flag is cleared to "0".

The DEC execution circuit 123 is a dedicated circuit for subtracting 1 from the value of a specific memory area. The specific memory area is not a fixed area, but is changed as appropriate according to the contents of the process executed by the program of the main MPU 72. Figures 66(a) and 66(b) are explanatory diagrams for explaining the state of the jump status flag 121 when the DEC execution circuit 123 subtracts 1 from the value of a specific memory area. When the DEC execution circuit 123 subtracts 1 from the value of a specific memory area, first, as shown in Figures 66(a1) and 66(b1), information on the specific memory area is stored in a pre-DEC storage buffer 123a provided in the DEC execution circuit 123. The pre-DEC storage buffer 123a has a data capacity of 1 byte. In addition, an area that can become a specific memory area has a data capacity of 8 bits or less.

The information stored in the pre-DEC storage buffer 123a is decremented by 1 by the DEC execution circuit 123. The result after decrement is stored in the post-DEC storage buffer 123b provided in the DEC execution circuit 123, as shown in Figures 66(a2) and 66(b2). The post-DEC storage buffer 123b has a data capacity of 1 byte. The information stored in the post-DEC storage buffer 123b is overwritten in a specific storage area.

Each bit of the post-DEC storage buffer 123b is connected to an OR circuit 123c, and the information stored in each bit is subjected to a logical OR operation in the OR circuit 123c. The result of the operation is stored in the jump status flag 121. Specifically, if the information in a specific storage area before subtraction of 1 is "00000010" as shown in FIG. 66(a1), it becomes "00000001" after subtraction of 1 as shown in FIG. 66(a2). In this case, a logical OR operation is performed, and "1" is stored in the jump status flag 121. Also, if the information in a specific storage area before subtraction of 1 is "00000001" as shown in FIG. 66(b1), it becomes "00000000" after subtraction of 1 as shown in FIG. 66(b2). In this case, a logical OR operation is performed, and "0" is stored in the jump status flag 121.

When the master MPU 72 executes processing according to a program, it basically executes various commands according to the program address in the order determined by the program address. However, if a JP command is set by the program, and the conditions specified by the JP command are met, it will execute the command at the program address that is advanced by the difference determined by the JP command, rather than the command at the program address next in order to the JP command. In this slot machine 10, the JR command and the JRS command are set as the JP command.

Figure 67(a) is an explanatory diagram for explaining the data structure of the JR instruction. As shown in Figure 67(a), the JR instruction has a data capacity of 2 bytes. The most significant byte of the 2 bytes of data is set with condition data that defines the condition for the program address to jump to a program address that is advanced by the difference defined in the JR instruction, rather than to the next program address in sequence. The least significant byte of the 2 bytes of data is set with address data that defines the difference in the program address when the program address is to be jumped.

Figure 67(b) is an explanatory diagram for explaining the data structure of a JRS instruction. As shown in Figure 67(b), a JRS instruction has a data capacity of 1 byte. The upper 5 bits of the 1 byte of data set condition data that defines the condition for jumping the program address to a program address that is advanced by the difference defined in the JRS instruction, rather than to the next program address in sequence. The lower 3 bits of the 1 byte of data set address data that defines the difference in the program address when the program address is to be jumped.

By setting the JR and JRS instructions as described above, using the JRS instruction, which has a relatively small data capacity as the JP instruction, makes it possible to compress the program capacity more than using the JR instruction, which has a relatively large data capacity. However, both the condition data and address data of the JRS instruction are smaller than those of the JR instruction.

The JR instruction sets a data capacity of 1 byte as the condition data, so complex conditions can be set as conditions for jumping, whereas the JRS instruction sets a data capacity of 5 bits as the condition data, so complex conditions cannot be set as conditions for jumping. In this case, the condition data for the JRS instruction is set to data that executes a jump if the jump status flag 121 of the 1-bit data capacity is "0", or data that executes a jump if the jump status flag 121 of the 1-bit data capacity is "1".

With the JR instruction, the address data has a data capacity of 1 byte, so the range defined as the program address difference for jumping is 0 to 255. In contrast, with the JRS instruction, the address data has a data capacity of 3 bits, so the range defined as the program address difference for jumping is 0 to 7.

Since the JR instruction and the JRS instruction are set as the JP instruction as described above, the JR instruction is used when a complex condition needs to be set as the condition for jumping or when the difference in the program address for jumping is 8 or more, and the JRS instruction is used when the condition for jumping corresponds to the two values of the jump status flag 121 and the difference in the program address for jumping is 7 or less. This makes it possible to compress the program size while still allowing the program to be executed properly.

Figure 68 is an explanatory diagram for explaining an example of the contents of a program in which both the JR instruction and the JRS instruction are executed as the JP instruction. Note that this example is the contents of a program constructed by using the jump status flag 121, the CLR execution circuit 122, the DEC execution circuit 123, the JR instruction, and the JRS instruction to perform the external output setting process (Figure 61) in the first embodiment.

As shown in FIG. 68, this program has program addresses set to "1001" through "1027." The command "CLR (SK1FG), 0" is set at program address "1001." "CLR" is a command to clear to "0" by the CLR execution circuit 122, and "SK1FG" is the first output start flag of the main RAM 74 in the first embodiment described above. Therefore, the command "CLR (SK1FG), 0" is a command to clear the first output start flag to "0" by the CLR execution circuit 122.

The instruction "JRS (JPSFG) = 1, 2" is set at the program address "1002". "JRS" is the JRS instruction. "JPSFG" is the jump status flag 121. Therefore, the instruction "JRS (JPSFG) = 1, 2" is an instruction that, as a result of the instruction at the most recent program address (specifically, "1001"), if the value of jump status flag 121 is "1", then the program address is jumped to "1004", which is "1002" plus "2", and if the value of jump status flag 121 is "0", then the program address proceeds to "1003", which is the next program address in the sequence. In other words, if the value of the first output start flag is "0" before the CLR command from program address "1001" is executed, it will jump to program address "1004" without executing the command from program address "1003", and if the value of the first output start flag is "1" before the CLR command from program address "1001" is executed, it will proceed to program address "1003".

The command "SET (STC), 1" is set at the program address "1003." "STC" is the output timing counter of the main RAM 74 in the first embodiment. Therefore, the command "SET (STC), 1" is a command to set the output timing counter to "1."

"SECP1" is set in the program address "1004". This is not a command, but data that is referenced when the developer of the slot machine 10 checks the program. Therefore, when proceeding to program address "1004", no command is executed and the program proceeds to program address "1005".

The command "CLR (SK2FG), 0" is set at the program address "1005". "SK2FG" is the second output start flag of the main RAM 74 in the first embodiment. Therefore, the command "CLR (SK2FG), 0" is a command to clear the second output start flag to "0" by the CLR execution circuit 122.

The program address "1006" has the command "JRS (JPSFG) = 1, 3". This command jumps the program address to "1009", which is "1006" plus "3", if the jump status flag 121 is "1" as a result of the command from the most recent program address (specifically "1005"), and proceeds to the next program address "1007" if the jump status flag 121 is "0". In other words, if the value of the second output start flag is "0" before the CLR command from the program address "1005" is executed, the program jumps to the program address "1009" without executing the commands from the program addresses "1007" and "1008", and if the value of the second output start flag is "1" before the CLR command from the program address "1005" is executed, the program proceeds to the program address "1007".

The instruction "SET (STC), 2" is set at the program address "1007". This instruction sets the output timing counter to "2". The instruction "CALL ONSET2" is set at the program address "1008". "ONSET2" is the second external signal ON setting process (step S3207) in the external output setting process (FIG. 61) in the first embodiment. Therefore, the instruction "CALL ONSET2" is an instruction to call out a subroutine called the second external signal ON setting process (step S3207). When the subroutine of the second external signal ON setting process (step S3207) is completed, the program proceeds to the program address "1009".

"SECP2" is set at program address "1009". This is not a command, but data that is referenced when the developer of the slot machine 10 checks the program. Therefore, when proceeding to program address "1009", no command is executed and the program proceeds to program address "1010".

The command "CLR (SK3FG), 0" is set at the program address "1010". "SK3FG" is the third output start flag of the main RAM 74 in the first embodiment. Therefore, the command "CLR (SK3FG), 0" is a command to clear the third output start flag to "0" by the CLR execution circuit 122.

The program address "1011" has the instruction "JRS (JPSFG) = 1, 2". This instruction is to jump to "1013", which is "1011" plus "2", if the jump status flag 121 is "1" as a result of the instruction by the most recent program address (specifically "1010"), and to proceed to the next program address "1012" if the jump status flag 121 is "0". In other words, if the value of the third output start flag is "0" before the CLR instruction by the program address "1010" is executed, the program will jump to the program address "1013" without executing the instruction by the program address "1012", and if the value of the third output start flag is "1" before the CLR instruction by the program address "1010" is executed, the program will proceed to the program address "1012". The instruction "SET (STC), 2" is set at the program address "1012." This instruction sets the output timing counter to "2."

"SECP3" is set at program address "1013". This is not a command, but data that is referenced when the developer of the slot machine 10 checks the program. Therefore, when proceeding to program address "1013", no command is executed and the program proceeds to program address "1014".

The instruction "JR (STC) = 0, 9" is set for the program address "1014". This instruction causes the program address to jump to "1023", which is "1014" plus "9", if the value of the output timing counter in the main RAM 74 is "0", and to proceed to the next program address "1015" if the value of the output timing counter is not "0". In this JP instruction, the condition data is not condition data corresponding to the value of the jump status flag 121, and furthermore the difference in the program addresses is 8 or more, so the JR instruction is used instead of the JRS instruction.

The instruction "DEC (STC)" is set at the program address "1015". "DEC" is an instruction to subtract 1 by the DEC execution circuit 123, and "STC" is the output timing counter of the main RAM 74, as already explained. Therefore, the instruction "DEC (STC)" is an instruction to subtract 1 from the value of the output timing counter by the DEC execution circuit 123.

The instruction "JRS (JPSFG) = 0, 3" is set for the program address "1016". This instruction is an instruction that, as a result of the instruction by the most recent program address (specifically "1015"), if the value of the jump status flag 121 is "0", the program address is jumped to "1019", which is "1016" plus "3", and if the value of the jump status flag 121 is "1", it proceeds to the next program address "1017". In other words, if the value of the output timing counter is "0" after the DEC instruction by the program address "1015" is executed, it jumps to the program address "1019" without executing the instructions of the program addresses "1017" and "1018", and if the value of the output timing counter is "1" after the DEC instruction by the program address "1015" is executed, it proceeds to the program address "1017".

The command "CALL OFFSET1" is set at the program address "1017". "OFFSET1" is the first external signal OFF setting process (step S3304) in the external output process (Figure 62) in the first embodiment. Therefore, the command "CALL OFFSET1" is a command to call out a subroutine called the first external signal OFF setting process (step S3304). When the first external signal OFF setting process (step S3304) subroutine ends, the program proceeds to the program address "1018".

The command "RET" is set at the program address "1018". In the first embodiment, the external output setting process (FIG. 61) is a subroutine executed in step S913 of the normal process (FIG. 25). Therefore, when the command "RET" is executed, the process proceeds to step S914 of the normal process (FIG. 25).

"SECP4" is set at program address "1019". This is not a command, but data that is referenced when the developer of the slot machine 10 checks the program. Therefore, when proceeding to program address "1019", the program proceeds to program address "1020" without any command being executed.

The command "CALL OFFSET2" is set at the program address "1020". "OFFSET2" is the second external signal OFF setting process (step S3305) in the external output process (FIG. 62) in the first embodiment described above. Therefore, the command "CALL OFFSET2" is a command to call out a subroutine called the second external signal OFF setting process (step S3305). When the second external signal OFF setting process (step S3305) subroutine ends, the program proceeds to the program address "1021".

The command "CALL ONSET1" is set at the program address "1021". "ONSET1" is the ON setting process of the first external signal (step S3306) in the external output process (FIG. 62) in the first embodiment described above. Therefore, the command "CALL ONSET1" is a command to call out the subroutine called the ON setting process of the first external signal (step S3306). When the subroutine of the ON setting process of the first external signal (step S3306) is completed, the program proceeds to the program address "1022".

The command "RET" is set at the program address "1022". In the first embodiment, the external output setting process (FIG. 61) is a subroutine executed in step S913 of the normal process (FIG. 25). Therefore, when the command "RET" is executed, the process proceeds to step S914 of the normal process (FIG. 25).

"SECP5" is set at program address "1023". This is not a command, but data that is referenced when the developer of the slot machine 10 checks the program. Therefore, when proceeding to program address "1023", no command is executed and the program proceeds to program address "1024".

The command "CLR (GSSFG), 0" is set at the program address "1024". "GSSFG" is the external output end flag of the main RAM 74 in the first embodiment. Therefore, the command "CLR (GSSFG), 0" is a command to clear the external output end flag to "0" by the CLR execution circuit 122.

The instruction "JRS (JPSFG) = 1, 2" is set in the program address "1025". This instruction is to jump to "1027", which is "1025" plus "2", if the jump status flag 121 is "1" as a result of the instruction of the most recent program address (specifically "1024"), and to proceed to the next program address "1026" if the jump status flag 121 is "0". In other words, if the value of the external output end flag is "0" before the CLR instruction of the program address "1024" is executed, the program will jump to the program address "1027" without executing the instruction of the program address "1026", and if the value of the external output end flag is "1" before the CLR instruction of the program address "1024" is executed, the program will proceed to the program address "1026".

The command "CALL OFFSET1" is set at the program address "1026". "OFFSET1" is the first external signal OFF setting process (step S3309) in the external output process (Figure 62) in the first embodiment described above. Therefore, the command "CALL OFFSET1" is a command to call out a subroutine called the first external signal OFF setting process (step S3309). When the first external signal OFF setting process (step S3309) subroutine ends, the program proceeds to the program address "1027".

The command "RET" is set at the program address "1027". In the first embodiment, the external output setting process (FIG. 61) is a subroutine executed in step S913 of the normal process (FIG. 25). Therefore, when the command "RET" is executed, the process proceeds to step S914 of the normal process (FIG. 25).

The present embodiment described above provides the following excellent advantages:

When any of the first output start flag, the second output start flag, the third output start flag, and the external output end flag of the main RAM 74 is cleared to "0" by the CLR execution circuit 122, if the value of the target flag was "0" before the "0" clear was executed, the jump status flag 121 is set to "1", and if the value of the target flag was "1" before the "0" clear was executed, the jump status flag 121 becomes "0". Then, different processing is executed when the jump status flag 121 has a value of "1" or "0". As a result, when the target flag is cleared to "0" by the CLR execution circuit 122, which is a dedicated circuit, a value corresponding to the value set in the target flag before the "0" clear was executed is automatically set in the jump status flag 121, and processing corresponding to the value set in the jump status flag 121 can be executed. As a result, it is possible to clear the target flag to "0" and execute processing corresponding to the value set in the flag before the "0" clear was executed while reducing the processing load using the program.

When the value of the output timing counter of the main RAM 74 is decremented by 1 by the DEC execution circuit 123, if the value of the output timing counter after decrement is other than "0", the jump status flag 121 is set to "1", and if the value of the output timing counter after decrement is "0", the jump status flag 121 becomes "0". Different processing is executed when the jump status flag 121 has a value of "1" or "0". As a result, when the DEC execution circuit 123, which is a dedicated circuit, decrements the value of the output timing counter after decrement, the jump status flag 121 automatically has a value corresponding to the value of the output timing counter after decrement, and processing corresponding to the value set in the jump status flag 121 can be executed. As a result, it is possible to execute processing to decrement the value of the output timing counter by 1 and processing corresponding to the value of the output timing counter after decrement while reducing the processing load using a program.

In the configuration described above that allows the CLR execution circuit 122 to clear to "0" and the DEC execution circuit 123 to subtract 1, setting a CLR command in the program allows the CLR execution circuit 122 to clear to "0" and set a value in the jump status flag 121, and setting a DEC command allows the DEC execution circuit 123 to subtract 1 and set a value in the jump status flag 121. This makes it possible to achieve the above-mentioned excellent effects while reducing the program capacity.

Jump instructions are provided as JR instructions, which have a relatively large data capacity, and JRS instructions, which have a relatively small data capacity. This makes it possible to reduce program capacity by using JR and JRS instructions appropriately as needed.

The JRS instruction has a narrower address range to which a jump can be made when the jump condition is met than the JR instruction, but the data capacity is smaller than that of the JR instruction. Therefore, by using the JRS instruction when the address range to jump to is narrow and the JR instruction when the address range to jump to is wide, it is possible to reduce the program capacity while still being able to properly execute the jump instruction.

The JRS instruction requires less data capacity for the condition data that can set jump conditions than the JR instruction, but the data capacity is smaller than that of the JR instruction. Therefore, by using the JRS instruction when the jump conditions are simple and the JR instruction when the jump conditions are complex, it is possible to reduce the program capacity while still being able to properly execute jump instructions.

The dedicated circuit provided in the main MPU 72 for changing the numerical information in a predetermined manner is not limited to the CLR execution circuit 122 for clearing to "0" and the DEC execution circuit 123 for subtracting 1, but may be, for example, a circuit for adding 1 or a circuit for inverting numerical information. Even with these circuits, it is preferable to configure the jump status flag 121 to have different information depending on whether the numerical information before or after the change by the circuit is the predetermined target numerical information or is not the predetermined target numerical information.

In addition, the JRS instruction is configured so that the data capacity of both the condition data and the address data is smaller than that of the JR instruction, but this is not limited to the above. The data capacity of the condition data may be the same for the JR instruction and the JRS instruction, but the data capacity of the address data may be smaller for the JRS instruction than that of the JR instruction, or the data capacity of the address data may be the same for the JR instruction and the JRS instruction, but the data capacity of the condition data may be smaller for the JRS instruction than that of the JR instruction.

Furthermore, the JRS instruction is not limited to a configuration in which data related to the value of the jump status flag 121 is set as condition data, and condition data unrelated to the jump status flag 121 may be set as the condition data of the JRS instruction.

Third Embodiment
In this embodiment, a part of the processing configuration of the main MPU 72 is different from that of the first embodiment. The configuration different from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figures 69(a) to 69(c) are explanatory diagrams for explaining the stack area 125 provided in the main RAM 74.

When the main MPU 72 is executing a specific process using a program, the process to be executed may be transferred to a subroutine process by a CALL command or the like. In this case, when the subroutine process ends, the process returns to the specific process, and in order to perform this return, the information on the return address in the program for the specific process (specifically, the program address) is saved. When saving this, the information on the return address in the program is saved in the stack area 125 of the main RAM 74.

When writing information to the stack area 125, the main MPU 72 executes a PUSH command, and when reading information from the stack area 125, the main MPU 72 executes a POP command. When reading information from the stack area 125, the order of writing to the stack area 125 is such that the information that was written last is read first.

In detail, as shown in FIG. 69(a) to FIG. 69(c), the stack area 125 has a plurality of unit memory areas 125a that can store information on the target return address when the PUSH command is executed. The unit memory areas 125a are set with a one-to-one correspondence, and the memory area addresses are set to be consecutive. A reference pointer that stores information on the memory area address is set in a dedicated register of the main MPU 72, and when the PUSH command is executed, the value stored in the reference pointer is incremented by one, and the return address information is stored in the unit memory area 125a corresponding to the memory area address of the value incremented by one. On the other hand, when the POP command is executed, the return address information is read from the unit memory area 125a corresponding to the memory area address of the value stored in the reference pointer, and the process corresponding to the read return address information is started. When the return address information is read, the value of the reference pointer is decremented by one.

Specifically, as shown in FIG. 69(a), when return address information is stored in each unit memory area 125a up to the memory area address of "k", the reference pointer stores information of "k". When a PUSH command is executed by the main MPU 72 in this situation, the value of the reference pointer is first incremented by 1, so that the reference pointer information becomes "k+1". Then, as shown in FIG. 69(b), the unit memory area 125a corresponding to the memory area address of "k+1", which is the information of the reference pointer, stores the return address information (specifically, "return address B") by this PUSH command. When a POP command is executed by the main MPU 72 in this situation, "return address B" is read from the unit memory area 125a corresponding to the memory area address of "k+1", which is the information of the reference pointer, and the process (i.e., the command) corresponding to the "return address B" is returned to. In this case, as shown in FIG. 69(c), the unit memory area 125a corresponding to the memory area address of "k+1" does not store return address information. After that, the value of the reference pointer is decremented by 1, so the reference pointer information becomes "k".

Next, the execution of the process using the PUSH command and POP command as described above will be explained below. Figure 70 is a flowchart showing the advantageous lottery process at the start of the game in this embodiment, which is executed by the main MPU 72.

If the second interval flag in the main RAM 74 is set to "1" and the current game state is neither the pseudo bonus state ST4 nor the AT state ST5 (step S3401: YES, step S3402: NO), other processing is executed (step S3404). In other processing, the same processing as steps S2204 to S2218 in the advantageous lottery processing at the start of the game in the first embodiment (FIG. 46) is executed.

When the second section flag of the master RAM 74 is set to "1" and the current game state is the pseudo bonus state ST4 or the AT state ST5 (step S3401: YES, step S3402: YES), a PUSH command is executed (step S3404), and then the processing for the advantageous state at the start of the game is executed as a subroutine (step S3405). The PUSH command in step S3404 adds 1 to the value of the reference pointer of the master MPU 72, and then stores return address information after the processing for the advantageous state at the start of the game is completed in the unit memory area 125a corresponding to the memory area address of the reference pointer value after the 1 addition. The return address information becomes address information corresponding to the processing in step S3406.

The advantageous state processing at the start of the game in step S3405 will be described later. After the processing in step S3405 is executed, a lottery process for advantageous effects is executed (step S3406). In the lottery process for advantageous effects, the type of advantageous effect to be executed in the pseudo bonus state ST4 or the AT state ST5 is determined by lottery. The advantageous effect is an effect executed by the upper lamp 61, the speaker 62, and the image display device 63 while the start of rotation of the reels 32L, 32M, and 32R is kept waiting for the freeze period. In the lottery process for advantageous effects, a lottery is performed so that in the pseudo bonus state ST4, a situation in which a transition to the AT state ST5 has been confirmed is more likely to select an advantageous effect of a type with a longer freeze period than a situation in which a transition to the AT state ST5 has not been confirmed, and in the AT state ST5, a lottery is performed so that a situation in which a transition to the added period has been confirmed is more likely to select an advantageous effect of a type with a longer freeze period than a situation in which a transition to the added period has not been confirmed.

After that, the setting process for the favorable performance is executed (step S3407). In this setting process, a process is executed to generate the type of freeze period selected in the lottery process for the favorable performance, and an advantageous performance command corresponding to the freeze period is sent to the performance side MPU92. This causes the currently selected type of advantageous performance to be executed.

If a negative judgment is made in step S3401, if the processing of step S3403 is executed, or if the processing of step S3407 is executed, a RET command is executed (step S3408). In the RET command, a POP command is first executed to read return address information from the unit memory area 125a corresponding to the memory area address of the value of the reference pointer in the master MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process proceeds to the process corresponding to the read return address information. Specifically, the process proceeds to step S1314 in the role selection process (FIG. 34).

Figure 71 is a flow chart showing the processing for advantageous states at the start of a game in step S3405 of the advantageous lottery processing at the start of a game (Figure 70).

If the value of the bet number setting counter 74a is "3" or more, the state is not CB, and the state is pseudo bonus ST4 (step S3501: YES, step S3502: NO, step S3503: YES), a PUSH command is executed (step S3504), and then an ending determination process is executed as a subroutine (step S3505). The PUSH command in step S3504 adds 1 to the value of the reference pointer of the master MPU 72, and then stores return address information after the ending determination process is completed in the unit memory area 125a corresponding to the memory area address of the reference pointer value after the 1 addition. The return address information becomes address information corresponding to the process in step S3506.

The ending determination process of step S3505 will be explained later. After executing the process of step S3505, the processes of steps S3506 to S3511 are executed. These processes of steps S3506 to S3511 are the same as steps S2705 to S2710 in the advantageous state process at the start of the game in the first embodiment (Figure 55). In other words, an AT transition lottery process is executed under specified conditions, and if an AT transition is won, a process is executed to confirm the transition to the AT state ST5.

On the other hand, if the game is in pseudo bonus state ST4 and a negative judgment is made in step S3503, a PUSH command is executed (step S3512), and then the processing for the AT state at the start of the game is executed as a subroutine (step S3513). The PUSH command in step S3512 adds 1 to the value of the reference pointer of the master MPU 72, and then stores return address information after the processing for the AT state at the start of the game is completed in the unit memory area 125a corresponding to the memory area address of the reference pointer value after the 1 is added. The return address information becomes address information corresponding to the processing in step S3514.

If a negative judgment is made in step S3501, if a positive judgment is made in step S3502, if a positive judgment is made in step S3506, if a negative judgment is made in step S3507, if a negative judgment is made in step S3509, if the processing of step S3511 is executed, or if the processing of step S3513 is executed, a RET command is executed (step S3514). In the RET command, a POP command is first executed to read return address information from the unit memory area 125a corresponding to the memory area address of the value of the reference pointer in the master MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process proceeds to the process corresponding to the read return address information. Specifically, the process proceeds to step S3406 in the advantageous lottery process at the start of the game (FIG. 70).

Figure 72 is a flowchart showing the processing for the AT state at the start of the game in step S3513 of the processing for the advantageous state at the start of the game (Figure 71).

First, a PUSH command is executed (step S3601), and then an ending determination process is executed as a subroutine (step S3602). The PUSH command in step S3601 adds 1 to the value of the reference pointer of the main MPU 72, and then stores return address information after the ending determination process is completed in the unit memory area 125a corresponding to the memory area address of the reference pointer value after the 1 is added. The return address information becomes address information corresponding to the process in step S3603.

The ending determination process of step S3602 will be explained later. After executing the process of step S3602, the processes of steps S3603 to S3616 are executed. These processes of steps S3603 to S3616 are the same as steps S3002 to S015 in the process for the AT state at the start of the game in the first embodiment (FIG. 59). In other words, if it is not the added-on period, a lottery process for the transition to the added-on period is executed under a specified condition, and if the transition to the added-on period is won, a process for confirming the transition to the added-on period is executed. Also, if the transition to the added-on period is not won, a first lottery process is executed under a specified condition, and if the transition to the added-on period is won, a process for increasing the remaining number of sets in the AT state ST5 is executed. Also, if it is the added-on period, a second lottery process is executed, and the number selected in the second lottery process is added to the remaining number of sets in the AT state ST5.

If a negative determination is made in step S3604, if the processing of step S3609 is executed, if a negative determination is made in step S3611, if the processing of step S3613 is executed, or if the processing of step S3616 is executed, a RET command is executed (step S3617). In the RET command, a POP command is first executed to read return address information from the unit memory area 125a corresponding to the memory area address of the value of the reference pointer in the master MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process proceeds to the process corresponding to the read return address information. Specifically, the process proceeds to step S3514 in the game start state process (FIG. 71).

Next, the ending determination process executed as a subroutine in step S3505 in the advantageous state process at the start of the game (FIG. 71) or in step S3602 in the AT state process at the start of the game (FIG. 72) will be described with reference to the flowchart in FIG. 73.

In the ending determination process, it is determined whether the ending condition of the second section SC2 is established, and if the ending condition is established, the AT transition lottery process (step S3508) is not executed if the state is pseudo bonus state ST4, and the transition lottery process for the added-on period (step S3605), the first added-on lottery process (step S3610), and the second added-on lottery process (step S3614) are not executed if the state is AT state ST5. In this embodiment, the second section SC2 can be continued even if the pseudo bonus state ST4 ends and the game state ST1 is entered without a transition to the AT state ST5, and the second section SC2 can be continued even if the AT state ST5 ends and the game state ST1 is entered. Therefore, the ending condition of the second section SC2 can be established not only in the middle of the AT state ST5, but also in the middle of the pseudo bonus state ST4, and it can be determined that the ending condition of the second section SC2 is established.

Regarding the ending determination process, first, it is determined whether the number of target games is equal to or greater than the upper limit number of games (step S3701). Specifically, if it is in the pseudo bonus state ST4, it is determined whether the sum of the value of the continuing game number counter 74c of the master RAM 74 and the value of the pseudo bonus continuation counter of the master RAM 74 is equal to or greater than the upper limit number of games in the second section SC2. Also, if it is in the AT state ST5, it is determined whether the sum of the value of the continuing game number counter 74c of the master RAM 74, the value of the AT continuation counter of the master RAM 74, the value of the set number counter of the master RAM 74, and the value of the initial number of continuing games in one set in the AT state ST5 (50 games) is equal to or greater than the upper limit number of games in the second section SC2.

Also, it is determined whether the target number is equal to or greater than the upper limit net increase in number of coins (step S3702). Specifically, if it is in the pseudo bonus state ST4, it is determined whether the result of multiplying the value of the pseudo bonus continuation counter by the expected value of the gaming media in the pseudo bonus state ST4 and adding the result to the value of the total acquisition number counter 74d is equal to or greater than the upper limit net increase in number of coins in the second section SC2. Also, if it is in the AT state ST5, it is determined whether the result of multiplying the value of the AT continuation counter, the value of the set number counter, and the value of the initial number of continued games in one set in the AT state ST5 (50 games) by the expected value of the gaming media in the AT state ST5 and adding the result to the value of the total acquisition number counter 74d is equal to or greater than the upper limit net increase in number of coins in the second section SC2.

If the determination is negative in both step S3701 and step S3702, a RET command is executed (step S3703). In the RET command, a POP command is first executed to read return address information from the unit memory area 125a corresponding to the memory area address of the value of the reference pointer in the main MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process proceeds to a process corresponding to the read return address information. Specifically, if the ending determination process is executed in step S3505 in the advantageous state process at the start of the game (FIG. 71), the process proceeds to step 3506 in the advantageous state process at the start of the game (FIG. 71). Also, if the ending determination process is executed in step S3602 in the AT state process at the start of the game (FIG. 72), the process proceeds to step S3603 in the AT state process at the start of the game (FIG. 72).

On the other hand, if a positive judgment is made in either step S3701 or step S3702, a POP command is executed (step S3704). Specifically, return address information is read from the unit memory area 125a corresponding to the memory area address of the value of the reference pointer in the main MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. However, even if the return address information is read, the process does not proceed to processing the return address information.

Then, the RET command is executed (step S3705). In the RET command, a POP command is first executed to read return address information from the unit memory area 125a corresponding to the memory area address of the reference pointer value in the main MPU 72. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process proceeds to the process corresponding to the read return address information.

Here, as described above, the POP command is executed in step S3704 before executing the POP command included in the RET command in step S3705. Therefore, the return address information to be read by the POP command included in the RET command in step S3705 is the value of the storage area address immediately before the storage area address of the reference pointer value when the ending determination process (Figure 73) is started. Thus, the RET command in step S3705 does not return to the processing in the subroutine that was executed immediately before the ending determination process (Figure 73) was executed, but rather returns to the processing in the subroutine that was executed immediately before the subroutine was executed.

If in pseudo bonus state ST4, the subroutine of the ending determination process (FIG. 73) is executed in step S3505 in the processing for the advantageous state at the start of the game (FIG. 71), so the RET command in step S3705 will transition to the processing of step S3406 in the advantageous lottery process at the start of the game (FIG. 70), which is transitioned to by the RET command in step S3514 in the processing for the advantageous state at the start of the game (FIG. 71). In other words, if the RET command in step S3705 is executed in pseudo bonus state ST4, the processing of steps S3506 to S3511 is not executed in the processing for the advantageous state at the start of the game (FIG. 71), and therefore the AT transition lottery process is not executed. As a result, the AT transition lottery process is not executed in a situation where it is determined that the ending condition is established in pseudo bonus state ST4.

If it is AT state ST5, the subroutine of the ending determination process (FIG. 73) is executed in step S3602 in the process for the AT state at the start of the game (FIG. 72), so the RET command in step S3705 will transition to the process of step S3514 in the process for the advantageous state at the start of the game (FIG. 71), which will be transitioned to by the RET command in step S3617 in the process for the AT state at the start of the game (FIG. 72). In other words, if the RET command in step S3705 is executed in AT state ST5, the processes of steps S3603 to S3617 are not executed in the process for the AT state at the start of the game (FIG. 72), so the transition lottery process for the added period, the first added lottery process, and the second added lottery process are not executed. As a result, in a situation where it is determined that the ending condition is established in AT state ST5, the transition lottery process for the added period, the first added lottery process, and the second added lottery process are not executed.

Here, we will explain the contents of a comparative example that employs a configuration in which, rather than executing an extra POP command, information in the main RAM 74 indicating that it is determined that the ending condition for the second section SC2 is met is used to skip the execution of processing that should not be executed in a situation in which it is determined that the ending condition for the second section SC2 is met.

Figure 74 is a flowchart showing the ending determination process in a comparative example.

Steps SA101 to SA103 execute the same processing as steps S3701 to S3703 of the ending determination process (FIG. 73) in this slot machine 10. If a positive determination is made in either step SA101 or step SA102, a regulation response flag provided in the master RAM in the comparative example is set to "1" (step SA104). After that, a RET command is executed (step SA105). In the RET command, a POP command is first executed to read return address information from a unit memory area corresponding to the memory area address of the reference pointer value provided in the master MPU in the comparative example. When the return address information is read, the value of the reference pointer is decremented by 1. Then, the process corresponding to the read return address information is executed. If the pseudo bonus state is in effect, the process returns to the advantageous state process at the start of the game (FIG. 75).

Figure 75 is a flowchart showing the advantageous state processing at the start of a game in a comparative example.

Steps SA111 to SA115 and steps SA117 to SA124 execute the same processing as steps S3501 to S3514 of the advantageous state processing at the start of a game in this slot machine 10 (FIG. 71). In the advantageous state processing at the start of a game in the comparative example, after executing the ending determination processing in step SA115, it is determined whether or not the regulation response flag in the main RAM in the comparative example is set to "1" (step SA116). If the regulation response flag is not set to "1" (step SA116: NO), the processing from step SA117 onwards is executed, whereas if the regulation response flag is set to "1" (step SA116: YES), the advantageous state processing at the start of the game is terminated as is.

As described above, in the comparative example, even if it is determined in the ending determination process (FIG. 74) that the ending condition of the second section SC2 is established, after setting the regulation response flag in the main RAM to "1", if it is in a pseudo bonus state, it returns to the advantageous state process at the start of the game (FIG. 75), and in step SA116 of the process, it is determined whether the regulation response flag is set to "1", and if the regulation response flag is set to "1", it ends the advantageous state process at the start of the game (FIG. 75) as it is. In this case, in order to skip the execution of the process from step SA117 onwards in the advantageous state process at the start of the game (FIG. 75) when it is determined that the ending condition of the second section SC2 is established, it is necessary to set the process (i.e., command) of step SA104 and step SA116 as a program, and to provide a regulation response flag in the main RAM. In the comparative example, such a configuration must also be adopted for the AT state process at the start of the game, which is executed in the AT state.

In contrast, in this slot machine 10, when it is determined that the ending condition of the second section SC2 will be met in the pseudo bonus state ST4 or the AT state ST5, the POP command is executed one extra time to forcibly adjust the return address to the previous return address, thereby skipping the execution of processing that should not be executed in a situation where it is determined that the ending condition of the second section SC2 will be met. This makes it possible to skip the execution of processing that should not be executed in a situation where it is determined that the ending condition of the second section SC2 will be met, while reducing the program capacity and the storage capacity required in the main RAM 74.

Note that the number of extra POP commands executed is not limited to one, but may be multiple, such as two or three.

Fourth Embodiment
In this embodiment, a part of the processing configuration of the main MPU 72 is different from that of the first embodiment. The configuration different from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 76 is a flow chart showing the calculation process of the wait period executed by the main MPU 72. As in the first embodiment, the wait period is a period that is forcibly guaranteed as the period from the start of rotation of reels 32L, 32M, and 32R in a given game to the start of rotation of reels 32L, 32M, and 32R in the next game. The calculation process of the wait period is executed in the timer subtraction process (step S506) of the timer interrupt process (Figure 19).

If it is time to set the wait period, that is, when the reels 32L, 32M, and 32R have started to rotate (step S3801: YES), the wait counter 126 (see FIG. 77(a)) in the main RAM 74 is set to information corresponding to the wait period (specifically, 4.1 seconds) (step S3802). In addition, the wait flag in the main RAM 74 is set to "1" (step S3803). The wait flag is a flag that allows the main MPU 72 to identify that the wait period is in the middle of being measured, and the wait counter 126 is a counter that allows the main MPU 72 to identify the remaining period of the wait period. If the wait flag is set to "1", the start of rotation of reels 32L, 32M, and 32R is awaited even after one game has started and the lottery process for winning combinations (Figure 34) has been completed, and reels 32L, 32M, and 32R will start to rotate when the wait flag is no longer set to "1".

If the determination in step S3801 is negative, and the wait flag in the main RAM 74 is set to "1" (step S3804: YES), a subtraction process is executed on the wait counter 126 (step S3805). The subtraction process subtracts 1 from the value of the wait counter 126, as will be described in detail later. Then, if the value of the wait counter 126 after the subtraction is "0" (step S3806: YES), the wait flag is cleared to "0" (step S3807).

Figures 77(a) to 77(c) are diagrams for explaining the contents of the subtraction process of the wait counter 126 in step S3805. Figure 77(a) is a diagram for explaining the configuration of the wait counter 126, Figure 77(b) is a diagram for explaining the contents of a specific instruction for the subtraction process of the wait counter 126, and Figure 77(c) is a diagram for explaining how a carryover of the digits of the upper byte TK1 occurs in the wait counter 126.

As shown in FIG. 77(a), the wait counter 126 has a two-byte structure consisting of a one-byte upper byte TK1 and a one-byte lower byte TK2. In step S3802 of the wait period calculation process (FIG. 76), information corresponding to the wait period (specifically, 4.1 seconds) is set in this two-byte wait counter 126.

In the process of decrementing the wait counter 126 in step S3805 of the wait period calculation process (Figure 76), the instruction shown in Figure 77 (b) is executed. Specifically, the instruction "SUB (TK2), 1" is set at the program address "4101". "SUB" is an instruction to decrement a specified numerical value by a specified value. Therefore, the instruction "SUB (TK2), 1" is an instruction to decrement the value of the lower byte TK2 of the wait counter 126 by 1. As a result of executing this command, the value of the lower byte TK2 is decremented by 1. However, if the value of the lower byte TK2 is "00000000" as shown in FIG. 77(c1), and the value is decremented by 1, the carry flag CF provided in the main MPU 72 is set to "1", and the value of the lower byte TK2 is inverted to "11111111" as shown in FIG. 77(c2).

The instruction "SBC (TK1), 1" is set in the program address of the following "4102". The instruction "SBC" is an instruction to subtract a specified value from a specified numerical value if the carry flag CF of the master MPU 72 is set to "1" in the immediately preceding instruction. Therefore, the instruction "SBC (TK1), 1" is an instruction to subtract 1 from the value of the upper byte TK1 of the wait counter 126 if the carry flag CF is set to "1" as a result of the value of the lower byte TK2 being subtracted by 1 in the immediately preceding instruction "4101". In this case, if the carry flag CF is not set to "1" in the immediately preceding instruction "4101", the value of the upper byte TK1 is maintained in the instruction "4102", and if the carry flag CF is set to "1" in the immediately preceding instruction "4101", the value of the upper byte TK1 is subtracted by 1 in the instruction "4102". In other words, if the value of the upper byte TK1 is "00000010" as shown in FIG. 77(c1), and the value of the lower byte TK2 is subtracted by 1 and the carry flag CF is set to "1", the value of the upper byte TK1 is subtracted by 1 and becomes "00000001" as shown in FIG. 77(c2).

The next program address, "4103," has the instruction "RET" set. Executing the instruction "RET" causes the program to proceed to step S3806 of the wait period calculation process (Figure 76).

Figure 78 is a flowchart showing the medal monitoring process executed by the main MPU 72. Note that the medal monitoring process is executed in the sensor monitoring process (step S505) of the timer interrupt process (Figure 19).

In this embodiment, the medal passage of the selector 52 for guiding medals inserted into the medal insertion port 45 to the hopper device 53 in a situation where medal acceptance is permitted is provided with a first inserted medal detection sensor and a second inserted medal detection sensor as the inserted medal detection sensor 45a. These first inserted medal detection sensor and second inserted medal detection sensor are arranged in parallel in the medal passing direction, with the first inserted medal detection sensor on the upstream side and the second inserted medal detection sensor on the downstream side. If a medal is detected by the second inserted medal detection sensor within a predetermined monitoring period after the first inserted medal detection sensor detects a medal, the main MPU 72 determines that one medal has been inserted through the medal insertion port 45. In the medal monitoring process, the period from when the medal is detected by the first inserted medal detection sensor to when the medal is detected by the second inserted medal detection sensor is monitored, and a process is executed to cause an abnormality to be notified if this period exceeds the predetermined monitoring period.

Specifically, first, an increment process is performed on the monitoring period counter KK (see FIG. 79(a)) provided in the main RAM 74 (step S3901). The monitoring period counter KK is a counter that allows the main MPU 72 to determine whether the period from when a medal is detected by the first inserted medal detection sensor to when a medal is detected by the second inserted medal detection sensor has exceeded a predetermined monitoring period.

After that, on the condition that a medal is detected by the first inserted medal detection sensor (step S3902: YES), the monitoring period counter KK is cleared to "0" (step S3903). If a medal is detected by the second inserted medal detection sensor (step S3904: YES), it is determined whether the value of the monitoring period counter KK is at its maximum value (step S3905). If the value of the monitoring period counter KK is at its maximum value (step S3905: YES), the abnormality flag provided in the main RAM 74 is set to "1" (step S3906), and an abnormality command is sent to the performance side MPU 92 (step S3907). As a result, an abnormality signal is output to the outside, and an abnormality notification is executed by the upper lamp 61, the speaker 62, and the image display device 63.

Figures 79(a) to 79(c) are diagrams for explaining the contents of the increment process of the monitoring period counter KK in step S3901. Figure 79(a) is a diagram for explaining the configuration of the monitoring period counter KK, Figure 79(b) is a diagram for explaining the contents of a specific command for the increment process of the monitoring period counter KK, and Figure 79(c) is a diagram for explaining how, when the value of the monitoring period counter KK reaches its maximum value, the state in which the maximum value is reached is maintained.

As shown in FIG. 79(a), the monitoring period counter KK is configured as one byte. In the increment process of the monitoring period counter KK in step S3901 in the medal monitoring process (FIG. 78), the command shown in FIG. 79(b) is executed. Specifically, the command "ADD (KK), 1" is set in the program address "5101". "ADD" is a command to increment a specified numerical value by a specified value. Therefore, the command "ADD (KK), 1" is a command to increment the value of the monitoring period counter KK by one. As a result of executing this command, the value of the monitoring period counter KK is incremented by one, but as shown in FIG. 79(c1), if the value of the monitoring period counter KK is "11111111", and the value is incremented by one, the carry flag CF provided in the main MPU 72 is set to "1", and the value of the monitoring period counter KK is inverted to "00000000" as shown in FIG. 79(c2).

The instruction "SBC (KK), 1" is set in the program address of the following "5102". As already explained, the instruction "SBC" is an instruction to subtract a specified value from a specified numerical value if the carry flag CF of the master MPU 72 is set to "1" in the immediately preceding instruction. Therefore, the instruction "SBC (KK), 1" is an instruction to subtract 1 from the value of the monitoring period counter KK if the carry flag CF is set to "1" as a result of the value of the monitoring period counter KK being incremented by 1 in the immediately preceding instruction "5101". In this case, if the carry flag CF is not set to "1" in the immediately preceding instruction "5101", the value of the monitoring period counter KK is maintained in the instruction "5102", and if the carry flag CF is set to "1" in the immediately preceding instruction "5101", the value of the monitoring period counter KK is decremented by 1 in the instruction "5102". That is, when the monitoring period counter KK has a value of "11111111" as shown in FIG. 79(c1), the monitoring period counter KK is incremented by one, and the carry flag CF is set to "1" as shown in FIG. 79(c2), and the monitoring period counter KK has a value of "00000000". In this case, the monitoring period counter KK is decremented by one and the monitoring period counter KK has a value of "11111111" as shown in FIG. 79(c3). As a result, when the process of step S3901 is executed in a situation where the monitoring period counter KK has already reached its maximum value, the monitoring period counter KK is maintained at its maximum value. Since a value "1" smaller than this maximum value corresponds to the predetermined monitoring period, when the monitoring period counter KK has reached its maximum value, the monitoring period corresponds to a state in which the monitoring period has exceeded the predetermined monitoring period. In this situation, when the second inserted medal detection sensor detects a medal, a positive judgment is made in steps S3904 and S3905, and an abnormality notification is executed.

The next program address, "5103," has the command "RET" set. Executing the command "RET" causes the process to proceed to step S3902 of the medal monitoring process (Figure 78).

Here, a configuration may be considered in which the "SBC" command is not used in the increment process of the monitoring period counter KK in step S3901. FIG. 79(d) is an explanatory diagram for explaining the contents of a comparative example in which the increment process of the monitoring period counter KK is performed without executing the "SBC" command.

In the comparative example, the instruction "ADD (KK), 1" is set at the program address "5101". As already explained, this instruction is an instruction to increment the value of the monitoring period counter KK by 1. As a result of executing this instruction, the value of the monitoring period counter KK is incremented by 1.

The next program address, "5102," has the instruction "JR NCF, 2." This instruction causes the program address to jump to "5104," which is "5102" plus "2," if the carry flag CF is not set to "1" as a result of the instruction at the most recent program address (specifically, "5101"), and to proceed to the next program address, "5103," if the carry flag CF is set to "1."

The instruction "LD (KK), 255" is set at the program address "5103". This instruction sets the value of the monitoring period counter KK to its maximum value of "11111111". As a result, when the value of the monitoring period counter KK is "11111111", and the value of the monitoring period counter KK is incremented by 1, the value of the monitoring period counter KK is inverted to "00000000" and the carry flag CF is set to "1", the value of the monitoring period counter KK will return to its maximum value of "11111111".

The command "RET" is set at the program address "5104". Executing the command "RET" causes the process to proceed to step S3902 of the medal monitoring process (Figure 78).

As described above, when the value of the monitoring period counter KK is incremented by 1 and the value of the monitoring period counter KK exceeds the maximum value, the process of returning the value to the maximum value is carried out. In a comparative example that does not use the "SBC" command, this process requires four commands, whereas by using the "SBC" command as in the slot machine 10, the process requires only three commands. This makes it possible to reduce the program capacity.

As already explained, the "SBC" instruction is an instruction used to cause a carryover of the upper byte TK1 in the wait counter 126 during the subtraction process (step S3805) of the wait counter 126 in the wait period calculation process (Figure 76). In other words, it is possible to reduce the program capacity as described above by using an instruction that is used for a different purpose in another process.

Fifth embodiment
In this embodiment, the configuration of the calculation process of the wait period and the medal monitoring process differs from that of the fourth embodiment. The configurations different from the fourth embodiment will be described below. Note that the description of the same configuration as the fourth embodiment will be basically omitted.

Figure 80 is a flowchart showing the wait period calculation process in this embodiment executed by the main MPU 72.

If it is time to set the wait period, i.e., when the reels 32L, 32M, and 32R have started to rotate (step S4001: YES), the wait counter 126 provided in the main RAM 74 is cleared to "0" (step S4002). The configuration of the wait counter 126 is the same as in the fourth embodiment. In addition, the wait flag in the main RAM 74 is set to "1" (step S4003).

If the result of step S4001 is negative, and the wait flag in the main RAM 74 is set to "1" (step S4004: YES), an increment process of the wait counter 126 is executed (step S4005). This increment process increments the value of the wait counter 126 by 1, as will be described in detail later. Then, if the value of the wait counter 126 after incrementing by 1 corresponds to the wait period (step S4006: YES), the wait flag is cleared to "0" (step S4007).

Figures 81(a) and 81(b) are diagrams for explaining the contents of the addition process of the wait counter 126 in step S4005. Figure 81(a) is a diagram for explaining the contents of a specific instruction for the addition process of the wait counter 126, and Figure 81(b) is a diagram for explaining the occurrence of a carryover of the digit of the upper byte TK1 in the wait counter 126.

In the addition process of the wait counter 126 in step S4005 in the calculation process of the wait period (FIG. 80), the instruction shown in FIG. 81(a) is executed. Specifically, the instruction "ADD (TK2), 1" is set in the program address of "4101". This instruction is an instruction to add 1 to the value of the lower byte TK2. As a result of executing this instruction, the value of the lower byte TK2 is added by 1, but if the value of the lower byte TK2 is "11111111" as shown in FIG. 81(b1) and the value is added by 1, the carry flag CF provided in the main MPU 72 is set to "1", and the value of the lower byte TK2 is inverted to "00000000" as shown in FIG. 81(b2).

The instruction "ADC (TK1), 1" is set in the program address of the following "4102". The instruction "ADC" is an instruction to add a specified value to a specified numerical value if the carry flag CF of the master MPU 72 is set to "1" in the immediately preceding instruction. Therefore, the instruction "ADC (TK1), 1" is an instruction to add 1 to the value of the upper byte TK1 of the wait counter 126 if the carry flag CF is set to "1" as a result of adding 1 to the value of the lower byte TK2 in the immediately preceding instruction "4101". In this case, if the carry flag CF is not set to "1" in the immediately preceding instruction "4101", the value of the upper byte TK1 is maintained in the instruction "4102", and if the carry flag CF is set to "1" in the immediately preceding instruction "4101", the value of the upper byte TK1 is added by 1 in the instruction "4102". In other words, as shown in FIG. 81(b1), when the value of the upper byte TK1 is "00000001", the value of the lower byte TK2 is incremented by 1 and the carry flag CF is set to "1", the value of the upper byte TK1 is incremented by 1 and the value of the upper byte TK1 becomes "00000010" as shown in FIG. 81(b2).

The next program address, "4103," has the instruction "RET" set. Executing the instruction "RET" causes the program to proceed to step S4006 of the wait period calculation process (Figure 80).

Figure 82 is a flowchart showing the medal monitoring process in this embodiment, which is executed by the main MPU 72.

First, the monitoring period counter KK in the main RAM 74 is decremented (step S4101). Then, on condition that a medal is detected by the first inserted medal detection sensor (step S4102: YES), the maximum value is set in the monitoring period counter KK (step S4103). As a result, the monitoring period counter KK becomes "11111111". Also, if a medal is detected by the second inserted medal detection sensor (step S4104: YES), it is determined whether the value of the monitoring period counter KK is "0" (step S4105). If the value of the monitoring period counter KK is "0" (step S4105: YES), the abnormality flag in the main RAM 74 is set to "1" (step S4106), and an abnormality command is sent to the performance side MPU 92 (step S4107). As a result, an abnormality signal is output to the outside, and an abnormality notification is executed by the upper lamp 61, the speaker 62, and the image display device 63.

Figures 83(a) and 83(b) are diagrams for explaining the contents of the decrement process of the monitoring period counter KK in step S4101. Figure 83(a) is a diagram for explaining the contents of a specific command for the increment process of the monitoring period counter KK, and Figure 83(b) is a diagram for explaining how the value of the monitoring period counter KK is maintained at its minimum value when it reaches its maximum value.

In the decrement process of the monitoring period counter KK in step S4101 of the medal monitoring process (FIG. 82), the command shown in FIG. 83(a) is executed. Specifically, the command "SUB (KK), 1" is set in the program address of "5101". This command is a command to decrement the value of the monitoring period counter KK by 1. As a result of executing this command, the value of the monitoring period counter KK is decremented by 1, but if the value of the monitoring period counter KK is "00000000" as shown in FIG. 83(b1) and the value is decremented by 1, the carry flag CF provided in the main MPU 72 is set to "1", and the value of the monitoring period counter KK is inverted to "11111111" as shown in FIG. 83(b2).

The instruction "ADC (KK), 1" is set in the program address of the following "5102". As already explained, the "ADC" instruction is an instruction to add a specified value to a specified numerical value if the carry flag CF of the master MPU 72 is set to "1" in the immediately preceding instruction. Therefore, the instruction "ADC (KK), 1" is an instruction to add 1 to the value of the monitoring period counter KK if the carry flag CF is set to "1" as a result of the value of the monitoring period counter KK being subtracted by 1 in the immediately preceding instruction "5101". In this case, if the carry flag CF is not set to "1" in the immediately preceding instruction "5101", the value of the monitoring period counter KK is maintained in the instruction "5102", and if the carry flag CF is set to "1" in the immediately preceding instruction "5101", the value of the monitoring period counter KK is added by 1 in the instruction "5102". That is, when the monitoring period counter KK has a value of "00000000" as shown in FIG. 83(b1), the monitoring period counter KK is decremented by one, and the carry flag CF is set to "1" as shown in FIG. 83(b2), and the monitoring period counter KK has a value of "11111111", the monitoring period counter KK is incremented by one and the monitoring period counter KK has a value of "00000000" as shown in FIG. 83(b3). As a result, when the process of step S4101 is executed in a situation where the monitoring period counter KK has already reached its minimum value, the monitoring period counter KK is maintained at its initial value. Since the situation where the monitoring period counter KK has a value of "00000001" corresponds to the predetermined monitoring period, when the monitoring period counter KK has reached its minimum value, the monitoring period exceeds the predetermined monitoring period. In this situation, if a medal is detected by the second inserted medal detection sensor, a positive judgment is made in steps S4104 and S4105, and an abnormality notification is issued.

The next program address, "5103," has the command "RET" set. Executing the command "RET" causes the process to proceed to step S4102 of the medal monitoring process (Figure 82).

Here, a configuration may be considered in which the "ADC" command is not used in the decrement process of the monitoring period counter KK in step S4101. FIG. 83(c) is an explanatory diagram for explaining the contents of a comparative example in which the decrement process of the monitoring period counter KK is performed without executing the "ADC" command.

In the comparative example, the instruction "SUB (KK), 1" is set at the program address "5101". As already explained, this instruction is an instruction to decrement the value of the monitoring period counter KK by 1. As a result of executing this instruction, the value of the monitoring period counter KK is decremented by 1.

The next program address, "5102," has the instruction "JR NCF, 2." This instruction causes the program address to jump to "5104," which is "5102" plus "2," if the carry flag CF is not set to "1" as a result of the instruction at the most recent program address (specifically, "5101"), and to proceed to the next program address, "5103," if the carry flag CF is set to "1."

The instruction "LD (KK), 0" is set at the program address "5103". This instruction sets the value of the monitoring period counter KK to its minimum value, "00000000". As a result, when the value of the monitoring period counter KK, which is "00000000", is decremented by 1, it is inverted to "11111111" and the carry flag CF is set to "1", so that the value of the monitoring period counter KK returns to its minimum value, "00000000".

The command "RET" is set at the program address "5104". Executing the command "RET" causes the process to proceed to step S4102 of the medal monitoring process (Figure 82).

As described above, when the monitoring period counter KK value is decremented by 1 and the value of the monitoring period counter KK falls below the minimum value, the process of returning the monitoring period counter KK to the minimum value requires four commands in a comparative example that does not use the "ADC" command, whereas by using the "ADC" command as in the slot machine 10, only three commands are required for the process. This makes it possible to reduce the program capacity.

As already explained, the "ADC" command is used to generate a carry in the upper byte TK1 of the wait counter 126 during the addition process (step S4005) of the wait counter 126 in the wait period calculation process (Figure 80). In other words, it is possible to reduce the program capacity as described above by using commands that are used for other purposes in other processes.

Sixth embodiment
In this embodiment, the configuration of the main processing executed by the main MPU 72 is different from that of the first embodiment. The configuration different from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 84 is a flowchart showing the main processing in this embodiment executed by the main MPU 72.

First, similarly to step S101 of the main processing (FIG. 10) in the first embodiment, the power failure signal is read (step S4201). In this case, the occurrence of a power failure is identified by monitoring the above-mentioned predetermined bit of the input port 72a. Then, by determining whether or not "1" is stored in the predetermined bit of the input port 72a, it is determined whether or not the power failure signal received from the power failure monitoring circuit 54b is at HI level (step S4202). If the power failure signal is not at HI level (step S4202: NO), the confirmation counter provided in the main RAM 74 is cleared to "0" (step S4203), and if the power failure signal is at HI level (step S4202: YES), the value of the confirmation counter in the main RAM 74 is incremented by 1 (step S4204). The confirmation counter is a counter for the main MPU 72 to identify the number of times that the power failure signal has been continuously confirmed to be at HI level.

When the process of step S4203 or step S4204 is executed, it is determined whether the value of the confirmation counter in the main RAM 74 is equal to or greater than the progress permission value (step S4205). The progress permission value can be any integer equal to or greater than 2, but in this embodiment, it is set to "5". If the value of the confirmation counter is less than the progress permission value (step S4205: NO), that is, if the number of times it has been confirmed that the power failure signal is continuously at a HI level is less than the progress permission value, the process returns to step S4201 and it is again confirmed whether the power failure signal is HI.

If the value of the confirmation counter is equal to or greater than the progress permission value (step S4205: YES), i.e., if the number of times that it has been confirmed that the power failure signal is continuously at HI level is equal to or greater than the progress permission value, an internal function setting process is executed (step S4206). In the internal function setting process, various initial settings are made for the registers and I/O devices in the main MPU 72. After that, other processes are executed (step S4207). In the other processes, the same processes as those in steps S104 to S121 of the main process (FIG. 10) in the first embodiment are executed.

According to the above configuration, when the supply of operating power to the main MPU 72 is started, the execution of the processing from step S4206 onwards in the main processing (Fig. 84) is put on hold until it is confirmed that the power failure signal is in a HI level state a number of times consecutively equal to or greater than the progress permission value, which is an integer equal to or greater than 2. This makes it possible to start processing for progressing the game under conditions in which a HI level power failure signal is being stably output.

Seventh embodiment
In this embodiment, the configuration of the main processing executed by the main MPU 72 is different from that of the first embodiment. The configuration different from the first embodiment will be described below. Note that the description of the same configuration as the first embodiment will basically be omitted.

Figure 85 is a flowchart showing the main processing in this embodiment executed by the main MPU 72.

First, the timer interrupt process (FIG. 19) is permitted to run (step S4301). The timer interrupt process (FIG. 19) is started at 1.49 millisecond intervals, as in the first embodiment, but if the timer interrupt process (FIG. 19) is permitted to run in step S4301, the timer interrupt process (FIG. 19) is started when 1.49 milliseconds have elapsed from this timing.

Then, the process waits until the timer interrupt process (FIG. 19) occurs once (step S4302). The processing time from when step S4301 is executed by the main MPU 72 until step S4302 is executed is several microseconds, and the processing time from when a negative judgment is made in step S4302 until the processing of step S4302 is executed again is also several microseconds. Therefore, the negative judgment in step S4302 is executed approximately 500 times before the timer interrupt process (FIG. 19) is executed once.

When the timer interrupt process (FIG. 19) has been executed once, the internal function setting process is executed (step S4303). In the internal function setting process, various initial settings are made to the registers and I/O devices in the main MPU 72. After that, other processes are executed (step S4304). In the other processes, the same processes as those in steps S104 to S121 of the main process (FIG. 10) in the first embodiment are executed.

According to the above configuration, when the supply of operating power to the main MPU 72 is started, the execution of the processing from step S4303 onwards in the main processing (Fig. 85) is put on hold until the interrupt period of the timer interrupt processing (Fig. 19), which is 1.49 milliseconds, has elapsed and the execution of the timer interrupt processing (Fig. 19) is completed. The period expected until the HI level power outage signal is stably output is shorter than the interrupt period of the timer interrupt processing (Fig. 19), which is 1.49 milliseconds. Therefore, it is possible to start processing to progress the game under the circumstances in which the HI level power outage signal is stably output.

The timer interrupt process (FIG. 19) is first processed when 1.49 milliseconds have elapsed since the supply of operating power to the main MPU 72 started. As described above, the period expected until the stable output of the HIGH level power failure signal is shorter than the interrupt period of 1.49 milliseconds for the timer interrupt process (FIG. 19). Therefore, even if the power failure process (step S503) is executed in the timer interrupt process (FIG. 19), the HIGH level power failure signal is being stably output by the time the power failure process is started. This makes it possible to prevent a situation in which power failure process is executed due to the unstable output state of the power failure signal in the timer interrupt process (FIG. 19) executed first after the supply of operating power is started.

<Other embodiments>
The present invention is not limited to the contents of the above-described embodiments, and various modifications and improvements are possible within the scope of the present invention. For example, the following modifications may be made. The configurations of the following alternative forms may be applied individually to the configurations of the above-described embodiments, or may be applied in combination. The configurations of the above-described embodiments may be applied in combination with each other, and the configurations of the following alternative forms may be applied individually or in combination with each other to a configuration in which the configurations of the above-described embodiments are combined with each other.

(1) The power failure monitoring circuit 54b may be configured to output a LOW level power failure signal to the main MPU 72 when the voltage applied from the external power source to the power supply unit 54a exceeds the reference voltage, and to output a HI level power failure signal to the main MPU 72 when the voltage applied from the external power source to the power supply unit 54a falls below the reference voltage. In this case, when the main MPU 72 confirms that the output level of the power failure signal has changed from HI level to LOW level in the power failure processing (FIG. 13), it will execute the processing at the time of power failure shown in steps S202 to S205. In addition, in the main processing (FIG. 10) of the first embodiment, the process waits without proceeding to the processing of steps S103 and thereafter until it is confirmed in step S102 that the output level of the power failure signal is at a LOW level, and in the main processing (FIG. 84) of the sixth embodiment, if it is confirmed in step S4202 that the output level of the power failure signal is at a LOW level, the process of step S4204 is executed, and if it is confirmed in step S4202 that the output level of the power failure signal is at a HI level, the process of step S4203 is executed.

(2) The power failure monitoring circuit 54b may be configured not to output any signal related to a power failure to the main MPU 72 when the voltage applied from the external power source to the power supply unit 54a exceeds the reference voltage, and to output a power failure signal to the main MPU 72 when the voltage applied from the external power source to the power supply unit 54a falls below the reference voltage. In this case, when the main MPU 72 confirms that a power failure signal has been received in the power failure processing (FIG. 13), it executes the processing at the time of a power failure shown in steps S202 to S205. Also, in the main processing (FIG. 10) in the first embodiment, it waits without proceeding to the processing after step S103 until it is confirmed in step S102 that a power failure signal has not been received, and in the main processing (FIG. 84) in the sixth embodiment, when it is confirmed in step S4202 that a power failure signal has not been received, it executes the processing of step S4204, and when it is confirmed in step S4202 that a power failure signal has been received, it executes the processing of step S4203.

(3) The configuration is not limited to one in which the main processing (FIGS. 10, 84, and 85) is put on hold until the reception status of the power failure signal becomes stable. Instead of or in addition to the configuration, the main processing (FIGS. 10, 84, and 85) may be put on hold until the reception status of the reset signal output to the main MPU 72 becomes stable.

(4) In the seventh embodiment described above, the main processing (FIG. 85) is configured to wait for the processing from step S4303 onwards to proceed until the timer interrupt processing (FIG. 19) is executed once, but this is not limited thereto, and the processing from step S4303 onwards may be configured to wait for the processing from step S4303 onwards to proceed until the timer interrupt processing (FIG. 19) is executed twice, or the processing from step S4303 onwards may be configured to wait for the processing from step S4303 onwards to proceed until the timer interrupt processing (FIG. 19) is executed three times, or the processing from step S4303 onwards may be configured to wait for the processing from step S4303 onwards to proceed until the timer interrupt processing (FIG. 19) is executed a predetermined number of times, which is four or more times.

(5) Although one information abnormality flag 74g is provided in common for the information abnormality of the power outage flag, the checksum abnormality, and the set value abnormality, the present invention is not limited to this, and the information abnormality flag 74g may be provided in one-to-one correspondence with the information abnormality of the power outage flag, the checksum abnormality, and the set value abnormality. Even in this case, the information abnormality flag 74g corresponding to the information abnormality of the power outage flag may be set to "1" before the process for determining whether or not the information abnormality of the power outage flag has occurred is executed, the information abnormality flag 74g corresponding to the checksum abnormality may be set to "1" before the process for determining whether or not the checksum abnormality has occurred is executed, and the information abnormality flag 74g corresponding to the set value abnormality may be set to "1" before the process for determining whether or not the set value abnormality has occurred is executed. In this configuration, it is preferable that after all the processes for determining whether or not each information abnormality has occurred are executed, it is determined whether or not any of the information abnormality flags 74g are set to "1", and if any of the information abnormality flags 74g are set to "1", an operation prohibition process is executed.

(6) After setting the information anomaly flag 74g to "1", it is determined whether or not an information anomaly has occurred, and if no information anomaly has occurred, the information anomaly flag 74g is cleared to "0", while if an information anomaly has occurred, the information anomaly flag 74g is maintained in a state where it is set to "1". This configuration may be applied to a configuration for monitoring anomalies other than information anomalies. Examples of different anomaly monitoring include a configuration for detecting unauthorized radio waves and a configuration for detecting unauthorized magnets.

(7) When the information anomaly flag 74g is set to "1", the operation prohibition process may be executed without executing the setting change process (FIG. 15) even if a setting change operation has been performed. In this case, it is possible to prioritize the operation prohibition process in response to the occurrence of an information anomaly over the execution of the setting change process (FIG. 15).

(8) When the setting change process (FIG. 15) is executed, the process of clearing the storage area of the main RAM 74 (steps S301 to S307) is executed regardless of whether the information abnormality flag 74g is set to "1" or not. However, the present invention is not limited to this. If the information abnormality flag 74g is not set to "1", the process of clearing the storage area of the main RAM 74 is not executed in the setting change process (FIG. 15), and if the information abnormality flag 74g is set to "1", the process of clearing the storage area of the main RAM 74 is executed in the setting change process (FIG. 15). Also, if the information abnormality flag 74g is set to "1" in this configuration, the information abnormality flag 74g may be cleared to "0" in the setting change process (FIG. 15), and other storage areas of the main RAM 74 are not subject to the execution of the clear process.

(9) If the setting change process (FIG. 15) is executed while the information abnormality flag 74g is set to "1", the operation prohibition process may be executed after the setting change process (FIG. 15) is completed. In this case, by clearing at least the information abnormality flag 74g to "0" during the setting change process (FIG. 15), it becomes possible to play with the setting value selected in the setting change process (FIG. 15) executed before the power was turned off by turning the power off and then on again.

(10) The execution manner of the process of clearing the memory area of the main RAM 74 (steps S301 to S307) in the setting change process (FIG. 15) may be the same whether or not the information abnormality flag 74g is set to "1". In this case, by configuring the information abnormality flag 74g to be cleared to "0" in the clearing process, even if the setting change process (FIG. 15) is executed in a situation where the information abnormality flag 74g is set to "1", the information abnormality flag 74g will be cleared to "0" after the setting change process (FIG. 15) is completed.

(11) The setting change operation is not limited to the configuration in which the supply of operating power is started when the setting key inserted into the setting key insertion hole 57 is turned ON. The setting change operation may be the configuration in which the supply of operating power is started when the reset button 56 is pressed, or the configuration in which the supply of operating power is started when the setting key is turned ON and the reset button 56 is pressed. In this case, the setting change process (FIG. 15) is likely to be started when the reset button 56 is continuously pressed. However, as in the first embodiment, the determination of whether the reset button 56 is pressed is performed for the first time in the setting change process (FIG. 18), and the setting value of the selection target is prevented from being changed by the continued pressing of the reset button 56 by performing the determination of the pressing of the reset button 56 a predetermined number of times in the sensor monitoring process (FIG. 20) of the timer interrupt process (FIG. 19).

(12) The main RAM 74 is not limited to a configuration in which the current reset state storage area 74h and the previous reset storage area 74i are provided, and only the previous reset storage area 74i may be provided, and if it is determined in the sensor monitoring process (FIG. 20) of the timer interrupt process (FIG. 19) that the reset button 56 has been pressed, the previous reset storage area 74i may be set to "1", and if it is determined that the reset button 56 has not been pressed, the previous reset storage area 74i may be cleared to "0". In this case, in step S409 of the setting change execution process (FIG. 18), if the signal received from the reset button 56 becomes a HI level corresponding to the pressing of the reset button 56 in a situation in which information indicating that the reset button 56 has not been pressed is not stored in the previous reset storage area 74i, the setting value of the selection target is changed as if the pressing of the reset button 56 has started. In this configuration, by ensuring that one timer interrupt process (FIG. 19) is executed before the process of step S409 is executed for the first time after the setting change process (FIG. 15) is started, it is possible to prevent the setting value that is the selection target from being changed by the continued pressing of the reset button 56 when the setting change process (FIG. 15) is started.

(13) When the supply of operating power to the main MPU 72 is started, the internal function setting process (step S103) of the main process (FIG. 10) may be configured to set "1" to both the reset current state storage area 74h and the reset previous state storage area 74i, or to set "1" only to the reset current state storage area 74h. In this case, even if the process of step S402 is not executed in the setting change execution process (FIG. 18), it is possible to prevent the setting value that is the selection target from being changed by the continued pressing of the reset button 56 when the setting change process (FIG. 15) is started.

(14) In a configuration in which the execution content of the performance executed on the image display device 63 can be selected by the player operating a selection button, a processing configuration (steps S402 and S406) for determining whether or not the reset button 56 has been pressed in the setting change execution process (FIG. 18) of the first embodiment described above may be applied in order to prevent switching of the execution content of the performance to be selected due to continued operation of the selection button that was started before the start of the selectable situation.

(15) The process of step S311 may not be executed in the setting change process (FIG. 15). In this case, when the process of clearing the memory area of the main RAM 74 (steps S301 to S307) in the setting change process (FIG. 15) is executed, the door status area 74e is cleared to "0", and the information in the door status area 74e remains "0" until the next monitoring process of the door open sensor 16 (FIG. 22) is executed. In this configuration, by setting both the "open information" set in the door status area 74e when it is determined that the front door 12 is in an open state, and the "closed information" set in the door status area 74e when it is determined that the front door 12 is in a closed state to information other than "0", if the monitoring process of the door open sensor 16 (Figure 22) determines that the front door 12 is in an open state after the clearing process of the memory area of the main RAM 74 (steps S301 to S307) is executed, an open command is sent to the performance side MPU 92, and if the monitoring process of the door open sensor 16 (Figure 22) determines that the front door 12 is in a closed state after the clearing process of the memory area of the main RAM 74 (steps S301 to S307) is executed, a close command is sent to the performance side MPU 92. Regardless of whether the main MPU 72 is executing the setting change process (Figure 15), the performance side MPU 92 is configured to initiate a door open notification when it receives an open command, and initiate a door closed notification when it receives a close command, making it possible to issue a notification corresponding to the state of the front door 12 after the memory area of the main RAM 74 has been cleared (steps S301 to S307).

(16) The information set in the door status area 74e in step S311 of the setting change process (Figure 15) may not be reset status information, but may be "open information" indicating that the front door 12 is open. In this case, if the front door 12 is closed when the setting change process (Figure 15) is terminated, a close command is sent to the production side MPU 92 and a door closed notification is executed. Also, the information set in the door status area 74e in step S311 of the setting change process (Figure 15) may not be reset status information, but may be "closed information" indicating that the front door 12 is closed. In this case, if the front door 12 is open when the setting change process (Figure 15) is terminated, an open command is sent to the production side MPU 92 and a door open notification is executed.

(17) In normal processing (FIG. 25), the timing at which the value of the bet number setting counter 74a is stored in the bet number history counter 74f is not limited to the timing after the medium dispensing process (step S910) is executed, and may be, for example, the timing before the role selection process (step S906) is started, the timing at which some of the reels 32L, 32M, and 32R have stopped spinning, or the timing at which all of the reels 32L, 32M, and 32R have stopped spinning.

(18) When the clear process (Figure 57) at the end of the bonus is executed, a turn-off command is sent to the production side MPU 92, and when the production side MPU 92 receives the turn-off command, it may be configured to execute a turn-off process for the upper lamp 61 and a blackout process for the image display device 63. In this case, when the final game of the pseudo bonus state ST4 ends, the upper lamp 61 goes into an off state and the image display device 63 goes into a blackout state in conjunction with the bet display unit 64 and the combined display unit 66 going into an off state. This makes it possible for the player to clearly recognize that the pseudo bonus state ST4 has ended.

(19) In addition to or instead of a configuration in which the clear process (FIG. 57) at the end of the bonus is executed when the final game of the pseudo bonus state ST4 ends, the clear process (FIG. 57) at the end of the bonus may be executed when the AT state ST5 ends.

(20) When a freeze period is set in response to a direct hit win in the direct hit lottery process and a transition to pseudo bonus state ST4 is confirmed, instead of a configuration in which a freeze period is prevented from occurring in the first game of pseudo bonus state ST4, which is the next game for the game in the freeze period, a configuration in which, when any freeze period occurs, the occurrence of a freeze period is prevented within a predetermined number of games from the game in which the freeze period occurred, even if an opportunity for the occurrence of the freeze period occurs may be used. In this case, the occurrence of a freeze period will prevent the occurrence of a new freeze period for a predetermined number of games. Note that the above-mentioned predetermined number of games is arbitrary and may be one game, two games, or three or more games.

(21) In a configuration in which there are multiple triggers for a freeze period to occur within a single game, if a freeze period occurs once within a single game, the occurrence of further freeze periods in that game may be prevented. This makes it possible to prevent freeze periods from occurring multiple times within a single game.

(22) In a configuration in which the start of rotation of the reels 32L, 32M, and 32R in the current game is put on hold until the predetermined wait period has elapsed from the start of rotation of the previous reels 32L, 32M, and 32R when the game is started, so that the period from when the reels 32L, 32M, and 32R start to when the reels 32L, 32M, and 32R start to rotate next is a predetermined wait period (for example, 4.1 seconds) or more, if a wait period of more than the restricted period occurs between the establishment of a predetermined game start condition and the start of rotation of the reels 32L, 32M, and 32R, even if a trigger for the occurrence of a freeze period occurs in the predetermined game, the occurrence of a freeze period may be prevented. This makes it possible to prevent excessive wait periods for the game. Note that the restricted period must be less than the predetermined wait period, and may be, for example, 1 second, 2 seconds, or 3 seconds.

(23) The game count mode lottery table 112 is configured such that the judgment value LV is set in an aggregated manner for each of the first to fifth game count modes that are to be selected in the game count mode lottery process, but the judgment value LV may be set in an aggregated manner for each set value. In this case, it is preferable that the aggregated judgment value LV for each set value is arranged so that the order of addresses in the game count mode lottery table 112 is either ascending order or descending order of the set values. This configuration may also be applied to the win rate mode lottery table 113.

(24) In the lottery process for the number of games mode, if none of the data set in the number of games mode lottery table 112 is selected, the first number of games mode is selected. Alternatively, the judgment value LV for the first number of games mode may also be set in the number of games mode lottery table 112. In this case, since the judgment value LV corresponding to each of the first to fifth number of games modes is set in the number of games mode lottery table 112, any of the data set in the number of games mode lottery table 112 is selected in the lottery process for the number of games mode. This configuration may also be applied to the winning rate mode lottery table 113.

(25) When extracting a 7-bit random number in the lottery process in the winning rate mode, the upper byte of the 2-byte second random number updated in the second random number circuit 76 is used, but this is not limited to this, and the lower byte of the 2-byte second random number may be used. Also, when extracting a 1-byte random number in the lottery process in the game count mode, the upper byte of the 2-byte second random number updated in the second random number circuit 76 is used, but this is not limited to this, and the lower byte of the 2-byte second random number may be used.

(26) In the lottery process in the game count mode, a 1-byte random number may be extracted using one of the upper and lower bytes of the 2-byte second random number updated by the second random number circuit 76, and in the lottery process in the winning rate mode, a 7-bit random number may be extracted using the other of the upper and lower bytes of the 2-byte second random number updated by the second random number circuit 76. Furthermore, this configuration of extracting a predetermined random number using one of the upper and lower bytes of the 2-byte second random number and extracting a specific random number using the other may be applied when the predetermined random number and the specific random number have the same number of bits, rather than when the predetermined random number and the specific random number have different numbers of bits.

(27) When extracting a 7-bit random number in the lottery process in the winning rate mode, the most significant bit of the upper byte of the second random number is cleared to "0", but this is not limited to the above, and the least significant bit may be cleared to "0" and then shifted one bit at a time to the lower side to extract a 7-bit random number.

(28) In the lottery process in the winning rate mode, the 7-bit random number is configured to be treated as 1 byte of data, but this is not limited to this and may be configured to be treated as 7-bit data.

(29) In the pseudo bonus state ST4, the output level of the first external signal is set to a HI level, but the present invention is not limited to this. In the pseudo bonus state ST4, the output level of the first external signal may be maintained at a LOW level. In this case, when the AT state ST5 is started, it is not necessary to switch the output level of the first external signal from a HI level to a LOW level. When the AT state ST5 is started, it is only necessary to switch the output level of the first external signal from a LOW level to a HI level. Therefore, when the AT state ST5 is started, that is, when the second output start flag of the main RAM 74 is set to "1", the output timing counter of the main RAM 74 may be set to "1". In this configuration, the output level of the second external signal may be maintained at a HI level in the pseudo bonus state ST4, and the output level of the second external signal may be maintained at a LOW level in game states other than the pseudo bonus state ST4, including the AT state ST5.

(30) An end signal may be output to the outside in addition to the first external signal and the second external signal, and when the AT state ST5 ends, the output level of the end signal may be switched from a LOW level to a HIGH level, and the HIGH level output state may be maintained for a predetermined period (e.g., 2 seconds).

(31) When the AT state ST5 starts, or when one set ends in the AT state ST5 and a new set starts, the period during which the output level of the first external signal is maintained at a LOW level is not limited to one game, and may be changed to a HIGH level at a timing during the game, such as at the start of a game following the game in which the output level of the first external signal was changed from a HIGH level to a LOW level, at the timing when the rotation of reels 32L, 32M, and 32R starts, or at the timing when the rotation of some of the reels 32L, 32M, and 32R stops.

In addition, the output level of the first external signal may be changed to HI level after two or three games for a game in which the output level of the first external signal has been changed from HI level to LOW level. For example, in a configuration in which the output level of the first external signal is changed to HI level after two games for a game in which the output level of the first external signal has been changed from HI level to LOW level, when the AT state ST5 is started, or when one set ends in the AT state ST5 and a new set starts, the output timing counter of the main RAM 74 is set to "3", and when step S3302 of the external output process (FIG. 62) is executed while the value of the output timing counter is "3" and the value of the output timing counter becomes "2", the output timing counter of the first external signal is set to "3". The output level of the first external signal is changed from HI level to LOW level, and when step S3302 of the external output process (FIG. 62) is executed in a situation where the value of the output timing counter is "2" and the value of the output timing counter becomes "1", the output level of the first external signal is maintained at the LOW level, and when step S3302 of the external output process (FIG. 62) is executed in a situation where the value of the output timing counter is "1" and the value of the output timing counter becomes "0", the output level of the first external signal is changed from LOW level to HI level.

(32) The value of the output timing counter of the main RAM 74 does not need to be subtractive, but may be additive. In this configuration, when the AT state ST5 starts, or when one set ends in the AT state ST5 and a new set starts, the output timing counter of the main RAM 74 is set to "1". Then, in the external output process (FIG. 62), if the value of the output timing counter is "1", the output level of the first external signal is changed from HI level to LOW level and the value of the output timing counter is incremented by 1, and if the value of the output timing counter is "2", the output level of the first external signal is changed from LOW level to HI level and the value of the output timing counter is cleared to "0", so that the output level of the first external signal becomes HI level after a period in which the LOW level is maintained in one game.

(33) Although the output level of the first external signal is configured to be switched between a LOW level and a HI level, this is not limiting, and the output level may be switched between a state in which the first external signal is not output to the outside and a state in which the first external signal is output to the outside. In this case, the state in which the first external signal is not output to the outside corresponds to the state in which the output level of the first external signal is a LOW level in the first embodiment, and the state in which the first external signal is output to the outside corresponds to the state in which the output level of the first external signal is a HI level in the first embodiment. In addition, the HI/LOW relationship of the output level of the first external signal may be the opposite of that in the first embodiment.

(34) Although the output level of the second external signal is configured to be switched between a LOW level and a HI level, this is not limiting, and the output level may be switched between a state in which the second external signal is not output to the outside and a state in which the second external signal is output to the outside. In this case, the state in which the second external signal is not output to the outside corresponds to the state in which the output level of the second external signal is a LOW level in the first embodiment, and the state in which the second external signal is output to the outside corresponds to the state in which the output level of the second external signal is a HI level in the first embodiment. In addition, the HI/LOW relationship of the output level of the second external signal may be the opposite of that in the first embodiment.

(35) The game states distinguished using the judgment value counter 74j are not limited to the CB state, the non-CB state in which the CB winning data is stored, and the non-CB state in which the CB winning data is not stored. For example, in a configuration in which a BB state that is advantageous to the player and an RB state that is advantageous to the player but less advantageous than the BB state exist instead of the CB state, the BB state, the RB state, the non-CB state in which the BB winning data is stored, the non-CB state in which the RB winning data is stored, and the non-CB state in which neither the BB winning data nor the RB winning data is stored may be distinguished using the judgment value counter 74j.

(36) The process for which the execution mode of the process is changed by using the judgment value counter 74j is not limited to the lottery process for the winning combination (FIG. 34), but may be, for example, a process for determining the content of the presentation, a process for setting a freeze period, or a process for determining the number of gaming media to be awarded when a winning combination corresponding to the award of gaming media occurs.

(37) The judgment value counter 74j is configured to add values corresponding to the presence or absence of a CB state, the presence or absence of CB winning data, and the number of bets. However, the judgment value counter 74j may be configured to have an initial value of 1 or more, and to subtract values corresponding to the presence or absence of a CB state, the presence or absence of CB winning data, and the number of bets from the initial value.

(38) The judgment value counter 74j is configured to add values corresponding to the presence or absence of a CB state, the presence or absence of CB winning data, and the number of bets. However, in addition to these game states or instead of some game states, the setting value to be used may be added to the judgment value counter 74j. In this case, it is possible to use the judgment value counter 74j to perform a lottery according to the setting value in the lottery process for winning combinations (FIG. 34).

(39) In the data groups 101a to 101q for IV=1 to 17, the point value data 102c to 104c are not set to a point value PV corresponding to a game situation that is definitely a loss, but this is not limited to the above, and the point value PV corresponding to a game situation that is definitely a loss may be set to "0". In this case, even if the game situation is definitely a loss, it is possible to obtain the point value PV from the point value data 102c to 104c in the data groups 101a to 101q for IV=1 to 17.

(40) The number of active lines is not limited to the main line ML, and may be two, three, four or more active lines. In this case, the number of active lines may be increased as the number of gaming media bets increases, or the maximum number of active lines may be set regardless of the number of gaming media bets.

(41) In each of the above embodiments, a bonus of paying out medals is awarded when a small winning combination is achieved, but the present invention is not limited to such a configuration and may be configured in any way as long as the bonus is awarded to the player. For example, a prize other than medals may be awarded when a small winning combination is achieved. In addition, in a slot machine that does not have a function for inserting actual medals or paying out medals, and instead manages medals owned by the player by credit, an increase in the number of credited medals corresponds to the awarding of a bonus.

(42) The present invention may be applied to so-called B-type slot machines, or to any type of slot machine, such as C-type, a combination of A-type and C-type, a combination of B-type and C-type, or a type equipped with an RT game, CT game, or AT game. The present invention may also be applied to a configuration in which a bonus state advantageous to the player exists.

(43) The symbols on each reel 32L, 32M, 32R are not limited to pictures, numbers, letters, etc., but may also be geometric lines, figures, etc. In addition, symbols may be formed using light, color, etc., or using three-dimensional shapes, etc., or may be a combination of these. In other words, the symbols may function as identifiable information.

(44) In each of the above embodiments, a specific example of a slot machine 10 is shown, but the present invention may be applied to a pachinko machine in which games are played using game balls as a gaming medium, or to a gaming machine that combines a slot machine and a pachinko machine.

<Inventions extracted from the above embodiments>
The following describes the features of the inventions extracted from the above-described embodiments, while indicating, as necessary, their effects, etc. In the following, for ease of understanding, the corresponding configurations in the above-described embodiments are appropriately indicated in parentheses, but the present invention is not limited to the specific configurations indicated in parentheses.

<Features Group A>
Feature A1. A control means (main MPU 72) for controlling games;
A signal transmission means (power failure monitoring circuit 54b) capable of transmitting a predetermined signal (power failure signal) to the control means;
Equipped with
In the gaming machine, the control means is configured to be in a state where processing is not executed based on the reception state of the predetermined signal becoming a specific state (reception of a power outage signal at a LOW level),
The gaming machine is characterized in that the control means is equipped with a waiting means for waiting the progress of processing until a predetermined condition for progress is met when the supply of operating power is started (in the first embodiment, a function for executing the processing of steps S101 and S102 in the main MPU 72, in the sixth embodiment, a function for executing the processing of steps S4201 to S4205 in the main MPU 72, and in the seventh embodiment, a function for executing the processing of steps S4301 and S4302 in the main MPU 72).

According to feature A1, in a configuration in which the control means does not execute processing based on the reception status of a specific signal becoming a specific status, when the supply of operating power is started, the processing is put on hold until a specific condition for progression is met. This makes it possible to prevent processing from progressing even if the reception status of the specific signal is not stable when the supply of operating power is started. Therefore, it is possible to prevent a situation in which processing is not executed at an unexpected timing due to the reception status of the specific signal becoming a specific status due to the reception status of the specific signal being unstable in a situation in which processing is progressing when the supply of operating power is started. Therefore, it becomes possible to preferably execute processing when the supply of operating power is started.

Feature A2. The gaming machine according to Feature A1, wherein the standby means suspends the progress of processing so that processing can be prevented from proceeding until the reception status of the predetermined signal becomes stable when the supply of operating power is started.

According to feature A2, when the supply of operating power starts, it is possible to prevent processing from proceeding until the reception condition of a specified signal stabilizes.

Feature A3. The control means is
A means for executing an interrupt process based on the lapse of an interrupt response period (a function for executing a timer interrupt process in the main MPU 72);
A status determination means (a function for executing the process of step S201 in the main MPU 72) for determining whether or not the reception status of the predetermined signal is the specific status in the interrupt process;
A means for causing the processing to be in a state in which processing is not executed based on the fact that the reception status of the predetermined signal is the specific status identified by the status identification means (a function for executing processing from step S202 onward in the main MPU 72);
Equipped with
The gaming machine according to feature A1 or A2, wherein the waiting means causes the progress of the processing to wait when the supply of operating power has started and before the execution of the interrupt processing is permitted.

According to feature A3, in a configuration in which processing is not executed based on the determination in interrupt processing that the reception status of a specific signal is in a specific state, when the supply of operating power is started and before execution of the interrupt processing is permitted, the progress of the processing is put on hold. This makes it possible to prevent the interrupt processing from determining whether the reception status of the specific signal is in a specific state before the reception status of the specific signal has stabilized.

Feature A4. The gaming machine according to any one of Features A1 to A3, characterized in that the signal transmission means changes the reception status of the predetermined signal in the control means from a predetermined status (reception of a HI-level power outage signal) to the specific status when the supply of operating power is stopped.

According to feature A4, when the supply of operating power is stopped, the reception status of the specified signal changes from a specified status to a specific status, and the control means is in a state where processing is not executed when the reception status of the specified signal becomes the specific status. This makes it possible to make the control means in a state where processing is not executed when the supply of operating power is stopped. In this case, it is expected that the reception status of the specified signal will not be stable immediately after the supply of operating power is started. In response to this, the configuration of feature A1 is provided, and when the supply of operating power is started, the progress of processing is put on hold until a specified progress condition is met. This makes it possible to prevent processing from progressing even if the reception status of the specified signal is not stable when the supply of operating power is started.

Feature A5. The gaming machine described in Feature A4, characterized in that the standby means releases the state of waiting for the progress of processing based on confirmation that the reception status of the predetermined signal has become the predetermined status when the supply of operating power is started (a function of executing the processing of step S102 of the main MPU 72 in the first embodiment).

According to feature A5, when the supply of operating power is started, the state of waiting for the processing to proceed is released based on confirmation that the reception status of the specified signal has become a specified status. This makes it possible to prevent the processing from proceeding if the reception status of the specified signal may become a specific status when the supply of operating power is started.

Feature A6. The gaming machine described in Feature A4 or A5, wherein the standby means releases the state of waiting for the progress of processing based on the fact that the reception status of the predetermined signal is in the predetermined status when the supply of operating power is started, the number of times being a predetermined number of times or more (a function of executing the processing of step S4205 of the main MPU 72 in the sixth embodiment).

According to feature A6, the state of waiting for the processing to proceed is released based on the fact that the reception status of the specified signal has become a specified status multiple times or more in succession, which is a specified number of confirmations, when the supply of operating power is started. This makes it possible to prevent the processing from proceeding if the reception status of the specified signal may become a specific status when the supply of operating power is started.

Feature A7. The control means is
A means for executing an interrupt process based on the lapse of an interrupt response period (a function for executing a timer interrupt process in the main MPU 72);
A first determination means (a function of executing the process of step S201 in the main MPU 72) for determining whether or not the reception state of the predetermined signal is the specific state in the interrupt process;
A means for causing the processing to be in a state in which processing is not executed based on the fact that the first identification means has identified that the reception status of the predetermined signal is the specific status (a function for executing processing from step S202 onward in the main MPU 72);
Equipped with
The waiting means is
A means for waiting the progress of the process when the supply of operating power is started and before the execution of the interrupt process is permitted (a function for executing the process of step S102 in the main MPU 72 in the first embodiment, and a function for executing the process of step S4205 in the main MPU 72 in the sixth embodiment);
A second determination means for determining whether or not the reception status of the predetermined signal is in the predetermined status while waiting for the processing to proceed (a function for executing the processing of step S101 in the main MPU 72 in the first embodiment, and a function for executing the processing of step S4201 in the main MPU 72 in the sixth embodiment);
A gaming machine described in any one of features A4 to A6, characterized in that it is equipped with a means for releasing the state of waiting for the processing to proceed based on the second identification means identifying that the reception status of the specified signal is the specified status (in the first embodiment, a function of making a positive judgment in step S102 in the main MPU 72, and in the sixth embodiment, a function of making a positive judgment in step S4205 in the main MPU 72).

According to feature A7, in a configuration in which processing is not executed based on the determination in interrupt processing that the reception status of a specific signal is in a specific state, when the supply of operating power is started and before the execution of the interrupt processing is permitted, the progress of the processing is put on hold. This makes it possible to prevent the interrupt processing from determining whether the reception status of the specific signal is in a specific state before the reception status of the specific signal has stabilized.

In addition, when the processing is on hold, the processing confirms whether the reception status of the specified signal has reached a specified status, and the state of waiting for the processing to proceed is released based on confirmation that the reception status of the specified signal has reached the specified status. This makes it possible to determine whether the reception status of the specified signal has stabilized, even in a configuration in which interrupt processing is not executed when the processing is on hold, and makes it possible to allow the processing to proceed when the reception status of the specified signal is stable.

Feature A8. The control means includes a means for executing an interrupt process based on the lapse of an interrupt response period (a function for executing a timer interrupt process in the main MPU 72),
The waiting means is a gaming machine described in feature A1 or A2, which is characterized in that when the supply of operating power is started, the progress of processing at the start of the supply of operating power is waited until the interrupt processing is executed once (a function of executing the processing of step S4302 of the main MPU 72 in the seventh embodiment).

According to feature A8, when the supply of operating power is started, the progress of the process at the start of the supply of operating power is put on hold until the interrupt process is executed once. This makes it possible to prevent the process at the start of the supply of operating power from progressing until the reception status of the specified signal is stabilized, and also makes it possible to generate an opportunity to release the pending state of the progress of the process by utilizing a configuration for executing an existing interrupt process.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features A1 to A8. This makes it possible to achieve a synergistic effect by combining the features.

<Characteristics Group B>
Feature B1. In a gaming machine that is in a predetermined event response state (a state in which the progress of the game is prevented by a positive determination in step S112 in the main MPU 72) based on the occurrence of a predetermined event (information abnormality in the power outage flag, an abnormality in the checksum, or an abnormality in the setting value),
A storage execution means (a function for executing the process of step S104 of the main MPU 72 in the first embodiment) for storing the event response information in the event response storage area (information anomaly flag 74g);
an event occurrence identification means (a function of executing the processes of steps S105 to S109 of the main MPU 72 in the first embodiment) for identifying whether or not the predetermined event has occurred after the event response information is stored in the event response storage area by the storage execution means;
An information erasing means for erasing the event response information from the event response storage area based on the fact that the event occurrence identification means has identified that the predetermined event has not occurred (a function for executing the process of step S110 of the main MPU 72 in the first embodiment);
a state response means (a function of executing the processes of steps S118 and S119 of the main MPU 72 in the first embodiment) for bringing the device into the predetermined event response state based on the fact that the event response information is stored in the event response storage area after the event occurrence determination means has determined whether the predetermined event has occurred;
A gaming machine comprising:

According to feature B1, in a configuration in which a predetermined event response state is established based on the event response information being stored in the event response storage area, the event response information is stored in the event response storage area before determining whether or not a predetermined event has occurred, and the event response information is subsequently erased from the event response storage area based on the determination that the predetermined event has not occurred, while the event response information is retained in the event response storage area when the occurrence of the predetermined event is determined. As a result, the event response information is stored in the event response storage area unless the event occurrence determination means determines that the predetermined event has not occurred, and the predetermined event response state is established based on the event response information being stored. Therefore, it is possible to establish a predetermined event response state when the event occurrence determination means does not identify the predetermined event due to the occurrence of electrical noise even though the predetermined event has actually occurred. This makes it possible to execute processing favorably.

Feature B2: The predetermined events include at least a first predetermined event (information abnormality of the power outage flag) and a second predetermined event (an abnormality of the checksum);
The event occurrence identification means includes:
a first event occurrence determination means (a function of executing the process of step S105 of the main MPU 72 in the first embodiment) for determining whether or not the first predetermined event has occurred after the event response information is stored in the event response storage area by the storage execution means;
a second event occurrence determination means (a function of executing the processes of steps S106 to S108 of the main MPU 72 in the first embodiment) for determining whether or not the second predetermined event has occurred after the event response information is stored in the event response storage area by the storage execution means;
Equipped with
the information erasing means, when the first event occurrence identifying means identifies that the first predetermined event has occurred, does not erase the event correspondence information from the event correspondence storage area, and when the second event occurrence identifying means identifies that the second predetermined event has occurred, does not erase the event correspondence information from the event correspondence storage area,
The gaming machine described in feature B1, characterized in that the state response means enters the specified event response state based on the event response information being stored in the event response memory area after the first event occurrence determination means has determined whether the first specified event has occurred and after the second event occurrence determination means has determined whether the second specified event has occurred.

According to feature B2, in a configuration in which a specified event response state is established whether a first specified event or a second specified event has occurred, event response information is stored in an event response storage area before determining whether the first specified event has occurred and whether the second specified event has occurred, and the event response information is erased from the event response storage area based on determining that neither the first specified event nor the second specified event has occurred. This makes it possible to reduce the required storage capacity compared to a configuration in which an event response storage area is provided in correspondence with each of the first specified event and the second specified event.

Feature B3: A means for executing a process (main process) at the start of supply of operating power when the supply of operating power is started (a function for executing the main process of the main MPU 72 in the first embodiment) is provided;
A gaming machine according to feature B1 or B2, characterized in that, during processing at the start of the supply of operating power, processing of each of the memory execution means, the event occurrence identification means, the information erasure means and the status response means is executed.

According to feature B3, if a specified event occurs when the supply of operating power starts, the device goes into a specified event response state, so if a specified event occurs, it becomes possible to deal with it before gameplay begins.

Feature B4: After the event occurrence determination means has determined whether the predetermined event has occurred, and before the state response means executes the process for bringing the device into the predetermined event response state, a trigger determination means (a function for executing the process of step S111 of the main MPU 72 in the first embodiment) for determining whether a special execution trigger (setting change operation) has occurred;
A special process execution means (a function of executing the process of step S120 of the main MPU 72 in the first embodiment) that executes a special process (a setting change process) based on the fact that the occurrence of the special execution trigger is identified by the trigger identification means;
Equipped with
The gaming machine described in any one of features B1 to B3, characterized in that the state response means does not enter the specified event response state if the trigger identification means identifies that the special execution trigger has occurred, even if the event response information is stored in the event response memory area after the event occurrence identification means identifies whether or not the specified event has occurred.

According to feature B4, in a configuration in which special processing is executed when a special execution trigger occurs, even if event response information is stored in the event response storage area, execution of special processing takes precedence over setting a predetermined event response state when a special execution trigger occurs. This makes it possible to prioritize execution of special processing in response to the occurrence of a special execution trigger.

Feature B5. Equipped with a means for executing a process for awarding benefits (a process for drawing lots for winning combinations) in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing a process for drawing lots for winning combinations in the main MPU 72);
The gaming machine according to feature B4, wherein the special process is a changeable process (setting change process) in which the setting value to be used can be changed.

Feature B5 makes it possible to prioritize the execution of a changeable process that can change the setting value to be used over the setting of a specific event response state.

Feature B6. The gaming machine described in Feature B5 is characterized in that it is equipped with an initialization means (a function for executing the processes of steps S301 to S307 of the main MPU 72 in the first embodiment) that initializes the memory area, including the event-responsive memory area, when the changeable process is executed.

According to feature B6, when a changeable process is executed, the memory area, including the event-corresponding memory area, is initialized. Therefore, even if event-corresponding information is stored in the event-corresponding memory area before the changeable process is executed, it is possible to make the event-corresponding information no longer be stored after the changeable process is executed.

Feature B7. The gaming machine described in Feature B6, characterized in that the initialization means causes the number of memory areas to be initialized to be greater when the event response information is stored in the event response memory area than when the event response information is not stored in the event response memory area.

According to feature B7, in a configuration in which execution of a changeable process is prioritized even when event response information is stored in an event response memory area, if the changeable process is executed and event response information is stored, the number of memory areas to be initialized is greater than when no event response information is stored. This makes it possible to thoroughly initialize memory areas when a specified event occurs.

Feature B8. The gaming machine according to any one of Features B1 to B7, characterized in that the specified event is an information abnormality in the storage means in which the event-response storage area is provided.

Feature B8 makes it possible to appropriately deal with the occurrence of information abnormalities in the storage means.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features B1 to B8. This makes it possible to achieve a synergistic effect by combining the features.

<Characteristics Group C>
Feature C1. A means for executing a process for awarding benefits (a process for drawing lots for winning combinations) in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing a process for drawing lots for winning combinations in the main MPU 72);
A changeable means (a function for executing the setting change process of the main MPU 72 in the first embodiment) that executes a changeable process (setting change process) that can change the setting value to be used based on the occurrence of a change response trigger (setting change operation);
An abnormality identification means (a function for executing the processing of steps S105 to S110 of the main MPU 72 in the first embodiment) for identifying whether or not a predetermined abnormality (information abnormality of the power failure flag, an abnormality of the checksum, or an abnormality of the set value) has occurred;
A state response means (a function of executing the processes of steps S118 and S119 of the main MPU 72 in the first embodiment) that sets the state to an abnormality response state based on the fact that the abnormality identification means has identified the occurrence of the predetermined abnormality;
Equipped with
The changeable means executes the changeable processing when the change response trigger occurs even if the abnormality identification means has identified that the specified abnormality has occurred.

According to feature C1, the profit-granting process is executed in a manner corresponding to the setting value set as the target of use, so the player will expect that the setting value set as the target of use will be advantageous. In addition, since the abnormality response state is established based on the identification of the occurrence of a specified abnormality, it is possible to deal with the occurrence of the specified abnormality. In this case, even if the occurrence of a specified abnormality is identified, if a change response trigger occurs, a changeable process that can change the setting value to be used is executed. This makes it possible to prioritize the execution of the changeable process over the establishment of an abnormality response state, and makes it possible to prevent the execution of the changeable process from being hindered by the occurrence of a specified abnormality even when a change response trigger occurs. This makes it possible to ensure that the process is executed in an optimal manner.

Feature C2. The gaming machine described in Feature C1, characterized in that when the changeable process is executed in a situation where the occurrence of the specified abnormality has been identified by the abnormality identification means, the abnormality response state is not entered.

According to feature C2, even if it is determined that a specific abnormality has occurred, if a changeable process is executed, the abnormality response state is not entered, so that it is possible to prevent the abnormality response state from entering after the changeable process is executed.

Feature C3: When the occurrence of the predetermined abnormality is identified by the abnormality identification means, the abnormality information is stored in the abnormality information storage area (information abnormality flag 74g),
The state response means determines the abnormality response state based on the abnormality information being stored in the abnormality information storage area,
This gaming machine is characterized in that it is equipped with a predetermined erasing means (a function of executing the processing of steps S301 to S307 of the main MPU 72 in the first embodiment) that erases the abnormality information when the changeable processing is executed, as described in feature C1 or C2.

According to feature C3, when the changeable process is executed, the abnormality information is erased. This makes it possible to prevent the abnormality response state from occurring when the changeable process is executed even in a situation where it has been determined that a specific abnormality has occurred.

Feature C4: The abnormality information storage area is provided in an information storage means (main RAM 74) having a plurality of storage areas,
The gaming machine described in feature C3 is characterized in that the predetermined erasing means is equipped with a specific erasing means (a function of making a positive judgment in each of steps S302 and S303 in the first embodiment and executing the processing of steps S305 to S307) that increases the number of memory areas among the multiple memory areas provided in the information storage means that are subject to an erasure processing that enables information erasure when the abnormality information is stored in the abnormality information storage area when the changeable processing is executed, compared to when the abnormality information is not stored in the abnormality information storage area.

According to feature C4, in a configuration in which information in the storage area of the information storage means is erased when the changeable process is executed, if abnormality information is stored in the abnormality information storage area when the changeable process is executed, the number of storage areas that are the subject of the erasure process that enables information erasure is greater than when abnormality information is not stored in the abnormality information storage area, so that when a specified abnormality occurs, it is possible to carefully erase information in the storage area of the information storage means when the changeable process is executed.

Feature C5. The gaming machine described in Feature C4, wherein the specific erasing means executes the erasing process on all of the multiple memory areas provided in the information storage means.

According to feature C5, when a changeable process is executed in a situation where it has been determined that a specified abnormality has occurred, an erasure process is executed on all of the multiple storage areas provided in the information storage means, making it possible to deal with the occurrence of the specified abnormality.

Feature C6. The gaming machine described in Features C4 or C5, wherein the specific erasing means, when the changeable process is executed and the abnormality information is not stored in the abnormality information storage area, if an erasure trigger (ON operation of the reset button 56) occurs, targets the same memory area as when the abnormality information is stored in the abnormality information storage area for the erasure process.

According to feature C6, when a changeable process is executed, the erasure process is performed on many storage areas not only when a specified abnormality occurs but also when an erasure trigger occurs. This makes it possible to include situations in which the erasure process is performed on many storage areas when a changeable process is executed, not only when a specified abnormality occurs but also when an erasure trigger occurs.

Feature C7. A gaming machine according to any one of Features C1 to C6, characterized in that the specified abnormality is an information abnormality in the information storage means (main RAM 74).

Feature C7 makes it possible to appropriately deal with information abnormalities in the information storage means.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features C1 to C7. This makes it possible to achieve a synergistic effect by combining the features.

<Feature D group>
Feature D1. A special setting means (a function of making a positive determination in step S111 of the main MPU 72 in the first embodiment) that sets a special execution situation (a situation in which a setting change process is executed) based on the occurrence of a special execution opportunity (a setting change operation);
An information update means (a function for executing the process of step S410 of the main MPU 72 in the first embodiment) for updating the contents (setting values) of the special information stored in the special storage area (the setting value storage area of the main RAM 74) based on the fact that the operation of the predetermined operation means (the reset button 56) is specified in the special execution situation;
Equipped with
A gaming machine characterized in that when the special execution situation occurs while the operation of the specified operation means is continuing, the content of the special information is not updated by the information update means through operation of the specified operation means (step S402 of the main MPU 72 in the first embodiment).

According to feature D1, in a configuration in which the contents of the special information are updated based on the identification of an operation of a specific operation means in a special execution situation, if a special execution situation occurs while the operation of the specific operation means is continuing, the contents of the special information are not updated by the operation of the specific operation means. This makes it possible to prevent the contents of the special information from being updated due to an operation of the specific operation means that is not intended to update the contents of the special information. This makes it possible to ensure that the processing is executed optimally.

Feature D2. Equipped with a means for executing a process for awarding benefits (a process for drawing lots for winning combinations) in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing a process for drawing lots for winning combinations in the main MPU 72);
the special execution situation is a situation in which the set value can be changed,
the special information is information on the setting value being selected,
A gaming machine as described in feature D1, characterized in that the setting value selected in the special execution situation is the object of use.

According to feature D2, when a special execution situation occurs, the setting value to be selected is changed based on the operation of the specified operation means, and the setting value selected in the special execution situation becomes the setting value to be used, so it is possible to set the setting value to be used to the desired one. In this case, if a special execution situation occurs while continuing to operate the specified operation means without intending to change the setting value of the selection target, if the setting value to be selected is changed by the operation of the specified operation means, there is a risk that it will not be possible to appropriately change the setting value. In contrast, with the configuration of feature D1, when a special execution situation occurs while continuing to operate the specified operation means, the setting value of the selection target is not changed by the operation of the specified operation means. This makes it possible to prevent the setting value of the selection target from being changed due to the operation of the specified operation means that is not intended to change the setting value of the selection target.

Feature D3: The special setting means sets the special execution status based on the occurrence of the special execution trigger when the supply of operating power is started,
This gaming machine is characterized in that it is equipped with a means for executing a predetermined operation response process (steps S305 to S307 after a positive judgment is made in step S303) other than setting the special execution status and updating the contents of the special information based on the fact that the predetermined operation means is operated when the supply of operating power is started (a function of making a positive judgment in step S303 of the main MPU 72 in the first embodiment and executing the processes of steps S305 to S307).

According to feature D3, when the supply of operating power is started, the predetermined operation response process is executed based on the fact that the predetermined operation means is operated. This makes it possible to use the predetermined operation means operated to update the contents of the special information in the special execution situation as the operation means for executing the predetermined operation response process when the supply of operating power is started. However, in this configuration, if the operation of the predetermined operation means for executing the predetermined operation response process is continued even in the special execution situation, there is a risk that the contents of the special information will be updated by the operation of the predetermined operation means. In contrast, with the configuration of feature D1, when the special execution situation occurs in a situation where the operation of the predetermined operation means is continued, the contents of the special information will not be updated by the operation of the predetermined operation means. This makes it possible to prevent the contents of the special information from being updated due to the operation of the predetermined operation means for executing the predetermined operation response process.

Feature D4: An operation recognition unit (a function for executing the process of step S602 of the main MPU 72 in the first embodiment) that executes a recognition process (step S602) for determining whether the predetermined operation unit has been operated;
An information storage means (main RAM 74) having a plurality of result storage areas (a reset current state storage area 74h, a reset previous state storage area 74i) for storing information on the grasping result by the grasping process, and capable of identifying the grasping results of the grasping process multiple times by using the information stored in the plurality of result storage areas;
A means for storing information on the results of the determination process for a specific number of times (two times), including the current execution of the determination process, in the multiple result storage areas based on the execution of the determination process (a function for executing the processes of steps S601, S603, and S604 of the main MPU 72 in the first embodiment);
A means for executing a content identification process (step S409) for identifying whether the content of the information stored in the plurality of result storage areas in the special execution situation is an operation corresponding content (the reset previous storage area 74i is "0", and the reset current state storage area 74h is "1") (a function for executing the process of step S409 of the main MPU 72 in the first embodiment);
Equipped with
the information update means updates the content of the special information stored in the special storage area based on the fact that the content of the information stored in the plurality of result storage areas is identified as the operation corresponding content in the content identification process;
A gaming machine described in any one of features D1 to D3, characterized in that the understanding process is executed before the first content identification process is executed in the special execution situation, so that when the special execution situation occurs while operation of the specified operation means is continuing, the content of the special information is not updated by the information update means through operation of the specified operation means.

According to feature D4, whether or not a specific operation means has been operated is grasped in a grasping process, and the grasping results of the multiple grasping processes are stored in multiple result storage areas. Then, if the contents of the information stored in the multiple result storage areas correspond to the operation, the contents of the special information are updated. This makes it possible to update the contents of the special information once for one operation of the specific operation means. In this case, the grasping process is executed before the first content identification process in the special execution situation is executed, so that if a special execution situation occurs while the operation of the specific operation means is continuing, the contents of the special information are not updated by the operation of the specific operation means. In other words, with a simple configuration that ensures the execution of the grasping process before the first content identification process in the special execution situation is executed, it becomes possible to prevent the contents of the special information from being updated by the operation of the specific operation means when a special execution situation occurs while the operation of the specific operation means is continuing.

Feature D5. The device includes a means for executing an interrupt process (timer interrupt process) including the grasping process based on the lapse of the interrupt response period (function for executing timer interrupt process in the main MPU 72);
The gaming machine described in feature D4 is characterized in that, when the special execution situation occurs while operation of the specified operation means is continuing, the progress of a process that may cause an interruption of the interrupt process is put on hold until the interrupt process is executed before the first content-specific process in the special execution situation is executed, and therefore, when the special execution situation occurs while operation of the specified operation means is continuing, the content of the special information is not updated by the information update means through operation of the specified operation means.

According to feature D5, the progress of a process that may cause an interruption of an interrupt process is put on hold until the interrupt process is executed before the first content identification process in a special execution situation is executed, thereby making it possible to guarantee the execution of the grasping process.

Feature D6. A grasping guarantee means (a function for executing the process of step S406 of the main MPU 72 in the first embodiment) for executing the grasping process at least once from when the content identification process is executed once in the special execution situation until the content identification process is executed next time;
A gaming machine described in feature D4 or D5, characterized in that it is equipped with a means (a function of executing the processing of step S402 of the main MPU 72 in the first embodiment) for ensuring that the grasping process is executed at least once separately from the grasping process by the grasping guarantee means before the first content identification process is executed in the special execution situation.

According to feature D6, since the grasping process is executed at least once between the execution of the content identification process once in a special execution situation and the execution of the next content identification process, it is possible to prevent the content of information stored in multiple result storage areas from being identified as the operation-related content multiple times for one operation of a specified operation means. In this case, before the first content identification process is executed, the grasping process is executed at least once separately from the grasping process. This makes it possible to prevent the content of the special information from being updated by the operation of the specified operation means when a special execution situation occurs while the operation of the specified operation means is continuing.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features D1 to D6. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to each of the features of group A, group B, group C, and group D can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the processing in the control means needs to be executed appropriately, and there is still room for improvement in this regard.

<Features Group E>
Feature E1. An opening/closing body (front door 12) that can be opened and closed;
An open detection means (door open sensor 16) for detecting whether the opening/closing body is in an open state;
an open/close corresponding storage area (door state area 74e) for storing information corresponding to the detection result of the open detection means;
a notification execution means (a function for executing the processing of steps S703 and S706 of the main MPU 72 in the first embodiment, and a function for executing the processing for notification in the performance side MPU 92) for executing notification response processing (steps S703 and S706 of the main MPU 72 in the first embodiment, and a function for executing the processing for notification in the performance side MPU 92) when it is determined that the state of the opening/closing body has switched to a notification target state, which is at least one of an open state and a closed state, by utilizing the information stored in the opening/closing corresponding memory area;
An erasure process execution means (a function of executing the processes of steps S301 to S307 of the main MPU 72 in the first embodiment) for executing an information erasure process (steps S301 to S307 of the main MPU 72 in the first embodiment) for the information storage means (main RAM 74) including the open/close corresponding storage area based on the occurrence of an erasure trigger (setting change operation, operation of the reset button 56);
Equipped with
A gaming machine characterized in that, when the erasure process is executed, the information in the opening/closing corresponding memory area becomes information (reset state information) different from the information indicating that the state is one that is subject to notification.

According to feature E1, when it is determined that the state of the opening/closing body is in a state that is subject to notification, a notification response process is executed, so that it is possible to make the manager of the game hall aware that the state of the opening/closing body is in a state that is subject to notification. In this case, when an erasure trigger occurs and an information erasure process is executed for the information storage means including the opening/closing corresponding memory area, the information in the opening/closing corresponding memory area becomes information different from the information indicating that the opening/closing body is in a state that is subject to notification. As a result, when an erasure process is executed in a situation where the opening/closing body is in a state that is subject to notification, the information in the opening/closing corresponding memory area becomes information different from the information indicating that the opening/closing body is in a state that is subject to notification, and the detection result of the opening detection means becomes a detection result indicating that the opening/closing body is in a state that is subject to notification. Therefore, when it is determined that the opening/closing body has switched to a state that is subject to notification, it is possible to execute the notification response process after the erasure process is executed. Therefore, it is possible to preferably execute an alarm corresponding to the state of the opening/closing body.

Feature E2. The gaming machine described in Feature E1, characterized in that the opening and closing body being in a closed state corresponds to the state to be notified.

According to feature E2, even if an act of fraudulently executing an erasure process while the opening/closing body is maintained in a closed state is performed, in this case, even if the opening/closing body is maintained in a closed state, a notification response process is executed to inform the user that the opening/closing body has switched to the closed state after the erasure process is executed. This makes it possible to deal with such fraudulent acts.

Feature E3. The gaming machine described in Feature E1 or E2, characterized in that the notification execution means executes the notification response process when it is determined that the state of the opening/closing body detected by the opening detection means has become the state to be notified in a situation where information different from the information corresponding to the state to be notified is stored in the opening/closing corresponding memory area.

According to feature E3, when it is determined that the state of the opening/closing body detected by the opening detection means has become a state to be notified in a situation where information different from the information corresponding to the state to be notified is stored in the opening/closing corresponding memory area, the notification response process is executed, so that it is possible to execute the notification response process in response to the state of the opening/closing body switching to a state to be notified. Then, when the erasure process is executed in this configuration, the information in the opening/closing corresponding memory area becomes information different from the information indicating that the state is a state to be notified, so that when the erasure process is executed in a situation where the opening/closing body is in a state to be notified, the notification response process is executed after the erasure process is executed.

Feature E4: Both the opening/closing body being in an open state and the opening/closing body being in a closed state correspond to the notification target state,
A gaming machine described in any one of features E1 to E3, characterized in that when the erasure process is executed, the information in the opening/closing corresponding memory area becomes information that is different from both information indicating that the opening/closing body is in an open state and information indicating that the opening/closing body is in a closed state.

According to feature E4, both the open state and the closed state of the opening/closing body correspond to states subject to notification, so notification response processing is executed when the opening/closing body switches to the open state, and notification response processing is executed when the opening/closing body switches to the closed state. In this case, when an information erasure process is executed for the information storage means including the opening/closing corresponding memory area due to the occurrence of an erasure trigger, the information in the opening/closing corresponding memory area becomes information different from both the information indicating that the opening/closing body is in the open state and the information indicating that the opening/closing body is in the closed state. This makes it possible to execute notification response processing when the erasure process is executed, regardless of whether the state of the opening/closing body at that time is the open state or the closed state.

Feature E5. The notification execution means includes:
a means for executing an open-response notification process (step S703 of the main MPU 72 in the first embodiment, step S805 of the performance side MPU 92) when the open detection means detects that the open-close body is in an open state in a situation where information other than information indicating that the open-close body is in an open state is stored in the open-close corresponding memory area (a function for executing the process of step S703 of the main MPU 72 in the first embodiment, and a function for executing the process of step S805 of the performance side MPU 92);
means for executing a notification response process for closure (step S706 of the main MPU 72 in the first embodiment, step S812 of the performance side MPU 92) when the opening detection means detects that the opening/closing body is in a closed state in a situation where information other than information indicating that the opening/closing body is in a closed state is stored in the opening/closing corresponding memory area (a function for executing the process of step S706 of the main MPU 72 in the first embodiment, and a function for executing the process of step S812 of the performance side MPU 92);
A gaming machine according to any one of features E1 to E4, characterized in that it is equipped with:

According to feature E5, when the opening/closing body is switched to the open state, an open-compatible notification response process is executed, and when the opening/closing body is switched to the closed state, a closed-compatible notification response process is executed. In this case, when the erasure process is executed, the information in the opening/closing compatible memory area becomes information different from both the information indicating that the opening/closing body is in the open state and the information indicating that the opening/closing body is in the closed state. As a result, when the erasure process is executed with the opening/closing body in the open state, the opening-compatible notification response process is executed after the erasure process is executed, and when the erasure process is executed with the opening/closing body in the closed state, the closed-compatible notification response process is executed after the erasure process is executed.

Feature E6. A gaming machine according to any one of Features E1 to E5, characterized in that when the erasure process is executed, the open/close corresponding memory area is cleared to "0", and the information in the open/close corresponding memory area becomes information different from the information indicating the state subject to notification.

According to feature E6, even if no additional processing is performed to set information in the open/close compatible storage area after the erasure processing is performed, it is possible to make the information in the open/close compatible storage area different from the information indicating that the storage area is in a state subject to notification when the erasure processing is performed.

Feature E7: The specific operation means (reset button 56, setting key insertion hole 57) is provided in a position exposed in front of the gaming machine when the opening and closing body is in an open state;
A gaming machine described in any one of features E1 to E6, characterized in that the erasure process execution means executes the erasure process based on the fact that the specific operation means is operated when the supply of operating power is started.

Feature E7 makes it possible to achieve the above-mentioned excellent effects in a configuration in which the supply of operating power must be started with the opening/closing body in the open state in order to execute the erasure process.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features E1 to E7. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group E above can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is necessary to appropriately provide notifications corresponding to the state of the opening and closing body that can be opened and closed, and there is still room for improvement in this regard.

<Feature Group F>
Feature F1. A value information storage area (a bet number setting counter 74a, a medium awarding counter of the main RAM 74) capable of storing value information relating to the number of game values (information on the number of bets and the number of game media that have been awarded),
A predetermined display control means (a function of executing the control process of the bet display unit of the main MPU 72 in the first embodiment, a function of executing the process of step S508 of the main MPU 72 in the first embodiment) that controls the display of a predetermined display means (a bet display unit 64, a dual-purpose display unit 66) so that a display corresponding to the value information stored in the value information storage area is performed;
A game control means (a function of executing the reel control process of the main MPU 72 in the first embodiment) controls the game execution means (the reels 32L, 32M, 32R) so that a game unit operation (spinning of the reels 32L, 32M, 32R) is started when a start trigger for one game occurs, and the game unit operation is ended when a termination trigger occurs;
A game corresponding execution means (a function of executing the second control process of the game section of the main MPU 72 in the first embodiment) that executes a game corresponding process (a second control process of the game section) using the value information after the game unit operation is completed;
A value information erasing means for erasing the value information stored in the value information storage area after the game unit operation is completed and before the game corresponding process is executed (a function for executing a clear process at the end of the bonus of the master MPU 72 in the first embodiment);
a separate storage execution means (a function of executing the process of step S911 of the master MPU 72 in the first embodiment) for storing the value information stored in the value information storage area in a separate storage area (a bet number history counter 74f, an award number history counter) before the value information stored in the value information storage area is erased by the value information erasing means within a range of one game;
Equipped with
The gaming machine is characterized in that the game-related execution means executes the game-related processing by utilizing the value information stored in the separate memory area.

According to feature F1, a display corresponding to the value information stored in the value information storage area is performed on a predetermined display means, so that the player can grasp information regarding the number of game values by checking the predetermined display means. In addition, a game-related process is executed using the value information after the game unit operation is completed, so that a process corresponding to the value information can be executed in each game.

In this case, the value information stored in the value information storage area may be erased after the game unit operation has ended and before the game response process is executed. By erasing the value information stored in the value information storage area, the display state of the specified display means is switched accordingly. This makes it possible to notify the user that the game unit operation of a specified game has ended by using the display state of the specified display means, and also makes it possible to switch the display state of the specified display means early when the game unit operation has ended.

In addition, before the value information stored in the value information storage area within the range of one game is erased, the value information stored in the value information storage area is stored in a separate storage area, and the game response process is executed using the value information stored in the separate storage area. This makes it possible to execute the game response process using the value information after the game unit operation is completed, while also making it possible to switch the display state of the predetermined display means early when the game unit operation is completed as described above.

As a result, it is possible to ensure that processing in each game is executed optimally.

Feature F2. The value information is information regarding the number of one or more game values;
The gaming machine described in feature F1, characterized in that the predetermined display control means sets the predetermined display means to a non-display state when the value information is not stored in the value information memory area.

According to feature F2, when the value information stored in the value information storage area is erased, the specified display means is switched to a non-display state. Then, when the game unit operation ends, this switching of the display state occurs quickly, so that it is possible to clearly notify the user by the specified display means that the game unit operation has ended.

Feature F3. A configuration in which the bet value is set in each game,
The gaming machine according to feature F1 or F2, wherein the value information is information corresponding to the number of gaming values bet.

Feature F3 makes it possible to achieve the excellent effects already described in a configuration in which the value information corresponds to the number of gaming values bet.

Feature F4: The game unit operation is executed based on the result of the execution of the game value corresponding to the awarding, and based on this, the game value is awarded to the player by the awarding means (the function of executing the process of step S910 of the master MPU 72 in the first embodiment).
A gaming machine according to any one of features F1 to F3, wherein the value information is information corresponding to the number of gaming values awarded by the awarding means in one game.

Feature F4 makes it possible to achieve the excellent effects already described in a configuration in which the value information corresponds to the number of game values awarded in one game.

Feature F5. A gaming machine according to any one of Features F1 to F4, characterized in that the value information erasing means erases the value information stored in the value information storage area after the game unit operation ends in the final game of a special game state (pseudo bonus state ST4) advantageous to the player and before the game response process is executed.

Feature F5 makes it possible to notify the player that the final game in the special game state has ended by switching the display state of the specified display means.

Feature F6: The value information is information on the number of the value information used in one game or information on the number of the value information granted to a player in one game;
A gaming machine described in any one of features F1 to F5, characterized in that the game-response execution means executes, as the game-response processing, a process for determining an increase or decrease in the number of value information of a player in one game using the value information.

Feature F6 makes it possible to achieve the excellent effects already described in a configuration in which the increase or decrease in the number of players' value information in one game is determined using value information when one game ends.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features F1 to F6. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group F above can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the processing for each game needs to be executed appropriately, and there is still room for improvement in this regard.

<Feature Group G>
Feature G1. A numerical value changing means (CLR execution circuit 122, DEC execution circuit 123 in the second embodiment) for changing numerical information in a predetermined storage area (the first output start flag, the second output start flag, the third output start flag, and the external output end flag in the main RAM 74) in a predetermined manner (clearing to "0" or subtracting 1);
information setting means (NOR circuit 122b, OR circuit 123c in the second embodiment) for setting different information in the target information storage area (jump status flag 121) depending on whether the numerical information before or after the change by the numerical value changing means is the predetermined target numerical information or is not the predetermined target numerical information;
a specific target execution means (a function of executing processing corresponding to the program addresses of “1002”, “1003”, “1005” to “1008”, “1011”, “1012”, “1016”, “1017”, “1025”, and “1026” of the main MPU 72 in the second embodiment) that executes specific target processing (processing of the program addresses of “1002”, “1003”, “1005” to “1008”, “1011”, “1012”, “1016”, “1017”, “1025”, and “1026” in the second embodiment) when the information in the target information storage area is specific target information after the change in the numerical information in the predetermined manner by the numerical value change means is executed;
Equipped with
A gaming machine characterized in that the numerical value changing means and the information setting means are provided as circuits.

According to feature G1, the numerical information in the specified storage area is changed in a specified manner by the numerical value changing means, and different information is set in the target information storage area when the numerical information either before or after the change by the numerical value changing means is the specified target numerical information and when it is not the specified target numerical information. Then, after the numerical value changing means changes the numerical information in a specified manner, a specific target process is executed if the information in the target information storage area is specific target information. This makes it possible not only to change the numerical information in a specified manner, but also to execute a specific target process according to the change manner. In this case, the numerical value changing means that changes the numerical information in the specified storage area in a specified manner and the information setting means that sets information in the target information storage area are provided as circuits. This makes it possible to achieve the above-mentioned excellent effects while reducing the processing load using a program.

Feature G2. The numerical value changing means operates to change the numerical value information in the predetermined manner by executing a change generating instruction in a program (an instruction corresponding to the program addresses "1001", "1005", "1010", "1015", and "1024" in the second embodiment);
The gaming machine described in feature G1, wherein the information setting means sets information in the target information memory area when the numerical value changing means operates.

According to feature G2, simply by setting a change command in the program, the numerical value changing means changes the numerical information in a predetermined manner and the information setting means sets information in the target information storage area. This makes it possible to achieve the above-mentioned excellent effects while reducing the program capacity.

Feature G3. The target information storage area is capable of storing "0" or "1";
A gaming machine described in feature G1 or G2, characterized in that the specific target information is either "0" or "1".

According to feature G3, the target information storage area is a storage area that stores binary information of "0" or "1," making it possible to reduce the storage capacity required for the target information storage area.

Feature G4. The gaming machine described in any one of Features G1 to G3, characterized in that the information setting means sets different information in the target information storage area when the numerical information before the change by the numerical value changing means is the predetermined target numerical information and when the numerical information is not the predetermined target numerical information.

According to feature G4, information corresponding to the numerical information before the change by the numerical change means is set in the target information storage area, so that it is possible to execute a specific target process according to the numerical information before the change without checking the numerical information before the change in the program.

Feature G5. The gaming machine described in Feature G4, wherein the numerical value changing means clears the numerical value information in the specified memory area to "0."

Feature G5 makes it possible to clear numerical information to "0" while reducing program capacity, and also makes it possible to execute processing corresponding to the numerical information before the "0" is cleared without checking the numerical information before the "0" is cleared in the program.

Feature G6. The gaming machine described in any one of Features G1 to G3, characterized in that the information setting means sets different information in the target information storage area when the numerical information after the change by the numerical value changing means is the predetermined target numerical information and when the numerical information is not the predetermined target numerical information.

According to feature G6, information corresponding to the numerical information after the change by the numerical value changing means is set in the target information storage area, so that it is possible to execute a specific target process according to the numerical information after the change without checking the numerical information after the change in the program.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features G1 to G6. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group G above can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the processing in the control means needs to be executed appropriately, and there is still room for improvement in this regard.

<Feature H Group>
Feature H1. In a gaming machine equipped with a control means (main MPU 72 in the second embodiment) that jumps a program to be executed to a program at an address specified in a jump command when a jump condition is satisfied in the jump command,
A first jump instruction (JR instruction) and a second jump instruction (JRS instruction) are set as the jump instructions,
The second jump command has a smaller data capacity than the first jump command.

According to feature H1, a first jump instruction having a relatively large data capacity and a second jump instruction having a relatively small data capacity are set as jump instructions. This makes it possible to reduce the program capacity by using the first jump instruction and the second jump instruction appropriately as needed.

Feature H2. The gaming machine described in Feature H1, characterized in that the second jump instruction has a narrower address range (the difference between program addresses specified by the address data) to which the second jump instruction can jump when the jump condition is satisfied than the first jump instruction.

According to feature H2, the second jump instruction has a smaller data capacity than the first jump instruction, but the address range to which the second jump instruction can jump when the jump condition is satisfied is narrower than that of the first jump instruction. Therefore, by using the second jump instruction when the address range to jump to is narrow, and using the first jump instruction when the address range to jump to is wide, it is possible to reduce the program capacity while still allowing the jump instruction to be executed appropriately.

Feature H3. The gaming machine described in Feature H1 or H2, characterized in that the second jump command has a smaller data capacity (data capacity of condition data) capable of setting the jump condition than the first jump command.

According to feature H3, the second jump instruction has a smaller data capacity than the first jump instruction in order to set a jump condition, but the second jump instruction has a smaller data capacity than the first jump instruction. Therefore, by using the second jump instruction when the jump condition is simple and using the first jump instruction when the jump condition is complex, it is possible to reduce the program capacity while still allowing the jump instruction to be executed appropriately.

Feature H4. A numerical value changing means (CLR execution circuit 122 and DEC execution circuit 123 in the second embodiment) for changing numerical information in a predetermined storage area (the first output start flag, the second output start flag, the third output start flag, and the external output end flag in the main RAM 74) in a predetermined manner (clearing to "0" or subtracting 1);
information setting means (NOR circuit 122b, OR circuit 123c in the second embodiment) for setting different information in the target information storage area (jump status flag 121) depending on whether the numerical information before or after the change by the numerical value changing means is the predetermined target numerical information or is not the predetermined target numerical information;
Equipped with
the numerical value changing means and the information setting means are provided as circuits,
A gaming machine described in any one of features H1 to H3, characterized in that the jump condition of the second jump command is set as to whether or not specified information is set in the target information memory area.

According to feature H4, the numerical information in the specified storage area is changed in a specified manner by the numerical value changing means, and different information is set in the target information storage area when the numerical information either before or after the change by the numerical value changing means is the specified target numerical information and when it is not the specified target numerical information. Then, after the numerical value changing means changes the numerical information in a specified manner, if the information in the target information storage area is the specified information, a jump to a program at a specified address is generated by a second jump command. This makes it possible not only to change the numerical information in a specified manner, but also to jump the program to be executed according to the change manner. In this case, the numerical value changing means that changes the numerical information in the specified storage area in a specified manner and the information setting means that sets information in the target information storage area are provided as circuits. This makes it possible to achieve the above-mentioned excellent effects while reducing the processing load using the program.

Feature H5. The numerical value changing means operates to change the numerical value information in the predetermined manner by executing a change generating instruction in a program (an instruction corresponding to the program addresses "1001", "1005", "1010", "1015", and "1024" in the second embodiment);
The gaming machine according to feature H4, wherein the information setting means sets information in the target information memory area when the numerical value changing means operates.

According to feature H5, simply by setting a change command in the program, the numerical value changing means changes the numerical information in a predetermined manner and the information setting means sets information in the target information storage area. This makes it possible to achieve the above-mentioned excellent effects while reducing the program capacity.

Feature H6. A gaming machine according to Feature H4 or H5, characterized in that the target information storage area is capable of storing "0" or "1".

According to feature H6, since the target information storage area is a storage area that stores binary information of "0" or "1", it is possible to reduce the storage capacity required for the target information storage area.

Feature H7. The gaming machine described in any one of Features H4 to H6, characterized in that the information setting means sets different information in the target information storage area when the numerical information before the change by the numerical value changing means is the predetermined target numerical information and when the numerical information is not the predetermined target numerical information.

According to feature H7, information corresponding to the numerical information before the change by the numerical value changing means is set in the target information storage area, so that it is possible to jump the program to be executed according to the numerical information before the change without checking the numerical information before the change in the program.

Feature H8. The gaming machine described in Feature H7, wherein the numerical value changing means clears the numerical value information in the specified memory area to "0."

Feature H8 makes it possible to clear numerical information to "0" while reducing program capacity, and also makes it possible to execute processing corresponding to the numerical information before the "0" is cleared without checking the numerical information before the "0" is cleared in the program.

Feature H9. The gaming machine described in any one of Features H4 to H6, characterized in that the information setting means sets different information in the target information storage area when the numerical information after the change by the numerical value changing means is the predetermined target numerical information and when the numerical information is not the predetermined target numerical information.

According to feature H9, information corresponding to the numerical information after the change by the numerical value changing means is set in the target information storage area, so that it is possible to jump the program to be executed according to the numerical information after the change without checking the numerical information after the change in the program.

Feature H10. In a gaming machine having a control means for jumping a program to be executed to a program at an address specified in a jump command when a jump condition is satisfied in the jump command,
A first jump instruction (JR instruction) and a second jump instruction (JRS instruction) are set as the jump instructions,
The second jump command has a narrower address range to which a jump can be made when the jump condition is satisfied than the first jump command.

According to feature H10, a first jump instruction is set as a jump instruction having a relatively wide address range that can be jumped to, and a second jump instruction is set as a jump instruction having a relatively narrow address range. This makes it possible to adjust the address range that can be jumped to by using the first jump instruction and the second jump instruction differently as necessary.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features H1 to H10. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group H above can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet on and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, it is preferable to reduce the program capacity required in the control means, and there is still room for improvement in this regard.

<Characteristics Group I>
Feature I1. A game control means (a function of executing the reel control process of the main MPU 72 in the first embodiment) that controls the game execution means (reels 32L, 32M, 32R) so that a game unit operation (spinning of the reels 32L, 32M, 32R) is started when a start trigger for one game occurs based on the operation of the player, and the game unit operation is ended when a termination trigger occurs based on the operation of the player;
a progress waiting means (a function for executing the processes of steps S2211, S2605, S2608, and S2610 of the main MPU 72 in the first embodiment) for setting a progress waiting state (a state in which a freeze period is occurring) in which the progress of the game unit operation based on the player's operation is waited for when a standby trigger occurs (a direct hit is won in the direct hit lottery process of step S2208 and the process of step S2211 is executed, and the start game of the pseudo bonus state ST4 is started and any of the processes of steps S2605, S2608, and S2610 is executed);
A standby restriction means (a function for executing the processes of steps S2602 and S2603 of the main MPU 72 in the first embodiment) that prevents the game from being set to the progress standby state even if the standby trigger occurs in a standby restriction situation (the game following the game in which a freeze period occurred due to a direct hit).
A gaming machine comprising:

According to feature I1, when a standby trigger occurs, the progress of the game unit operation based on the player's operation is put on hold, making it possible to create a situation in which the progress of the game unit operation is put on hold. In this case, if a standby trigger occurs in a standby restriction situation, the game is not set to a progress standby state. This makes it possible to prevent the game from being set to a progress standby state even if a standby trigger occurs in a situation that is not favorable for game progress.

Feature I2. The gaming machine described in Feature I1, wherein the standby restriction means sets the standby restriction state to occur within a range of a predetermined number of games (one game) from the game set in the standby state.

According to feature I2, the game will not be set to the standby state even if a standby trigger occurs within a range of a specified number of games from the game that has been set to the standby state, so it is possible to prevent the standby state from being set repeatedly within a short number of games.

Feature I3. The progress waiting means is
A first progress waiting means (a function for executing the process of step S2211 of the main MPU 72 in the first embodiment) for setting the progress waiting state when a first standby opportunity (a direct winning in the direct lottery process of step S2208) occurs as the standby opportunity;
A second progress waiting means (a function for executing the processes of steps S2605, S2608, and S2610 of the master MPU 72 in the first embodiment) for setting the progress waiting state when a second waiting opportunity (start of the start game of the pseudo bonus state ST4) occurs as the waiting opportunity;
Equipped with
When the progress waiting state is set by the first progress waiting means, the progress waiting state is ended and then the waiting restriction state is entered,
The gaming machine according to feature I1 or I2, wherein the waiting restriction means prevents the progress waiting state from being set even if the second waiting opportunity occurs in the waiting restriction situation.

According to feature I3, the progress waiting state is set when the first waiting trigger occurs, and the progress waiting state is also set when the second waiting trigger occurs. This makes it possible to diversify the situations in which the progress waiting state is set. In this case, if the progress waiting state is set due to the occurrence of the first waiting trigger, the progress waiting state ends and then the progress waiting state becomes a restricted waiting state, and even if the second waiting trigger occurs in the restricted waiting state, the progress waiting state is not set. This makes it possible to create a situation in which, when the progress waiting state is set due to the occurrence of the first waiting trigger, the progress waiting state is not set even if the second waiting trigger occurs.

Feature I4. The first waiting opportunity occurs when a determined event occurs (a direct hit is won in the direct hit lottery process of step S2208) that determines that the player will transition to a special game state (pseudo bonus state ST4) that is advantageous to the player,
A gaming machine described in feature I3, characterized in that the second waiting trigger occurs during the special game state.

According to feature I4, when a definite event occurs that determines a transition to a special game state, the game is set to a progress waiting state, making it possible for the player to clearly recognize that the definite event has occurred. In this case, if the progress waiting state is set due to the occurrence of a first waiting trigger, a waiting restriction state occurs after the progress waiting state ends, and the game is not set to a progress waiting state even if a second waiting trigger occurs in the waiting restriction state. This makes it possible to prevent the game from being set to a progress waiting state in the subsequent special game state when a definite event occurs and the game is set to a progress waiting state.

Feature I5. The game following the game in which the fixed event occurs is the first game in the special game state,
the first standby trigger occurs in a game in which the determined event occurs,
The gaming machine described in feature I4, wherein the second waiting trigger occurs in the first game of the special gaming state.

According to feature I5, the standby state is basically set in the first game of the special game state, so that the player can clearly recognize that the special game state has started. In this case, when a definite event occurs and a transition to the special game state occurs, the standby state is set in the game where the definite event occurred, but the standby state is not set in the first game of the special game state. This makes it possible to prevent the standby state from being set for two consecutive games.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features I1 to I5. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of Group I above can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

In gaming machines such as those exemplified above, it is undesirable for excessive periods of time to occur during which the progress of the game based on the player's operation is forcibly suspended, and there is still room for improvement in this regard.

<Characteristics Group J>
Feature J1. A sequential change means (a function for executing the processes of steps S2407, S2412, S2417, and S2422 of the main MPU 72 in the first embodiment) for sequentially changing the selection target (second to fifth game number modes, second to fifth winning rate modes) that is the subject of the lottery among a plurality of types of selection targets (first to fifth game number modes, first to fifth winning rate modes);
A numerical information acquisition means (a function of executing the LV acquisition process of the main MPU 72 in the first embodiment) for acquiring the numerical information for selection (determination value LV) corresponding to the selection object to be selected from a predetermined numerical information group (the game number mode selection table 112, the winning rate mode selection table 113);
A winning determination means (a function of executing the processes of steps S2410, S2411, S2420, and S2421 of the main MPU 72 in the first embodiment) that determines whether or not the selected object that is the subject of the lottery will be a winning object by using the lottery numerical information acquired by the numerical information acquisition means;
Equipped with
The selection numerical information corresponding to the selection object is configured to be variable according to a game situation (a set value), and there are specific types (six types) of the game situation that can vary the selection numerical information;
A gaming machine characterized in that the group of specified numerical information has a number of lottery numerical information set corresponding to the product of the number of selection objects that can be set as lottery objects by the sequential change means and the number of the specific types.

According to feature J1, the selection objects are changed in sequence among multiple types of selection objects, and the selection numerical information corresponding to the selection object being selected is obtained from a predetermined numerical information group, and the obtained selection numerical information is used to determine whether the selection object being selected will win. In this case, in a configuration in which the selection numerical information corresponding to each selection object can change depending on a specific type of game situation, the predetermined numerical information group is set with a number of selection numerical information corresponding to the product of the number of selection objects that can be set as the selection object and the number of the specific type of game situation. This makes it possible to make the predetermined numerical information group common to all combinations of selection objects and game situations that can be selected. In addition, since the number of selection numerical information corresponding to the specific type of game situation is set for any selection object that can be selected, it is possible to standardize the process when reading out the selection numerical information corresponding to the combination of the selection object and game situation set as the selection object from the predetermined numerical information group. This makes it possible to perform the lottery process preferably.

Feature J2: In a specific game situation among the specific types of game situations, the selection object of a predetermined type is not a winning option (for example, a fifth game number mode when the set value is “1”),
The gaming machine described in feature J1 is characterized in that the group of specified numerical information has non-winning numerical information (a judgment value LV of "0") set as the lottery numerical information corresponding to the specific game situation and the specified type of selection object.

According to feature J2, even if a specific type of selection target does not result in a winning combination in a specific game situation, the specific numerical information group has numerical information corresponding to a non-winning combination set as the selection numerical information corresponding to the specific type of selection target in the specific game situation. As a result, even for selection targets in which a game situation exists in which they are definitely non-winning, there is numerical information for selection corresponding to the specific number. Therefore, for any selection target that can be a selection target, a number of numerical information for selection corresponding to the specific type of game situation is set, and it is possible to standardize the process when reading out the numerical information for selection corresponding to the combination of the selection target and game situation set as the selection target from the specific numerical information group.

Feature J3: In the predetermined numerical information group, the number of the lottery numerical information corresponding to the number of the specific types for each type of the selection object is set,
The gaming machine described in feature J1 or J2 is characterized in that the lottery numerical information of a number corresponding to the number of the specific type corresponding to one type of selection object in the predetermined numerical information group is set so that addresses in the data (address information D(1) to D(24), address information E(1) to E(24)) are consecutive numbers.

According to feature J3, the number of selection numerical information corresponding to the number of specific types corresponding to one type of selection object in the predetermined numerical information group is set so that the addresses in the data are consecutive. As a result, the number of selection numerical information corresponding to the number of specific types for each type of selection object is collectively set in the predetermined numerical information group, making it easier to obtain the selection numerical information corresponding to the current game situation from the selection numerical information corresponding to the selection object that is the subject of the lottery.

Feature J4. The gaming machine described in Feature J3, characterized in that the address order of the data for the lottery numerical information, the number of which corresponds to the number of the specific types of selection objects aggregated for each type of selection object in the predetermined numerical information group, is a fixed order according to the type of the corresponding game situation.

According to feature J4, the order of addresses of the data for the number of selection numerical information corresponding to the number of specific types aggregated for each type of selection object in the predetermined numerical information group is a fixed order according to the type of corresponding game situation. As a result, the order of addresses in the data in which the selection numerical information corresponding to the current game situation among the selection numerical information corresponding to the selection object that is the subject of the lottery is set is uniquely determined according to the type of the game situation. Therefore, it becomes easier to obtain the selection numerical information corresponding to the current game situation among the selection numerical information corresponding to the selection object that is the subject of the lottery.

Feature J5. The gaming machine described in Feature J4, characterized in that the numerical information acquisition means executes an address derivation calculation process (steps S2501 to S2504) using numerical information corresponding to the arrangement order in the predetermined numerical information group of the selection objects that are the subject of the lottery and numerical information corresponding to the order set in accordance with the current game status in the fixed order, thereby acquiring an address in the data in which the numerical information for lottery is set that corresponds to the combination of the selection objects that are the subject of the lottery and the current game status in the predetermined numerical information group.

According to feature J5, an address deriving operation is performed using numerical information corresponding to the arrangement order in a predetermined numerical information group of the selection objects to be selected and numerical information corresponding to an order set in a certain order corresponding to the current game status, thereby obtaining an address in the data in which numerical information for selection corresponding to the combination of the selection objects to be selected and the current game status in the predetermined numerical information group is set. This makes it possible to reduce the processing load when obtaining numerical information for selection corresponding to the combination of the selection objects to be selected and the current game status.

Feature J6: Equipped with a means for executing a profit awarding process (a lottery process for a winning combination) in a manner corresponding to a set value set as a target for use from among a plurality of set values corresponding to the player's advantage level (a function for executing a lottery process for a winning combination in the main MPU 72);
The setting values that can be set as the target for use are of the specific type,
A gaming machine according to any one of features J1 to J5, characterized in that the specific types of gaming situations each have different setting values that are set as the object of use.

Feature J6 makes it possible to achieve the above-mentioned excellent effects in a configuration in which lottery numerical information corresponding to the setting value set as the target for use is obtained.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features J1 to J6. This makes it possible to achieve a synergistic effect by combining the features.

<Feature K group>
Feature K1. A numerical value update means (the second random number circuit 76 in the first embodiment) that updates the predetermined number of bits (16 bits) of predetermined numerical value information (second random number) stored in the predetermined numerical value storage area every time an update trigger occurs;
A first lottery execution means (a function of executing the process of step S2403 of the main MPU 72 in the first embodiment) that executes a first lottery process (step S2403 in the first embodiment) by using the predetermined numerical information;
A partial acquisition means for acquiring numerical information of a specific number of bits (8 bits or 7 bits) that is less than the predetermined number of bits from the predetermined numerical information (a function for executing the processes of steps S2406, S2415, and S2416 of the main MPU 72 in the first embodiment);
A second lottery execution means (a function of executing the processing of steps S2407 to S2413 and steps S2417 to S2423 of the main MPU 72 in the first embodiment) that executes a second lottery process (steps S2407 to S2413 and steps S2417 to S2423 in the first embodiment) using the numerical information of the specific number of bits acquired by the part acquisition means;
A gaming machine comprising:

According to feature K1, in a configuration in which a predetermined number of bits of predetermined numerical information is updated each time an update trigger occurs, there are cases in which a first lottery process is executed using the predetermined number of bits of the predetermined numerical information, and cases in which a second lottery process is executed using a specific number of bits of numerical information that is a number of bits less than the predetermined number of bits of the predetermined numerical information. This makes it possible to increase the number of lottery processes while suppressing an increase in the number of numerical update means. This makes it possible to execute the lottery processes in an optimal manner.

Feature K2: The part acquisition means is
A numerical value reading means for reading the predetermined numerical value information from the predetermined numerical value storage area (a function for storing a second random number in the latch area 111);
An acquisition execution means for acquiring the specific number of bits of numerical information from the predetermined numerical information read by the numerical value reading means (a function for executing the processes of steps S2406, S2415, and S2416 of the main MPU 72 in the first embodiment);
The gaming machine according to feature K1 is characterized by comprising:

According to feature K2, when using numerical information of a specific number of bits, the specific numerical information is read from the specific numerical storage area, and the specific numerical information of the specific number of bits is obtained from the read specific numerical information. This makes it possible to read the specific numerical information from the specific numerical storage area in the same way as when the first lottery process is executed, even when using numerical information of a specific number of bits.

Feature K3. The gaming machine according to Feature K2, wherein the acquisition execution means acquires the specific number of bits of numerical information by clearing to "0" target bits that are different from the specific number of bits to be used in the predetermined numerical information read by the numerical value reading means.

According to feature K3, the specific number of bits of numerical information are obtained by clearing to "0" target bits that are different from the specific number of bits to be used in the specific numerical information read from the specific numerical storage area. This makes it possible to simplify the processing configuration for obtaining the specific number of bits of numerical information from the specific number of bits of the specific numerical information.

Feature K4. The gaming machine described in Feature K3, characterized in that the predetermined numerical information is data in units of bytes, and the numerical information of the specific number of bits is also data in units of bytes including the specific number of bits and the target bit.

According to feature K4, even if the numerical information is a specific number of bits, it can be treated as data in units of bytes, just like specified numerical information.

Feature K5. A gaming machine according to any one of features K1 to K4, characterized in that the predetermined numerical information is updated by the numerical update means one or more times between the time when the predetermined numerical information is used in one of the first lottery process and the second lottery process and the time when the predetermined numerical information is used in the other lottery process.

According to feature K5, in a configuration in which the predetermined numerical information stored in the predetermined numerical memory area is used in either the first lottery process or the second lottery process, the predetermined numerical information is updated by the numerical update means one or more times between the time the predetermined numerical information is used in one of the lottery processes and the time the predetermined numerical information is used in the other lottery process. This makes it possible to prevent the lottery results of the first lottery process and the second lottery process from being synchronized, even in a configuration in which the predetermined numerical information stored in the predetermined numerical memory area is used in either the first lottery process or the second lottery process.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features K1 to K5. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to each of the features of the above group of features J and group of features K can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the lottery process needs to be executed appropriately, and there is still room for improvement in this regard.

<Feature L group>
Feature L1. A first setting means (a function for executing the processing of steps S3206 and S3210 of the main MPU 72 in the first embodiment) that sets the first output information (information of "2") in the output information storage area (output timing counter of the main RAM 74) when a special opportunity (transition to AT state ST5, continuation of the set of AT state ST5) occurs;
An output stop means (a function of executing the process of step S3304 of the main MPU 72 in the first embodiment) that stops the output of a predetermined external signal (a first external signal of a HI level) based on the first output information being set in the output information storage area;
A second setting means (a function of executing the process of step S3302 of the main MPU 72 in the first embodiment) for setting second output information (information of “1”) in the output information storage area when the output of the predetermined external signal is stopped by the output stopping means;
An output start means (a function of executing the process of step S3306 of the main MPU 72 in the first embodiment) that starts output of the predetermined external signal based on the second output information being set in the output information storage area;
A gaming machine comprising:

According to feature L1, in a configuration in which the output of a specified external signal is stopped once and then restarted when a special trigger occurs, the first output information is first set in the output information storage area, and then when the output of the specified external signal is stopped, the second output information is set in the output information storage area. This makes it possible to stop the output of the specified external signal once and then restart the output of the specified external signal simply by sequentially updating the information set in the output information storage area. This makes it possible to perform processing for outputting the specified external signal in an optimal manner.

Feature L2. A gaming machine as described in Feature L1, characterized in that it is provided with a third setting means (a function of executing the processing of step S3203 of the main MPU 72 in the first embodiment) that sets the second output information to a state in which the second output information is set in the output information storage area when a predetermined output trigger (a transition to pseudo bonus state ST4) occurs that is different from the case in which the output stopping means stops the output of the predetermined external signal.

According to feature L2, when the output of the specified external signal is simply started, rather than when the output of the specified external signal is stopped once and then restarted, the output of the specified external signal is started by setting the second output information in the output information storage area. This makes it possible to use the output information storage area to control the output of the specified external signal in both cases when the output of the specified external signal is stopped once and then restarted, and when the output of the specified external signal is simply started.

Feature L3: When the output start means starts outputting the predetermined external signal, sustain information is set in the output information storage area,
A gaming machine according to feature L1 or L2, characterized in that the state of the predetermined external signal is not changed in a state in which the sustain information is set in the output information memory area.

Feature L3 makes it possible to maintain the state in which a specific external signal is output by utilizing the output information storage area.

Feature L4. The information set in the output information storage area is numerical information;
A gaming machine described in any one of features L1 to L3, characterized in that the second output information is numerical information obtained by varying the first output information by a predetermined target value ("1").

According to feature L4, by varying the numerical information by a predetermined variation target value, it is possible to restart the output of a predetermined external signal that has been temporarily stopped.

Feature L5. A gaming machine according to any one of features L1 to L4, characterized in that the process of determining whether to cause the output stop means to stop output of the predetermined external signal and the output start means to start output of the predetermined external signal based on the information stored in the output information storage area (steps S3301 and S3303 in the first embodiment) is performed at a predetermined timing in one game.

According to feature L5, when the output of a specified external signal is stopped once and then restarted, it is possible to guarantee a period of one game as the period during which the output of the specified external signal is stopped.

Feature L6. A gaming machine according to any one of features L1 to L5, characterized in that the special trigger occurs in a situation where the specified external signal is being output.

Feature L6 makes it possible to achieve the above-mentioned excellent effects when the output of a specified external signal is stopped once and then restarted.

Feature L7. A gaming machine according to any one of features L1 to L6, characterized in that the first setting means sets the first output information in the output information storage area as the occurrence of the special opportunity when a period advantageous to the player (a set of pseudo bonus state ST4 and AT state ST5) ends and the advantageous period (continuation of the set of AT state ST5) or another advantageous period (start of AT state ST5) begins.

Feature L7 makes it possible to achieve the above-mentioned excellent effects when the output of a specific external signal is temporarily stopped and then restarted in a situation where an advantageous period continues.

Feature L8. When a plurality of games are executed in a predetermined game state (AT state ST5) and one execution round is completed, if the continuation condition is satisfied, a new execution round is started by an execution round continuation means (a function for executing the processing of steps S3114 to S3116 of the main MPU 72 in the first embodiment);
The gaming machine according to any one of features L1 to L7, wherein the special opportunity occurs when a new execution round is started by the execution round continuing means.

Feature L8 makes it possible to achieve the above-mentioned excellent effects when the output of the specified external signal is temporarily stopped and then restarted when one execution round of a specified game state ends and a new execution round begins.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features L1 to L8. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group L of features above can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the output of external signals needs to be executed appropriately, and there is still room for improvement in this regard.

<Feature M group>
Feature M1. In a gaming machine in which at least a first gaming status (CB status, non-CB status in which CB winning data is stored, non-CB status in which CB winning data is not stored) and a second gaming status (when the number of bets is "2" and when the number of bets is "3") exist as gaming statuses, and a game is executed in a manner corresponding to the contents of these gaming statuses,
A first update means (a function for executing the processes of steps S1402 and S1405 of the master MPU 72 in the first embodiment) for updating the judgment numerical information (judgment value) in the judgment storage area (judgment value counter 74j) so that the judgment numerical information (judgment value) varies according to the contents of the first game status;
A second update means (a function of executing the process of step S1403 of the master MPU 72 in the first embodiment) for updating the determination numerical information in the determination storage area so that the determination numerical information varies depending on the content of the second game situation;
An information response execution means (a function of executing the lottery process of the hand of the main MPU 72 in the first embodiment) that executes information response processing (lottery process of the hand) by using the judgment numerical information of the judgment storage area;
A gaming machine comprising:

According to feature M1, the judgment numerical information in the judgment memory area is updated to vary according to the content of the first game situation, and is updated to vary according to the content of the second game situation. Then, information response processing is executed using the judgment numerical information in the judgment memory area. In other words, information based on the content of multiple game situations, including the content of the first game situation and the content of the second game situation, is aggregated as judgment numerical information, and it is possible to execute information response processing according to the content of the multiple game situations simply by referring to the aggregated judgment numerical information. Therefore, it is possible to simplify the processing configuration for executing information response processing according to the content of the multiple game situations.

Feature M2: The first update means changes the numerical information for judgment in the storage area for judgment to one of an increasing side and a decreasing side,
The gaming machine described in feature M1 is characterized in that the second update means changes the judgment numerical information in the judgment memory area to the same side as the side to which the first update means changes it, out of the sides to which the judgment numerical information increases and decreases.

According to feature M2, the numerical information for judgment in the memory area for judgment fluctuates to either the increasing or decreasing side depending on the content of each game situation. This makes it possible to prevent the correspondence between the combinations of the content of multiple game situations and the numerical information for judgment from becoming complicated.

Feature M3. The content of the first game situation is of multiple types;
The first update means varies the numerical information for determination in the memory area for determination by an amount of variation corresponding to a type of content of the first game situation,
The second game status has a plurality of types,
A gaming machine of feature M1 or M2, characterized in that the second update means varies the judgment numerical information in the judgment memory area by an amount of variation corresponding to the type of content of the second game status.

According to feature M3, the numerical information for judgment is changed by an amount of change according to the type of content of the first game situation, and the numerical information for judgment is changed by an amount of change according to the content of the second game situation. This makes it possible to aggregate information based on the content of multiple game situations, including the content of the first game situation and the content of the second game situation, as the numerical information for judgment.

Feature M4. A gaming machine according to any one of features M1 to M3, characterized in that when the content of the first game situation is a specific type of content (CB state), the first update means changes the numerical information for judgment in the judgment memory area by an amount corresponding to the specific type of content, while the second update means does not change the numerical information for judgment.

According to feature M4, when the content of the first game situation is a specific type of content, the numerical information for judgment is changed by an amount corresponding to the specific type of content, while the numerical information for judgment is not changed according to the content of the second game situation. This makes it possible to prevent multiple types of numerical information for judgment from existing for a situation in which the content of the second game situation does not affect the execution content of the information response process when the content of the first game situation is a specific type of content.

Feature M5. The first gaming state is a gaming state;
A gaming machine according to any one of features M1 to M4, wherein the second gaming status is the number of bets in one game.

Feature M5 makes it possible to achieve the excellent effects already described when executing information response processing according to the game status and number of bets.

Feature M6. The gaming machine according to any one of features M1 to M5, characterized in that the information-corresponding execution means executes the lottery process in a manner corresponding to the judgment numerical information in the judgment memory area.

According to feature M6, information based on the contents of multiple game situations, including the contents of the first game situation and the contents of the second game situation, is aggregated as numerical information for judgment, and it becomes possible to execute a lottery process according to the contents of multiple game situations simply by referring to the aggregated numerical information for judgment. This makes it possible to simplify the processing configuration for executing a lottery process according to the contents of multiple game situations.

Feature M7: The information response execution means
A sequential change means (a function for executing the processes of steps S1304 and S1309 of the main MPU 72 in the first embodiment) for sequentially changing the selection target to be selected from among a plurality of types of selection targets (index value IV);
A numerical information acquisition means (a function of executing the PV acquisition process of the main MPU 72 in the first embodiment) for acquiring numerical information for selection (point value PV) for selection based on collating the numerical information for judgment in the judgment storage area with a corresponding information group (data group 101a to 101q for IV=1 to 17) provided in correspondence with the selection object for selection;
A winning determination means (a function of executing the process of step S1307 of the main MPU 72 in the first embodiment) that determines whether the selected object that is the subject of the lottery will be a winning object by using the lottery numerical information acquired by the numerical information acquisition means;
A gaming machine described in any one of features M1 to M6, characterized in that it is equipped with:

According to feature M7, the selection numerical information is acquired by comparing the judgment numerical information in the judgment memory area with a corresponding information group corresponding to the selection object that is the subject of the lottery, and the selection numerical information is used to determine whether the selection object that is the subject of the lottery has been won. As a result, even if the selection numerical information corresponding to the selection object is configured to vary depending on the content of various game situations, the selection numerical information can be acquired only by comparing the judgment numerical information with the corresponding information group corresponding to the selection object, which simplifies the processing configuration for acquiring the selection numerical information.

Feature M8: In the corresponding information group (IV=17 data group 101q) corresponding to the predetermined selection object, the lottery numerical information is not set for the predetermined judgment numerical information (judgment value counter 74j="1");
The gaming machine described in feature M7 is characterized in that the numerical information acquisition means is equipped with a means (a function of executing the processing of step S1509 of the main MPU 72 in the first embodiment) for deriving non-winning numerical information ("0") as the lottery numerical information corresponding to a specific judgment numerical information when the lottery numerical information corresponding to the judgment numerical information is not set in the corresponding information group.

According to feature M8, in a configuration in which a predetermined selection target is not guaranteed to be a winner when the combination of various game states is a predetermined combination, the corresponding information group corresponding to the selection target does not have lottery numerical information set for the judgment numerical information corresponding to the predetermined combination. This makes it possible to reduce the data capacity of the corresponding information group. In addition, for judgment numerical information for which lottery numerical information is not set in the corresponding information group, numerical information corresponding to a non-win is derived separately, making it possible to make the judgment numerical information a non-win.

Feature M9. In the corresponding information group, the lottery numerical information is set so that the order of the corresponding judgment numerical information corresponds to the address on the data (address data A(0) to A(3), B(0) to B(4), C(0) to C(1));
The gaming machine described in feature M7 or M8 is characterized in that the numerical information acquisition means is equipped with a means for acquiring the lottery numerical information set in an order corresponding to the judgment numerical information in the judgment memory area from the corresponding information group (a function for executing the processing of step S1508 of the main MPU 72 in the first embodiment).

According to feature M9, it is only necessary to obtain the numerical information for lottery selection, which is set in an order corresponding to the numerical information for judgment, from the corresponding information group, thereby simplifying the processing configuration for obtaining the numerical information for lottery selection from the corresponding information group.

Feature M10: The corresponding information group has a number of judgment areas (game state data 102a) corresponding to the number of types of the judgment numerical information,
The first information ("1") is set in the judgment area corresponding to the type of the judgment numerical information set in the lottery numerical information,
The second information ("0") is set in the judgment area corresponding to the type of the judgment numerical information in which the lottery numerical information is not set,
The gaming machine described in any one of features M7 to M9, characterized in that the numerical information acquisition means is equipped with a means for acquiring the lottery numerical information set in correspondence with the judgment area in the corresponding information group when the first information is set in the judgment area corresponding to the judgment numerical information in the judgment memory area in the corresponding information group being referenced (a function for executing the processing of step S1508 of the main MPU 72 in the first embodiment).

According to feature M10, simply by determining whether the first information or the second information is set in the determination area, it is possible to determine whether the corresponding information group corresponding to the selection target has lottery numerical information set corresponding to the judgment numerical information. Therefore, it is possible to simplify the processing configuration for determining whether the corresponding information group has lottery numerical information corresponding to the judgment numerical information set.

Feature M11. The gaming machine described in Feature M10, characterized in that the numerical information acquisition means includes a means (a function of executing the process of step S1509 of the main MPU 72 in the first embodiment) for deriving non-winning numerical information ("0") as the lottery numerical information corresponding to the judgment numerical information when the second information is set in the judgment area corresponding to the judgment numerical information in the corresponding information group being referenced.

According to feature M11, when second information is set in the judgment area, the lottery numerical information corresponding to that judgment numerical information is not set in the corresponding information group, and the numerical information corresponding to the non-winning lottery is derived separately. This makes it possible to reduce the data capacity of the corresponding information group.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features M1 to M11. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the features of group M of features above can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the processing in the control means needs to be executed appropriately, and there is still room for improvement in this regard.

<Feature N group>
Feature N1. A sequential change means (a function for executing the processes of steps S1304 and S1309 of the main MPU 72 in the first embodiment) for sequentially changing the selection target to be selected from among a plurality of selection targets (index value IV),
A numerical information acquisition means (a function of executing a PV acquisition process of the main MPU 72 in the first embodiment) for acquiring numerical information for selection (point value PV) corresponding to the selection object that is the object of the selection;
A winning determination means (a function of executing the process of step S1307 of the main MPU 72 in the first embodiment) that determines whether the selected object that is the subject of the lottery will be a winning object by using the lottery numerical information acquired by the numerical information acquisition means;
Equipped with
The determination of whether or not a win is determined by the winning determination means is performed in each of a plurality of game states (CB state, non-inner state with two bets, non-inner state with three bets, inner state with two bets, and inner state with three bets),
In a predetermined game state (e.g., CB state) among the plurality of game states, the predetermined type of selection target (index value IV=17) is not the winning option,
The gaming machine is characterized in that the predetermined type of selection object is made the lottery object by the sequential change means even in the predetermined game status.

According to feature N1, numerical lottery information corresponding to a selection object that is the subject of a lottery among multiple types of selection objects is acquired, and the acquired numerical lottery information is used to determine whether or not the selection object that is the subject of the lottery will be a winner. Furthermore, the determination of whether or not the selection object will be a winner is made in each of multiple types of game situations. In this case, although a configuration is such that a selection object of a predetermined type is not a winner in a predetermined game situation, the selection object of the predetermined type is subject to a lottery even in the predetermined game situation. This makes it possible to unify the types of selection objects in any game situation. Therefore, it is possible to make the processing configuration for determining whether or not a selection object is a winner common to multiple types of game situations, and it is possible to make the configuration for conducting the lottery optimal.

Feature N2. The gaming machine described in Feature N1, characterized in that the types of selection objects that can be selected by the sequential change means in the multiple types of game situations are the same.

According to feature N2, the types of selection objects that can be selected in the lottery are the same in multiple types of game situations, so it is possible to make the processing configuration for determining whether or not the selection object is a winning object common to multiple types of game situations, and it is possible to make the configuration for conducting the lottery optimal.

Feature N3. A corresponding information group (data group 101a to 101q for IV=1 to 17) is set corresponding to each of the plurality of types of selection objects,
The gaming machine described in feature N1 or N2 is characterized in that the numerical information acquisition means acquires the numerical information for the lottery by comparing information corresponding to the current game situation (the value of the judgment value counter 74j) with the corresponding information group corresponding to the selection object that is the subject of the lottery.

According to feature N3, a corresponding information group is set corresponding to each of the multiple types of selection objects, and the selection numerical information is obtained by comparing the information corresponding to the current game situation with the corresponding information group corresponding to the selection object that is the subject of the lottery. This makes it possible to simplify the processing configuration for obtaining the selection numerical information.

Feature N4. The corresponding information group (IV=17 data group 101q) corresponding to the predetermined selection object does not have the lottery numerical information set for a predetermined game situation,
The gaming machine described in feature N3 is characterized in that the numerical information acquisition means is equipped with a means for deriving numerical information corresponding to a non-winning result ("0") as the numerical information for lottery when the numerical information for lottery corresponding to the specified gaming situation is not set in the corresponding information group (a function for executing the processing of step S1509 of the main MPU 72 in the first embodiment).

According to feature N4, in a configuration in which a predetermined selection target is not guaranteed to be a winning combination when the combination of various game states is a predetermined combination, the corresponding information group corresponding to the selection target does not have lottery numerical information set for the predetermined combination. This makes it possible to reduce the data capacity of the corresponding information group. In addition, for the above-mentioned predetermined combination for which lottery numerical information is not set in the corresponding information group, numerical information corresponding to a non-winning result is derived separately, making it possible to make the predetermined combination a non-winning result.

Feature N5. The corresponding information group has a number of judgment areas (game status data 102a) corresponding to the plurality of types of game situations,
The first information ("1") is set in the judgment area corresponding to the type of game situation for which the lottery numerical information is set,
The second information ("0") is set in the judgment area corresponding to the type of game situation in which the lottery numerical information is not set,
The gaming machine described in feature N3 or N4 is characterized in that the numerical information acquisition means is equipped with a means for acquiring the lottery numerical information set in the corresponding information group in correspondence with the judgment area corresponding to the current game status when the first information is set in the judgment area in the corresponding information group being referenced (a function for executing the processing of step S1508 of the main MPU 72 in the first embodiment).

According to feature N5, simply by determining whether the first information or the second information is set in the judgment area, it is possible to determine whether the corresponding information group corresponding to the selection target has lottery numerical information set corresponding to the current game situation. Therefore, it is possible to simplify the processing configuration for determining whether the corresponding information group has lottery numerical information set corresponding to the current game situation.

Feature N6. The gaming machine described in Feature N5, characterized in that the numerical information acquisition means includes a means (a function for executing the process of step S1509 of the main MPU 72 in the first embodiment) for deriving numerical information corresponding to a non-winning event ("0") as the lottery numerical information when the second information is set in the judgment area corresponding to the current game status in the corresponding information group being referenced.

According to feature N6, when the second information is set in the judgment area, the lottery numerical information corresponding to the current game situation is not set in the corresponding information group, and the numerical information corresponding to non-winning is derived separately. This makes it possible to reduce the data capacity of the corresponding information group.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features N1 to N6. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to the above group of feature N can solve the following problems:

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the lottery process needs to be executed appropriately, and there is still room for improvement in this regard.

<Characteristic group O>
Feature O1. When a call trigger (PUSH command) occurs to call and execute another process (ending determination process in the third embodiment) in a situation where a predetermined process (process for advantageous state at the start of a game in the third embodiment, process for AT state at the start of a game) is being executed, information storage and execution means (function for executing the processes of steps S3504 and S3601 of the main MPU 72 in the third embodiment) for storing information of the return address of the predetermined process after the end of the other process in a specific storage area (stack area 125);
An information reading means (a function of executing the processes of steps S3703, S3704, and S3705 of the main MPU 72 in the third embodiment) for reading information of the return address from the specific storage area when a read opportunity (a POP command) occurs that enables the end of the other process and return to the specified process;
Equipped with
The specific storage area has a plurality of unit storage areas (unit storage areas 125a),
the information storage execution means, when the call trigger occurs a plurality of times without the information readout means reading out the information of the return address, stores the information of the return address in the plurality of unit storage areas in a predetermined order;
the information reading means, when the read trigger occurs in a situation where a plurality of pieces of information of the return address are stored, reads the information of the return address stored in a later order,
This gaming machine is
A process return means (a function of executing the processes of steps S3703 and S3705 of the main MPU 72 in the third embodiment) that returns to a process corresponding to the information of the return address when the information of the return address is read by the information reading means due to the occurrence of the read trigger;
A non-return means (a function of executing the process of step S3704 of the main MPU 72 in the third embodiment) that does not return to the process corresponding to the information of the return address even though the information of the return address is read by the information reading means due to the occurrence of the read trigger;
A gaming machine comprising:

According to feature O1, when a call trigger occurs to read and execute another process while a specific process is being executed, the return address information of the specific process is stored in the unit memory area that is the storage target in the specific memory area. Also, when a read trigger occurs to return to the specific process after the other process is completed, the return address information is read from the unit memory area that is the read target in the specific memory area. Then, by returning to the process corresponding to the read return address information, the process to be returned to in the specific process is returned to. Also, when multiple call triggers occur without reading the return address information, the return address information is stored in a specified order in multiple unit memory areas, and when a read trigger occurs in a situation where multiple return address information is stored, the stored order is read from the information of the later return address. As a result, if the process is repeatedly called before the process is returned, the order that was the call source is returned to starting from the later process.

In the above configuration, even if the information of the return address is read due to the occurrence of a read trigger, the process corresponding to the information of the return address may not be returned to. As a result, while the processes are basically returned to in the order from which they were read, starting with the last process, it is possible to exceptionally not follow this order and return to the process to be returned to in an order that skips a certain number of processes. This makes it possible to execute the processes in an optimal manner.

Feature O2: A means for changing the unit storage area to be the storage target in the predetermined order when the return address information is stored in the unit storage area to be the storage target among the plurality of unit storage areas (a function for executing the processes of steps S3504 and S3601 of the main MPU 72 in the third embodiment);
a means for changing the unit storage area to be read out in an order reverse to the predetermined order when information of the return address is read out from the unit storage area to be read out among the plurality of unit storage areas (a function for executing the processes of steps S3703, S3704, and S3705 of the main MPU 72 in the third embodiment);
A gaming machine according to feature O1, characterized in that it is equipped with:

According to feature O2, the unit memory areas in which the return address information is stored are changed in a predetermined order, while the unit memory areas in which the return address information is read are changed in the reverse order to the predetermined order. In this configuration, if an event occurs in which the return address information is read due to a read trigger, but the process corresponding to the return address information is not returned to, the next unit memory area in the reverse order to the predetermined order relative to the unit memory area in which the return address information was stored becomes the next read target. This makes it possible to return the processes to be returned to in an order skipping a predetermined number of processes.

Feature O3. A gaming machine according to feature O1 or O2, characterized in that when it is determined that a special condition is satisfied in the other process (when a positive determination is made in step S3701 or step S3702), after an event occurs in which the information of the return address is read by the information reading means due to the occurrence of the read trigger but the non-returning means does not return to the process corresponding to the information of the return address, an event occurs in which the information of the return address is read by the information reading means due to the occurrence of the read trigger and the process return means returns to the process corresponding to the information of the return address.

According to Feature O3, in a configuration in which another process is called and executed while a specific process is being executed, if a special condition is met, return address information for returning to the specific process is read from a specific storage area, but a return to the specific process is not made. Then, the return address information that was stored in the specific storage area before the return address information was stored is read, and a return is made to the process corresponding to the return address information. This makes it possible to return to the processes to be returned to in an order skipping a specific number of processes when a special condition is met.

Feature O4. A gaming machine according to Feature O3, characterized in that if it is determined that the special condition is not satisfied in the other process (if a negative determination is made in each of steps S3701 and S3702), an event that does not cause a return to the process corresponding to the information at the return address occurs even though the information at the return address is read by the information reading means due to the occurrence of the read trigger, an event that causes the information at the return address to be read by the information reading means and causes the process returning means to return to the process corresponding to the information at the return address occurs, and a process (steps S3506 to S3511, steps S3603 to S3616) corresponding to the special condition not being satisfied in the specific process to which the game machine has returned is executed.

According to feature O4, when it is determined that the special condition is not satisfied in another process, an event does not occur that prevents a return to the process corresponding to the return address information even though the return address information has been read, and the process is returned to the process corresponding to the read return address information. Then, in the specified process to which the process has been returned, a process corresponding to the special condition not being satisfied is executed. This makes it possible to differentiate the progress of the process between when the special condition is satisfied in the other process and when it is not satisfied. Also, since there is no return to the specified process when the special condition is satisfied in the other process, there is no need to set a process to prevent the process corresponding to the special condition not being satisfied in the specified process from being executed.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features O1 to O4. This makes it possible to achieve a synergistic effect by combining the features.

<Feature P group>
Feature P1. A predetermined calculation means (a function for executing the process of step S3901 in the main MPU 72 in the fourth embodiment, and a function for executing the process of step S4101 in the main MPU 72 in the fifth embodiment) that executes a predetermined calculation process (step S3901 in the fourth embodiment, and step S4101 in the fifth embodiment) on the calculation target numerical information (the value of the monitoring period counter KK),
a corresponding storage area (carry flag CF) in which limit exceeding corresponding information ("1") is stored when the calculation target numerical information exceeds a predetermined limit value (a maximum value in the fourth embodiment, a minimum value in the fifth embodiment) as a result of the predetermined calculation processing by the predetermined calculation means;
A limit value setting means for setting the numerical information to be calculated as the predetermined limit value when the limit exceeding corresponding information is stored in the corresponding storage area (a function for executing an SBC command in the main MPU 72 in the fourth embodiment, and a function for executing an ADC command in the main MPU 72 in the fifth embodiment);
A gaming machine comprising:

According to feature P1, when a predetermined calculation process is performed on the numerical information to be calculated, if the numerical information to be calculated exceeds a predetermined limit value, limit-exceeding information is stored in the corresponding memory area, and when limit-exceeding information is stored in the corresponding memory area, the numerical information to be calculated is set to the predetermined limit value. This makes it possible to hold the numerical information to be calculated at a predetermined limit value when the numerical information to be calculated reaches a predetermined limit value as a result of performing a predetermined calculation process on the numerical information to be calculated. Therefore, it becomes possible to identify that the numerical information to be calculated has reached the predetermined limit value by referring to the numerical information to be calculated, and it becomes possible to suitably perform processing to identify that the numerical information to be calculated has reached the predetermined limit value.

Feature P2: A means for performing subtraction processing on the lower byte of numerical information (numerical information of the wait counter 126) having an upper byte (upper byte TK1) and a lower byte (lower byte TK2) (a function for performing the processing of step S3805 of the main MPU 72 in the fourth embodiment);
When the lower byte exceeds a minimum value as a result of the subtraction process being performed on the lower byte, the limit exceeding corresponding information is stored in the corresponding storage area,
When a predetermined command (SBC command) is executed by specifying the upper byte, if the limit exceeding corresponding information is stored in the corresponding storage area as a result of the subtraction process being executed on the lower byte, a process of subtracting 1 from the numerical information of the upper byte is executed;
The predetermined calculation means executes an addition process (step S3901 in the fourth embodiment) on the calculation target numerical information as the predetermined calculation process,
The limit value setting means specifies the numerical information to be calculated and executes the specified command, so that when the addition process is executed on the numerical information to be calculated, causing the numerical information to exceed a maximum value and be inverted, and the limit-exceeding corresponding information is stored in the corresponding memory area, the numerical information to be calculated is decremented by 1 and the numerical information to be calculated is set to its maximum value.

According to feature P2, by using a specified instruction for carrying down digits to the upper byte, it is possible to perform an addition process on the numerical information to be calculated, and when the numerical information to be calculated reaches a maximum value, the numerical information to be calculated can be held at the maximum value. In addition, by using a single specified instruction, it is possible to hold the numerical information to be calculated at the maximum value when the numerical information to be calculated reaches the maximum value, making it possible to reduce the program capacity.

Feature P3: A means for performing an addition process on the lower byte of the numerical information (numerical information of the wait counter 126) having an upper byte (upper byte TK1) and a lower byte (lower byte TK2) (a function for performing the process of step S4005 of the main MPU 72 in the fifth embodiment);
When the lower byte exceeds a maximum value as a result of the addition process being performed on the lower byte, the limit exceeding corresponding information is stored in the corresponding storage area,
When a specific command (ADC command) is executed by specifying the upper byte, when the limit exceeding corresponding information is stored in the corresponding storage area as a result of the addition process being executed on the lower byte, a process of adding 1 to the numerical information of the upper byte is executed,
The predetermined calculation means executes a subtraction process (step S4101 in the fifth embodiment) on the calculation target numerical information as the predetermined calculation process,
The limit value setting means specifies the numerical information to be calculated and executes the specific command, so that when the subtraction process is executed on the numerical information to be calculated, causing the numerical information to exceed a minimum value and invert, resulting in the limit-exceeding corresponding information being stored in the corresponding memory area, the numerical information to be calculated is incremented by 1 and the numerical information to be calculated is set to the minimum value.

According to feature P3, by using a specific instruction for carrying digits to the upper byte, it is possible to perform a subtraction process on the numerical information to be calculated, and when the numerical information to be calculated reaches a minimum value, the numerical information to be calculated is held at the minimum value. In addition, by using a single instruction, the specific instruction, it is possible to hold the numerical information to be calculated at the minimum value when the numerical information to be calculated reaches the minimum value, and therefore it is possible to reduce the program capacity.

Note that any one or more of the features A1 to A8, features B1 to B8, features C1 to C7, features D1 to D6, features E1 to E7, features F1 to F6, features G1 to G6, features H1 to H10, features I1 to I5, features J1 to J6, features K1 to K5, features L1 to L8, features M1 to M11, features N1 to N6, features O1 to O4, and features P1 to P3 may be applied to the features P1 to P3. This makes it possible to achieve a synergistic effect by combining the features.

The invention relating to each of the features in the above group of features O and group of features P can solve the following problems.

Pachinko machines and slot machines are known as gaming machines. For example, pachinko machines are equipped with a storage section for storing gaming balls, and the gaming balls stored in the storage section are guided to a gaming ball launching device and launched toward the gaming area in response to the player's launching operation. Then, for example, when a gaming ball enters a ball entry section provided in the gaming area, a lottery process is executed, or a process is executed to increase the number of gaming balls available to the player.

In a slot machine, when a game value such as medals has been bet and the start lever is operated to start a new game, a lottery process is executed by the control means. Also, when the lottery process is executed, the control means executes rotation start control to start the rotation of the reels, and when the stop button is operated while the reels are rotating, the control means executes rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player.

Here, in gaming machines such as those exemplified above, the processing in the control means needs to be executed appropriately, and there is still room for improvement in this regard.

The basic configuration of a gaming machine to which the above features can be applied is shown below.

Pachinko game machine: A game machine that has an operating means operated by the player, a game ball launching means that launches game balls based on the operation of the operating means, a ball passage that guides the launched game balls to a specified game area, and various game components arranged within the game area, and that awards a special prize to the player when the game ball passes through a specified passage section of each of the game components.

Slot machines and other reel-type gaming machines: A gaming machine that starts the rotation of a rotating body based on the operation of a start operation means, stops the rotation of the rotating body based on the operation of a stop operation means, and awards a bonus to the player based on the image that appears after the rotation has stopped.

10...slot machine, 12...front door, 16...door open sensor, 32L, 32M, 32R...reels, 54b...power failure monitoring circuit, 56...reset button, 57...setting key insertion hole, 64...bet display section, 66...combined display section, 72...main MPU, 74...main RAM, 74a...bet number setting counter, 74e...door status area, 74f...bet number history counter, 74g...information abnormality flag, 74h...reset current status memory area, 74i...reset previous status memory area, 74j...judgment value counter, 76...second random number circuit, 92...performance side M PU, 101a-101q...data group for IV=1-17, 102a...game status data, 111...latch area, 112...game number mode lottery table, 113...win rate mode lottery table, 121...jump status flag, 122...CLR execution circuit, 122b...NOR circuit, 123...DEC execution circuit, 123c...OR circuit, 125...stack area, 125a...unit memory area, 126...wait counter, CF...carry flag, KK...monitoring period counter, TK1...upper byte, TK2...lower byte.

Claims (1)

A sequential change means for sequentially changing a selection object to be selected from among a plurality of types of selection objects;
a numerical information acquiring means for acquiring numerical information for selection corresponding to the selection object that is the object of the lottery;
a winning determination means for determining whether or not the selection target that is the subject of the lottery will be a winning item by utilizing the lottery numerical information acquired by the numerical information acquisition means;
Equipped with
The determination of whether or not a win has been made by the winning determination means is performed in each of a plurality of game states,
In a predetermined game status among the plurality of game statuses, the selection target of a predetermined type does not become the winning target,
The predetermined type of selection object is selected as the selection object by the sequential change means even in the predetermined game state,
a correspondence information group is set corresponding to each of the plurality of types of selection objects,
the numerical information acquiring means acquires the numerical information for selection by comparing information corresponding to a current game status with the corresponding information group corresponding to the selection object to be selected;
A gaming machine characterized in that the corresponding information group includes information for identifying the selected object that has become a winner in subsequent processing when the selected object corresponding to the corresponding information group is determined to be a winner by the win determination means.

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