JP2024076062A - Light-receiving element and light detection device - Google Patents

Abstract

To provide a light-receiving element with improved homogeneity in sensitivity between pixels, and a light detection device.SOLUTION: A light-receiving element 100 includes a substrate 10 having a first main surface 10a, an n-type contact layer 21 on the first main surface, a light-receiving layer 31 thereon, a pixel separation adjustment layer 33 thereon, a p-type contact layer 22 thereon, a plurality of first grooves 71 separating the p-type contact layer and the pixel separation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface, a second groove 72 reaching the n-type contact layer and formed in the p-type contact layer, the pixel separation adjustment layer, and the light-receiving layer outside the first grooves in the first direction, a third groove 73 formed in the p-type contact layer and the light-receiving layer between the first grooves and the second groove in the first direction, a first n electrode 51 in contact with the n-type contact layer at a bottom of the second groove, and a second n electrode 53 provided on the p-type contact layer. The third groove continues to the first groove that exists on the outermost side in the first direction among the first grooves.SELECTED DRAWING: Figure 2

Description

This disclosure relates to a light receiving element and a light detection device.

As a light receiving element that detects infrared rays, a light receiving element is disclosed in which a groove for separating pixels is formed in a semiconductor layer provided on a light receiving layer.

JP 2021-034644 A

There is a demand for improved uniformity in sensitivity between pixels in light receiving elements.

The present disclosure aims to provide a light receiving element and a light detection device that can improve the uniformity of sensitivity between pixels.

The light receiving element of the present disclosure includes a substrate having a first main surface, a first contact layer of a first conductivity type provided on the first main surface, a light receiving layer provided on the first contact layer, a pixel isolation adjustment layer provided on the light receiving layer, a second contact layer of a second conductivity type provided on the pixel isolation adjustment layer, a plurality of first grooves separating the second contact layer and the pixel isolation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface, a second groove formed in the second contact layer, the pixel isolation adjustment layer, and the light receiving layer outside the plurality of first grooves in the first direction and reaching the first contact layer, a third groove formed in the second contact layer and the light receiving layer between the plurality of first grooves and the second groove in the first direction, a first electrode in contact with the first contact layer at the bottom of the second groove, and a second electrode provided on the second contact layer, and the third groove is connected to the first groove located outermost in the first direction among the plurality of first grooves.

This disclosure makes it possible to improve the uniformity of sensitivity between pixels.

FIG. 1 is a schematic diagram showing a light receiving element according to the first embodiment. FIG. 2 is a cross-sectional view showing the light receiving element according to the first embodiment. FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing the light-receiving element according to the first embodiment. FIG. 4 is a cross-sectional view (part 2) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 5 is a cross-sectional view (part 3) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 6 is a cross-sectional view (part 4) illustrating the method for manufacturing the light-receiving element according to the first embodiment. FIG. 7 is a cross-sectional view (part 5) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 8 is a cross-sectional view (part 6) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 9 is a cross-sectional view (part 7) illustrating the method for manufacturing the light-receiving element according to the first embodiment. FIG. 10 is a cross-sectional view (part 8) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 11 is a cross-sectional view (part 9) showing the method for manufacturing the light-receiving element according to the first embodiment. FIG. 12 is a cross-sectional view showing a light receiving element according to a reference example. FIG. 13 is a cross-sectional view showing a light receiving element according to the second embodiment. FIG. 14 is a cross-sectional view (part 1) showing a method for manufacturing a light-receiving element according to the second embodiment. FIG. 15 is a cross-sectional view (part 2) showing the method for manufacturing the light-receiving element according to the second embodiment. FIG. 16 is a cross-sectional view (part 3) showing the method for manufacturing the light-receiving element according to the second embodiment. FIG. 17 is a cross-sectional view (part 4) showing the method for manufacturing the light-receiving element according to the second embodiment. FIG. 18 is a cross-sectional view showing a light detection device according to the third embodiment.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be listed and described.

[1] A light receiving element according to one aspect of the present disclosure includes a substrate having a first main surface, a first contact layer of a first conductivity type provided on the first main surface, a light receiving layer provided on the first contact layer, a pixel isolation adjustment layer provided on the light receiving layer, a second contact layer of a second conductivity type provided on the pixel isolation adjustment layer, a plurality of first grooves separating the second contact layer and the pixel isolation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface, a second groove formed in the second contact layer, the pixel isolation adjustment layer, and the light receiving layer outside the plurality of first grooves in the first direction and reaching the first contact layer, a third groove formed in the second contact layer and the light receiving layer between the plurality of first grooves and the second groove in the first direction, a first electrode in contact with the first contact layer at the bottom of the second groove, and a second electrode provided on the second contact layer, and the third groove is connected to the first groove located outermost in the first direction among the plurality of first grooves.

When light is incident on the light receiving layer, holes and electrons are generated in the light receiving layer, and in each pixel, the holes and electrons flow toward the first contact layer or the second contact layer separately depending on the potential difference between the first contact layer and the second contact layer. At this time, holes and electrons may also be generated in the portion outside the third groove, i.e., outside the pixel, but because the third groove is formed, the holes and electrons are less likely to flow toward the second contact layer. Each pixel is less susceptible to the effects of holes and electrons generated in the light receiving layer outside the third groove, which reduces the variation in sensitivity between pixels and improves the uniformity of sensitivity between pixels.

[2] In [1], the pixel separation adjustment layer of the pixel located outermost in the first direction among the plurality of pixels may have, in a plan view perpendicular to the first main surface, a first region between two of the plurality of first grooves and a second region between the first region and the third groove, and the dimension of the second region in the first direction may be 2.5 μm or more and 3.5 μm or less. In this case, it is easy to achieve both suppression of dark current in the outermost pixel and improvement of uniformity of sensitivity between pixels.

[3] In [2], the dimension of the second region in the first direction may be 2.7 μm or more and 3.5 μm or less. In this case, it is particularly easy to achieve both suppression of dark current in the outermost pixels and improvement of uniformity of sensitivity between pixels.

[4] In any of [1] to [3], the first contact layer may be exposed at the bottom surface of the third groove. In this case, it is particularly easy to improve the uniformity of sensitivity between pixels.

[5] In any of [1] to [4], the pixel separation adjustment layer may have a first semiconductor layer of the first conductivity type provided on the light receiving layer, and a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, and the first semiconductor layer may be exposed at the bottom surface of the first groove. In this case, pixel separation can be easily and reliably performed.

[6] A light receiving element according to another aspect of the present disclosure includes a substrate having a first main surface, a first contact layer of a first conductivity type provided on the first main surface, a light receiving layer provided on the first contact layer, a pixel isolation adjustment layer provided on the light receiving layer, a second contact layer of a second conductivity type provided on the pixel isolation adjustment layer, a plurality of first grooves separating the second contact layer and the pixel isolation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface, a second groove formed in the second contact layer, the pixel isolation adjustment layer, and the light receiving layer outside the plurality of first grooves in the first direction and reaching the first contact layer, a first electrode in contact with the first contact layer at the bottom of the second groove, and a second electrode provided on the second contact layer, and the second groove is connected to the first groove located outermost in the first direction among the plurality of first grooves.

As in [1], when light is incident on the light receiving layer, holes and electrons are generated in the light receiving layer, and in each pixel, the holes and electrons flow toward the first contact layer or the second contact layer separately depending on the potential difference between the first contact layer and the second contact layer. At this time, holes and electrons may also be generated in the portion outside the second groove, i.e., outside the pixel, but because the second groove is formed, the holes and electrons are less likely to flow toward the second contact layer. Each pixel is less susceptible to the effects of holes and electrons generated in the light receiving layer outside the second groove, which reduces the variation in sensitivity between pixels and improves the uniformity of sensitivity between pixels.

[7] In [6], the pixel separation adjustment layer of the pixel located outermost in the first direction among the plurality of pixels may have, in a plan view perpendicular to the first main surface, a first region between two of the plurality of first grooves and a second region between the first region and the second groove, and the dimension of the second region in the first direction may be 2.5 μm or more and 3.5 μm or less. In this case, it is easy to achieve both suppression of dark current in the outermost pixel and improvement of uniformity of sensitivity between pixels.

[8] In [7], the dimension of the second region in the first direction may be 2.7 μm or more and 3.5 μm or less. In this case, it is particularly easy to achieve both suppression of dark current in the outermost pixels and improvement of uniformity of sensitivity between pixels.

[9] In any of [6] to [8], the pixel separation adjustment layer may have a first semiconductor layer of the first conductivity type provided on the light receiving layer, and a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, and the first semiconductor layer may be exposed at the bottom surface of the first groove. In this case, pixel separation can be easily and reliably performed.

[10] A photodetector according to yet another aspect of the present disclosure has a photodetector according to any one of [1] to [9] and a circuit board connected to the photodetector. By having the photodetector have the above-mentioned photodetector, it is possible to improve the uniformity of sensitivity between pixels.

[Details of the embodiment of the present disclosure]
Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant description. In addition, in the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the attitude of the light receiving element or the light detection device. In addition, when viewed from an arbitrary point, the +Z side may be referred to as the upper side, the upper side, or the top, and the -Z side may be referred to as the lower side, the lower side, or the bottom.

First Embodiment
A first embodiment will be described. The first embodiment relates to a light receiving element. FIG. 1 is a schematic diagram showing a light receiving element according to the first embodiment. FIG. 2 is a cross-sectional view showing a light receiving element according to the first embodiment. FIG. 1 shows the arrangement of mesas, bumps, and grooves in a plan view. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

The light receiving element 100 according to the first embodiment has a plurality of pixels 1 that form a two-dimensional array. For example, 256 x 320 pixels are formed with a pitch of 30 μm. The pixel pitch may be, for example, 50 μm or 90 μm. For example, 512 x 640 pixels or 32 x 128 pixels may be formed in the light receiving element 100.

1, the light receiving element 100 has a substrate 10, an n-type contact layer 21, a light receiving layer 31, an intermediate layer 32, a pixel separation adjustment layer 33, and a p-type contact layer 22. The light receiving element 100 further has a passivation film 41, an anti-reflection film 36, a p-electrode 52, a first n-electrode 51, a second n-electrode 53, wiring 54, an indium (In) bump 61, and an In bump 62.

The substrate 10 is, for example, an n-type indium phosphide (InP) substrate. The substrate 10 contains, for example, sulfur (S) at a concentration of about 5×10 ¹⁸ cm ⁻³ . The substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. The thickness of the substrate 10 is, for example, about 300 μm.

The n-type contact layer 21 is provided on the first major surface 10a. The n-type contact layer 21 is, for example, an n-type InP layer. The thickness of the n-type contact layer 21 is, for example, about 2.0 μm. The n-type contact layer 21 contains, for example, silicon (Si) at a concentration of 1×10 ¹⁸ cm ⁻³ or more. The n-type contact layer 21 is an example of a first contact layer.

The absorption layer 31 is provided on the n-type contact layer 21. The absorption layer 31 is, for example, an indium gallium arsenide (InGaAs) layer. The absorption layer 31 has a thickness of, for example, about 4.0 μm. The absorption layer 31 is not doped with an impurity element, and the concentration of the impurity element contained in the absorption layer 31 is 1×10 ¹⁵ cm ⁻³ or less.

The intermediate layer 32 is provided on the light receiving layer 31. The intermediate layer 32 includes, for example, an indium gallium arsenide phosphide (InGaAsP) layer. The thickness of the intermediate layer 32 is, for example, about 0.05 μm. The intermediate layer 32 is not doped with an impurity element, and the concentration of the impurity element contained in the intermediate layer 32 is 2×10 ¹⁵ cm ⁻³ or less. The band gap of the intermediate layer 32 is wider than the band gap of the light receiving layer 31 and narrower than the band gap of the pixel separation adjustment layer 33. The intermediate layer 32 may include a plurality of InGaAsP layers having different compositions. In this case, among the plurality of InGaAsP layers, the closer the InGaAsP layer is to the intermediate layer 32, the narrower the band gap is. That is, among the plurality of InGaAsP layers, the band gap becomes wider stepwise as it moves away from the intermediate layer 32.

The pixel isolation adjustment layer 33 is provided on the intermediate layer 32. The pixel isolation adjustment layer 33 has an n-type wide gap layer 34 and a p-type wide gap layer 35. The n-type wide gap layer 34 is provided on the intermediate layer 32, and the p-type wide gap layer 35 is provided on the n-type wide gap layer 34. The n-type wide gap layer 34 is, for example, an n-type InP layer. The thickness of the n-type wide gap layer 34 is, for example, about 0.5 μm. The n-type wide gap layer 34 contains, for example, Si at a concentration of 2×10 ¹⁵ cm ⁻³ or less. The p-type wide gap layer 35 is, for example, a p-type InP layer. The thickness of the p-type wide gap layer 35 is, for example, about 0.3 μm. The p-type wide gap layer 35 contains, for example, zinc (Zn) at a concentration of 1×10 ¹⁸ cm ⁻³ or more. A pn junction 39 is provided at the interface between the n-type wide gap layer 34 and the p-type wide gap layer 35. The band gap of the n-type wide gap layer 34 and the band gap of the p-type wide gap layer 35 are wider than the band gap of the intermediate layer 32 and the band gap of the absorption layer 31. The n-type wide gap layer 34 is an example of a first semiconductor layer, and the p-type wide gap layer 35 is an example of a second semiconductor layer.

The p-type contact layer 22 is provided on the p-type wide gap layer 35. The p-type contact layer 22 is, for example, a p-type InGaAs layer. The p-type contact layer 22 contains, for example, Zn at a concentration of 2×10 ¹⁹ cm ⁻³ to 6×10 ¹⁹ cm ⁻³ . The thickness of the p-type contact layer 22 is, for example, about 0.2 μm. The p-type contact layer 22 is an example of a second contact layer.

A plurality of first grooves 71 are formed in the p-type contact layer 22, the p-type wide gap layer 35, and a portion of the n-type wide gap layer 34. The first grooves 71 reach the n-type wide gap layer 34. The n-type wide gap layer 34 is exposed at the bottom surface of the first grooves 71. The first grooves 71 penetrate the pn junctions 39. The first grooves 71 form a mesa 81 for each pixel 1, isolating the pixels. A portion of the first grooves 71 is formed at a constant pitch in the X-axis direction and extends in the Y-axis direction. Another portion of the first grooves 71 is formed at a constant pitch in the Y-axis direction and extends in the X-axis direction. The first grooves 71 separate the p-type contact layer 22 and the pixel isolation adjustment layer 33 into a plurality of pixels 1 in the X-axis direction or the Y-axis direction parallel to the first main surface 10a. For example, the depth of the first grooves 71 is about 0.5 μm, and the width is about 5 μm. The planar shape of the mesa 81 is, for example, a square with a side length of 85 μm.

Outside the multiple first grooves 71 in the X-axis direction or the Y-axis direction, second grooves 72 are formed in the p-type contact layer 22, the p-type wide gap layer 35, the n-type wide gap layer 34, the intermediate layer 32, the light receiving layer 31, and a part of the n-type contact layer 21. The second grooves 72 reach the n-type contact layer 21. The n-type contact layer 21 is exposed at the bottom surface of the second grooves 72. The second grooves 72 are formed in a ring shape in a plan view perpendicular to the first main surface 10a, and surround all the first grooves 71. The pixel region 11 and the electrode connection region 12 are separated from each other by the second grooves 72. The mesa 81 is formed in the pixel region 11. The mesa 82 is formed in the electrode connection region 12. The width of the second grooves 72 is, for example, about 450 μm.

Between the multiple first grooves 71 and the multiple second grooves 72 in the X-axis direction or the Y-axis direction, a third groove 73 is formed in the p-type contact layer 22, the p-type wide gap layer 35, the n-type wide gap layer 34, the intermediate layer 32, and the light-receiving layer 31. The third groove 73 reaches the n-type contact layer 21. The n-type contact layer 21 is exposed at the bottom surface of the third groove 73. The third groove 73 is formed in a ring shape in a plan view perpendicular to the first main surface 10a, and surrounds all the first grooves 71. The third groove 73 connects to the first groove 71 located most outside in the X-axis direction and the first groove 71 located most outside in the Y-axis direction among the multiple first grooves 71. The light-receiving layer 31 of the pixel 1 located at the outermost periphery of the two-dimensional array is exposed to the third groove 73. In other words, the light-receiving layer 31 of the pixel 1 located most outside in the X-axis direction and the light-receiving layer 31 of the pixel 1 located most outside in the Y-axis direction among the multiple pixels 1 are exposed to the third groove 73. The width of the third groove 73 is, for example, 1.5 μm or more and 3.0 μm or more. A mesa 83 is formed between the second groove 72 and the third groove 73. The width of the mesa 83 is, for example, 60 μm.

The passivation film 41 covers the p-type contact layer 22, the p-type wide gap layer 35, the n-type wide gap layer 34, the intermediate layer 32, the light receiving layer 31, the n-type contact layer 21, and the substrate 10. The passivation film 41 is, for example, a silicon nitride (SiN) film. The thickness of the passivation film 41 is, for example, about 0.2 μm. The passivation film 41 has an opening 41a that exposes the p-type contact layer 22 of the mesa 81, and an opening 41b that exposes the n-type contact layer 21 between the pixel region 11 and the electrode connection region 12. The side of the pn junction 39 is in contact with the passivation film 41.

A p-electrode 52 is formed on the p-type contact layer 22 in each mesa 81. The p-electrode 52 contacts the p-type contact layer 22 through the opening 41a. The p-electrode 52 is made of a metal laminate film, for example, in which a titanium (Ti) layer and a platinum (Pt) layer are laminated in this order. For example, the thickness of the Ti layer is about 50 nm, and the thickness of the Pt layer is about 80 nm.

A first n-electrode 51 is formed on the n-type contact layer 21 between the pixel region 11 and the electrode connection region 12. The first n-electrode 51 contacts the n-type contact layer 21 through the opening 41b. A second n-electrode 53 is formed on the passivation film 41 above the mesa 82. The first n-electrode 51 and the second n-electrode 53 are composed of a metal laminate film, for example, in which a Ti layer and a Pt layer are laminated in order. For example, the Ti layer has a thickness of about 50 nm, and the Pt layer has a thickness of about 80 nm.

The wiring 54 connects the first n-electrode 51 and the second n-electrode 53. The wiring 54 is formed on the passivation film 41. The wiring 54 is made of a metal laminate film, for example, in which a Ti layer and a gold (Au) layer are laminated in this order. For example, the thickness of the Ti layer is about 50 nm, and the thickness of the Au layer is about 600 nm.

An In bump 62 is provided on the p-electrode 52. In each pixel 1 in the pixel region 11, a p-electrode 52 having a circular planar shape is formed on the upper surface of the mesa 81, and an In bump 62 having a circular planar shape is formed on the p-electrode 52.

In the electrode connection region 12, an In bump 61 is provided on the second n-electrode 53. The In bump 61 has a circular planar shape and is formed on the second n-electrode 53.

The second n-electrode 53 and the p-electrode 52 are connected to electrodes provided on the readout circuit board 400 (see FIG. 18) via In bumps 61 and 62, respectively. The height of the In bumps 61 and 62 is, for example, about 10 μm.

The anti-reflection film 36 is provided on the second main surface 10b. The anti-reflection film 36 is, for example, a SiN film.

Next, a method for manufacturing the light receiving element 100 according to the first embodiment will be described. Figures 3 to 11 are cross-sectional views showing the method for manufacturing the light receiving element according to the first embodiment.

First, as shown in FIG. 3, the n-type contact layer 21, the light receiving layer 31, the intermediate layer 32, the n-type wide gap layer 34, the p-type wide gap layer 35, and the p-type contact layer 22 are formed in this order by epitaxial growth on the first main surface 10a of the substrate 10. Metal organic vapor phase epitaxy (MOVPE) is used for the epitaxial growth of the above compound semiconductor layers. The thickness of the substrate 10 is, for example, 400 μm or more and 500 μm or less.

Next, as shown in FIG. 4, a SiN film 191 having a thickness of about 0.4 μm is formed on the p-type contact layer 22 by plasma chemical vapor deposition (CVD). Next, a photoresist is applied onto the SiN film 191, and a resist pattern (not shown) is formed by exposing the photoresist to light using an exposure device and developing the photoresist. This resist pattern has openings in the area where the first groove 71 is to be formed, the area where the second groove 72 is to be formed, and the area where the third groove 73 is to be formed. The SiN film 191 in the openings of the resist pattern is removed by wet etching using buffered hydrofluoric acid, thereby forming a mask from the SiN film 191. The resist pattern is then removed by an organic solvent or the like.

Next, as shown in FIG. 5, the p-type contact layer 22, the p-type wide gap layer 35, and a part of the n-type wide gap layer 34 exposed in the opening of the SiN film 191 are removed by dry etching such as reactive ion etching (RIE). In this RIE, for example, a mixed gas of silicon tetrachloride (SiCl ₄ ) gas and argon (Ar) gas is used. In this manner, the first groove 71 for separating pixels is formed. Also, a provisional groove 72X is formed in the region where the second groove 72 is to be formed, and a provisional groove 73X is formed in the region where the third groove 73 is to be formed. With the formation of the first groove 71, a mesa 81 is formed, and each pixel 1 (see FIG. 1) is separated.

Next, the deposits (not shown) generated by the dry etching are removed. The deposits can be removed using buffered hydrofluoric acid. Furthermore, damage may occur in the vicinity of the first groove 71 of the p-type contact layer 22, the p-type wide gap layer 35, and the n-type wide gap layer 34 during dry etching. For this reason, after removing the deposits, wet etching is performed to remove the portions that were damaged during dry etching. For example, the portions of the p-type contact layer 22, the p-type wide gap layer 35, and the n-type wide gap layer 34 exposed in the first groove 71 are removed to a thickness of 0.1 μm. Then, the SiN film 191 is removed using buffered hydrofluoric acid.

6, a SiN film 192 having a thickness of about 0.8 μm is formed by plasma CVD to cover the p-type contact layer 22, the p-type wide gap layer 35, and the n-type wide gap layer 34. Next, a photoresist is applied onto the SiN film 192, and a resist pattern (not shown) is formed by exposing the photoresist to light using an exposure device and developing the photoresist. This resist pattern has openings in the area where the second groove 72 is to be formed and the area where the third groove 73 is to be formed. The SiN film 192 in the openings of the resist pattern is removed by wet etching using buffered hydrofluoric acid to form a mask from the SiN film 192. The resist pattern is then removed by an organic solvent or the like.

Next, as shown in FIG. 7, the n-type wide gap layer 34, the intermediate layer 32, the absorption layer 31, and a part of the n-type contact layer 21 exposed in the opening of the SiN film 192 are removed by dry etching such as RIE. In this RIE, for example, a mixed gas of SiCl ₄ gas and Ar gas is used. In this manner, the second groove 72 and the third groove 73 are formed, and the mesa 82 is formed on the outside of the second groove 72 as viewed from the mesa 81. In addition, the mesa 83 is formed between the first groove 71 and the second groove 72. Note that since the width of the third groove 73 is narrower than the width of the second groove 72, the etching rate differs between the second groove 72 and the third groove 73 due to the microloading effect, but both the second groove 72 and the third groove 73 can be formed to reach the n-type contact layer 21.

Next, the deposits (not shown) generated by the dry etching are removed. The deposits can be removed using buffered hydrofluoric acid. Furthermore, damage may occur during dry etching in the vicinity of the second groove 72 or the third groove 73 of the n-type wide gap layer 34, the intermediate layer 32, the light receiving layer 31, and the n-type contact layer 21. For this reason, after removing the deposits, wet etching is performed to remove the portions that were damaged during dry etching. For example, the portions exposed in the second groove 72 or the third groove 73 of each of the n-type wide gap layer 34, the intermediate layer 32, the light receiving layer 31, and the n-type contact layer 21 are removed to a thickness of 0.1 μm. Then, the SiN film 192 is removed using buffered hydrofluoric acid.

Next, as shown in FIG. 8, a passivation film 41 is formed. Specifically, a SiN film (not shown) is formed on the entire surface by plasma CVD, a photoresist is applied on the formed SiN film, and a resist pattern (not shown) is formed by exposing and developing the photoresist using an exposure device. This resist pattern has openings in the region where the p-electrode 52 is formed and the region where the first n-electrode 51 is formed, and the SiN film in the openings of the resist pattern is removed by dry etching such as RIE. As a result, a passivation film 41 is formed that has an opening 41a that exposes the surface of the p-type contact layer 22 of the mesa 81 and an opening 41b that exposes the surface of the n-type contact layer 21.

9, a p-electrode 52 is formed on the p-type contact layer 22, a first n-electrode 51 is formed on the n-type contact layer 21, and a second n-electrode 53 is formed on the mesa 82 via a passivation film 41. The p-electrode 52, the first n-electrode 51, and the second n-electrode 53 are formed by a lift-off method. Specifically, a resist pattern (not shown) having openings in the region where the p-electrode 52 is formed, the region where the first n-electrode 51 is formed, and the region where the second n-electrode 53 is formed is formed, and a metal laminate film in which a Ti layer and a Pt layer are laminated in order is formed by electron beam (EB) deposition, and then immersed in an organic solvent or the like. As a result, the metal laminate film on the resist pattern is removed together with the resist pattern, and the p-electrode 52, the first n-electrode 51, and the second n-electrode 53 are formed from the remaining metal laminate film.

Furthermore, the wiring 54 connecting the first n-electrode 51 and the second n-electrode 53 is formed by lift-off. Specifically, a resist pattern (not shown) having an opening in the area where the wiring 54 is to be formed is formed, and a metal laminate film in which a Ti layer and an Au layer are laminated in order is formed by EB deposition, and then immersed in an organic solvent or the like. As a result, the metal laminate film on the resist pattern is removed together with the resist pattern, and the wiring 54 is formed from the remaining metal laminate film. The EB deposition for forming the wiring 54 is, for example, oblique deposition from a direction inclined from a direction perpendicular to the first main surface 10a.

Next, as shown in FIG. 10, the second main surface 10b of the substrate 10 is polished to a mirror surface. Next, an anti-reflection film 36 is formed on the second main surface 10b. The anti-reflection film 36 is formed by plasma CVD.

Next, as shown in FIG. 11, an In bump 61 is formed on the second n-electrode 53, and an In bump 62 is formed on the p-electrode 52. The In bumps 61 and 62 are formed by the lift-off method. After this, the substrate is divided into chips.

In this manner, the light receiving element 100 according to the first embodiment can be manufactured.

The light receiving element 100 is used with a reverse bias voltage of, for example, -8 V applied between the p-electrode 52 and the second n-electrode 53. When near-infrared light is incident on the light receiving layer 31 from the second major surface 10b of the substrate 10 with a reverse bias voltage applied, holes and electrons are generated in the light receiving layer 31, the electrons flow toward the n-type contact layer 21, and the holes flow toward the p-type contact layer 22.

Holes and electrons are generated not only in the light-receiving layer 31 below the mesa 81 in the pixel region 11, but also in the light-receiving layer 31 below the mesa 83. However, in this embodiment, the light-receiving layer 31 below the mesa 83 is separated from the light-receiving layer 31 below the mesa 81 by the third groove 73. Therefore, even if holes and electrons are generated in the light-receiving layer 31 below the mesa 83, the holes do not flow toward the p-type contact layer 22 in the pixel region 11, and the holes and electrons recombine and disappear in the light-receiving layer 31. Therefore, each pixel 1 in the pixel region 11 is not affected by the holes and electrons generated in the light-receiving layer 31 below the mesa 83. Therefore, when light of the same intensity is incident, the same amount of photocurrent flows in each pixel 1. In other words, the variation in sensitivity between pixels 1 is suppressed.

Here, a reference example will be described for comparison with the first embodiment. FIG. 12 is a cross-sectional view showing a light receiving element according to the reference example. FIG. 12 corresponds to the cross-sectional view taken along line II-II in FIG. 1.

In the light receiving element 100X according to the reference example, the third groove 73 is not formed. Therefore, in the light receiving element 100X, when holes and electrons are generated in the light receiving layer 31 below the mesa 83, the holes can flow toward the nearest pixel 1, i.e., the p-type contact layer 22 of the pixel 1 located at the outermost periphery of the two-dimensional array. For this reason, when light of the same intensity is incident, a larger photocurrent flows in the pixel 1 located at the outermost periphery than in the other pixels 1. In other words, the sensitivity of the pixel 1 located at the outermost periphery is higher than the sensitivity of the other pixels 1.

In this way, the light receiving element 100 can suppress the variation in sensitivity and improve the uniformity of the sensitivity.

Mesa 83 functions as a dummy mesa for mesa 81 and helps ensure uniformity of exposure and etching when forming first groove 71.

By exposing the n-type wide gap layer 34 at the bottom surface of the first groove 71, pixel separation can be easily and reliably achieved.

The pixel isolation adjustment layer 33 of the pixel 1 located at the outermost periphery, i.e., the pixel 1 closest to the third groove 73, has a first region 33a between the two first grooves 71 and a second region 33b between the first region 33a and the third groove 73 in a plan view perpendicular to the first main surface 10a. The dimensions of the second region 33b in the X-axis direction and the Y-axis direction are preferably 2.5 μm or more and 3.5 μm or less. If the dimensions of the second region 33b in the X-axis direction and the Y-axis direction are less than 2.5 μm, dark current may easily flow through the side surface of the pixel 1. If the dimensions of the second region 33b in the X-axis direction and the Y-axis direction are more than 3.5 μm, the sensitivity of the pixel 1 may be higher than the sensitivity of other pixels 1. The dimensions of the second region 33b are more preferably 2.7 μm or more and 3.5 μm or less.

The third groove 73 only needs to separate at least a portion of the light-receiving layer 31 in the thickness direction, and does not need to reach the n-type contact layer 21. In other words, the light-receiving layer 31 may be exposed at the bottom surface of the third groove 73. If the third groove 73 separates at least a portion of the light-receiving layer 31 in the thickness direction, the flow from the light-receiving layer 31 below the mesa 83 to the p-type contact layer 22 in the pixel region 11 can be suppressed, and the variation in sensitivity between pixels 1 can be suppressed. However, if the n-type contact layer 21 is exposed at the bottom surface of the third groove 73, it is particularly easy to improve the uniformity of sensitivity between pixels 1.

Second Embodiment
A second embodiment will be described. The first embodiment differs from the first embodiment mainly in that the mesa 83 is not included. Fig. 13 is a cross-sectional view showing a light receiving element according to the second embodiment. Fig. 13 corresponds to a cross-sectional view taken along line II-II in Fig. 1.

In the light receiving element 200 according to the second embodiment, a plurality of first grooves 71 are formed in the p-type contact layer 22, the p-type wide gap layer 35, and a portion of the n-type wide gap layer 34. In addition, outside the plurality of first grooves 71 in the X-axis direction or the Y-axis direction, a second groove 72 is formed in the p-type contact layer 22, the p-type wide gap layer 35, the n-type wide gap layer 34, the intermediate layer 32, the light receiving layer 31, and a portion of the n-type contact layer 21. However, the third groove 73 is not formed in the light receiving element 200. The second groove 72 connects to the first groove 71 located at the outermost position in the X-axis direction and the first groove 71 located at the outermost position in the Y-axis direction among the plurality of first grooves 71. The light receiving layer 31 of the pixel 1 located at the outermost position in the two-dimensional array is exposed to the second groove 72. In other words, the light receiving layer 31 of the pixel 1 located at the outermost position in the X-axis direction and the light receiving layer 31 of the pixel 1 located at the outermost position in the Y-axis direction among the plurality of pixels 1 are exposed to the second groove 72. The width of the second groove 72 is, for example, approximately 450 μm.

The other configurations of the second embodiment are the same as those of the first embodiment.

Next, a method for manufacturing the light receiving element 100 according to the first embodiment will be described. Figures 14 to 17 are cross-sectional views showing a method for manufacturing the light receiving element according to the second embodiment.

First, as in the first embodiment, the n-type contact layer 21, the absorption layer 31, the intermediate layer 32, the n-type wide gap layer 34, the p-type wide gap layer 35, and the p-type contact layer 22 are formed in this order by epitaxial growth on the first main surface 10a of the substrate 10 (see FIG. 3).

Next, as shown in FIG. 14, a SiN film 291 with a thickness of about 0.4 μm is formed on the p-type contact layer 22 by plasma CVD. Next, a photoresist is applied onto the SiN film 291, and a resist pattern (not shown) is formed by exposing and developing the photoresist with an exposure device. This resist pattern has openings in the area where the first groove 71 is to be formed and the area where the second groove 72 is to be formed. The SiN film 291 in the openings of the resist pattern is removed by wet etching using buffered hydrofluoric acid, thereby forming a mask from the SiN film 291. The resist pattern is then removed with an organic solvent or the like.

Next, as shown in FIG. 15, the p-type contact layer 22, the p-type wide gap layer 35, and a part of the n-type wide gap layer 34 exposed in the opening of the SiN film 291 are removed by dry etching such as RIE. In this manner, the first groove 71 for isolating the pixels is formed. Also, a provisional groove 72X is formed in the region where the second groove 72 is to be formed. With the formation of the first groove 71, a mesa 81 is formed, and each pixel 1 (see FIG. 1) is separated.

Next, deposits (not shown) generated by the dry etching are removed. Next, wet etching is performed to remove any areas that were damaged during the dry etching. Next, the SiN film 291 is removed using buffered hydrofluoric acid.

16, a SiN film 292 having a thickness of about 0.8 μm is formed by plasma CVD to cover the p-type contact layer 22, the p-type wide gap layer 35, and the n-type wide gap layer 34. Next, a photoresist is applied onto the SiN film 292, and a resist pattern (not shown) is formed by exposing the photoresist to light using an exposure device and developing the photoresist. This resist pattern has openings in the areas where the second grooves 72 are to be formed. The SiN film 292 in the openings of the resist pattern is removed by wet etching using buffered hydrofluoric acid, forming a mask from the SiN film 292. The resist pattern is then removed by an organic solvent or the like.

17, the n-type wide gap layer 34, the intermediate layer 32, the absorption layer 31, and a part of the n-type contact layer 21 exposed in the opening of the SiN film 292 are removed by dry etching such as RIE. In this manner, the second groove 72 is formed, and the mesa 82 is formed outside the second groove 72 when viewed from the mesa 81.

Next, similar to the first embodiment, the processes following removal of the deposits (not shown) generated by dry etching are performed.

In this manner, the light receiving element 200 according to the second embodiment can be manufactured.

The light receiving element 200 can also suppress variation in sensitivity and improve uniformity of sensitivity.

In the pixel 1 located at the outermost periphery, as in the first embodiment, the dimension in the X-axis direction and the dimension in the Y-axis direction of the second region 33b are preferably 2.5 μm or more and 3.5 μm or less, and more preferably 2.7 μm or more and 3.5 μm or less.

Third Embodiment
Next, a third embodiment will be described. The third embodiment relates to a photodetector including the light receiving element 100 according to the first embodiment. Fig. 18 is a cross-sectional view showing the photodetector according to the third embodiment.

The photodetector 300 according to the third embodiment has a light receiving element 100 and a read out integrated circuit (ROIC) 400. The read out circuit 400 has a wiring board 410, a pixel electrode 452, and a common electrode 451. The pixel electrode 452 and the common electrode 451 are arranged on one side of the wiring board 410. The read out circuit 400 includes a circuit, such as a multiplexer, that reads out a signal output from the light receiving element 100. The read out circuit 400 is an example of a circuit board.

The photodetector 300 further includes a connection member 352 that connects the p-electrode 52 and the pixel electrode 452, and a connection member 351 that connects the second n-electrode 53 and the common electrode 451. The connection member 351 includes an In bump 61 and an In bump that was provided on the common electrode 451 of the readout circuit board 400 before bonding. The connection member 352 includes an In bump 62 and an In bump that was provided on the pixel electrode 452 of the readout circuit board 400 before bonding.

According to the third embodiment, it is possible to improve the uniformity of sensitivity between pixels.

In addition, light receiving element 200 may be used instead of light receiving element 100.

Although the embodiments have been described in detail above, the invention is not limited to specific embodiments, and various modifications and variations are possible within the scope of the claims.

1: pixel 10: substrate 10a: first main surface 10b: second main surface 11: pixel region 12: electrode connection region 21: n-type contact layer 22: p-type contact layer 31: light receiving layer 32: intermediate layer 33: pixel separation adjustment layer 33a: first region 33b: second region 34: n-type wide gap layer 35: p-type wide gap layer 36: anti-reflection film 39: pn junction 41: passivation films 41a, 41b: opening 51: First n-electrode 52: p-electrode 53: second n-electrode 54: wiring 61, 62: In bump 71: first groove 72: second groove 72X, 73X: temporary groove 73: third groove 81, 82, 83: mesas 100, 100X, 200: light receiving elements 191, 192, 291, 292: SiN film 300: light detecting devices 351, 352: connection member 400: readout circuit board 410: wiring board 451: common electrode 452: pixel electrode

Claims (10)

a substrate having a first major surface;
a first contact layer of a first conductivity type provided on the first major surface;
an absorption layer provided on the first contact layer;
a pixel separation adjustment layer provided on the light receiving layer;
a second contact layer of a second conductivity type provided on the pixel isolation adjustment layer;
a plurality of first grooves that separate the second contact layer and the pixel isolation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface;
a second groove formed in the second contact layer, the pixel isolation adjustment layer, and the light receiving layer outside the plurality of first grooves in the first direction and reaching the first contact layer;
a third groove formed in the second contact layer and the absorption layer between the plurality of first grooves and the second groove in the first direction;
a first electrode in contact with the first contact layer at a bottom of the second groove;
a second electrode provided on the second contact layer;
having
The third groove is connected to a first groove that is located outermost in the first direction among the plurality of first grooves. The pixel isolation adjustment layer of the pixel located outermost in the first direction among the plurality of pixels, in a plan view perpendicular to the first main surface,
a first region between two first grooves of the plurality of first grooves;
a second region between the first region and the third groove;
having
The light-receiving element according to claim 1 , wherein the dimension of the second region in the first direction is not less than 2.5 μm and not more than 3.5 μm. The light receiving element according to claim 2, wherein the dimension of the second region in the first direction is 2.7 μm or more and 3.5 μm or less. The light receiving element according to any one of claims 1 to 3, wherein the first contact layer is exposed at the bottom surface of the third groove. The pixel separation adjustment layer is
a first semiconductor layer of the first conductivity type provided on the absorption layer;
a second semiconductor layer of the second conductivity type provided on the first semiconductor layer;
having
The light-receiving element according to claim 1 , wherein the first semiconductor layer is exposed at a bottom surface of the first groove. a substrate having a first major surface;
a first contact layer of a first conductivity type provided on the first major surface;
a light receiving layer provided on the first contact layer;
a pixel separation adjustment layer provided on the light receiving layer;
a second contact layer of a second conductivity type provided on the pixel isolation adjustment layer;
a plurality of first grooves that separate the second contact layer and the pixel isolation adjustment layer into a plurality of pixels in a first direction parallel to the first main surface;
a second groove formed in the second contact layer, the pixel isolation adjustment layer, and the light receiving layer outside the plurality of first grooves in the first direction and reaching the first contact layer;
a first electrode in contact with the first contact layer at a bottom of the second groove;
a second electrode provided on the second contact layer;
having
The second groove is connected to a first groove that is located outermost in the first direction among the plurality of first grooves. The pixel isolation adjustment layer of the pixel located outermost in the first direction among the plurality of pixels, in a plan view perpendicular to the first main surface,
a first region between two first grooves of the plurality of first grooves;
a second region between the first region and the second groove;
having
The light-receiving element according to claim 6 , wherein a dimension of the second region in the first direction is not less than 2.5 μm and not more than 3.5 μm. The light receiving element according to claim 7, wherein the dimension of the second region in the first direction is 2.7 μm or more and 3.5 μm or less. The pixel separation adjustment layer is
a first semiconductor layer of the first conductivity type provided on the absorption layer;
a second semiconductor layer of the second conductivity type provided on the first semiconductor layer;
having
The light-receiving element according to claim 6 , wherein the first semiconductor layer is exposed at a bottom surface of the first groove. A light receiving element according to claim 1, claim 2, claim 3, claim 6, claim 7 or claim 8;
A circuit board connected to the light receiving element;
A light detection device comprising:

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