JP2024067906A - Photodetector - Google Patents

Abstract

[Problem] To provide a photodetector capable of counting the number of photons of incident light at high illuminance with a high SNR. [Solution] The photodetector according to the present disclosure includes a first photodiode, a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light, a counter that counts the number of breakdowns of the first photodiode based on the voltage of the sense node, and a count control unit that controls the number of breakdowns by increasing the count value of the counter by 1 according to the count value of the counter. [Selected Figure] Figure 2

Description

This disclosure relates to a light detection device.

There is a technology for photon count sensors that reduces the number of photons counted when the incident light is of high illuminance by providing a pixel rest period (Patent Document 1). With this technology, photons of high illuminance incident light are thinned out and detected, and the actual number of photons is calculated by statistical processing.

JP 2020-123846 A International Application Publication No. 2022-018515 JP 2018-157387 A

However, because the photons of the incident light are thinned out for detection, the number of photons at high illuminance may differ from the actual number of photons, even though the dynamic range is expanded. In this case, the signal-noise ratio (SNR) is degraded.

Therefore, the present disclosure provides a light detection device that can count the number of photons of incident light at high illuminance with a high SNR.

The photodetector according to one aspect of the present disclosure includes a first photodiode, a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light, a counter that counts the number of breakdowns of the first photodiode based on the voltage of the sense node, and a count control unit that controls the number of breakdowns by increasing the count value of the counter by 1 according to the count value of the counter.

The count control unit includes a first capacitor and a switch connected in series between the sense node and a reference voltage source.

The switch is non-conductive when the count value is less than a predetermined value, and is conductive when the count value is equal to or greater than the predetermined value.

When the switch is in a non-conductive state, the counter increments the count value by one each time the first photodiode breaks down, and when the switch is in a conductive state, the counter increments the count value by one each time the first photodiode breaks down n times (n is an integer equal to or greater than 2).

The photodetector device further includes a first transistor provided between a voltage source and a sense node and controlled by breakdown of the photodiode, a second transistor provided between the first transistor and the sense node and controlled by breakdown of the photodiode with a delay relative to the first transistor, and a second capacitor connected between a node between the first transistor and the second transistor and a reference voltage source.

The count control unit controls the value of n based on the ratio between the capacitance of the sense node and the capacitance of the node between the first transistor and the second transistor.

The sensor further includes a pixel region in which a plurality of pixels are arranged, and each of the plurality of pixels includes a first photodiode, a counter, and a count control unit.

The first photodiode is a SPAD (Single Photon Avalanche Diode) that undergoes avalanche breakdown once upon the incidence of one photon.

The count control unit is connected in parallel to the second capacitor.

It further includes a second photodiode disposed between the sense node and a reference voltage source.

During one exposure period of the first photodiode, the cycle for charging the sense node includes a first cycle and a second cycle that is longer than the first cycle.

In one exposure period of the first photodiode, the cycle for charging the sense node includes a first cycle and a second cycle that is longer than the first cycle, and the switch is in a conductive state in the first cycle and in a non-conductive state in the second cycle.

The switch is controlled by a signal from outside the counter and the count control circuit.

A photodetector according to another aspect of the present disclosure includes a first photodiode in which the number of incident photons at the time of breakdown changes depending on a forward bias voltage, a power supply circuit that applies a forward bias voltage to the first photodiode, a sense node in which the voltage changes due to the breakdown of the first photodiode caused by the incidence of light, a counter that counts the breakdown of the first photodiode, and a count control unit that controls the forward bias voltage from the power supply circuit depending on the count value of the counter.

The count control unit sets the forward bias voltage to a first voltage when the count value is less than a predetermined value, and sets the forward bias voltage to a second voltage smaller than the first voltage when the count value is equal to or greater than the predetermined value.

When the forward bias voltage is the first voltage, the first photodiode breaks down every time one photon is incident, and when the forward bias voltage is the second voltage, the first photodiode breaks down every time n photons (n is an integer equal to or greater than 2) are incident.

1 is a block diagram showing a schematic configuration of a photodetector according to a first embodiment. FIG. 2 is a block diagram showing an example of the internal configuration of one pixel. 5 is a timing chart showing an example of the operation of the photodetector according to the first embodiment. 5 is a timing chart showing an example of the operation of the photodetector when a switch is turned on. 11 is a graph showing the relationship between the number of incident photons and the count value. FIG. 13 is a block diagram showing a part of another example of the internal configuration of one pixel. FIG. 11 is a block diagram showing an example of the internal configuration of a pixel according to a second embodiment. FIG. 11 is a timing chart showing an example of the operation of the photodetector according to the second embodiment. 5 is a timing chart showing an example of the operation of the photodetector when a switch is turned on. FIG. 13 is a block diagram showing an example of the internal configuration of a pixel according to a third embodiment. FIG. 11 is a timing chart showing an example of the operation of the photodetector according to the third embodiment. 5 is a timing chart showing an example of the operation of the photodetector when a switch is turned on. FIG. 13 is a block diagram showing an example of the internal configuration of a pixel according to a fourth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fourth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fourth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fourth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fourth embodiment. FIG. 13 is a block diagram showing an example of the internal configuration of a pixel according to the fifth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fifth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the fifth embodiment. FIG. 13 is a conceptual diagram showing a charging period in the fifth embodiment. 11 is a graph showing the relationship between the photon incidence rate and the count value. 1 is a graph showing the relationship between photon incidence rate and SNR. FIG. 13 is a block diagram showing an example of the internal configuration of a pixel according to the sixth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the sixth embodiment. FIG. 13 is a timing chart showing an example of the operation of the photodetector according to the sixth embodiment. FIG. 23 is a block diagram showing an example of the internal configuration of a pixel according to the seventh embodiment. FIG. 23 is a timing chart showing an example of the operation of the photodetector according to the seventh embodiment. FIG. 23 is a timing chart showing an example of the operation of the photodetector according to the seventh embodiment. FIG. 23 is a timing chart showing an example of the operation of the photodetector according to the seventh embodiment. FIG. 23 is a timing chart showing an example of the operation of the photodetector according to the seventh embodiment. FIG. 23 is a block diagram showing an example of the internal configuration of a pixel according to the eighth embodiment. FIG. 23 is a block diagram showing a part of an example of the internal configuration of a pixel according to the ninth embodiment. FIG. 2 is a schematic diagram showing an example of a chip stack configuration of a light detection device. FIG. 2 is a schematic diagram showing an example of a chip stack configuration of a light detection device. FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

Specific embodiments to which the present technology is applied will be described in detail below with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions will be omitted as appropriate.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a photodetection device according to the first embodiment.

The photodetection device 100 according to this embodiment includes a pixel region 10, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output circuit 60, and a control circuit 70.

The pixel region 10 has a plurality of pixels P arranged two-dimensionally in a matrix in the row and column directions. In FIG. 1, 36 pixels P arranged in six rows from row 0 to row 5 and six columns from column 0 to column 5 are shown with reference numbers indicating the row and column numbers. For example, the pixel P arranged in the first row and fourth column is given the reference number P14.

The number of rows and columns of the pixel array constituting the pixel region 10 is not particularly limited. Furthermore, the pixels P do not necessarily need to be arranged two-dimensionally in the pixel region 10. For example, the pixel region 10 may be composed of one pixel P, or the pixels P may be arranged one-dimensionally in the row or column direction in the pixel region 10. Furthermore, the pixels P may be arranged three-dimensionally. The pixel region 10 may be configured as a laminate in which multiple substrates on which pixels P are formed are stacked.

Each row of the pixel array in the pixel region 10 is provided with a control line PVSEL extending in the X direction. The control line PVSEL is connected to each of the multiple pixels P aligned in the X direction, and serves as a signal line common to these pixels P. The X direction in which the control line PVSEL extends may be referred to as the row direction or horizontal direction. Note that in FIG. 1, the control line PVSEL is shown together with a reference symbol indicating the row number. For example, the control line in the first row is given the reference symbol PVSEL[1].

The control line PVSEL of each row is connected to the vertical selection circuit 30. The vertical selection circuit 30 is a circuit section that supplies a control signal for driving a signal generation circuit (not shown) in the pixel P to the pixel P via the control line PVSEL. The vertical selection circuit 30 controls the start and end of the period during which the counter in the pixel P accumulates the count.

Each column of the pixel array in the pixel region 10 is provided with an output line POUT that extends in the Y direction intersecting (e.g., perpendicular to) the X direction. The output line POUT is connected to each of the multiple pixels P aligned in the Y direction, and serves as a signal line common to these pixels P. The Y direction in which the output line POUT extends may be referred to as the column direction or the vertical direction. Note that in FIG. 1, the output line POUT is shown together with a symbol indicating the column number. For example, the output line of the fourth column is labeled POUT4. Each output line POUT has n signal lines for outputting an n-bit digital signal.

The output line POUT is connected to a signal processing circuit 40. The signal processing circuits 40 are provided corresponding to each column of the pixel array in the pixel region 10, and are connected to the output line POUT of the corresponding column. The signal processing circuit 40 has a function of holding a signal output from the pixel P via the output line POUT of the corresponding column. Since the signal output from the pixel P is an n-bit signal input via n signal lines of the output line POUT, each of the signal processing circuits 40 has at least n holding units to hold each bit of the signal.

The horizontal selection circuit 50 is a circuit section that supplies the signal processing circuit 40 with a control signal for reading out a signal from the signal processing circuit 40. The horizontal selection circuit 50 supplies a control signal to the signal processing circuit 40 of each column via a control line PHSEL. The signal processing circuit 40 that receives a control signal from the horizontal selection circuit 50 outputs the signal held in the holding section to the output circuit 60 via the horizontal output line HSIG. Note that in FIG. 1, the control line PHSEL is shown together with a symbol indicating the column number. For example, the control line for the fourth column is marked with the symbol PHSEL[4]. The horizontal output line HSIG has n signal lines for outputting an n-bit digital signal.

The output circuit 60 is a circuit section for outputting the signal supplied via the horizontal output line HSIG as an output signal SOUT to the outside of the photodetection device 100. The control circuit 70 is a circuit section for supplying control signals that control the operation and timing of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60. Note that at least some of the control signals that control the operation and timing of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60 may be supplied from the outside of the photodetection device 100.

Figure 2 is a block diagram showing an example of the internal configuration of one pixel P. Each pixel P includes an avalanche multiplication photodiode PD, a pixel control circuit 12, a count control circuit 14, and a counter circuit 16.

The anode of the photodiode PD is connected to a reference voltage source. The reference voltage source is, for example, a ground or a negative voltage source. The cathode of the photodiode PD is connected to the source of the transistor Trch of the pixel control circuit 12. When the reverse bias voltage applied between the anode and cathode of the photodiode PD is equal to or higher than the breakdown voltage, the photodiode PD undergoes avalanche breakdown in response to the incidence of a photon, generating a multiplied avalanche current. When the avalanche current flows through the photodiode PD, the cathode voltage of the photodiode PD changes. In response to the change in the cathode voltage, the pixel control circuit 12 changes the output signal of the inverter INV5 and outputs a light detection pulse PLS to the counter circuit 16. The photodiode PD is, for example, a single photon avalanche diode (SPAD) that undergoes avalanche breakdown once in response to the incidence of one photon.

The pixel control circuit 12 includes transistors Trch, Ts, Ta, and Trst, inverters INV1 to INV5, capacitors CPs and CPa, and a count control circuit 14.

The transistor Trch is connected between the high-level voltage source VDDH and the cathode of the photodiode PD. The drain of the transistor Trch is connected to the voltage source VDDH, and its source is connected to the cathode of the photodiode PD and the input of the inverter INV1. The gate of the transistor Trch is connected to one of the control lines PVSEL and receives a control signal Vq from the vertical selection circuit 30.

When the transistor Trch is in a conductive state, it charges the cathode of the photodiode PD with the voltage source VDDH. As a result, a reverse bias voltage is applied to the photodiode PD. When the transistor Trch is in a non-conductive state, the photodiode PD is held in a state in which a reverse bias voltage is applied, and waits for the incidence of photons. At this time, the cathode voltage of the photodiode PD is set to VK. In this way, the transistor Trch is used to charge and recharge the photodiode PD. The transistor Trch may be, for example, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

The inverters INV1 to INV3 are connected in series between the cathode of the photodiode PD and the gate of the transistor Ta. The output of the inverter INV1 is connected to the gate of the transistor Ts. The inverters INV1 to INV3 function as buffers and delay circuits.

The transistor Ts is connected between a voltage source VDDL and a sense node SN. The voltage source VDDL is a voltage source lower than the voltage source VDDH but higher than the reference voltage source. The drain of the transistor Ts is connected to the voltage source VDDL, and the source of the transistor Ts is connected to the drain of the transistor Ta and one end of the capacitor CPs. The gate of the transistor Ts is connected to the output of the inverter INV1 and receives the inverted voltage VS of the voltage VK. The transistor Ts is controlled to a conductive state by the avalanche breakdown of the photodiode PD.

When the cathode voltage of the photodiode PD is charged, the transistor Ts is in a non-conductive state, electrically disconnecting one end of the capacitor CPs from the voltage source VDDL. When the photodiode PD undergoes avalanche breakdown and the cathode voltage VK drops, the transistor Ts becomes conductive and the capacitor CPs is charged by the voltage source VDDL. The voltage of the capacitor CPs is Vcs. The transistor Ts may be, for example, an n-type MOSFET.

Transistor Ta is connected between transistor Ts and sense node SN. The drain of transistor Ta is connected to the source of transistor Ts and one end of capacitor CPs, and the source is connected to sense node SN. The gate of transistor Ta is connected to the output of inverter INV3 and receives inverted voltage VA of voltage VK. Voltages VS and VA are signals of the same logic (voltages of the same level). However, since voltage VA passes through inverters INV2 and INV3, it is input to the gate of transistor Ta with a delay from voltage VS input to the gate of transistor Ts. Therefore, transistor Ta becomes conductive later than transistor Ts due to avalanche breakdown of photodiode PD.

When the cathode voltage VK of the photodiode PD is charged, the transistor Ta is in a non-conductive state, electrically disconnecting one end of the capacitor CPs from the sense node SN. When the photodiode PD receives a photon and undergoes avalanche breakdown, causing the cathode voltage VK to drop, the transistor Ts temporarily becomes conductive. This causes the capacitor CPs to be charged by the voltage source VDDL. When the voltage VK is recharged by quenching of the photodiode PD, the transistor Ts returns to a non-conductive state. After the transistor Ts returns to a non-conductive state, the transistor Ta becomes conductive. This causes the sense node SN to be charged by the capacitor CPs. The transistor Ta may be, for example, an n-type MOSFET.

The transistor Trst is connected between the sense node SN and a reference voltage source (e.g., ground). The drain of the transistor Trst is connected to the sense node SN, and the source is connected to the reference voltage source. The gate of the transistor Trst is connected to the output of the inverter INV5 (i.e., the output of the pixel control circuit 12) and receives the light detection pulse PLS.

The transistor Trst is in a non-conductive state when the light detection pulse PLS is not output, and becomes conductive every time the light detection pulse PLS is output to the counter circuit 16. When the transistor Trst becomes conductive, the voltage Vsn of the sense node SN is reset to a reference voltage (e.g., ground voltage). However, the light detection pulse PLS is output with a delay via inverters INV4 and INV5 relative to the change in the sense node SN. Therefore, after the voltage Vsn of the sense node SN has changed sufficiently, the transistor Trst can reset the voltage Vsn of the sense node SN. The transistor Trst may be, for example, an n-type MOSFET.

Capacitor CPs is a fixed capacitance connected between the node between transistor Ts and transistor Ta and a reference voltage source (e.g., ground). Capacitor CPs includes the parasitic capacitance of the node between transistor Ts and transistor Ta. Capacitor CPs is charged by voltage source VDDL when transistor Ts is in a conductive state. Capacitor CPs also charges sense node SN when transistor Ta is in a conductive state. Capacitor CPs has a capacitance Cs set to a predetermined value.

Capacitor CPa is a fixed capacitance connected between the sense node SN and a reference voltage source. Capacitor CPa includes the parasitic capacitance of the sense node SN. Capacitor CPa is charged by capacitor CPs when transistor Ta is in a conductive state. On the other hand, capacitor CPa is discharged and reset when transistor Trst is in a conductive state. The capacitance Ca of capacitor CPa is also set to a predetermined value.

The count control circuit 14 includes a capacitor CPv and a switch SW1 connected in series between the sense node SN and a reference voltage source (e.g., ground). The switch SW1 is connected between the sense node SN and one end of the capacitor CPv. The switch SW1 may be a transistor controlled by the counter circuit 16. The capacitor CPv is a fixed capacitance connected between the switch SW1 and the reference voltage source. The capacitance Cv of the capacitor CPv is set to a predetermined value.

The switch SW1 is controlled by a control signal from a predetermined bit of the counter circuit 16. For example, the switch is non-conductive when the count value is less than a predetermined value, and is conductive when the count value is equal to or greater than the predetermined value. When the count value is less than the predetermined value and the switch SW1 is non-conductive, the capacitance of the sense node SN is Ca. At this time, one light detection pulse PLS is output each time the photodiode PD undergoes an avalanche breakdown (detects one photon).

On the other hand, when the count number of the counter circuit 16 reaches a predetermined value and a corresponding predetermined bit is inverted, the switch SW1 becomes conductive. This causes the capacitor CPv to be connected in parallel to the capacitor CPa, and the capacitance of the sense node SN increases from Ca to Ca+Cv. As a result, each time the photodiode PD avalanche breakdowns multiple times (detects multiple photons), one light detection pulse PLS is output.

In this way, the count control circuit 14 changes the capacitance of the sense node SN according to the count value of the counter circuit 16, and controls the number of breakdowns of the photodiode PD required to increase the count value by 1.

The counter circuit 16 is connected to the output of the inverter INV5 (the output of the pixel control circuit 12). The counter circuit 16 counts the light detection pulse PLS based on the voltage Vsn of the sense node SN. That is, the counter circuit 16 counts the number of breakdowns of the photodiode PD. The counter circuit 16 may be, for example, a register circuit that integrates the rising edges of the light detection pulse PLS. If the count value is less than a predetermined value, the counter circuit 16 makes the switch SW1 non-conductive and increases the count value by 1 each time the photodiode PD detects one photon. When the count value reaches a predetermined value and a predetermined bit of the counter circuit 16 is inverted, the counter circuit 16 inverts the control signal of the switch SW1 and makes the switch SW1 conductive. As a result, as described above, the counter circuit 16 increases the count value by 1 each time the photodiode PD detects multiple photons.

Next, we will explain the operation of the light detection device according to the first embodiment.

Figure 3 is a timing diagram showing an example of the operation of the photodetector according to the first embodiment. In Figure 3, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is Ca, which is relatively small. This operation is suitable for a low-illuminance mode in which low-illuminance light is detected.

First, while waiting for photons before t1, the control signal Vq is set to a high-level voltage and the transistor Trch is in a conductive state. This causes the cathode of the photodiode PD to be charged by the high-level voltage source VDDH, and the cathode voltage VK rises. A reverse bias voltage is applied to the photodiode PD. In this state, the photodiode PD waits for the incidence of photons.

At t1, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, causing the cathode voltage VK to decrease.

At t2, when the cathode voltage VK falls below the threshold Vt1, the voltage Vs rises. This causes the transistor Ts to become conductive, and the capacitor CPs is charged by the voltage source VDDL through the transistor Ts. The voltage Vcs becomes approximately equal to the voltage of the voltage source VDDL.

Because the transistor Trch remains conductive, the cathode voltage VK continues to rise when the photodiode PD is quenched and returns to its original state before breakdown.

At t3, when the cathode voltage VK exceeds the threshold Vt1, the gate voltage VS of the transistor Ts falls. This causes the transistor Ts to go into a non-conductive state, and the capacitor CPs is disconnected from the voltage source VDDL while remaining in a charged state.

After the voltage Vs falls, the delay circuit of the inverters INV2 and INV3 causes the voltage VA to rise with a delay relative to the voltage VS. After the gate voltage VS falls, the gate voltage VA rises at t4. This causes the transistor Ta to be conductive, and the capacitors CPs and CPa are connected in parallel between the sense node SN and the reference voltage source. A part of the charge stored in the capacitor CPs moves to the capacitor CPa, and the voltage Vsn of the sense node SN and the voltage Vcs of the capacitor CPs become approximately equal. At this time, both the voltages Vcs and Vsn satisfy the formula 1.
Vcs=Vsn=VDDL×(Cs/(Cs+Ca)) (Equation 1)

When the voltage Vsn of the sense node SN exceeds the threshold Vt2, the light detection pulse PLS rises at t5. After the voltage Vsn exceeds the threshold Vt2, the light detection pulse PLS rises with a delay due to the delay circuit of the inverters INV4 and INV5.

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The rising edge of the light detection pulse PLS is fed back to the gate of the transistor Trst. As a result, at t6, the transistor Trst becomes conductive, and the voltage Vsn of the sense node SN is reset to the reference voltage source. Furthermore, when the voltage Vsn of the sense node SN is reset to the reference voltage source, the light detection pulse PLS falls at t7.

After that, t1 to t7 are repeated each time a photon is incident on the photodiode PD.

Here, in FIG. 3, the switch SW1 is in a non-conductive state, and the capacitance of the sense node SN is a relatively small Ca. Therefore, at t4 to t5, when the transistor Ta is in a conductive state, the voltage Vcs is divided by the capacitance of the capacitor CPs and the capacitor CPa. The voltage Vsn of the sense node SN is determined by the ratio Cs/(Cs+Ca) of the capacitance of the capacitor CPs (the capacitance of the node between the transistor Ts and the transistor Ta) to the capacitance of the capacitor CPa (the capacitance of the sense node SN), and is expressed as in Equation 1. If the capacitance Ca is small, the voltage Vsn of the sense node SN becomes large. If the capacitance Ca of the capacitor CPa is set so that the voltage Vsn of the sense node SN at this time exceeds the threshold value Vt2, the light detection pulse PLS is generated every time the photodiode PD avalanche breakdown occurs. This allows the counter circuit 16 to count each time a photon is incident on the photodiode PD. That is, the counter circuit 16 can count the number of photons incident on the photodiode PD.

When the number of photons counted reaches a predetermined value, a predetermined bit of the counter circuit 16 is inverted. At this time, the counter circuit 16 inverts the control signal of the switch SW1 to make the switch SW1 conductive.

Figure 4 is a timing diagram showing an example of the operation of the photodetector when switch SW1 is in a conductive state. In Figure 4, switch SW1 is in a conductive state, and the capacitance of sense node SN is relatively large (Ca + Cv). This operation is suitable for a high-illuminance mode that detects high-illuminance light.

When waiting for photons, the control signal Vq is set to a high-level voltage, and the transistor Trch is in a conductive state. The cathode voltage VK of the photodiode PD is charged by the high-level voltage source VDDH. A reverse bias voltage is applied to the photodiode PD. In this state, the photodiode PD waits for the incidence of photons.

At t11, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, causing the cathode voltage VK to decrease.

At t12, when the cathode voltage VK falls below the threshold Vt1, the voltage VS rises. This causes the transistor Ts to become conductive, and the capacitor CPs is charged by the voltage source VDDL via the transistor Ts. The voltage Vcs becomes approximately equal to the voltage of the voltage source VDDL.

Since the transistor Trch remains conductive, when the photodiode PD is quenched and returns to its original state before breakdown, the cathode voltage VK rises again.

At t13, when the cathode voltage VK exceeds the threshold Vt1, the gate voltage VS of the transistor Ts falls. This causes the transistor Ts to go into a non-conductive state, and the capacitor CPs is disconnected from the voltage source VDDL while remaining in a charged state.

After the voltage VS falls, the delay circuit of the inverters INV2 and INV3 causes the voltage VA to rise with a delay relative to the voltage VS. After the gate voltage VS falls, the gate voltage VA rises at t14. This causes the transistor Ta to be conductive, and the capacitors CPs, CPa, and CPv are connected in parallel between the sense node SN and the reference voltage source. A part of the charge stored in the capacitor CPs moves to the capacitors CPa and CPv, and the voltage Vsn of the sense node SN and the voltage Vcs at one end of the capacitor CPs become approximately equal. At this time, both the voltages Vcs and Vsn satisfy the formula 2.
Vcs=Vsn=VDDL×(Cs/(Cs+Ca+Cv)) (Equation 2)

Here, since the switch SW1 is in a conductive state, the capacitance of the sense node SN increases from Ca to (Ca+Cv). Therefore, from t14 to t15, the voltage Vcs is divided by the capacitor CPs and the capacitors CPa and CPv. As a result, the voltage Vsn of the sense node SN is determined by the ratio Cs/(Cs+Ca+Cv) of the capacitance of the capacitor CPs (the capacitance of the node between the transistor Ts and the transistor Ta) to the capacitance of the capacitors CPa and CPv (the capacitance of the sense node SN), and is expressed as in Equation 2. Since the capacitance (Ca+Cv) is greater than the capacitance Ca, the voltage Vsn of the sense node SN becomes smaller than when the switch SW1 is in a non-conductive state. If the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN at this time does not exceed the threshold value Vt2, the light detection pulse PLS will not be generated by the first avalanche breakdown of the photodiode PD. That is, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

Since the light detection pulse PLS is not generated, the transistor Trst remains non-conductive and the voltage Vsn of the sense node SN is not reset.

After the gate voltage VA falls at t15, at t16 the second photon is incident on the photodiode PD, causing the photodiode PD to undergo avalanche breakdown, similar to the operation at t11, and the cathode voltage VK falls again.

The operations from t17 to t18 are the same as those from t12 to t13, respectively.

At t18, after the voltage VS falls, the delay circuit of the inverters INV2 and INV3 causes the voltage VA to rise with a delay relative to the voltage VS. After the gate voltage VS falls, the gate voltage VA rises at t19. This causes the transistor Ta to be conductive, and the capacitors CPs, CPa, and CPv are electrically connected in parallel. A part of the charge stored in the capacitor CPs further moves to the capacitors CPa and CPv, and the voltage Vsn of the sense node SN and the voltage Vcs of the capacitor CPs are averaged and become almost equal. At this time, both the voltages Vcs and Vsn satisfy the formula 3.
Vcs=Vsn=VDDL×(Cs×(Cs+2Ca+2Cv)/(Cs+Ca+Cv) ² ) (Equation 3)

Here, when the first photon is incident, the light detection pulse PLS is not generated, so the sense node SN is not reset. Therefore, the voltage Vsn of the sense node SN is maintained in a charged state of VDDL×(Cs/(Cs+Ca+Cv)). Furthermore, when the second photon is incident, the sense node SN is further charged, and the voltage Vsn of the sense node SN becomes VDDL×(Cs×(Cs+2Ca+2Cv)/(Cs+Ca+Cv) ² ). If the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN at this time exceeds the threshold value Vt2, the light detection pulse PLS is generated by the second avalanche breakdown of the photodiode PD. This allows the counter circuit 16 to count one every time two photons are incident on the photodiode PD.

In order for the counter circuit 16 to perform one count for the detection of one photon, Cs and Ca are set to satisfy Equation 4. In order for the counter circuit 16 to perform one count for the detection of two photons, Cs, Ca, and Cv are set to satisfy Equations 5 and 6. Note that Vth is the threshold voltage of the inverter INV4.
Ca<Cs(VDDL-Vth)/Vth (Equation 4)
Ca+Cv>Cs(VDDL-Vth)/Vth (Equation 5)
VDDL×Cs(Cs+2Ca+sCv)>Vth(Cs+Ca+Cv) ² (Equation 6)

When the light detection pulse PLS rises at t20, the counter circuit 16 increments the count value by 1 and raises the control signal to the transistor Trst. As a result, at t21, the transistor Trst becomes conductive and the voltage Vsn of the sense node SN is reset to the reference voltage source. Furthermore, when the voltage Vsn of the sense node SN is reset by the reference voltage source, the light detection pulse PLS falls at t22.

After that, t11 to t22 are repeated each time two photons are incident on the photodiode PD.

In this way, the photodetector 100 according to this embodiment can control the increase in the count value relative to the number of breakdowns of the photodiode PD according to the count value of the counter circuit 16.

For example, FIG. 5 is a graph showing the relationship between the number of incident photons and the count value. The horizontal axis shows the number of photons incident on the photodiode PD. The vertical axis shows the count value of the counter circuit 16.

When the count value of the counter circuit 16 is less than a predetermined value M (in the case of low illuminance light), the switch SW1 of the count control circuit 14 is in a non-conducting state, electrically disconnecting the capacitor CPv from the sense node SN. Therefore, the capacitance of the sense node SN is relatively small at Ca, and the voltage Vsn of the sense node SN rises significantly due to the charge from the capacitor CPs. This causes the pixel control circuit 12 to output a light detection pulse PLS every time the photodiode PD undergoes avalanche breakdown. The counter circuit 16 increases the count value by one every time the photodiode PD detects one photon.

On the other hand, when the count value of the counter circuit 16 is equal to or greater than a predetermined value M (high illuminance light), the switch SW1 of the count control circuit 14 becomes conductive and electrically connects the capacitor CPv to the sense node SN. As a result, the capacitance of the sense node SN increases from Ca to (Ca+Cv), and the increase in the voltage Vsn of the sense node SN becomes smaller due to the charge from the capacitor CPs. This causes the pixel control circuit 12 to output a light detection pulse PLS every time the photodiode PD undergoes multiple avalanche breakdowns. The counter circuit 16 increases the count value by one every time the photodiode PD detects multiple photons.

When the switch SW1 is in a conductive state, the counter circuit 16 increases the count value by one each time the photodiode PD detects two photons. By changing the capacitance Cv of the capacitor CPv, the counter circuit 16 can increase the count value by one each time the photodiode PD breaks down n times (n is an integer equal to or greater than 2) (each time n photons are detected).

As described above, according to this embodiment, while the photodiode PD detects all incident photons, the capacitance of the sense node SN is controlled to limit the frequency of generation of the light detection pulse PLS and reduce the count value of the counter circuit 16.

For example, when low-illuminance light is incident, the counter circuit 16 increases the count value for one photon. This allows the light detection device 100 to detect low-illuminance light with a high SNR.

When high-intensity light is incident, the counter circuit 16 increases the count value for one photon until the count value reaches a predetermined value M, and increases the count value for n photons when the count value exceeds the predetermined value M. This suppresses the increase in the count value (number of bits) of the counter circuit 16 even in the case of high-intensity light, making it difficult to reach the upper limit of the count value. This allows the count value of the counter circuit 16 to be further reduced. Therefore, the counter circuit 16 is less likely to saturate in response to high-intensity light, and can count the number of photons of light with a higher illuminance.

Even in the case of high-intensity light, the photodiode PD detects all photons without thinning them out, and the number of photons can be accurately calculated by referring to the count value of the counter circuit 16. In other words, even when high-intensity light is incident, the counter circuit 16 can count photons without degrading the SNR. Therefore, the photodetector 100 according to this embodiment can expand the dynamic range without degrading the SNR.

In addition, even under high-intensity light, the frequency with which the count value reaches its upper limit is reduced, and the number of times the counter circuit 16 is read out can be reduced. In addition, under high-intensity light, the count value of the counter circuit 16 and the generation of the light detection pulse PLS are reduced. This allows the power consumption of the light detection device 100 to be reduced.

The count control circuit 14 is provided for each pixel P. Therefore, the count control circuit 14 can switch the sensitivity for each pixel P between a low-illuminance mode and a high-illuminance mode.

Reducing the number of bits in the register circuit of the counter circuit 16 also leads to a reduction in the layout area of each pixel P.

The count control circuit 14 may also be controlled from outside the photodetection device 100. In this case, it is difficult to switch each pixel P, but it is possible to switch the entire pixel region 10.

(Modification)
FIG. 6 is a block diagram showing a part of another example of the internal configuration of one pixel P. In the first embodiment, the count control circuit 14 changes the capacitance of the sense node SN by the capacitor CPv. However, as in this modification, the count control circuit 14 may be connected in parallel to the capacitor CPs to make the capacitance of the node between the transistor Ts and the transistor Ta variable. In this case, in the low illuminance mode, the count control circuit 14 makes the switch SW1 conductive, electrically connects the capacitor CPv in parallel to the capacitor CPs, and increases the capacitance of the node between the transistor Ts and the transistor Ta. In the high illuminance mode, the count control circuit 14 makes the switch SW1 non-conductive, electrically disconnects the capacitor CPv from the capacitor CPs, and reduces the capacitance of the node between the transistor Ts and the transistor Ta. The switch SW1 may be controlled by a control signal from the counter circuit 16, as in the above embodiment. The control signal of the switch SW1 has the reverse logic to that of the first embodiment. Thus, similarly to the above embodiment, the photodetector 100 can control the increase in the count value relative to the number of breakdowns of the photodiode PD in accordance with the count value of the counter circuit 16 .

Other configurations and operations of this modified example may be the same as those of the first embodiment. As a result, this modified example can achieve the same effects as those of the first embodiment.

Second Embodiment
7 is a block diagram showing an example of the internal configuration of a pixel P according to the second embodiment. In the second embodiment, the sense node SN is connected to the cathode of the photodiode PD via a resistor element RK. The sense node SN is connected to a voltage source VDDH via a transistor Trch. As a result, the voltage Vsn of the sense node SN is determined by the voltage source VDDH and the resistor element RK, etc., regardless of the voltage source VDDL.

In the second embodiment, the pixel P includes a photodiode PD, a transistor Trch, a resistive element RK, capacitors CPa and CK1, a count control circuit 14, a counter circuit 16, and inverters INV6 and INV7. The photodiode PD, the capacitor CPa, the count control circuit 14, and the counter circuit 16 are the same as those in the first embodiment.

The transistor Trch is connected between the voltage source VDDH and the resistive element RK. The gate of the transistor Trch is connected to the output of the inverter INV7. The transistor Trch is controlled by receiving an inverted signal of the light detection pulse PLS. The transistor Trch is, for example, composed of a p-type MOSFET.

The resistor element RK is connected between the drain of the transistor Trch and the cathode of the photodiode PD.

Capacitor CPk1 is connected between the cathode of photodiode PD and a reference voltage source (e.g., ground).

The inverter INV6 is connected between the sense node SN and the counter circuit 16. The inverter INV7 is connected between the output of the inverter INV6 and the gate of the transistor Trch.

Next, we will explain the operation of the photodetector according to the second embodiment.

Figure 8 is a timing diagram showing an example of the operation of the photodetector according to the second embodiment. In Figure 8, switch SW1 is in a non-conducting state, and the capacitance of sense node SN is relatively small, Ca. Figure 8 shows the operation in the low-illumination mode.

First, the capacitors CPk1 and Ca are charged by the high-level voltage source VDDH, and then the transistor Trch is in a non-conductive state. Since the light detection pulse PLS is at a low-level voltage, the control signal XRCG is set to a high-level voltage. The cathode voltage VK1 and the voltage Vsn of the sense node SN are maintained at high-level voltages. As a result, a reverse bias voltage is applied to the photodiode PD. In this state, the photodiode PD waits for photons to enter.

At t1, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, and the cathode voltage VK1 drops. At this time, the sense node SN is connected to the cathode of the photodiode PD via a resistor element RK. Therefore, if the resistor element RK is sufficiently large, the voltage Vsn drops with a delay from the cathode voltage VK1. After the multiplication of the photodiode PD stops, the charge is distributed between the cathode of the photodiode PD and the sense node SN, and the voltage Vsn drops. At this time, the voltage Vsn is determined by the ratio of the capacitance CK1 of the capacitor CPk1 (the capacitance of the cathode of the photodiode PD) to the capacitance Ca of the capacitor CPa (the capacitance of the sense node SN), as shown in Equation 7.
Vsn=ΔVK1×(CK1/(CK1+Ca)) (Equation 7)
It should be noted that ΔVK1 is the amount of change in the cathode voltage VK before and after the breakdown of the photodiode PD.

At t2, when the voltage Vsn of the sense node SN falls below the threshold Vt12, the photodetection pulse PLS rises due to the inverter INV6.

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The rising edge of the light detection pulse PLS is fed back to the gate of the transistor Trch via the inverter INV7. At this time, the rising edge of the light detection pulse PLS is delayed by the inverter INV7 and fed back to the gate of the transistor Trch. As a result, at t3, the transistor Trch becomes conductive, and the cathode voltage VK and the voltage Vsn of the sense node SN are recharged by the voltage source VDDH. At this time, at t4, when the voltage Vsn of the sense node SN exceeds the threshold, the light detection pulse PLS falls. The falling edge of the light detection pulse PLS is delayed by the inverter INV7 and fed back to the gate of the transistor Trch as a control signal XRCG. As a result, at t5, the transistor Trch becomes non-conductive, and the cathode voltage VK and the voltage Vsn of the sense node SN are isolated from the voltage source VDDH in a recharged state.

After that, t1 to t5 are repeated each time a photon is incident on the photodiode PD.

Here, in FIG. 8, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is a relatively small Ca. Therefore, when the photodiode PD undergoes avalanche breakdown from t2 to t3, the voltages VK1 and Vsn are divided by the capacitance of the capacitor CPk1 and the capacitor CPa. The voltage Vsn of the sense node SN is determined by the ratio Cs/(Cs+Ca) of the capacitance of the capacitor CPk1 (capacity of the photodiode PD) to the capacitance of the capacitor CPa (capacity of the sense node SN), and is expressed as in Equation 7. When the capacitance Ca is small, the voltage Vsn of the sense node SN changes significantly. If the capacitance Ca of the capacitor CPa is set so that the voltage Vsn of the sense node SN at this time exceeds the threshold value Vt12, the light detection pulse PLS is generated every time the photodiode PD undergoes avalanche breakdown. This allows the counter circuit 16 to count each time a photon is incident on the photodiode PD. That is, the counter circuit 16 can count the number of photons incident on the photodiode PD.

When the photon count value reaches a predetermined value, a predetermined bit of the counter circuit 16 is inverted. At this time, the counter circuit 16 inverts the control signal of the switch SW1 to make the switch SW1 conductive.

Figure 9 is a timing diagram showing an example of the operation of the photodetector when switch SW1 is in a conductive state. In Figure 9, switch SW1 is in a conductive state, and the capacitance of sense node SN is relatively large (Ca+Cv). Figure 9 shows the operation in high illumination mode.

Before t11, the capacitors CPk1, Ca, and Cv are charged by the high-level voltage source VDDH, and then the transistor Trch is in a non-conductive state. This causes a reverse bias voltage to be applied to the photodiode PD. In this state, the photodiode PD waits for a photon to be incident.

At t11, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, causing the cathode voltage VK1 to decrease.

The drop in the cathode voltage VK1 is delayed by the resistive element RK and appears in the voltage Vsn of the sense node SN. Therefore, at t12, as the cathode voltage VK1 drops, the voltage Vsn also drops.

Furthermore, a part of the charge moves between the capacitors CPa, CPv and the capacitor CPk1, so that the voltage VK1 and the voltage Vsn of the sense node SN become substantially equal.
VK1=Vsn=ΔVK1×(CK1/(CK1+Ca+Cv)) (Equation 8)

Here, when the switch SW1 is in a conductive state, the capacitance of the sense node SN increases from Ca to (Ca+Cv). Therefore, from t11 to t12, the voltage VK1 is divided by the capacitor CPk1 and the capacitors CPa and CPv. As a result, the voltage Vsn of the sense node SN is determined by the ratio CK1/(CK1+Ca+Cv) of the capacitance of the capacitor CPk1 (capacity of the photodiode PD) to the capacitance of the capacitors CPa and CPv (capacity of the sense node SN), and is expressed as in Equation 8. Since the capacitance (Ca+Cv) is larger than the capacitance Ca, the voltage Vsn of the sense node SN becomes smaller than when the switch SW1 is in a non-conductive state. If the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN at this time does not fall below the threshold value Vt12, the light detection pulse PLS will not be generated by the first avalanche breakdown of the photodiode PD. That is, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

Since the light detection pulse PLS is not generated, the transistor Trst remains non-conductive and the voltage Vsn of the sense node SN is not reset.

After the photodiode PD is quenched, at t13, when a photon is again incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, similar to the operation at t11, and the cathode voltage VK drops again.

The drop in the cathode voltage VK1 is delayed by the resistive element RK and appears in the voltage Vsn of the sense node SN. Therefore, at t14, as the cathode voltage VK1 drops, the voltage Vsn also drops.

In addition, some of the charge moves between capacitors CPa, CPv and capacitor CPk1, and voltage VK1 and voltage Vsn of sense node SN become approximately equal. At this time, both voltages VK1 and Vsn satisfy equation 8.

During the period from t13 to t14, a part of the charge moves between the capacitors CPa, CPv and the capacitor CPk1, and the voltage Vsn of the sense node SN and the voltage VK1 at one end of the capacitor CPk1 are averaged and become substantially equal. At this time, both the voltages VK1 and Vsn satisfy the formula 9.
VK1=Vsn=ΔVK1×(CK1×(CK1+2Ca+2Cv)/(CK1+Ca+Cv) ² ) (Equation 9)

Here, when the first photon is incident, the light detection pulse PLS is not generated, so the sense node SN is not reset. Therefore, the voltage Vsn of the sense node SN maintains a state of being charged to ΔVK1×(CK1/(CK1+Ca+Cv)). Furthermore, when the second photon is incident, the sense node SN is further charged, and the voltage Vsn of the sense node SN becomes ΔVK1×(CK1×(CK1+2Ca+2Cv)/(CK1+Ca+Cv) ² ). If the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN at this time falls below the threshold value Vt12, the light detection pulse PLS is generated every time the photodiode PD avalanche breakdown occurs twice. This allows the counter circuit 16 to count one every time two photons are incident on the photodiode PD.

At t14, when the light detection pulse PLS rises, the counter circuit 16 increments the count by 1 and feeds the light detection pulse PLS back to the gate of the transistor Trch. As a result, at t15, the transistor Trch becomes conductive and recharges the voltage VK1 and the voltage Vsn to the voltage source VDDH.

At t16, when the voltage Vsn of the sense node SN exceeds the threshold Vt12, the light detection pulse PLS falls. At t17, the transistor Trch returns to a non-conductive state. This causes the cathode voltage VK and the voltage Vsn of the sense node SN to be isolated from the voltage source VDDH in a recharged state.

After that, t11 to t17 are repeated each time two photons are incident on the photodiode PD.

In this way, according to the second embodiment, while the photodiode PD detects all incident photons, the capacitance of the sense node SN is controlled to limit the frequency of generation of the light detection pulse PLS and reduce the count value of the counter circuit 16. Therefore, the second embodiment can obtain the same effect as the first embodiment.

In the second embodiment, as in the first embodiment, by changing the capacitance Cv of the capacitor CPv, the counter circuit 16 can increase the count value by 1 every time the photodiode PD breaks down n times (every time n photons are detected). This allows the count value of the counter circuit 16 to be reduced.

Third Embodiment
10 is a block diagram showing an example of the internal configuration of a pixel P according to the third embodiment. In the third embodiment, a transistor Tclip is connected between the source of the transistor Trch and the cathode of the photodiode PD, instead of the resistive element RK. The transistor Tclip is controlled to be in a conductive state or a non-conductive state by a control signal CLIP from the vertical selection circuit 30. The transistor Tclip is, for example, configured of a p-type MOSFET.

In the second embodiment, the resistive element RK determines the timing of generating the light detection pulse PLS, but in the third embodiment, the control signal CLIP determines the timing of generating the light detection pulse PLS. The control signal CLIP may periodically repeat high/low. The other configurations of the third embodiment may be similar to those of the second embodiment.

Next, we will explain the operation of the light detection device according to the third embodiment.

Figure 11 is a timing diagram showing an example of the operation of the photodetector according to the third embodiment. In Figure 11, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is Ca, which is relatively small. Figure 11 shows the operation in the low-illumination mode.

The operation up to t1 is the same as in the second embodiment. In this state, the photodiode PD waits for a photon to be incident. Note that the transistor Tclip is in a non-conducting state with a reverse bias voltage applied to the photodiode PD.

At t1, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, and the cathode voltage VK1 drops. At this time, the transistor Tclip is in a non-conductive state, so the voltage Vsn of the sense node SN does not drop.

At t2, when the signal CLIP falls, the transistor Tclip becomes conductive. This causes the voltage Vsn of the sense node SN to be connected to the cathode voltage VK1 and to drop.

At t3, when the voltage Vsn of the sense node SN falls below the threshold Vt12, the photodetection pulse PLS rises due to the inverter INV6.

In this way, the timing of the fall of voltage Vsn and the timing of the rise of the light detection pulse PLS can be controlled by the timing of the fall of signal CLIP. The charge of capacitor CPk1 is distributed between the cathode of photodiode PD and sense node SN, causing voltage Vsn to decrease and voltage VK1 to increase. At this time, voltage Vsn is determined by the ratio of capacitance CK1 of capacitor CPk1 (capacitance of the cathode of photodiode PD) to capacitance Ca of capacitor CPa (capacitance of sense node SN), as shown in Equation 7.

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The rising edge of the light detection pulse PLS is delayed and fed back to the gate of the transistor Trch via the inverter INV7. As a result, at t4, the transistor Trch becomes conductive, and the cathode voltage VK and the voltage Vsn of the sense node SN are recharged to the voltage source VDDH. At t5, when the voltage Vsn of the sense node SN exceeds the threshold value Vt12, the light detection pulse PLS falls. The falling edge of the light detection pulse PLS is delayed by the inverter INV7 and fed back to the gate of the transistor Trch. As a result, at t6, the transistor Trch returns to a non-conductive state, and the cathode voltage VK and the sense node SN are isolated from the voltage source VDDH in a recharged state.

After the cathode voltage VK and the sense node SN are recharged, at t7, the control signal CLIP rises and the transistor Tclip becomes non-conductive. This returns to the state before t1.

After that, t1 to t7 are repeated each time a photon is incident on the photodiode PD. The control signal CLIP may periodically alternate between high and low.

In the third embodiment, the control signal CLIP determines the timing of generating the light detection pulse PLS. The other operations of the third embodiment may be similar to those of the second embodiment. This allows the counter circuit 16 to count each time a photon is incident on the photodiode PD.

When the number of photons counted reaches a predetermined value, a predetermined bit of the counter circuit 16 is inverted. At this time, the counter circuit 16 inverts the control signal to make the switch SW1 conductive.

Figure 12 is a timing diagram showing an example of the operation of the photodetector when switch SW1 is in a conductive state. In Figure 12, switch SW1 is in a conductive state, and the capacitance of sense node SN is relatively large (Ca+Cv). Figure 12 shows the operation in high illumination mode.

The operation up to t11 is the same as in the second embodiment. In this state, the photodiode PD waits for a photon to be incident. Note that the transistor Tclip is in a non-conducting state with a reverse bias voltage applied to the photodiode PD.

At t11, when a photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, and the cathode voltage VK1 drops. At this time, the transistor Tclip is in a non-conductive state, so the voltage Vsn of the sense node SN does not drop.

At t12, when the signal CLIP falls, the transistor Tclip becomes conductive. As a result, the voltage Vsn of the sense node SN is connected to the cathode voltage VK1 and drops. At t13, some of the charge stored in the capacitor CPk1 moves to the capacitors CPa and CPv, and the voltage VK1 and the voltage Vsn of the sense node SN become approximately equal. At this time, both voltages VK1 and Vsn satisfy equation 8.

Since the switch SW1 is in a conductive state, if the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN does not fall below the threshold value Vt12, as in the second embodiment, the light detection pulse PLS is not generated by the first avalanche breakdown of the photodiode PD. In other words, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

Since the light detection pulse PLS is not generated, the transistor Trch remains non-conductive, and the voltage CK1 of the capacitor CPk1 and the voltage Vsn of the sense node SN are not reset.

Next, at t14, the control signal CLIP is raised to make the transistor Tclip non-conductive.

Next, at t15, when a second photon is incident on the photodiode PD, the photodiode PD undergoes avalanche breakdown, similar to the operation at t11, and the cathode voltage VK1 drops again.

At t16, when the signal CLIP falls, the transistor Tclip becomes conductive. As a result, the voltage Vsn of the sense node SN is connected to the cathode voltage VK1 and drops. Some of the charge stored in the capacitor CPk1 moves to the capacitors CPa and CPv, and the voltage VK1 and the voltage Vsn of the sense node SN become approximately equal. At this time, both voltages VK1 and Vsn satisfy equation 9.

Here, since the light detection pulse PLS is not generated when the first photon is incident, the sense node SN is not reset. Therefore, the voltage Vsn of the sense node SN maintains a state of being charged to ΔVK1×(CK1/(CK1+Ca+Cv)). Furthermore, when the second photon is incident, the sense node SN is further charged, and the voltage Vsn of the sense node SN becomes ΔVK1×(CK1×(CK1+2Ca+2Cv)/(CK1+Ca+Cv) ² ). If the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN at this time falls below the threshold value Vt12, the light detection pulse PLS is generated every time the photodiode PD avalanche breakdown occurs twice. This allows the counter circuit 16 to count one every time two photons are incident on the photodiode PD.

When the light detection pulse PLS rises at t17, the counter circuit 16 increments the count by 1 and the light detection pulse PLS is fed back to the gate of the transistor Trch. As a result, at t18, the signal XRCG falls, the transistor Trch becomes conductive, and the voltage VK1 and the voltage Vsn are recharged to the voltage source VDDH. When the voltage Vsn of the sense node SN is recharged to the voltage source VDDH, the light detection pulse PLS falls at t19, and at t20, the signal XRCG rises, and the transistor Trch returns to a non-conductive state.

After that, t11 to t21 are repeated each time two photons are incident on the photodiode PD.

In this way, according to the third embodiment, while the photodiode PD detects all incident photons, the capacitance of the sense node SN is controlled to limit the frequency of generating the light detection pulse PLS and reduce the count value of the counter circuit 16. Therefore, the third embodiment can obtain the same effect as the second embodiment.

In the third embodiment, as in the second embodiment, by changing the capacitance Cv of the capacitor CPv, the counter circuit 16 can increase the count value by 1 every time the photodiode PD breaks down n times (every time n photons are detected). This allows the count value of the counter circuit 16 to be further reduced.

In the third embodiment, a transistor Tclip is used instead of the resistive element RK. Therefore, by reducing the on-resistance of the transistor Tclip, the recharging time of the capacitors CPk1, Ca, and Cv can be shortened.

Fourth Embodiment
13 is a block diagram showing an example of the internal configuration of a pixel P according to the fourth embodiment. In the fourth embodiment, a plurality of photodiodes PD1, PD2, a plurality of capacitors CPk1, CPk2, and a plurality of transistors Tclip1, Tclip2 are connected in parallel between a common sense node SN and a reference voltage source. The photodiode PD2 and the transistor Tclip2 may have the same configurations as the photodiode PD, the capacitor CPk1, and the transistor Tclip in the third embodiment. As a result, in the fourth embodiment, one counter circuit 16 counts the photons incident on the plurality of photodiodes PD1, PD2. The other configurations of the fourth embodiment may be the same as those of the third embodiment.

Next, we will explain the operation of the light detection device according to the fourth embodiment.

Figures 14 and 15 are timing diagrams showing an example of the operation of the photodetector according to the fourth embodiment. In Figures 14 and 15, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is Ca, which is relatively small. Figures 14 and 15 show the operation in the low illuminance mode. Figure 14 shows the operation when one photodiode PD1 detects photons. Figure 15 shows the operation when both photodiodes PD1 and PD2 detect photons.

The operations up to t1 and t1a in FIG. 14 and FIG. 15 are basically the same as those in the second embodiment. At this time, the capacitors CPk1, CPk2, and Ca are in a charged state. In this state, the photodiodes PD1 and PD2 wait for the incidence of photons. Note that the transistors Tclip1 and Tclip2 are in a non-conducting state with a reverse bias voltage applied to the photodiodes PD1 and PD2.

(Photons incident only on PD1)
14, when a photon is incident on the photodiode PD1 at time t1, the photodiode PD1 undergoes avalanche breakdown, and the cathode voltage VK1 drops. At this time, the transistor Tclip1 is in a non-conductive state, so the voltage Vsn of the sense node SN does not drop. Also, since no photons are incident on the photodiode PD2, the cathode voltage VK2 of the photodiode PD2 does not drop.

At t2, when the control signals CLIP1 and CLIP2 fall, the transistors Tclip1 and Tclip2 become conductive. As a result, the voltage Vsn of the sense node SN is connected to the cathode voltage VK1 and drops.

At t3, when the voltage Vsn of the sense node SN falls below the threshold Vt12, the photodetection pulse PLS rises due to the inverter INV6.

In this way, the timing of the fall of voltage Vsn and the timing of the rise of the light detection pulse PLS can be controlled by the timing of the fall of control signals CLIP1 and CLIP2. The charge of capacitor CPk1 is distributed between the cathode of photodiode PD1 and sense node SN, voltage Vsn decreases, and voltage VK1 increases. At this time, voltages Vsn, VK1, and VK2 become approximately equal. Voltage Vsn is determined by the ratio (CK1/(CK1+CK2+Ca)) of capacitances CK1 and CK2 of capacitors CPk1 and CPk2 (capacity of the cathodes of photodiodes PD1 and PD2) to capacitance Ca of capacitor CPa (capacity of sense node SN).

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The subsequent recharging operation from t4 to t7 can be the same as in the third embodiment.

After the capacitors CPk1 and CPk2 and the sense node SN are recharged, at t7, the control signals CLIP1 and CLIP2 rise and the transistors Tclip1 and Tclip2 become non-conductive. This returns to the state before t1. The control signals CLIP1 and CLIP2 are synchronized and periodically repeat high and low.

The operation of the photodetector 100 when photons are incident only on the photodiode PD2 can be easily understood by referring to FIG. 14, so a description thereof will be omitted.

(Photons incident on both PD1 and PD2)
15, when photons are incident on both the photodiodes PD1 and PD2 at times t1a and t1b, the photodiodes PD1 and PD2 undergo avalanche breakdown, and the cathode voltages VK1 and VK2 both drop. At this time, the transistors Tclip1 and Tclip2 are in a non-conductive state, so the voltage Vsn of the sense node SN does not drop.

At t2, when the control signals CLIP1 and CLIP2 fall, the transistors Tclip1 and Tclip2 become conductive. This connects the sense node SN to the capacitors CPk1 and CPk2, and the voltage Vsn is reduced by the cathode voltages VK1 and VK2.

At t3, when the voltage Vsn of the sense node SN falls below the threshold Vt12, the photodetection pulse PLS rises due to the inverter INV6.

In this way, the timing of the fall of voltage Vsn and the timing of the rise of the light detection pulse PLS can be controlled by the timing of the fall of control signals CLIP1, CLIP2. The charge of capacitors CPk1, CPk2 is distributed between the sense node SN, voltage Vsn decreases, and voltages VK1, VK2 increase. At this time, voltages Vsn, VK1, VK2 become approximately equal. Voltage Vsn is determined by the ratio (CK1+CK2/(CK1+CK2+Ca)) of capacitances CK1, CK2 of capacitors CPk1, CPk2 (capacity of the cathodes of photodiodes PD1, PD2) to capacitance Ca of capacitor CPa (capacity of sense node SN).

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The subsequent recharging operation from t4 to t7 can be the same as in the third embodiment.

After the capacitors CPk1 and CPk2 and the sense node SN are recharged, at t7, the control signals CLIP1 and CLIP2 rise and the transistors Tclip1 and Tclip2 become non-conductive. This returns to the state before t1. The control signals CLIP1 and CLIP2 are synchronized and periodically repeat high and low.

In this way, in the low illuminance mode, when at least one of the two photodiodes PD1 and PD2 detects a photon, a light detection pulse PLS is generated and the counter circuit 16 counts the light detection pulses PLS.

Figures 16 and 17 are timing diagrams showing an example of the operation of the photodetector according to the fourth embodiment. In Figures 16 and 17, the switch SW1 is in a conductive state, and the capacitance of the sense node SN is relatively large, (Ca+Cv). Figures 16 and 17 show the operation in the high illuminance mode. Figure 16 shows the operation when one photodiode PD1 detects photons. Figure 17 shows the operation when both photodiodes PD1 and PD2 detect photons.

The operations up to t11 and t11a in FIG. 16 and FIG. 17 are basically the same as those in the second embodiment. At this time, the capacitors CPk1, CPk2, and Ca are in a charged state. In this state, the photodiodes PD1 and PD2 wait for the incidence of photons. Note that the transistors Tclip1 and Tclip2 are in a non-conducting state with a reverse bias voltage applied to the photodiodes PD1 and PD2.

(Photons incident only on PD1)
16, when a photon is incident on the photodiode PD1 at time t11, the photodiode PD1 undergoes avalanche breakdown, and the cathode voltage VK1 drops. At this time, the transistor Tclip1 is in a non-conductive state, so the voltage Vsn of the sense node SN does not drop. Also, since no photons are incident on the photodiode PD2, the cathode voltage VK2 of the photodiode PD2 does not drop.

At t12, when the control signals CLIP1 and CLIP2 fall, the transistors Tclip1 and Tclip2 become conductive. This causes the voltage Vsn of the sense node SN to be connected to the cathode voltage VK1 and to drop. At t13, some of the charge stored in the capacitor CPk1 moves to the capacitors CPa, CPv, and CPk2, and the voltages VK1 and VK2 and the voltage Vsn of the sense node SN become approximately equal.

Since the switch SW1 is in a conductive state, if the capacitances Ca and Cv of the capacitors CPa and CPv are set so that the voltage Vsn of the sense node SN does not fall below the threshold value Vt12, as in the second embodiment, the light detection pulse PLS is not generated by the first avalanche breakdown of the photodiode PD. In other words, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

Since the light detection pulse PLS is not generated, the transistor Trch remains non-conductive, and the voltage CK1 of the capacitor CPk1 and the voltage Vsn of the sense node SN are not reset.

Next, at t14, the control signal CLIP is raised to put the transistor Tclip into a non-conductive state. This causes the photodetector 100 to return to the state it was in before t11. The control signals CLIP1 and CLIP2 are synchronized and periodically repeat high/low states.

(Photons incident on both PD1 and PD2)
17, when photons are incident on both the photodiodes PD1 and PD2 at times t11a and t11b, the photodiodes PD1 and PD2 undergo avalanche breakdown, and the cathode voltages VK1 and VK2 both fall. At this time, the transistors Tclip1 and Tclip2 are in a non-conductive state, so the voltage Vsn of the sense node SN does not fall.

At t12, when the control signals CLIP1 and CLIP2 fall, the transistors Tclip1 and Tclip2 become conductive. This connects the sense node SN to the capacitors CPk1 and CPk2, and the voltage Vsn decreases due to the cathode voltages VK1 and VK2.

At t13, when the voltage Vsn of the sense node SN falls below the threshold Vt12, the photodetection pulse PLS rises due to the inverter INV6.

In this way, the timing of the fall of voltage Vsn and the timing of the rise of the light detection pulse PLS can be controlled by the timing of the fall of control signals CLIP1, CLIP2. The charge of capacitors CPk1, CPk2 is distributed between the sense node SN, voltage Vsn decreases, and voltages VK1, VK2 increase. At this time, voltages Vsn, VK1, VK2 become approximately equal. Voltage Vsn is determined by the ratio (CK1+CK2/(CK1+CK2+Ca)) of capacitances CK1, CK2 of capacitors CPk1, CPk2 (capacity of the cathodes of photodiodes PD1, PD2) to capacitance Ca of capacitor CPa (capacity of sense node SN).

The counter circuit 16 counts the rising edges of the light detection pulse PLS.

The subsequent recharging operations from t14 to t17 can be the same as those from t4 to t7 in Figure 15.

After the capacitors CPk1 and CPk2 and the sense node SN are recharged, at t17, the control signals CLIP1 and CLIP2 rise, and the transistors Tclip1 and Tclip2 become non-conductive. This returns to the state before t11. The control signals CLIP1 and CLIP2 are synchronized and periodically repeat high and low.

In this way, in the high illuminance mode, even if only one of the two photodiodes PD1 and PD2 detects a photon, a light detection pulse PLS is not generated and the counter circuit 16 does not increase the count value. On the other hand, when both of the two photodiodes PD1 and PD2 detect a photon, a light detection pulse PLS is generated and the counter circuit 16 counts the light detection pulses PLS.

In this way, in the fourth embodiment, when both of the two photodiodes PD1 and PD2 detect a photon, the counter circuit 16 increases the count value by 1, so that the count value of the counter circuit 16 can be reduced. In other words, when the photodiodes PD1 and PD2 detect a total of two photons, the counter circuit 16 increases the count value by 1. As a result, the fourth embodiment can obtain the same effect as the third embodiment.

If the number of photodiodes PD connected in parallel to one counter circuit 16 (one sense node SN) is n, the counter circuit 16 can increase the count value by 1 each time n photodiodes PD break down (each time n photons are detected) in the high illuminance mode. This allows the count value of the counter circuit 16 to be further reduced.

In order for the counter circuit 16 to count one for each detection of one photon using either of the two photodiodes PD1 and PD2, Ca, Ck1, and Ck2 are set to satisfy formulas 10 and 11. In order for the counter circuit 16 to count one when both of the two photodiodes PD1 and PD2 detect one photon each, Ca, Ck1, and Ck2 are set to satisfy formulas 12 to 14. Note that Vth is the threshold voltage of the inverter INV6. ΔVK1 is the amount of change in the cathode voltage VK1 before and after the breakdown of the photodiode PD1. ΔVK2 is the amount of change in the cathode voltage VK2 before and after the breakdown of the photodiode PD2.
Ca<Ck1(ΔVk1−Vth)/Vth (Equation 10)
Ca<Ck2(ΔVk2−Vth)/Vth (Equation 11)
Ca+Cv>Ck1(ΔVk1−Vth)/Vth (Equation 12)
Ca+Cv>Ck2(ΔVk2−Vth)/Vth (Equation 13)
Ca+Cv<Ck1(ΔVk1−Vth)/Vth+Ck2(ΔVk2−Vth)/Vth (Equation 14)

The rest of the configuration of the fourth embodiment may be the same as that of the third embodiment. Therefore, the fourth embodiment can achieve the same effects as the third embodiment.

Fifth Embodiment
18 is a block diagram showing an example of the internal configuration of a pixel P according to the fifth embodiment. In the fifth embodiment, the transistor Trch and the switch SW1 are controlled by a vertical selection circuit 30 or a control circuit 70 outside the pixel P. Therefore, switching between the low illuminance mode and the high illuminance mode, and the timing of charging the capacitors CPk1, Ca (and Cv) are controlled by external control signals XRCG and XSW. The other configurations of the fifth embodiment may be similar to those of the second embodiment.

In the fifth embodiment, the timing of charging the capacitors CPk1, Ca (and Cv) can be set arbitrarily, regardless of the light detection pulse PLS. In other words, the charging period of the capacitors CPk1, Ca (and Cv) can be set arbitrarily. The light detection device 100 can detect that a predetermined number n of photons are incident on the photodiode PD during the arbitrarily set charging period of the capacitors CPk1, Ca.

For example, in low illuminance mode, the charging period is set long to increase sensitivity, and in high illuminance mode, the charging period is set short to suppress saturation. Furthermore, when a predetermined number n of photons are incident on the photodiode PD, the counter circuit 16 can increase the count value by 1. This allows the photodetector 100 to expand the dynamic range and improve the SNR while suppressing an increase in the count value. Other operations of the fifth embodiment may be similar to those of the second embodiment.

Figure 19 is a timing diagram showing an example of the operation of the photodetector according to the fifth embodiment. In Figure 19, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is Ca, which is relatively small. Figure 19 shows the operation in the low illuminance mode.

In the fifth embodiment, the vertical selection circuit 30 causes the control signal XRCG to fall with a period CLK, and charges the capacitors CPk1 and Ca via the transistors Trch with a period CLK.

When a photon is incident on the photodiode PD at t1 between the charging of the capacitors CPk1 and Ca and the next charging, the photodiode PD undergoes avalanche breakdown, causing the cathode voltage VK1 and the voltage Vsn of the sense node SN to decrease. At this time, the operation of the pixel P from t1 to t5 may be the same as that of the second embodiment. However, the light detection pulse PLS is not fed back to the gate of the transistor Trch.

As a result, when one photon is incident on the photodiode PD within the period of the cycle CLK, the counter circuit 16 increases the count value by 1. In other words, the counter circuit 16 can detect photons that are incident on the photodiode PD for each cycle CLK.

Figure 20 is a timing diagram showing an example of the operation of the photodetector according to the fifth embodiment. In Figure 20, the switch SW1 is in a conductive state, and the capacitance of the sense node SN is relatively large, (Ca + Cv). Figure 20 shows the case where one photon is incident on the photodiode PD during operation in high illuminance mode.

The operation of pixel P from t11 to t12 may be the same as that of the second embodiment. When a photon is incident on the photodiode PD at t11, the photodiode PD undergoes avalanche breakdown, and the cathode voltage VK1 drops. However, since the voltage Vsn of the sense node SN does not fall below the threshold Vt12, the light detection pulse PLS is not generated. Therefore, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

If the second photon does not enter, the control signal XRCG falls in the next charging operation from t15 to t17, and the capacitors CPk1 and Ca are recharged via the transistor Trch. This resets them to the state of t11.

In the high-illuminance mode, when two photons are incident within the period of the cycle CLK, the operation of the fifth embodiment may be the same as that of the second embodiment shown in FIG. 9. Therefore, the fifth embodiment can obtain the same effect as the second embodiment. Also, in the fifth embodiment, in the low-illuminance mode, the charging cycle CLK is set long to increase sensitivity, and in the high-illuminance mode, the charging cycle CLK is set short to suppress saturation. This allows the photodetector 100 to expand the dynamic range and improve the SNR while suppressing an increase in the count value.

Figure 21 is a conceptual diagram showing charging periods CLK1 and CLK2 in the fifth embodiment. In the fifth embodiment, a single exposure period of the photodiode PD may include multiple charging periods CLK1 and CLK2. For example, charging period CLK1 is shorter than charging period CLK2 and is suitable for a high-illuminance mode in which the count value is increased when multiple photons are detected. On the other hand, charging period CLK2 is longer than charging period CLK1 and is suitable for a low-illuminance mode in which the count value is increased when one photon is detected. This allows the photodetector 100 to expand the dynamic range and improve the SNR while suppressing an increase in the count value.

Figure 22 is a graph showing the relationship between the photon incidence rate and the count value. The charging cycle CLK1 is used in the high illuminance mode, and the count value is increased when multiple photons are detected. In the high illuminance mode, the switch SW1 is in a conductive state. The charging cycle CLK2 is used in the low illuminance mode, and the count value is increased when one photon is detected. In the low illuminance mode, the switch SW1 is in a conductive state. Therefore, when the photon incidence rate is small, the charging cycle CLK2 is used, and when the photon incidence rate is large, the charging cycle CLK1 is used.

The total count value TTL is the sum of the count value of charging period CLK1 and the count value of charging period CLK2.

In the low-illuminance mode, the counter circuit 16 applies a charging cycle CLK2 and the switch SW1 is in a non-conducting state, so that the counter circuit 16 increases the count value for each photon. This makes it possible to increase the SNR in the low-illuminance mode. On the other hand, in the high-illuminance mode, the counter circuit 16 applies a charging cycle CLK1 and the switch SW1 is in a conducting state, so that the counter circuit 16 increases the count value for each set of photons. This makes it possible to keep the total count value TTL low. This suppresses saturation of the count value in the high-illuminance mode, leading to an increase in the dynamic range.

23 is a graph showing the relationship between the photon incidence rate and the SNR. The SNR is proportional to N/N ^1/2 , where N is the number of photons detected by the photodiode PD.

In the low-illuminance mode, the counter circuit 16 increases the count value for each photon. In the high-illuminance mode, the counter circuit 16 increases the count value for each set of photons. This allows the counter circuit 16 to accurately count many photons by increasing the count value for each set of photons. Therefore, the SNR can be maintained high even in the high-illuminance mode.

Sixth Embodiment
FIG. 24 is a block diagram showing an example of the internal configuration of a pixel P according to the sixth embodiment. In the sixth embodiment, the transistor Trch and the switch SW1 are controlled by the vertical selection circuit 30 or the control circuit 70 outside the pixel P. Therefore, the switching between the low illuminance mode and the high illuminance mode, and the timing of charging the capacitors CPk1, Ca (and Cv) are controlled by the control signals XRCG and XSW from the outside of the counter circuit 16 and the count control circuit 14. The other configurations of the sixth embodiment may be the same as those of the third embodiment. That is, the sixth embodiment is a combination of the third embodiment and the fifth embodiment. Therefore, the sixth embodiment can obtain the same effects as those of the third and fifth embodiments.

Figure 25 is a timing diagram showing an example of the operation of the photodetector according to the sixth embodiment. In Figure 25, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is Ca, which is relatively small. Figure 25 shows the operation in the low illuminance mode.

In the sixth embodiment, the vertical selection circuit 30 causes the control signal XRCG to fall with a period CLK, and charges the capacitors CPk1 and Ca via the transistors Trch.

When a photon is incident on the photodiode PD at t1 between the charging of the capacitors CPk1 and Ca and the next charging, the photodiode PD undergoes avalanche breakdown and the cathode voltage VK1 drops. At this time, the control signal CLIP is rising, so the transistor Tclip is in a non-conductive state and the voltage Vsn of the sense node SN is maintained in a charged state.

After the signal CLIP falls, the operation of pixel P from t2 to t7 may be the same as that in the third embodiment. However, the light detection pulse PLS is not fed back to the gate of transistor Trch. At t4, when the control signal XRCG falls periodically, capacitors CPk1 and Ca are recharged via transistor Trch.

As a result, when one photon is incident on the photodiode PD within the period of the cycle CLK, the counter circuit 16 increases the count value by 1. In other words, the counter circuit 16 can detect photons that are incident on the photodiode PD for each cycle CLK.

Figure 26 is a timing diagram showing an example of the operation of the photodetector according to the sixth embodiment. In Figure 26, the switch SW1 is in a conductive state, and the capacitance of the sense node SN is relatively large (Ca+Cv). Figure 26 shows a case in which one photon is incident on the photodiode PD during operation in high illuminance mode.

The operation of pixel P from t11 to t14 may be the same as that of the third embodiment. When a photon is incident on the photodiode PD at t11, the photodiode PD undergoes avalanche breakdown, and the cathode voltage VK1 drops. However, even if the control signal CLIP falls and the transistor Tclip becomes conductive, the voltage Vsn of the sense node SN does not fall below the threshold Vt12, so the light detection pulse PLS is not generated. Therefore, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

If the second photon is not incident, at t16, the control signal CLIP falls, but the voltage Vsn remains almost unchanged. From t18 to t20, the control signal XRCG falls in the next charging operation, recharging the capacitors CPk1, Ca, and Cv via the transistor Trch. At t12, the control signal CLIP rises. This resets the state to that of t11.

In the high-illuminance mode, when two photons are incident within the period of the cycle CLK, the operation of the sixth embodiment may be the same as that of the third embodiment shown in FIG. 12. Therefore, the sixth embodiment can obtain the same effect as the third embodiment. Also, in the sixth embodiment, in the low-illuminance mode, the charging cycle CLK is set long to increase sensitivity, and in the high-illuminance mode, the charging cycle CLK is set short to suppress saturation. This allows the photodetector 100 to expand the dynamic range and improve the SNR while suppressing an increase in the count value.

Seventh Embodiment
FIG. 27 is a block diagram showing an example of the internal configuration of a pixel P according to the seventh embodiment. In the seventh embodiment, the transistor Trch and the switch SW1 are controlled by a vertical selection circuit 30 or a control circuit 70 outside the pixel P. Therefore, the switching between the low illuminance mode and the high illuminance mode, and the timing of charging the capacitors CPk1, Ca (and Cv) are controlled by control signals XRCG and XSW from the outside. The other configurations of the seventh embodiment may be similar to those of the fourth embodiment. That is, the seventh embodiment is a combination of the fourth and fifth embodiments. Therefore, the seventh embodiment can obtain the same effects as those of the fourth and fifth embodiments.

Figures 28 and 29 are timing diagrams showing an example of the operation of the photodetector according to the seventh embodiment. In Figures 28 and 29, the switch SW1 is in a non-conducting state, and the capacitance of the sense node SN is a relatively small value Ca. Figures 28 and 29 show the operation in the low illuminance mode. Figure 28 shows the operation when one photodiode PD1 detects photons. Figure 29 shows the operation when both photodiodes PD1 and PD2 detect photons.

The operations up to t1 and t1a in Figures 28 and 29 are basically the same as those in the second embodiment. At this time, the capacitors CPk1, CPk2, and Ca are in a charged state. In this state, the photodiodes PD1 and PD2 wait for the incidence of photons. Note that the transistors Tclip1 and Tclip2 are in a non-conducting state with a reverse bias voltage applied to the photodiodes PD1 and PD2.

(Photons incident only on PD1)
As shown in FIG. 28, in the seventh embodiment, the vertical selection circuit 30 causes the control signal XRCG to fall with a period CLK to charge the capacitors CPk1, CPk2, and Ca via the transistors Trch.

When a photon is incident on the photodiode PD1 at t1 between the charging of the capacitors CPk1, CPk2, and Ca and the next charging, the photodiode PD1 undergoes avalanche breakdown and the cathode voltage VK1 drops. At this time, the control signal CLIP1 is rising, so the transistor Tclip1 is in a non-conductive state and the voltage Vsn of the sense node SN is maintained in a charged state.

After the signals CLIP1 and CLIP2 fall, the operation of pixel P from t2 to t7 may be the same as that of the fourth embodiment. However, the light detection pulse PLS is not fed back to the gate of transistor Trch. At t4, when the control signal XRCG falls periodically, capacitors CPk1, CPk2, and Ca are recharged via transistor Trch.

As a result, when one photon is incident on the photodiode PD1 within the period of the cycle CLK, the counter circuit 16 increases the count value by 1. In other words, the counter circuit 16 can detect photons that are incident on the photodiode PD for each cycle CLK.

The operation of the photodetector 100 when photons are incident only on the photodiode PD2 can be easily understood by referring to FIG. 14, so a description thereof will be omitted.

(Photons incident on both PD1 and PD2)
29, when photons are incident on both the photodiodes PD1 and PD2 at times t1a and t1b, the photodiodes PD1 and PD2 undergo avalanche breakdown, and the cathode voltages VK1 and VK2 both drop. At this time, the transistors Tclip1 and Tclip2 are in a non-conductive state, so the voltage Vsn of the sense node SN does not drop.

After the signals CLIP1 and CLIP2 fall, the operation of pixel P from t2 to t7 may be the same as that of the fourth embodiment. However, the light detection pulse PLS is not fed back to the gate of transistor Trch. At t4, when the control signal XRCG falls periodically, capacitors CPk1, CPk2, and Ca are recharged via transistor Trch.

As a result, when a photon is incident on each of the photodiodes PD1 and PD2 within the period of the cycle CLK, the counter circuit 16 increases the count value by 1. In other words, the counter circuit 16 can detect two photons that are incident on the photodiodes PD1 and PD2 for each cycle CLK.

Figures 30 and 31 are timing diagrams showing an example of the operation of the photodetector according to the seventh embodiment. In Figures 30 and 31, the switch SW1 is in a conductive state, and the capacitance of the sense node SN is relatively large at (Ca+Cv). Figures 30 and 31 show the operation in the high illuminance mode. Figure 30 shows the operation when one photodiode PD1 is detecting photons. Figure 31 shows the operation when both photodiodes PD1 and PD2 are detecting photons.

The operation up to t11 in Figures 30 and 31 is basically the same as in the second embodiment. At this time, the capacitors CPk1, CPk2, and Ca are in a charged state. In this state, the photodiodes PD1 and PD2 wait for the incidence of photons. Note that the transistors Tclip1 and Tclip2 are in a non-conductive state with a reverse bias voltage applied to the photodiodes PD1 and PD2.

(Photons incident only on PD1)
As shown in FIG. 30, in the seventh embodiment, the vertical selection circuit 30 causes the control signal XRCG to fall with a period CLK to charge the capacitors CPk1, CPk2, Ca, and Cv via the transistors Trch.

At time t11 between the charging of capacitors CPk1, CPk2, Ca, and Cv, a photon is incident on photodiode PD1, causing avalanche breakdown of photodiode PD1 and a drop in cathode voltage VK1. At this time, because control signal CLIP1 is rising, transistor Tclip1 is in a non-conductive state and voltage Vsn of sense node SN is maintained in a charged state.

After the signals CLIP1 and CLIP2 fall, the operation of pixel P from t12 to t14 may be the same as that of the fourth embodiment. That is, because switch SW1 is in a conductive state, the voltage Vsn of the sense node SN does not fall below the threshold Vt12, as in the fourth embodiment. Therefore, the counter circuit 16 does not count even if one photon is incident on the photodiode PD.

However, the light detection pulse PLS is not fed back to the gate of the transistor Trch. At t14, when the control signal XRCG falls periodically, the capacitors CPk1, CPk2, Ca, and Cv are recharged via the transistor Trch. This returns the light detection device 100 to the state it was in before t11.

(Photons incident on both PD1 and PD2)
31, when photons are incident on both the photodiodes PD1 and PD2 at times t11a and t11b, the photodiodes PD1 and PD2 undergo avalanche breakdown, and the cathode voltages VK1 and VK2 both drop. At this time, the transistors Tclip1 and Tclip2 are in a non-conductive state, so the voltage Vsn of the sense node SN does not drop.

After the signals CLIP1 and CLIP2 fall, the operation of pixel P from t12 to t17 may be the same as that of the fourth embodiment. However, the light detection pulse PLS is not fed back to the gate of transistor Trch. At t14, when the control signal XRCG falls periodically, capacitors CPk1, CPk2, Ca, and Cv are recharged via transistor Trch.

As a result, when a photon is incident on each of the photodiodes PD1 and PD2 within the period of the cycle CLK, the counter circuit 16 increases the count value by 1. In other words, the counter circuit 16 can detect two photons that are incident on the photodiodes PD1 and PD2 for each cycle CLK.

In the high-illuminance mode, when two photons are incident within the period of the cycle CLK, the operation of the seventh embodiment may be the same as the operation of the fourth embodiment shown in FIG. 15 or FIG. 17. Therefore, the seventh embodiment can obtain the same effect as the fourth embodiment. Also, in the seventh embodiment, in the low-illuminance mode, the charging cycle CLK is set long to increase sensitivity, and in the high-illuminance mode, the charging cycle CLK is set short to suppress saturation. This allows the photodetector 100 to expand the dynamic range and improve the SNR while suppressing an increase in the count value.

Eighth embodiment
32 is a block diagram showing an example of the internal configuration of a pixel P according to the eighth embodiment. In the eighth embodiment, the photodiode PD is a dynamic photo diode (DPD). The number of incident photons at the time of breakdown of the DPD changes depending on the forward bias voltage. The anode of the photodiode PD is connected to the sense node SN. The cathode of the photodiode PD is connected to a reference voltage source (e.g., ground).

The power supply circuit 114 applies a forward bias voltage to the photodiode PD. The power supply circuit 114 is connected between the voltage source VDDH and the resistive element RK. The power supply circuit 114 can change the forward bias voltage applied to the photodiode PD upon receiving a feedback signal from the count control circuit 14.

In the eighth embodiment, the count control circuit 14 may be a wire connected between the counter circuit 16 and the power supply circuit 114. When a predetermined bit of the counter circuit 16 is inverted, the count control circuit 14 inverts the control signal fed back to the power supply circuit 114 to change the voltage of the power supply circuit 114. For example, when the count value is less than a predetermined value, the count control unit 14 keeps the control signal low and sets the forward bias voltage to a first voltage. When the count value becomes equal to or greater than the predetermined value, the count control unit 14 raises the control signal and sets the forward bias voltage to a second voltage smaller than the first voltage.

The resistive element RK is connected between the count control circuit 14 and the anode (sense node SN) of the photodiode PD. As a result, the voltage Vsn of the sense node SN changes due to the breakdown of the photodiode PD caused by the incidence of light. The counter circuit 16 counts the light detection pulses PLS generated by the breakdown of the photodiode PD. The count control unit 14 controls the forward bias voltage from the power supply circuit according to the count value of the counter circuit 16.

In the eighth embodiment, the capacitor CPv and the switch SW1 are not provided. The control signal fed back from the counter circuit 16 is applied to the power supply circuit 114. When the count value of the counter circuit 16 is less than a predetermined value, the count control circuit 14 makes the voltage of the power supply circuit 114 applied to the anode of the photodiode PD relatively high, making the forward bias voltage relatively large. As a result, the photodiode PD breaks down every time one photon is incident, and the inverter INV6 generates a light detection pulse PLS. In this case, the counter circuit 16 increases the count value by 1 every time one photon is detected.

When the count value of the counter circuit 16 exceeds a predetermined value, the count control circuit 14 makes the voltage of the power supply circuit 114 applied to the anode of the photodiode PD relatively low, making the forward bias voltage relatively small. As a result, the photodiode PD breaks down every time n (n is an integer equal to or greater than 2) photons are incident on it, and the inverter INV6 generates a light detection pulse PLS. In this case, the counter circuit 16 increases the count value every time the photodiode PD breaks down, but in effect, increases the count value by 1 every time n photons are detected.

In this way, by using DPD for the photodiode PD and using the count control circuit 14 and the power supply circuit 114, it is possible to switch the number of photons that increases the count value between the low illumination mode and the high illumination mode. Therefore, the eighth embodiment can achieve the same effects as the other embodiments.

Furthermore, according to the eighth embodiment, in the high illuminance mode, the number of breakdowns of the photodiode PD and the number of times the light detection pulse PLS is generated are reduced. Therefore, power consumption can be reduced.

Ninth embodiment
33 is a block diagram showing a part of an internal configuration example of a pixel P according to the ninth embodiment. In the ninth embodiment, the positional relationship between the photodiode PD and the transistor Trch is reversed from that in the third embodiment. That is, the anode of the photodiode PD is connected to the voltage source VDDH, and the cathode of the photodiode PD is connected to the drain of the transistor Tclip. The capacitor CPk1 is connected in parallel to the photodiode PD. Therefore, one end of the capacitor CPk1 is connected to the voltage source VDDH, and the other end is connected to the drain of the transistor Tclip.

The source of transistor Tclip is connected to the sense node SN and the drain of transistor Trch. Transistor Tclip is, for example, configured as an n-type MOSFET.

The drain of the transistor Trch is connected to the sense node SN and the source of the transistor Tclip. The drain of the transistor Trch is connected to a reference voltage source (e.g., ground). The transistor Trch is, for example, configured as an n-type MOSFET.

Other configurations of the ninth embodiment may be the same as those of the third embodiment. The conductivity types of the transistors Tclip and Trch are the opposite conductivity types to those of the third embodiment. Therefore, the control signals CLIP and XRCG of the transistors Tclip and Trch have the opposite logic to those of the third embodiment.

Even with the configuration of the ninth embodiment, it operates in the same way as the third embodiment, and can obtain the same effects as the third embodiment. A resistive element RK may be provided between the sense node SN and the photodiode PD instead of the transistor Tclip. The ninth embodiment can also be applied to other embodiments.

(Chip stacking)
34A and 34B are schematic diagrams showing an example of a chip stacking configuration of the photodetector 100. The semiconductor chip 112 is, for example, a stacked chip of an upper substrate 112a and a lower substrate 112b. For example, the upper substrate 112a is provided with a pixel region 10 in which pixels P are two-dimensionally arranged, and a control circuit 122 that controls the pixels P. The control circuit 122 includes all or part of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, the output circuit 60, and the control circuit 70. The lower substrate 112b is provided with a logic circuit 123 such as a signal processing circuit that processes pixel signals output from the pixels. Alternatively, as shown in FIG. 34B, only the pixel region 10 may be provided on the upper substrate 112a, and the control circuit 122 and the logic circuit 123 may be provided on the lower substrate 112b.

In this way, the semiconductor chip 112 may have one or both of the control circuit 122 and the logic circuit 123 provided on a lower substrate 112b separate from the upper substrate 112a of the pixel region 10. This allows the chip size to be smaller than when the pixel region 10, the control circuit 122, and the logic circuit 123 are arranged in a planar direction on a single substrate.

Furthermore, the pixel region 10 may be formed as multiple semiconductor chips that are then stacked together. In this case, the chip size can be further reduced.

The upper substrate 112a and the lower substrate 112b may be connected to each other by through electrodes, or the wiring may be connected to each other by Cu-Cu bonding.

(Example of application to moving objects)
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

Figure 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 35, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (Interface) 12053.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device for generating a drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.

The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020. The body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

The microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

The microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

The microcomputer 12051 can also output control commands to the body system control unit 12030 based on information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.

The audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to the occupants of the vehicle or to the outside of the vehicle. In the example of FIG. 35, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

Figure 36 shows an example of the installation position of the imaging unit 12031.

In FIG. 36, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

In addition, FIG. 36 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer 12051 can obtain the distance to each solid object within the imaging range 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on the driver's operation.

For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

An example of a vehicle control system to which the technology disclosed herein can be applied has been described above. The technology disclosed herein can be applied to, for example, the imaging unit 12031 of the configuration described above.

The present technology can be configured as follows.
(1)
A first photodiode;
a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light;
a counter that counts the number of breakdowns of the first photodiode based on the voltage of the sense node;
a count control unit that controls the number of yields to increase the count value by 1 in accordance with the count value of the counter.
(2)
The photodetector according to (1), wherein the count control section includes a first capacitor and a switch connected in series between the sense node and a reference voltage source.
(3)
The photodetector according to (2), wherein the switch is in a non-conductive state when the count value is less than a predetermined value, and is in a conductive state when the count value is equal to or greater than the predetermined value.
(4)
When the switch is in a non-conductive state, the counter increments the count value by one each time the first photodiode breaks down;
The photodetection device according to claim 3, wherein, when the switch is in a conductive state, the counter increases the count value by 1 every time the first photodiode breaks down n times (n is an integer equal to or greater than 2).
(5)
a first transistor between a voltage source and the sense node, the first transistor being controlled by a breakdown of the photodiode;
a second transistor provided between the first transistor and the sense node, the second transistor being controlled by breakdown of the photodiode with a delay relative to the first transistor;
The photodetection device according to any one of (1) to (4), further comprising: a second capacitor connected between a node between the first transistor and the second transistor and a reference voltage source.
(6)
The photodetection device according to (5), wherein the count control unit controls the value of n based on a ratio between a capacitance of the sense node and a capacitance of a node between the first transistor and the second transistor.
(7)
Further comprising a pixel area in which a plurality of pixels are arranged,
The photodetection device according to any one of (1) to (6), wherein each of the plurality of pixels includes the first photodiode, the counter, and the count control unit.
(8)
The photodetector according to any one of (1) to (7), wherein the first photodiode is a single photon avalanche diode (SPAD) that undergoes avalanche breakdown once upon incidence of one photon.
(9)
The photodetector according to (5), wherein the count control unit is connected in parallel to the second capacitor.
(10)
The photodetection device according to any one of (1) to (9), further comprising a second photodiode provided between the sense node and a reference voltage source.
(11)
2. The photodetection device according to claim 1, wherein, in one exposure period of the first photodiode, a cycle for charging the sense node includes a first cycle and a second cycle longer than the first cycle.
(12)
a period for charging the sense node during one exposure period of the first photodiode includes a first period and a second period longer than the first period;
The photodetection device according to any one of (3) to (5), wherein the switch is in a conductive state in the first period and the switch is in a non-conductive state in the second period.
(13)
The photodetector according to (2), wherein the switch is controlled by a signal from outside the counter and the count control circuit.
(14)
a first photodiode in which the number of incident photons at the time of breakdown changes in response to a forward bias voltage;
a power supply circuit that applies the forward bias voltage to the first photodiode;
a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light;
a counter for counting breakdowns of the first photodiode;
a count control unit that controls the forward bias voltage from the power supply circuit in accordance with a count value of the counter.
(15)
The photodetection device of claim 14, wherein the count control unit sets the forward bias voltage to a first voltage when the count value is less than a predetermined value, and sets the forward bias voltage to a second voltage smaller than the first voltage when the count value is equal to or greater than the predetermined value.
(16)
When the forward bias voltage is the first voltage, the first photodiode breaks down for each photon incident thereon;
The photodetector according to claim 15, wherein when the forward bias voltage is the second voltage, the first photodiode breaks down every time n (n is an integer equal to or greater than 2) photons are incident on the first photodiode.

Note that this disclosure is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

P pixel, PD photodiode, 12 pixel control circuit, 14 count control circuit, 16 counter, Trch, Ts, Ta, Trst transistors, INV1 to INV7 inverters, CPs, CPa, CPv, CPk1, CPk2 capacitors

Claims (16)

A first photodiode;
a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light;
a counter that counts the number of breakdowns of the first photodiode based on the voltage of the sense node;
a count control unit that controls the number of yields to increase the count value by 1 in accordance with the count value of the counter. The photodetector according to claim 1, wherein the count control section includes a first capacitor and a switch connected in series between the sense node and a reference voltage source. The photodetector according to claim 2, wherein the switch is in a non-conductive state when the count value is less than a predetermined value, and is in a conductive state when the count value is equal to or greater than the predetermined value. When the switch is in a non-conductive state, the counter increments the count value by one each time the first photodiode breaks down;
4. The photodetector according to claim 3, wherein when the switch is in a conductive state, the counter increases the count value by 1 every time the first photodiode breaks down n times (n is an integer equal to or greater than 2). a first transistor between a voltage source and the sense node, the first transistor being controlled by a breakdown of the first photodiode;
a second transistor provided between the first transistor and the sense node, the second transistor being controlled by breakdown of the first photodiode with a delay from that of the first transistor;
2. The photodetector apparatus of claim 1, further comprising: a second capacitor connected between a node between the first transistor and the second transistor and a reference voltage source. The photodetector according to claim 5, wherein the count control unit controls the value of n based on a ratio between the capacitance of the sense node and the capacitance of a node between the first transistor and the second transistor. Further comprising a pixel area in which a plurality of pixels are arranged,
The photodetection device according to claim 1 , wherein each of the plurality of pixels comprises the first photodiode, the counter, and the count control unit. The optical detection device according to claim 1, wherein the first photodiode is a single photon avalanche diode (SPAD) that undergoes avalanche breakdown once upon incidence of one photon. The photodetector according to claim 5, wherein the count control unit is connected in parallel to the second capacitor. The photodetector device of claim 1, further comprising a second photodiode disposed between the sense node and a reference voltage source. The photodetection device according to claim 1, wherein, during one exposure period of the first photodiode, a period for charging the sense node includes a first period and a second period longer than the first period. a period for charging the sense node during one exposure period of the first photodiode includes a first period and a second period longer than the first period;
4. The photodetector according to claim 3, wherein the switch is in a conductive state in the first period and in a non-conductive state in the second period. The photodetector according to claim 2, wherein the switch is controlled by a signal from outside the counter and the count control unit. a first photodiode in which the number of incident photons at the time of breakdown changes in response to a forward bias voltage;
a power supply circuit that applies the forward bias voltage to the first photodiode;
a sense node whose voltage changes due to breakdown of the first photodiode caused by incidence of light;
a counter for counting breakdowns of the first photodiode;
a count control unit that controls the forward bias voltage from the power supply circuit in accordance with a count value of the counter. The photodetector according to claim 14, wherein the count control unit sets the forward bias voltage to a first voltage when the count value is less than a predetermined value, and sets the forward bias voltage to a second voltage smaller than the first voltage when the count value is equal to or greater than the predetermined value. When the forward bias voltage is the first voltage, the first photodiode breaks down every time one photon is incident thereon;
16. The photodetector according to claim 15, wherein when the forward bias voltage is the second voltage, the first photodiode breaks down every time n (n is an integer of 2 or more) photons are incident on the first photodiode.

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