JP2024050019A - Power semiconductor module and power conversion device - Google Patents

Abstract

[Problem] To provide a power semiconductor module capable of suppressing cracks in an insulating substrate. [Solution] A resin-sealed power semiconductor module 200 that does not have a support member for the insulating substrate, the power semiconductor module 200 includes an insulating substrate 50, a conductor layer pattern 11, a conductor layer pattern 12, and a conductor layer pattern 13, a first semiconductor chip group 31, 32 bonded onto the conductor layer pattern 11, a second semiconductor chip group 33, 34 bonded onto the conductor layer pattern 12, a lead frame 21 that electrically connects the opposite side of the conductor layer pattern 11 to the conductor layer pattern 12, and a lead frame 22 that electrically connects the opposite side of the conductor layer pattern 12 to the conductor layer pattern 13, each of the lead frames being disposed across slits 71, 72 between the conductor layer pattern 11 and the conductor layer pattern 12, and being disposed so that the lead frames are in a single layer in a direction perpendicular to the arrangement surface of the insulating substrate on which each conductor layer pattern is disposed. [Selected Figure] Figure 1

Description

The present invention relates to the structure of a power semiconductor module, and in particular to a technology that is effective when applied to a resin-sealed power semiconductor module that is manufactured without including a base plate or heat sink that serves as a support member for an insulating substrate.

Power semiconductor modules using switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), as well as semiconductor elements such as freewheel diodes, are used for power control and motor control in industrial equipment, electric railway vehicles, automobiles, home appliances, etc. In recent years, the need for power semiconductor modules for vehicle-mounted inverters has increased, especially with the spread of electric vehicles. In order to provide vehicle-mounted inverters at a low price while increasing the power utilization efficiency, power semiconductor modules must achieve low loss while also reducing costs.

There are several options for achieving low-loss characteristics, including the use of new materials such as GaN (gallium nitride) and SiC (silicon carbide) for power semiconductor chips, and the use of new Si (silicon) IGBTs with reverse conductivity. Meanwhile, there are various technological directions for reducing the cost of power semiconductor modules. Costs can also be reduced by replacing the components that make up the module with cheaper ones, or by changing the manufacturing process, such as changing the method of molding the module's exterior from the conventional case method to a molded resin sealing method, which has a lower manufacturing cost. However, in practice, manufacturing bottlenecks arise.

Ceramic substrates are mainly used for insulating substrates, which are one of the components of the module, to ensure their insulating properties. Silicon nitride (SiN) substrates with high toughness and aluminum nitride (AlN) substrates with high thermal conductivity have excellent characteristics but are expensive, which is a dilemma. For power semiconductor modules for vehicle inverters, which are mass-produced in large quantities _, it is desirable to use inexpensive alumina ( _Al2O3 ) substrates, but they have a problem of weak bending strength.

In addition, in order to further reduce costs by introducing resin sealing using transfer molding or potting methods in the process of molding the module's exterior, a module structure that can withstand the shrinkage stress that occurs during the resin cooling and hardening process is required. In other words, even if an inexpensive ceramic substrate with weak bending strength is used, it is important to have technology that can suppress defects such as cracks in the ceramic substrate caused by stress generated during the resin sealing process.

Even in the case of power semiconductor modules that are resin-sealed, problems such as cracks in the ceramic substrate caused by the above-mentioned stress do not become apparent if the module is configured to include support members such as a base plate or heat sink with high mechanical rigidity. However, in on-board inverters that combine multiple small power semiconductor modules to meet the required rated current, a simple configuration in which semiconductor switching elements are mounted on an insulating substrate and then resin-sealed is often used. Therefore, in the manufacturing process for power semiconductor modules, if a base plate or heat sink that serves as a support member for the insulating substrate is not provided, it is necessary to overcome problems caused by stress such as cracks in the ceramic substrate and increase the manufacturing yield.

As background technology in this technical field, there is, for example, technology such as Patent Document 1. Patent Document 1 shows a configuration that makes it possible to reduce surge voltages more than conventional ones. A ceramic substrate is used, and multiple electrode bars are used to connect circuit patterns on the substrate. By arranging the electrode bars in a laminated structure, inductance is reduced and surge voltage is suppressed. Although there is no mention of sealing resin, Figure 1 of Patent Document 1 discloses that a laminated electrode bar structure that can improve rigidity is arranged in the center of the plane of the ceramic substrate.

Patent document 2 also describes that the terminal case 88, which determines the external shape of the semiconductor module 100, is made of a thermosetting resin, and discloses a structure in which a bridging member spans the slits between the wiring patterns on the ceramic substrate in order to improve the thermal balance of multiple semiconductor chips arranged on the substrate.

JP 2004-214452 A International Publication No. 2020/071102

Referring to Figure 1 of the above-mentioned Patent Document 1, the chip arrangement of the IGBTs and diodes that make up the half-bridge circuit and the shapes of the electrode bars 32, 33, and 34 that electrically connect them are shown. It is stated that the multiple electrode bars are arranged close to each other with an insulator between them.

Referring to FIG. 2 of the above-mentioned Patent Document 2, a structure is described in which wiring patterns on a ceramic substrate are connected by a lead frame composed of a chip joint 180, a wiring joint 182, legs 185 and 186, and a bridge 184.

However, when it comes to preventing cracks in ceramic substrates, the above conventional techniques have several problems.

In the configuration of Patent Document 1, assuming that the module outer shape is formed by resin sealing, the electrode bars are overlapped on the flat surface of the ceramic substrate, and it can be easily inferred that the resin thickness must be made thicker in order to seal the entire module. This creates issues such as increased shrinkage stress and rising costs due to the increase in the total amount of resin. Therefore, as mentioned above, it can be said that it is difficult to apply this to on-board inverters, which aim for small, inexpensive power semiconductor modules.

Patent Document 2 also shows that a lead frame including a bridge-like portion straddles the slits that occur between the wiring patterns 164-1 to 164-3, which can be said to be a structure that reinforces the rigidity of the ceramic substrate. However, the arrangement of the lead frame is limited, and for example, no lead frame is arranged in the longest slit in the center of the ceramic substrate. In order to reinforce the rigidity of the ceramic substrate, it is necessary to identify the location where the greatest stress occurs during cooling and hardening after resin sealing and where cracks are likely to occur, and then take measures to do so. Therefore, it is considered difficult to prevent cracks from occurring in the ceramic substrate with the configuration of Patent Document 2, which does not address the long slit in the center of the substrate.

The object of the present invention is to provide a power semiconductor module and a power conversion device using the same that can effectively suppress cracks in the insulating substrate that tend to occur when the sealing resin cools and hardens in a resin-sealed power semiconductor module that does not use a base plate or heat sink as a support member for the insulating substrate.

In order to solve the above problems, the present invention provides a resin-sealed power semiconductor module that does not have a support member for an insulating substrate, comprising an insulating substrate, a first conductor layer pattern disposed on the insulating substrate, a second conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern, a third conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern and the second conductor layer pattern, a first semiconductor chip group having one or more semiconductor chips bonded onto the first conductor layer pattern, and a second semiconductor chip group having one or more semiconductor chips bonded onto the second conductor layer pattern. , a first lead frame electrically connecting the second conductor layer pattern to the side opposite the bonding surface with the first conductor layer pattern of the first semiconductor chip group, and a second lead frame electrically connecting the third conductor layer pattern to the side opposite the bonding surface with the second conductor layer pattern of the second semiconductor chip group, each of the first lead frame and the second lead frame being arranged across the slit between the first conductor layer pattern and the second conductor layer pattern, and being arranged so that the lead frames are in a single layer in a direction perpendicular to the arrangement surface of each conductor layer pattern of the insulating substrate.

The present invention makes it possible to realize a power semiconductor module that can effectively suppress cracks in the insulating substrate that tend to occur when the sealing resin cools and hardens in a resin-sealed power semiconductor module that does not use a base plate or heat sink as a support member for the insulating substrate, and a power conversion device that uses the same.

This allows an alumina (Al ₂ O ₃ ) substrate to be used as the insulating substrate of the power semiconductor module, thereby improving the manufacturing yield and reducing costs of the power semiconductor module, and reducing the cost of the power conversion device.

Problems, configurations, and advantages other than those described above will become clear from the description of the embodiments below.

FIG. 1 is a plan view of a power semiconductor module according to a first embodiment of the present invention. This is a cross-sectional view of A-A' in Figure 1. This is a cross-sectional view of B-B' in Figure 1. FIG. 1 is a plan view of a conventional power semiconductor module. This is a cross-sectional view of C-C' in Figure 4. FIG. 13 is a diagram showing an example of an analysis result of stress in a ceramic substrate. FIG. 7 is a diagram showing an outline of the analysis model in FIG. 6 (conventional example). FIG. 7 is a diagram showing an outline of the analysis model of FIG. 6 (present invention). FIG. 11 is a plan view of a power semiconductor module according to a second embodiment of the present invention. A diagram conceptually showing mutual inductance at the D-D' cross section of Figure 8. FIG. 1 is an outline view of a power semiconductor module according to a first embodiment and a second embodiment of the present invention. FIG. 11 is a block diagram showing a circuit configuration of a power conversion device according to a third embodiment of the present invention. 2 is a diagram conceptually showing mutual inductance at the A-A' cross section of Figure 1. FIG. 2 is an equivalent circuit diagram showing a main circuit inductance path in FIG. 1 . FIG. 9 is an equivalent circuit diagram showing a main circuit inductance path in FIG. 8 .

Below, an embodiment of the present invention will be described with reference to the drawings. Note that in each drawing, the same reference numerals are used to designate the same configuration or configurations having similar functions, and detailed descriptions of overlapping parts will be omitted.

A power semiconductor module according to a first embodiment of the present invention will be described with reference to Figures 1 to 7B and 10. In this embodiment, a module structure is shown that suppresses the occurrence of cracks in the ceramic insulating substrate when the sealing resin cools and hardens in a power semiconductor module that uses a ceramic insulating substrate, and the effect of reducing stress applied to the ceramic insulating substrate is described.

<Overview of the device>
Fig. 1 shows a schematic configuration of a power semiconductor module 200 of this embodiment. It should be noted that in the plan view of Fig. 1, the layout of components in a lower layer that is not visible due to the presence of a sealing resin 60 is shown, for convenience, as a see-through view. Fig. 1 shows a plan view of the power semiconductor module 200 as seen from above, and Figs. 2 and 3 show cross-sectional structural diagrams taken along the section lines A-A' and B-B' shown in the plan view, respectively.

<Plane composition>
1, a power semiconductor module 200 of this embodiment has a half-bridge circuit formed on a single insulating substrate (ceramic substrate) 50. The area of a resin seal 60 indicated by a dotted line indicates the outer shape of the power semiconductor module.

As shown in FIG. 1, the power semiconductor module 200 of this embodiment is a so-called 2-in-1 type power semiconductor module that includes two combinations of IGBT chips and diode chips (reference numbers 31 and 32, and reference numbers 33 and 34), and has three external main terminals 1, 2, and 3.

External main terminal 1 functions as a high-voltage power supply terminal, and external main terminal 3 functions as a low-voltage power supply terminal to supply DC voltage to the half-bridge circuit on the insulating substrate 50, while external main terminal 2 functions as an AC voltage terminal to supply a load current to the outside.

The three external main terminals 1, 2, and 3 are connected to three conductor layer patterns 11, 12, and 13, respectively, that are disposed on an insulating substrate 50 and are electrically insulated from one another.

The conductor layer pattern 11 is disposed in one region of the insulating substrate 50 (the region on the right side of the insulating substrate 50 in FIG. 1) so as to extend along one side of the insulating substrate 50 in the Y direction. The conductor layer pattern 12 is disposed in the other region of the insulating substrate 50 (the region on the left side of the insulating substrate 50 in FIG. 1) so as to extend along the other side of the insulating substrate 50 in the Y direction. A slit 71 is formed between the conductor layer pattern 11 and the conductor layer pattern 12, and the slit 71 separates the conductor layer pattern 11 and the conductor layer pattern 12 and electrically insulates them.

The conductor layer pattern 13 extends along one side of the insulating substrate 50 in the X direction, with a portion of it being disposed in one region of the insulating substrate 50 (the region on the right side of the insulating substrate 50 in FIG. 1) and another portion being disposed in the other region (the region on the left side of the insulating substrate 50 in FIG. 1). A slit 72 is formed between the conductor layer pattern 11 and the conductor layer pattern 12 and the conductor layer pattern 13, and the slit 72 separates the conductor layer pattern 11 and the conductor layer pattern 12 from the conductor layer pattern 13 and electrically insulates them.

The external main terminal 1 is electrically connected to the conductor layer pattern 11 bonded onto the insulating substrate 50. In FIG. 1, an IGBT chip 31 as a semiconductor switching element and a diode chip 32 as a semiconductor diode element are connected in inverse parallel to the conductor layer pattern 11 to form an upper arm circuit. The collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32 are electrically and mechanically connected to the conductor layer pattern 11 via solder and sintered material. The signal terminals 5 and 6 are a gate control terminal and an emitter sense terminal that control the switching of the IGBT chip 31. The terminals connected to the conductor layer patterns 15 and 16 are connected to the gate electrode 303 and the emitter electrode 302 on the IGBT chip 31 via bonding wires 25 and 26, respectively.

The emitter electrode 302 of the IGBT chip 31 and the anode electrode 304 of the diode chip 32 are both electrically and mechanically connected to the conductor layer pattern 12 to which the potential of the AC voltage terminal is applied via the lead frame 21. The connection method is via solder and sintered material, similar to the collector electrode of the IGBT chip 31 and the cathode electrode of the diode chip 32.

The conductor layer pattern 12 is connected to the collector electrode of the IGBT chip 33 and the cathode electrode of the diode chip 34 that constitute the lower arm circuit, as well as to an external main terminal 2 that is an AC voltage terminal. The lead frame 22 connects the emitter electrode 302 of the IGBT chip 33 and the anode electrode 304 of the diode chip 34, and is also connected to the conductor layer pattern 13. As with the upper arm circuit, a signal terminal (gate control terminal) 7 and a signal terminal (emitter sense terminal) 8 control the switching of the IGBT chip 33.

Here, the sintered material is a sintered copper bonding material containing copper nanoparticles formed of a plurality of single crystals having a grain size of 0.1 nm to 10 nm, and a copper oxide layer formed on the surface containing copper oxide. The sintered copper bonding technology uses the copper nanoparticles as a bonding material for a semiconductor chip, and forms a sintered copper bonding layer by sintering the copper nanoparticles together. Copper has a higher fracture resistance than conventional solder and silver, and can extend the fracture life of the bond even when used at high temperatures, for example, at 175°C or higher. In addition, the sintered copper bonding material has high bonding properties with non-precious metals such as copper and nickel, and does not require expensive gold or silver plating films on the electrode material to be bonded, so the cost required for bonding can be reduced.

The feature of the present invention is the arrangement of lead frames 21 and 22 relative to slit 71 that occurs between conductor layer pattern 11 and conductor layer pattern 12. Lead frames 21 and 22 each become L-shaped after extending in the arrangement direction of multiple semiconductor chips (Y direction in FIG. 1), and are shaped to straddle slit 71 at a right angle. Note that the angle is not necessarily limited to a right angle (90°), and may be an approximately right angle or a diagonal shape.

The two chip groups, IGBT chip 31 and diode chip 32, and IGBT chip 33 and diode chip 34, are generally point-symmetrical with respect to the center position of the slit 71, so the two L-shaped lead frames 21 and 22 are also arranged point-symmetrically with respect to the center position of the slit 71, as shown in FIG. 1. The lead frames 21 and 22 form a structure that adds a so-called bridge-type reinforcement structure, and this arrangement makes it possible to shorten the length of the slit 71 from the distance Y1 shown in FIG. 1 to Y2.

<Cross-section structure>
2 and 3 show the module structure at the cross-sectional lines A-A' and B-B' shown in FIG. 1, respectively. In order to make the internal structure of the power semiconductor module 200 easier to understand, some of the components in the depth direction as viewed from the A-A' cross section and the B-B' cross section are also shown. The A-A' cross-sectional view in FIG. 2 shows the positional relationship between the lead frame 21 and the lead frame 22 and the slit 71 and the slit 72. The conductor layer pattern 14 is a conductor layer pattern that is bonded to the lower flat surface of the insulating substrate 50.

The A-A' cross-sectional view in FIG. 2 is viewed from the lead frame 22 toward the lead frame 21, and shows that a bridge structure formed by the semiconductor chips (diode chip 32, IGBT chip 33) and the conductors formed by the lead frames 21, 22 spans the slit 71. Of the external shape of the power semiconductor module 200 formed by the sealing resin 60, the length Z1 shown in the figure is defined as the height of the power semiconductor module 200.

The B-B' cross-sectional view in FIG. 3 shows the cross-sectional configuration of the area where the lead frames 21 and 22 are not placed on the slit 71. The cross-sectional shape of the lead frames 21 and 22 is a two-stage shape with an upper and lower part, and the lower half that connects to each electrode of the semiconductor chip (IGBT chip 31, diode chip 34) is set to a shape that matches the width of the electrodes of the semiconductor chip.

In the power semiconductor module 200 of this embodiment, as shown in FIG. 3, the external shape of the sealing resin 60 is given a characteristic feature to suppress the contraction stress that imposes mechanical stress on the slit 71. Since the lead frame 21 and the lead frame 22 are shaped to surround the center of the insulating substrate 50, the shape of the sealing resin 60 is partially deformed in the central portion where there are no lead frames to provide a recessed shape 61 (width X4) as shown in FIG. 3. The height of the power semiconductor module 200 at the recessed shape 61 is defined as Z1a.

In this way, the structure of this embodiment allows for the placement of a lead frame to reinforce the rigidity across the slits 71 that occur on the insulating substrate 50, while simultaneously making the thickness of the sealing resin 60 thinner in the central part of the substrate where the reinforcement by the lead frame does not reach.

Figure 10 shows an outline diagram of the power semiconductor module 200 after molding. In the center of the figure, there is a recessed shape 61, and its planar shape is rectangular (rectangular). The recessed shape 61 is formed in a substantially rectangular area surrounded by the lead frames 21 and 22. The length X4 of the short side is a value determined by reflecting the distance between the lead frames, but it is preferable to set it to 4 mm or more in order to obtain the effect of thinning. In addition, as an example of the values of the heights Z1 and Z1a of the power semiconductor module 200 described above, Z1 = 5 mm and Z1a = 3 mm, and as a result, the recess height of the recessed shape 61 is the difference of 2 mm. It is preferable that the recess height (depth) of this recessed shape 61 is 2 mm or more.

The external shape of the power semiconductor module 200 shown in FIG. 10 is the same as that of the power semiconductor module 202 of Example 2 (FIG. 8) described later.

The following is an approximate calculation as an example of a quantitative evaluation of stiffness.

It is assumed that an alumina ( _Al2O3 ) substrate is used for the insulating substrate 50, _with a thickness of 0.3 mm and a Young's modulus of 300 GPa. The lead frame is made of copper, with a thickness of 1.5 mm and a Young's modulus of 130 GPa. Since rigidity can be roughly calculated by the product of thickness and Young's modulus, if the alumina substrate and the lead frame were the same width, the rigidity of the copper lead frame would be just over 200% of that of the alumina substrate. However, if we assume that the total width of the lead frame is 40% of the width of the slit 71, which governs the rigidity of the alumina substrate, the increase in rigidity due to the introduction of the lead frame can be roughly calculated as an 80% increase compared to before the introduction.

In addition, since the lead frame exerts its rigidity through the power semiconductor chips (IGBT chips and diode chips) and their bonding material, the selection of the chip type and die bond bonding material is important. It goes without saying that the effect of the present invention will be more pronounced by selecting a bonding method using SiC chips, which have high hardness, instead of Si chips, and sintered copper or sintered silver, which can ensure more than twice the bonding strength instead of solder.

<Example of conventional lead frame configuration>
In order to make the configuration and the effects of this embodiment easier to understand, a configuration example of a conventional power semiconductor module will be described with reference to Figs.

Figure 4 is a plan view of a conventional power semiconductor module 201, and Figure 5 is a cross-sectional view taken along the line C-C' in Figure 4. As with Figures 2 and 3, some of the components in the depth direction as viewed from the C-C' cross section are also shown in order to make it easier to understand the internal structure of the power semiconductor module 201.

The conventional power semiconductor module 201 shown in FIG. 4 illustrates a module configuration that realizes a half-bridge circuit similar to that shown in FIG. 1 on an insulating substrate 50. Although lead frames 21 and 22 are used, the configuration shown is that of a conventional example.

Unlike the configuration of this embodiment (Figure 1), there is no rigid reinforcement structure, and a slit 71 with a length Y3 is generated in the center of the insulating substrate 50. When the sealing resin 60 cools and hardens, stress is generated around the slit 71, and there is a high risk of a crack occurring in the center of the insulating substrate 50.

Qualitative trends based on analysis results
The stress at the center of the insulating substrate 50 will be described with reference to FIGS. 6 to 7B.

Figure 6 shows the results of an analysis of the stress N at the center of the ceramic substrate using a simulator. Figures 7A and 7B are diagrams showing an overview of the analysis model of Figure 6, showing cross-sectional structures that mimic the structure of a conventional example and the structure of the present invention, respectively.

Copper conductor layer patterns 11, 12, and _{14 having a thickness of 0.4 mm were arranged on an insulating substrate (ceramic substrate) 50 assumed to be made of alumina (Al2O3 )} . The observation position of the stress N was the center part of the insulating substrate (ceramic substrate) 50 having a thickness of 0.3 mm, and directly below the slit 71.

Figure 7B, which is a model of the structure of the present invention, shows a configuration in which a copper plate LF equivalent to a lead frame is additionally placed to cover the slit 71. In both Figures 7A and 7B, it is assumed that epoxy resin is placed on the conductor layer patterns 11 and 12 with a thickness T as the sealing resin 60, and Figure 6 shows the dependence of stress N when the T value is changed. Here, T values of 4 mm to 7 mm are used. A realistic T value is about 4 mm, and considering the thickness of the insulating substrate 50 and the conductor layer patterns 11 and 12, the overall thickness of the resin-sealed power semiconductor module is about 5 mm.

In relation to the change in resin thickness T shown on the horizontal axis of Figure 6, in the case of the cross-sectional structure simulating the conventional structure shown in Figure 7A (plotted with ▲ in the figure), it can be seen that stress N does not decrease but remains high even when the resin thickness T becomes thinner. On the other hand, in the cross-sectional structure simulating the structure of the present invention shown in Figure 7B (plotted with ◯ in the figure), it can be seen that stress N itself is lower than in the conventional structure, and that stress N decreases as the resin thickness T becomes thinner.

This tendency qualitatively indicates that the combined measures of adding a lead frame with a structure that reinforces rigidity and partially thinning the resin thickness, as described in this embodiment, are effective. In addition, as shown by the data for the conventional example in Figure 6, it was also found that simply thinning the resin thickness T cannot be expected to have a stress reduction effect. Although the tendency of these analysis results fluctuates depending on the thermal expansion coefficient of the resin and the copper conductive layer pattern and their relationship with their respective thicknesses and is not a constant tendency, it does indicate the effect of the present invention.

As described above, the power semiconductor module of this embodiment is a resin-sealed power semiconductor module that does not have a base plate or a heat sink that serves as a support member for the insulating substrate 50, and includes an insulating substrate 50, a first conductor layer pattern 11 arranged on the insulating substrate 50, a second conductor layer pattern 12 arranged on the insulating substrate 50 and electrically insulated from the first conductor layer pattern 11, a third conductor layer pattern 13 arranged on the insulating substrate 50 and electrically insulated from the first conductor layer pattern 11 and the second conductor layer pattern 12, a first semiconductor chip group (IGBT chip 31, diode chip 32) having one or more semiconductor chips bonded on the first conductor layer pattern 11, and a second semiconductor chip group having one or more semiconductor chips bonded on the second conductor layer pattern 12. The semiconductor device includes a chip group (IGBT chip 33, diode chip 34), a first lead frame 21 that electrically connects the opposite side of the bonding surface with the first conductor layer pattern 11 of the first semiconductor chip group to the second conductor layer pattern 12, and a second lead frame 22 that electrically connects the opposite side of the bonding surface with the second conductor layer pattern 12 of the second semiconductor chip group to the third conductor layer pattern 13. Each of the first lead frame 21 and the second lead frame 22 is arranged across the slit 71 between the first conductor layer pattern 11 and the second conductor layer pattern 12, and is arranged so as not to overlap each other in the direction perpendicular to the arrangement surface of the insulating substrate 50 on which the conductor layer patterns 11, 12, and 13 are arranged, i.e., so that the lead frames 21 and 22 are single-layered.

The slit 71 is also located in the center of the insulating substrate 50 and is the longest of the multiple slits between the conductor layer patterns 11, 12, and 13 formed on the insulating substrate 50.

In addition, the thickness of the sealing resin 60 in the area including at least a portion of the slit 71 is thinner than the thickness of the sealing resin 60 in other areas.

In addition, in a direction perpendicular to the arrangement surface of each conductor layer pattern 11, 12, 13 of the insulating substrate 50, only the sealing resin 60 is arranged on the first lead frame 21 and the second lead frame 22.

This effectively prevents cracks in the insulating substrate 50 that tend to occur when the sealing resin 60 cools and hardens.

The power semiconductor module of the second embodiment of the present invention will be described with reference to Figures 8, 9, 12 to 14. Note that Figures 12 and 13 are figures relating to the first embodiment, and are shown for comparison with this embodiment.

Figure 8 is a plan view of the power semiconductor module 202 of this embodiment. Compared to the configuration of embodiment 1 (Figure 1), the terminal shapes of the external main terminals 1 and 3 and the shape of the conductor layer pattern around them are changed. The shapes of the lead frame 21 and the lead frame 22A relative to the slit 71 are the same as those of embodiment 1 (Figure 1).

The lead frame 22A has an L-shaped frame shape, and is shaped to also function as the external main terminal 3 shown in Example 1 (Figure 1). This shape allows the path from the IGBT chip 33 to the external main terminal 3A to be made of a uniform, thick conductor. For example, the conductor layer patterns 11-13 are copper circuit patterns with a thickness of 0.4 mm. Meanwhile, the lead frames 21 and 22A can use thick copper lead frames regardless of the thickness of the conductor layer patterns 11-13, so the thickness can be set to 1.0 mm to 1.5 mm.

Compared to the external main terminal 1 of Example 1 (Figure 1), the length of the external main terminal 1A on the insulating substrate 50 is extended to the vicinity of the diode chip 32, and the shape passes above the conductor layer pattern 13.

Figure 9 shows a cross-sectional view taken along the line D-D' in Figure 8. By adopting the configuration of this embodiment as described above, the external main terminal 3A (which is also the lead frame 22A) which is a low-voltage power supply terminal can have two features in comparison with the external main terminal 1A which is a high-voltage power supply terminal: (1) they can be arranged in parallel with each other with thick conductor cross-sectional shapes, and (2) there is an area in which they are arranged in parallel with the conductor layer pattern 13 in a plan view. In other words, the external main terminal 1A can be arranged in parallel with the lead frame 22A with thick conductor cross-sectional shapes, and can also be arranged in parallel with the conductor layer pattern 13 over a wide width.

The external main terminal 1A and the external main terminal 3A are wiring paths that constitute the main circuit inductance Ls that affects the switching characteristics of the power semiconductor module 202. Figure 14 shows an equivalent circuit of the main circuit inductance path of the power semiconductor module 202 of this embodiment shown in Figure 8. The external main terminal 1A corresponds to Term 1A in the figure, and the external main terminal 3A corresponds to Term 3A.

Term1A is connected to IGBT chip 31 and diode chip 32 via L1A and L1B, which correspond to the inductance generated at external main terminal 1A. These semiconductor chips are connected to IGBT chip 33 and diode chip 34 via inductance L21, which corresponds to lead frame 21, and are further connected to Term3A via inductances L22A, L22B, and L13, which correspond to lead frame 22A and conductor layer pattern 13, and L3, which indicates the inductance of external main terminal 3A.

The total inductance of the path from Term1A to Term3A is the main circuit inductance Ls, and the smaller this value is, the more the surge voltage during switching can be reduced, thereby reducing switching losses.

From the equivalent circuits shown in Figures 9 and 14, in the configuration of this embodiment, mutual inductances M1-13, M1-22, and M1-3 are generated between the conductor layer pattern 13 and the lead frame 22A (which also serves as the external main terminal 3A) for inductances L1A and L1B. As shown in Figure 9, the currents flowing through the external main terminals 1A and 3A in opposite directions, so mutual inductance M is generated, which has the effect of reducing the value of the main circuit inductance Ls described above. The value of the main circuit inductance Ls is reduced because the sign of mutual inductance M is negative, opposite to the self-inductance of the conductor layer pattern and lead frame that make up Ls.

Here, we will compare the configuration with that of Example 1 (Figure 1) using Figures 12 and 13.

In the cross-sectional structure of Example 1 shown in Figure 12 (cross-section A-A' in Figure 1), a mutual inductance M11-13 occurs between the conductor layer pattern 11 and the laminated structure of the conductor layer pattern 13 and the lead frame 22.

Figure 13 shows an equivalent circuit of the main circuit inductance path of the power semiconductor module 200 of Example 1 (Figure 1). Focusing on the path of the main circuit inductance, in addition to the above-mentioned M11-13, a mutual inductance M1-3 is generated between the conductor layer pattern 13 and the external main terminal 3, in response to the inductances L1 and L11 generated between the external main terminal 1 and the conductor layer pattern 11.

Comparing Example 1 (Fig. 1) and Example 2 (Fig. 8), the lengths of the external main terminals, conductor layer patterns, and lead frames are equivalent, but as can be seen from a comparison of Fig. 13 and Fig. 14, the mutual inductance is different. When comparing the magnitude of the difference in mutual inductance between Example 1 and Example 2, the relationship of formula (1) holds.

|M1-13 + M1-22| > |M11-13| ... (Equation 1)
In other words, by arranging the external main terminals 1 and 3 and the surrounding conductor layer patterns and lead frames as shown in the present embodiment (FIG. 8) rather than as shown in the embodiment 1 (FIG. 1), the value of the mutual inductance that affects the main circuit inductance Ls can be increased, and therefore, in the present embodiment, it is possible to keep the main circuit inductance Ls smaller than in the embodiment 1.

As described above, the power semiconductor module of this embodiment has an external main terminal 1A electrically connected to the first conductor layer pattern 11, and a portion of the external main terminal 1A is configured to face the second lead frame 22A across the sealing resin 60 on the arrangement surface of each conductor layer pattern 11, 12, and 13 of the insulating substrate 50, and to face the third conductor layer pattern 13 across the sealing resin 60.

In addition, the external main terminal 3A is molded integrally with the second lead frame 22A.

In this embodiment, the main circuit inductance Ls can be reduced by changing the shape of the external main terminal while mitigating stress on the insulating substrate (ceramic substrate) 50.

Therefore, by introducing an insulating substrate such as an alumina ( _Al2O3 ) substrate _, which is inexpensive but has weak bending strength, into a resin-sealed power semiconductor module, the risk of substrate cracking can be reduced and manufacturing can be achieved with a high yield, thereby making it possible to reduce the cost of the power semiconductor module.

In addition, since the main circuit inductance can be reduced, switching losses can be reduced.

The power conversion device of the third embodiment of the present invention will be described with reference to FIG. 11. FIG. 11 is a block diagram showing the circuit configuration of the power conversion device of this embodiment.

Figure 11 shows an example of a three-phase AC motor that drives the axle of an electric vehicle, which is composed of a battery 250, a power conversion device 260, and a load motor 270.

The power conversion device 260 of this embodiment includes three leg circuits for one phase, each of which is configured with a 2-in-1 power semiconductor module 200 or a power semiconductor module 202, a capacitor 240, and a control circuit 230. The power conversion device 260 includes gate drive circuits 210 (210a to 210c) equal to the number of AC phases.

The power conversion device 260 holds the main voltage (Vcc) using the capacitor 240, and the gate drive signals for the semiconductor switching elements in each power semiconductor module 200 (202) generated by the control circuit 230 are input to each power semiconductor module 200 (202) via the gate drive circuits 210a, 210b, and 210c.

Leg circuits 220a, 220b, and 220c respectively constitute a first-phase inverter leg, a second-phase inverter leg, and a third-phase inverter leg. The output of each inverter leg is connected to the electric motor 270.

In this embodiment, leg circuits 220a, 220b, and 220c have the same circuit configuration. Therefore, the circuit configuration will be explained using leg circuit 220a as an example.

The leg circuit 220a includes a pair of upper and lower arms formed by the power semiconductor module 200a (202a) and a gate drive circuit 210a that controls the on/off state of the power semiconductor module 200a (202a).

According to this embodiment, the power semiconductor module described in either embodiment 1 or embodiment 2 is used for the power semiconductor module 200 or power semiconductor module 202 mounted on the power conversion device 260, and the cost of the power conversion device 260 and the electric vehicle motor drive system including the same can be reduced.

In addition, by using the power semiconductor module 202 described in Example 2, the main circuit inductance can be reduced, and therefore the switching loss can be reduced compared to the conventional module configuration.

As a result, the power conversion device 260 and the electric vehicle motor drive system that includes it can be made less expensive and less prone to loss.

The present invention is not limited to the above-described embodiments, but includes various modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those having all of the configurations described. It is also possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

For example, the dimensions and insulation distances of the components constituting power semiconductor module 200 and power semiconductor module 202 may be arbitrary depending on the application.

Furthermore, the chip arrangement of the semiconductor switching elements that constitute the power semiconductor module 200 and the power semiconductor module 202 is not limited to the form shown in the figure.

The power semiconductor module 200 or the power semiconductor module 202 may be a parallel connection of an IGBT and a diode as described in each embodiment, a parallel connection of multiple MOSFET chips, a unipolar device such as a JFET (Junction Field Effect Transistor), or a bipolar device such as a BJT (Bipolar Junction Transistor). Depending on the device, the names of the main terminals and sense terminals may be called "drain" and "source" in addition to the above-mentioned "collector" and "emitter".

The power conversion device 260 using the power semiconductor module 200 or the power semiconductor module 202 can also be used in motor drive systems for electric vehicles, as well as in power conditioning systems (PCSs) in solar power generation systems and railway vehicle electrical systems.

1, 1A...External main terminal (high voltage power supply terminal)
2...External main terminal (AC voltage terminal)
3, 3A...External main terminal (low voltage power supply terminal)
5, 7...Signal terminals (gate control terminals)
6, 8...Signal terminals (emitter sense terminals)
11...Conductor layer pattern (potential of high voltage power supply terminal)
12...Conductor layer pattern (potential of AC voltage terminal)
13...Conductor layer pattern (electric potential of low voltage power supply terminal)
14... Conductive layer pattern 15, 18... Conductive layer patterns (potential of gate voltage terminal)
16, 19...Conductor layer pattern (potential of emitter sense voltage terminal)
21, 22, 22A... Lead frame 25, 27... (for gate wiring) bonding wire 26, 28... (for emitter sense wiring) bonding wire 31, 33... IGBT chip 32, 34... Diode chip 50... Insulating substrate (ceramic substrate)
60... Sealing resin 61... Recess shape (of sealing resin) 71, 72... Slits (between conductor layer patterns) 200, 201, 202... Power semiconductor module 210, 210a to 210c... Gate drive circuit 220, 220a to 220c... Leg circuit 230... Control circuit 240... Capacitor 250... Battery 260... Power conversion device 270... Motor 301... Collector electrode 302... Emitter electrode 303... Gate electrode 304... Anode electrode 305... Cathode electrode X1, X4, Y1, Y2, Y3, Y4... Distance T... Thickness of sealing resin

Claims (12)

A resin-sealed power semiconductor module that does not have a support member for an insulating substrate,
An insulating substrate;
a first conductor layer pattern disposed on the insulating substrate;
a second conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern;
a third conductor layer pattern disposed on the insulating substrate and electrically insulated from the first conductor layer pattern and the second conductor layer pattern;
a first semiconductor chip group having one or more semiconductor chips bonded onto the first conductor layer pattern;
a second semiconductor chip group having one or more semiconductor chips bonded onto the second conductor layer pattern;
a first lead frame electrically connecting a surface of the first semiconductor chip group opposite to a surface to be bonded to the first conductor layer pattern and the second conductor layer pattern;
a second lead frame electrically connecting a surface of the second semiconductor chip group opposite to a bonding surface with the second conductor layer pattern to the third conductor layer pattern,
A power semiconductor module characterized in that each of the first lead frame and the second lead frame is arranged across a slit between the first conductor layer pattern and the second conductor layer pattern, and the lead frames are arranged in a single layer in a direction perpendicular to the arrangement surface of the insulating substrate on which each conductor layer pattern is arranged. 2. The power semiconductor module according to claim 1,
A power semiconductor module, characterized in that the first lead frame and the second lead frame do not overlap each other in a direction perpendicular to a surface of the insulating substrate on which the conductor layer patterns are arranged. 2. The power semiconductor module according to claim 1,
the slit is disposed in a central portion of the insulating substrate,
A power semiconductor module, characterized in that among a plurality of slits between the respective conductor layer patterns formed on the insulating substrate, the slit has the longest length. 4. The power semiconductor module according to claim 3,
a sealing resin that seals the insulating substrate, the first semiconductor chip group, the second semiconductor chip group, the first lead frame, and the second lead frame;
A power semiconductor module, characterized in that the thickness of the sealing resin in a region including at least a portion of the slit is thinner than the thickness of the sealing resin in other regions. 2. The power semiconductor module according to claim 1,
A power semiconductor module, characterized in that in a direction perpendicular to the arrangement surface of the insulating substrate on which each of the conductor layer patterns is arranged, only a sealing resin is arranged on the first lead frame and the second lead frame. 5. The power semiconductor module according to claim 4,
the sealing resin has a recess on a surface thereof;
The recess is an area where the sealing resin is thin, and has a depth of 2 mm or more. 5. The power semiconductor module according to claim 4,
the sealing resin has a recess on a surface thereof;
The recess is a region where the sealing resin is thin, and is a rectangular shape with a short side of 4 mm or more when the power semiconductor module is viewed in a plan view. 2. The power semiconductor module according to claim 1,
an external terminal electrically connected to the first conductor layer pattern;
a portion of the external terminal facing the second lead frame across a sealing resin, and facing the third conductor layer pattern across a sealing resin, on a placement surface of the insulating substrate on which each conductor layer pattern is arranged. 2. The power semiconductor module according to claim 1,
The power semiconductor module, wherein the insulating substrate is a ceramic substrate containing alumina (Al ₂ O ₃ ) as a main component. 2. The power semiconductor module according to claim 1,
a bonding or connection between the first semiconductor chip group and the first conductor layer pattern, the connection between the first semiconductor chip group and the first lead frame, the bonding between the second semiconductor chip group and the second conductor layer pattern, and the connection between the second semiconductor chip group and the second lead frame, wherein at least one of these is a bonding or connection made by sintered copper. 2. The power semiconductor module according to claim 1,
a first external terminal electrically connected to the first conductor layer pattern;
a second external terminal electrically connected to the third conductor layer pattern;
The power semiconductor module, wherein the second external terminal is molded integrally with the second lead frame. A main circuit having one or more pairs of upper and lower arms;
A drive circuit for driving the upper and lower arms,
A power conversion device using the power semiconductor module according to claim 1 in the upper and lower arms.

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