JP2024047766A - Electro-optical devices and electronic equipment - Google Patents

Abstract

[Problem] To suppress the intrusion of incident light into a semiconductor layer and reduce flicker caused by off-leakage. [Solution] A wiring 124b electrically connected to a source region of a semiconductor layer 131 has a protruding portion 124ba protruding along the X-axis in a plan view, a wiring 124a is electrically connected to a drain region, and has a gap Ap1 between the wiring 124a and the protruding portion 124ba in a region overlapping with an LDD region 133b in a plan view, and a wiring 125a is electrically connected to the wiring 124a and covers the gap Ap1 in a plan view. [Selected Figure] FIG.

Description

The present invention relates to an electro-optical device and an electronic device.

For example, in an electro-optical device that uses liquid crystal elements as display elements, liquid crystal is sandwiched between a pair of substrates that are spaced apart by a fixed distance. In more detail, pixel electrodes are arranged in a matrix on one of the substrates, the element substrate, and a common electrode is provided on the other substrate, the opposing substrate, so that it is common to all pixels, and liquid crystal is sandwiched between the pixel electrodes and the common electrode. Transistors are provided between the pixel electrodes and the data lines, and the transistors are controlled to be on or off depending on the potential of the scanning lines.

A liquid crystal element sandwiches liquid crystal between a pixel electrode and an opposing electrode, forming a type of capacitance. To increase the apparent capacitance, a capacitive element (pixel additional capacitance) is provided in parallel with the liquid crystal element. With the recent advances in miniaturization and high resolution, it is becoming more difficult to ensure the capacitance of the capacitive element.

Therefore, a technology has been proposed in which an insulating substrate is etched to provide an L-shaped trench that extends in a first direction and a second direction intersecting the first direction in a plan view, and a first capacitance electrode, an insulating layer, and a second capacitance electrode are formed in the trench (see, for example, the description in Patent Document 1). Patent Document 1 also discloses that a data line connected to a source region of a transistor and a relay wiring connected to a drain region are provided by patterning one conductive layer, and that a capacitance line connected to the relay wiring is provided by patterning another conductive layer above the one conductive layer.

JP 2021-068774 A

However, in the technology described in the above Patent Document 1, the incident light from the light source penetrates the semiconductor layer of the transistor, particularly the LDD (Lightly Doped Drain) region, through a gap in another wiring layer and then a gap in one wiring layer. The penetration of this light causes off-leakage, which fluctuates the holding voltage of the liquid crystal element, and this is visually recognized as a change in transmittance (or reflectance), i.e., flicker.
In consideration of these circumstances, an object of one aspect of the present disclosure is to provide a technique for suppressing intrusion of incident light into a semiconductor layer and reducing flicker caused by off-leakage.

In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure includes a transistor having a semiconductor layer and a gate electrode, the semiconductor layer having one source drain region, the other source drain region, a channel region located between the one source drain region and the other source drain region, and an LDD region located between the other source drain region and the channel region; a scanning line electrically connected to the gate electrode, extending along a first direction, and having light-shielding properties; a first data line extending along a second direction intersecting the first direction, electrically connected to the one source drain region, having a first protrusion protruding along the first direction in a planar view, and having light-shielding properties; a first light-shielding member having a gap between the first protrusion and the first protrusion in a region overlapping the LDD region or the other source drain region in a planar view, and electrically connected to the other source drain region; and a second light-shielding member covering the gap between the first light-shielding member and the first protrusion in a planar view and electrically connected to the first light-shielding member.

An electro-optical device according to another embodiment includes a transistor having a semiconductor layer and a gate electrode, the semiconductor layer having one source drain region, the other source drain region, a channel region located between the one source drain region and the other source drain region and overlapping with the gate electrode in a planar view, and an LDD region located between the other source drain region and the channel region; a scanning line electrically connected to the gate electrode, extending along a first direction, and having a light-shielding property; a first data line extending along a second direction intersecting the first direction, electrically connected to the one source drain region, protruding to one side along the first direction in a planar view, having a first protrusion overlapping with the LDD region or the other source drain region in a planar view, and having a light-shielding property; and a light-shielding wiring extending along the second direction and having a light-shielding property, the first data line having a second protrusion protruding to one side along the first direction in a planar view and covering the first protrusion.

1 is a diagram showing a projection type display device to which an electro-optical device according to a first embodiment is applied. FIG. 2 is a block diagram showing an electrical configuration of the projection display device. FIG. 1 is a perspective view illustrating a configuration of an electro-optical device. 1 is a cross-sectional view showing a structure of an electro-optical device. FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. FIG. 2 is a diagram illustrating a configuration of a pixel circuit in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate. 10A to 10C are diagrams illustrating a manufacturing process for an element substrate in an electro-optical device according to a second embodiment. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are diagrams illustrating a manufacturing process of an element substrate in an electro-optical device. 5A to 5C are cross-sectional views illustrating a manufacturing process of the element substrate.

The electro-optical device according to the embodiment will be described below with reference to the drawings. Note that in each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

First Embodiment
FIG. 1 is a diagram showing an optical configuration of a projection display device 10 to which an electro-optical device 100 according to a first embodiment is applied. As shown in the figure, the projection display device 10 includes electro-optical devices 100R, 100G, and 100B. A lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projection display device 10. The projection light emitted from the lamp unit 2102 is separated into three primary colors, red (R), green (G), and blue (B), by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Of these, the R light is incident on the electro-optical device 100R, the G light is incident on the electro-optical device 100G, and the B light is incident on the electro-optical device 100B.
Since the optical path of B is longer than the optical paths of R and G, it is necessary to prevent loss in the optical path of B. For this reason, a relay lens system 2121 consisting of an entrance lens 2122, a relay lens 2123, and an exit lens 2124 is provided in the optical path of B.

The electro-optical devices 100R, 100G, and 100B are, for example, transmissive liquid crystal panels, each having a plurality of pixel circuits. Each of the plurality of pixel circuits includes a liquid crystal element. The liquid crystal element of the electro-optical device 100R is driven based on a data signal corresponding to R, as described below, to have a transmittance according to the voltage of the data signal.
For this reason, in the electro-optical device 100R, an R transmission image is generated by individually controlling the transmittance of the liquid crystal elements. Similarly, in the electro-optical device 100G, a G transmission image is generated based on a data signal corresponding to G, and in the electro-optical device 100B, a B transmission image is generated based on a data signal corresponding to B.

The transmitted images of each color generated by electro-optical devices 100R, 100G, and 100B are incident on dichroic prism 2112 in three directions. In dichroic prism 2112, R and B light are refracted at 90 degrees, while G light travels straight. Therefore, the images of each color are combined in dichroic prism 2112 to generate a color image by additive color mixing. The combined image by dichroic prism 2112 is incident on projection lens 2114, which enlarges and projects the combined image onto screen Scr.

Note that the transmitted images from the electro-optical devices 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmitted image from the electro-optical device 100G is projected in a straight line. Therefore, the transmitted images from the electro-optical devices 100R and 100B are in a left-right inverted relationship with the transmitted image from the electro-optical device 100G.

Figure 2 is a block diagram showing the electrical configuration of the projection display device 10. The projection display device 10 includes a display control circuit 20 and the electro-optical devices 100R, 100G, and 100B described above.

Video data Vid-in is supplied from a higher-level device such as a host device (not shown) in synchronization with the synchronization signal Sync. The video data Vid-in specifies the gradation level of pixels in the image to be displayed, for example, 8 bits for each RGB.

In the projection display device 10, the color image projected on the screen Scr is expressed by synthesizing the transmitted images of the electro-optical devices 100R, 100G, and 100B as described above. Therefore, the pixel, which is the smallest unit of a color image, can be divided into a red subpixel of the electro-optical device 100R, a green subpixel of the electro-optical device 100G, and a blue subpixel of the electro-optical device 100B. However, when it is not necessary to specify the color of the subpixels in the electro-optical devices 100R, 100G, and 100B, or when only brightness is an issue, there is no need to refer to them as subpixels. Therefore, in this description, the display unit in the electro-optical devices 100R, 100G, and 100B will be referred to simply as a pixel.

The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid-in, a horizontal synchronization signal that instructs the start of horizontal scanning, and a clock signal that indicates the timing of one video pixel in the video data Vid-in.

The display control circuit 20 separates the video data Vid-in from the higher-level device into RGB components, converts them into analog voltage data signals, and supplies them to the electro-optical devices 100R, 100G, and 100B. Specifically, the display control circuit 20 converts the R component of the video data Vid-in into analog and supplies it to the electro-optical device 100R as a data signal Vid-R. Similarly, the display control circuit 20 converts the G component of the video data Vid-in into analog and supplies it to the electro-optical device 100G as a data signal Vid-G, and converts the B component into analog and supplies it to the electro-optical device 100B as a data signal Vid-B.
The display control circuit 20 sequentially supplies the data signals Vid_R, Vid_G, and Vid_B in synchronization with a control signal Ctr for controlling the driving of the electro-optical devices 100R, 100G, and 100B.

Next, electro-optical devices 100R, 100G, and 100B will be described. Electro-optical devices 100R, 100G, and 100B have the same structure, but differ only in the color, i.e., wavelength, of the light that enters them. Therefore, electro-optical devices 100R, 100G, and 100B will be generally described, with the reference number 100, without specifying the color.

FIG. 3 is a perspective view showing the appearance of the electro-optical device 100, and FIG. 4 is a cross-sectional view taken along line Hh in FIG.
As shown in these figures, in the electro-optical device 100, an element substrate 100a on which a pixel electrode 126 is provided and an opposing substrate 100b on which a common electrode 72 is provided are bonded together with a sealing material 90 so that their electrode forming surfaces face each other while maintaining a certain gap, and liquid crystal 62 is filled in this gap.

The element substrate 100a and the counter substrate 100b are each made of a substrate having optical transparency and insulation properties, such as glass or quartz. As shown in FIG. 3, one side of the element substrate 100a protrudes from the counter substrate 100b. In this protruding area, a plurality of terminals 7 are provided along the horizontal direction in the figure. One end of an FPC (Flexible Printed Circuits) substrate (not shown) is connected to the plurality of terminals 7. The other end of the FPC substrate is connected to the display control circuit 20, and the various signals described above are supplied.

On the surface of the element substrate 100a facing the counter substrate 100b, pixel electrodes 126 are provided by patterning a transparent conductive layer, as will be described in detail later. In addition, various elements other than the electrodes are provided on the opposing surfaces of the element substrate 100a and the counter substrate 100b, but these are omitted in FIG. 4.

Figure 5 is a block diagram showing the electrical configuration of the electro-optical device 100. The electro-optical device 100 has a scanning line driving circuit 30 and a data line driving circuit 40 provided on the periphery of the display area 5.

In the display area 5 of the electro-optical device 100, pixel circuits 50 are arranged in a matrix. In detail, in the display area 5, a plurality of scanning lines 12 are provided extending along the horizontal X-axis in the figure. The X-axis is an example of a case where the orientation is not specified in the first direction. Furthermore, a plurality of data lines 14 are provided extending along the vertical Y-axis and electrically insulated from the scanning lines 12. The Y-axis is an example of a case where the orientation is not specified in the second direction. The pixel circuits 50 are provided in a matrix corresponding to the intersections of the plurality of scanning lines 12 and the plurality of data lines 14.
In addition, the X-axis and the Y-axis are in a relative relationship, and in short, the scanning lines 12 extend along one of the X-axis or the Y-axis, and the data lines 14 extend along the other of the X-axis or the Y-axis. Therefore, if the data lines 14 extend along the X-axis from one side to the other in the first direction, it can be said that the scanning lines 12 extend along the Y-axis from one side to the other in the second direction.

If the number of scanning lines 12 is m and the number of data lines 14 is n, the pixel circuits 50 are arranged in a matrix of m rows and n columns. Both m and n are integers of 2 or more. In order to distinguish the rows of the matrix in the scanning lines 12 and pixel circuits 50, they may be referred to as 1, 2, 3, ..., (m-1), m rows from the top in the figure. Similarly, in order to distinguish the columns of the matrix in the data lines 14 and pixel circuits 50, they may be referred to as 1, 2, 3, ..., (n-1), n columns from the left in the figure.

The scanning line driving circuit 30 selects the scanning lines 12 one by one in the order of, for example, the 1st, 2nd, 3rd, ..., mth rows in accordance with a control signal Ctr from the display control circuit 20, and sets the scanning signal to the selected scanning line 12 to H level. The scanning line driving circuit 30 sets the scanning signals to the scanning lines 12 other than the selected scanning line 12 to L level.
The data line driving circuit 40 latches one row of data signals of the corresponding color from the data signals supplied from the display control circuit 20, and outputs them via the data line 14 to the pixel circuit 50 located on that scanning line 12 during the period when the scanning signal to that scanning line 12 is at the H level.

Figure 6 is a diagram showing an equivalent circuit of four pixel circuits 50 arranged in two vertical rows and two horizontal columns corresponding to the intersections of two adjacent scanning lines 12A and 12B and two adjacent data lines 14A and 14B. The pixel circuits 50 have the same circuit configuration. Therefore, focusing on the pixel circuit 50 corresponding to the intersection of scanning line 12A and data line 14A, this pixel circuit 50 will be described.

The pixel circuit 50 includes a liquid crystal element 60, a transistor 130, and a storage capacitor 140. The transistor 130 is, for example, an n-channel thin film transistor. In the pixel circuit 50, the gate electrode of the transistor 130 is electrically connected to the scanning line 12A, while its source region is electrically connected to the data line 14A, and its drain region is electrically connected to the pixel electrode 126 and one end of the storage capacitor 140.

In transistor 130, when the direction of current flow is reversed, the source and drain are swapped; however, in this description, the region electrically connected to data line 14A is referred to as the source region (one of the source/drain regions), and the region electrically connected to pixel electrode 126 is referred to as the drain region (the other source/drain region).
In addition, in this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and also includes, for example, a case where different wiring is connected via a contact hole even if two or more elements are not directly connected to each other on an element substrate.

A common electrode 72 is provided in common to all pixels so as to face the pixel electrode 126. A voltage LCcom is applied to the common electrode 72. As described above, the liquid crystal 62 is sandwiched between the pixel electrode 126 and the common electrode 72. Therefore, for each pixel circuit 50, a liquid crystal element 60 is formed in which the liquid crystal 62 is sandwiched between the pixel electrode 126 and the common electrode 72.
In addition, a storage capacitor 140 is provided electrically in parallel with the liquid crystal element 60. One end of the storage capacitor 140 is connected to the pixel electrode 126, and the other end is connected to a capacitance line 74. A time-constant voltage, for example, a voltage LCcom that is the same as the voltage applied to the common electrode 72, is applied to the capacitance line 74.

In FIG. 6, the capacitance line 74 is arranged along the X-axis, which is the extension direction of the scanning line 12. However, in reality, as will be described later, a plurality of wirings are connected via contact holes and arranged in a mesh shape when viewed in a plane along the X-axis and Y-axis.
6, the two scanning lines are distinguished by the reference symbols 12A and 12B, and the two data lines are distinguished by the reference symbols 14A and 14B. When the scanning lines and the data lines are not distinguished, the reference symbols are 12 and 14, as shown in FIG.

The pixel circuits 50 are arranged in a matrix along the X-axis along the scanning lines 12 and the Y-axis along the data lines 14, so the pixel electrodes 126 included in the pixel circuits 50 are also arranged along the X-axis and the Y-axis.

When the scanning signal for a scanning line 12 is at H level, the transistor 130 of the pixel circuit 50 corresponding to that scanning line 12 is turned on. When the transistor 130 is turned on, the data line 14 and the pixel electrode 126 are electrically connected, and the data signal supplied to the data line 14 reaches the pixel electrode 126 via the transistor 130 in the on state. When the scanning line 12 is turned to L level, the transistor 130 is turned off, but the voltage of the data signal that reaches the pixel electrode 126 is held by the liquid crystal element 60 and the storage capacitance 140.

As is well known, in the liquid crystal element 60, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 126 and the common electrode 72. Therefore, the liquid crystal element 60 has a transmittance that corresponds to the effective value of the applied voltage.
If the liquid crystal element 60 is in a normally black mode, the transmittance increases as the voltage applied to the liquid crystal element 60 increases.
The region that functions as a pixel in the liquid crystal element 60, that is, the region that has a transmittance according to the effective value of the voltage, is the region where the pixel electrode 126 overlaps with the common electrode 72 when the element substrate 100a and the counter substrate 100b are viewed in plan. Since the pixel electrode 126 is, for example, a square in plan view, the shape of the pixel in the electro-optical device 100 is also a square in plan view.
In this description, a plan view refers to a case where the substrate is viewed along a perpendicular axis to the substrate surface, and in particular, a plan view of the element substrate 100a refers to a case where the opposing surface of the element substrate 100a is viewed from the opposing substrate 100b.

The operation of supplying data signals to the pixel electrodes 126 of the liquid crystal elements 60 is executed in the order of the 1st, 2nd, 3rd, ..., mth rows in one vertical scanning period. As a result, a voltage corresponding to the data signal is held in each of the liquid crystal elements 60 of the pixel circuits 50 arranged in m rows and n columns, each liquid crystal element 60 has a target transmittance, and a transmitted image of the corresponding color is generated by the liquid crystal elements 60 arranged in m rows and n columns.
In this manner, the generation of a transmission image is executed for each of RGB, and a color image obtained by combining RGB is projected onto the screen Scr.

The element substrate 100a in the electro-optical device 100 will be described.
13 is a plan view showing the opposing surface of the element substrate 100a. On the opposing surface of the element substrate 100a, pixel electrodes 126 are provided in a matrix shape along the X-axis and Y-axis with gaps between them.
One pixel electrode 126 is electrically connected to a wiring 125a through a contact hole Ct56 provided at approximately the center of the lower side when viewed in a plan view. The wiring 125a is a relay wiring electrically connected to the drain region of the transistor 130 and one end of the storage capacitor 140, as described later.

13, line A-a is an imaginary line that connects, in a plan view, a source region of a transistor 130 (described later) to a point J1 along the right direction of the X axis, and from point J1 to a point J3 along the upward direction of the Y axis. When focusing on a pixel electrode 126, point J1 is the imaginary center point of a gap generated by four adjacent pixel electrodes 126 at the lower right of the pixel electrode 126.
Line B-b is a virtual line that runs along the X-axis when viewed in a plane, and includes the gap between a pixel electrode 126 of interest and the pixel electrode 126 located immediately to the right of the pixel electrode of interest, and is used to explain the structure of storage capacitance 140.
Line Cc is a virtual line along the Y axis in a plan view, including the contact hole Ct56, and is used to explain the structure of the transistor 130 in the vicinity of the gate electrode.

7 to 13, including the above-mentioned Fig. 13, are plan views showing the manufacturing process of the element substrate 100a. Note that various insulating layers and dielectric layers are omitted as appropriate in the plan views of Fig. 7 to 13.
14 to 20 are cross-sectional views showing the manufacturing process of the element substrate 100a, and are schematic cross-sectional views of the element substrate 100a taken along line Aa in the plan views of FIGS. 7 to 13, respectively.
Figures 21 to 27 are cross-sectional views showing the manufacturing process of the element substrate 100a, and of these figures, the left columns are schematic cross-sectional views of the element substrate 100a taken along line B-b in the plan views of Figures 7 to 13, respectively, and the right columns are cross-sectional views of the element substrate 100a taken along line C-c in the plan views of Figures 7 to 13, respectively.
In addition, in order to avoid complicating the drawings, lines Aa, Bb, and Cc are omitted in FIGS. 10, 11, and 12.

First, as shown in the right columns of FIG. 14 and FIG. 21, wiring 122 is provided on the upper surface of a substrate 101 made of quartz or the like and having optical transparency and insulating properties.
7, the wiring 122 is formed row by row along the X-axis. The wiring 122 is formed by patterning a first conductive layer made of, for example, tungsten (W) or tungsten silicide (WSi) having light blocking properties and electrical conductivity. "Row by row" means that the wiring 122 corresponds one-to-one with the scanning line 12.
7, the wiring 122 includes a wide portion 122a provided for each pixel circuit 50. The wide portion 122a is provided to receive two contact holes Ct23, which will be described later.

In the plan view, the contact holes are indicated by two types of symbols: a simple square frame and a mark with an X superimposed on a square frame. Of these, the former simple square frame indicates the position of the lower wiring (closer to the substrate 101) of the two wirings to be connected, and the latter square frame with an X superimposed on it indicates the position of the upper wiring (farther from the substrate 101) of the two wirings to be connected.
As shown in the left column of FIG. 21, the wiring 122 is not provided in the portion broken along line Bb.

Next, as shown in the left columns of Fig. 15 and Fig. 22, trench Ta is provided by etching the substrate 101. The trench Ta is provided in a rectangular shape along the Y axis between points J1 and J3 in a plan view as shown in Fig. 8. Therefore, trench Ta is not provided in the portion broken along line Cc as shown in the right column of Fig. 22.
The trench Ta is a region where most of the storage capacitance 140 is formed.

Next, as shown in the right column of FIG. 16 and FIG. 23, a first interlayer insulating film 112 is provided so as to cover the substrate 101 or the wiring 122. After this, a semiconductor layer 131 is provided on the upper surface of the first interlayer insulating film 112 or the wiring 122, particularly in the trench Ta, on the upper surface of the first interlayer insulating film 112. The semiconductor layer 131 constitutes a part of the storage capacitance 140 and the transistor 130, and is formed into an L-shape along the line A-a as shown in FIG. 9 when viewed in a plane by patterning the high-temperature polysilicon film.

In terms of the equivalent circuit relationship shown in FIG. 6, the semiconductor layer 131 of the transistor 130 in the pixel circuit 50 corresponding to the scanning line 12A and the data line 14B is arranged to overlap the scanning line 12A and the data line 14B located to the right of the data line 14A in a planar view. Note that the data line 14A is an example of a first data line, and the data line 14B is an example of a second data line.

A portion of the region of the semiconductor layer 131 that overlaps with the wiring 122 including the wide portion 122a is formed narrower than the line width of the wiring 122. As described below, this portion of the region becomes the source region, channel region, and LDD region of the transistor 130. Since this portion of the region is narrower than the line width of the wiring 122, returning light from the back surface is blocked by the wiring 122, and the configuration is such that the returning light is less likely to enter the channel region and LDD region of the transistor 130.
The line width refers to the dimension in a direction perpendicular to the extending direction of the wiring. The semiconductor layer 131 penetrates to the bottom of the trench Ta, as shown in the left columns of FIGS.

As shown in FIGS. 17 and 24, a gate insulating film 151 is provided so as to cover the first interlayer insulating film 112 or the semiconductor layer 131, and a part of it is removed by photolithography.
The region from which the gate insulating film 151 is removed is an L-shaped region that is to become the remaining region of the drain region, which will be described later, although it is omitted in FIG. 10. The photoresist is opened in the L-shaped region, and the gate insulating film 151 is removed in the region corresponding to the opening, exposing the semiconductor layer 131. Using this photoresist as a mask, ions are implanted into the exposed portion of the semiconductor layer 131, which is used as one end of the storage capacitor 140. The dielectric film and the deposited polysilicon film are then patterned to form dielectric films 152a, 152b and deposited polysilicon films 153a and 153b, as shown in FIG. 17 and FIG. 24 when viewed in cross section.

As shown in the right column of FIG. 24, two contact holes Ct23 are provided corresponding to one pixel circuit 50. The contact holes Ct23 are openings formed in the deposited polysilicon film 153a, the dielectric film 152a, the gate insulating film 151, and the first interlayer insulating film 112, in that order. The wiring 122 is exposed by the contact holes Ct23.

A gate electrode 123a and wiring 123b are provided on the upper surface of the first interlayer insulating film 112, for example, by patterning a second conductive layer that has light-shielding and conductive properties.

Of these, wiring 123b constitutes a part of capacitance line 74, which is an example of capacitance wiring, and is arranged so as to overlap with each row of trenches Ta along the Y axis as shown in FIG. 10, and in cross-sectional view, is arranged so as to overlap with deposited polysilicon film 153b and dielectric film 152b as shown in the left column of FIGS. 17 and 24.
As a result, the storage capacitor 140 is formed by sandwiching the dielectric film 152b between the remaining region excluding a part of the drain region of the semiconductor layer 131, the wiring 123b and the deposited polysilicon film 153b.
In the storage capacitance 140, in the trench Ta, a conductive layer/dielectric film/conductive layer is formed not only at the bottom of the trench Ta but also on the sidewalls, so that the capacitance can be increased accordingly.

The wiring 123b has a protruding portion 123ba that protrudes to the left so as to overlap with the semiconductor layer 131 of each row as shown in Fig. 10 in a plan view. The protruding portion 123ba is provided to receive the contact hole Ct35.
Since the dielectric film 152b is also provided on the protruding portion 123ba, the storage capacitance 140 is also formed in a portion other than the trench Ta.

10, the gate electrode 123a is provided in an island shape so as to overlap a narrow portion of the semiconductor layer 131 between the two contact holes Ct23 in a plan view. As a result, the gate electrode 123a is electrically connected to the wiring 122 via the two contact holes Ct23.
The gate electrode 123 a has a line width wider than that of the wiring 122 in a region overlapping with the wiring 122 and the semiconductor layer 131 .

In the semiconductor layer 131, LDD regions 131a and 131b are provided by ion implantation using the gate electrode 123a as a mask. In Fig. 10, the LDD regions 131a and 131b are hatched regions. As shown in Fig. 10 and Fig. 17, in the semiconductor layer 131, the left side of the LDD region 131a is the source region, and the right side of the LDD region 131b is the drain region.
The source region is a doped region with a higher concentration than the low concentration LDD region 131a, and the drain region is a doped region with a higher concentration than the low concentration LDD region 131b.

A part of the drain region overlaps with the wiring 123b including the protruding portion 123ba as shown in Fig. 10 or 17. The region overlapping with the wiring 123b including the protruding portion 123ba, in other words, the region where the remaining L-shaped region excluding a part of the drain region overlaps with the wiring 123b in a plan view, has already become a highly doped region by ion implantation using a photoresist as a mask as described above.
Furthermore, a portion of the semiconductor layer 131 that overlaps with the gate electrode 123a in plan view is a channel region 131c.
In this manner, the source region, drain region, LDD regions 131a, 131b and channel region 131c of the transistor 130 are provided.

Next, as shown in FIGS. 18 and 25, a second interlayer insulating film 113 is provided so as to cover the gate insulating film 151, the gate electrode 123a, or the wiring 123b.
18, contact holes Cts4 and Ctd4 are provided. The contact holes Cts4 and Ctd4 are formed in sequence in the second interlayer insulating film 113 and the gate insulating film 151, respectively. The contact hole Cts4 exposes the source region of the semiconductor layer 131, and the contact hole Ctd4 exposes the drain region of the semiconductor layer 131.

On the upper surface of the second interlayer insulating film 113, wirings 124a and 124b are provided by patterning a third conductive layer having light shielding properties and conductivity, such as aluminum.
The wiring 124a is an example of a first light blocking member, is formed in an island shape, and is electrically connected to the drain region of the semiconductor layer 131 via a contact hole Ctd4.
The wiring 124b constitutes the data line 14, and has a protrusion 124ba that protrudes to the right in each row when viewed in a plan view, as shown in Fig. 11. The protrusion 124ba of the wiring 124b is an example of a first protrusion, and is electrically connected to the source region of the semiconductor layer 131 via a contact hole Cts4. In addition, the portion of the wiring 124b excluding the protrusion 124ba is an example of a main body portion.
The wiring 124a covers the drain region of the semiconductor layer 131, and the protruding portion 124ba covers the source region, the LDD region 131a, the LDD region 131b, and the gate electrode 123a of the semiconductor layer 131. Here, in a region overlapping with the drain region in a plan view, a gap Ap1 is generated between the wiring 124a and the protruding portion 124ba.

The gap Ap1 may be provided in a region overlapping with the LDD region 131b in plan view, instead of in a region overlapping with the drain region.
11, if the leftmost wiring 124b corresponds to the data line 14A, the central wiring 124b corresponds to the data line 14B. Therefore, the semiconductor layer 131 whose source region is connected to the wiring 124b corresponding to the data line 14A overlaps with the wiring 122 corresponding to the scanning line 12 in a planar view, and is bent at a point J1 to overlap along the data line 14B in a planar view.
In FIG. 11, in order to avoid complication, only the wirings 124a and 124b, the semiconductor layer 131, and the gate electrode 123a are shown, and other wirings including the protruding portion 123ba are omitted.

As shown in FIGS. 19 and 26, a third interlayer insulating film 114 is provided so as to cover the wirings 124 a and 124 b or the second interlayer insulating film 113 .
19, contact holes Ct35 and Ct45 are provided. The contact hole Ct35 is formed in the third interlayer insulating film 114 and the second interlayer insulating film 113 in this order. The contact hole Ct35 exposes the wiring 123b. The contact hole Ct45 is formed in the third interlayer insulating film 114. The contact hole Ct45 exposes the wiring 124a.

On the upper surface of the third interlayer insulating film 114, wirings 125a and 125b are provided by patterning a fourth conductive layer having light shielding properties and conductivity, such as aluminum.
The wiring 125a is an example of a second light-shielding member, and is formed in an island shape in a plan view as shown in Fig. 12, and is electrically connected to the wiring 124a via a contact hole Ct45. As shown in Fig. 19, the wiring 125a covers the gap Ap1 generated between the wiring 124a and the protrusion 124ba.

The wiring 125b is an example of a light-shielding wiring, and constitutes a part of the capacitance line 74. When viewed in a plan view, the portion along the Y-axis is formed in the same shape as the wiring 123b in Fig. 10. The wiring 125b has a protruding portion 125ba that protrudes to the left in each row, and is electrically connected to the wiring 123b via a contact hole Ct35.
The wiring 125a covers a part of the wiring 124a and a part of the protruding portion 124ba in a plan view.
A gap Ap2 is generated between the wiring 125a and the protruding portion 125ba of the wiring 125b on the right side in FIG.
In FIG. 12, to avoid complication, only the wires 125a and 125b are shown, and other wires are omitted.

As shown in FIGS. 20 and 27, a fourth interlayer insulating film 115 is provided so as to cover the wirings 125 a and 125 b or the third interlayer insulating film 114 .
27, a contact hole Ct56 is provided. The contact hole Ct56 is formed in the fourth interlayer insulating film 115. The wiring 125a is exposed by the contact hole Ct56.

As shown in FIG. 27 and the above-described FIG. 14, a pixel electrode 126 is provided on the upper surface of the fourth interlayer insulating film 115 by patterning a fifth conductive layer that is transparent and conductive.
The pixel electrode 126 is electrically connected to the wiring 125a through a contact hole Ct56.
In FIG. 13, in order to avoid complication, only the pixel electrode 126 and the wirings 125a and 125b are shown, and other wirings are omitted.

In this embodiment, the drain region of the semiconductor layer 131 constituting the transistor 130 is electrically connected to the pixel electrode 126 in the order of the contact hole Ctd4, the wiring 124a, the contact hole Ct45, the wiring 125a, and the contact hole Ct56.
Furthermore, the source region of the semiconductor layer 131 is electrically connected to the wiring 124b constituting the data line 14, through the contact hole Cts4 and the protruding portion 124ba in this order.
The gate electrode 123a is electrically connected to the wiring 122 constituting the scanning line 12 through a contact hole Ct23.
The other end of the storage capacitor 140, that is, the wiring 123b and the deposited polysilicon film 153b, is electrically connected to a wiring 125b via a contact hole Ct35.

19 and 20, the gap Ap1 generated between the wiring 124a and the protruding portion 124ba is covered with the wiring 125a. Therefore, the incident light from the light source is blocked by the wiring 125a and is unlikely to penetrate into the semiconductor layer 131, particularly the LDD region 131b, through the gap Ap1.
Furthermore, incident light from the light source enters through a gap Ap2 occurring between the wirings 125a and 125b. However, the entering light is blocked by the wiring 124a, and is therefore unlikely to enter the semiconductor layer 131.
Therefore, in this embodiment, it is possible to prevent the incident light from the light source from entering the semiconductor layer 131 .

In addition, the LDD regions 131a, 131b and the channel region 131c of the semiconductor layer 131 overlap the wiring 122 in a plan view, and the line widths of the LDD regions 131a, 131b and the channel region 131c are narrower than the line width of the wiring 122. Therefore, the returning light is blocked by the wiring 122 and is less likely to enter the semiconductor layer 131.

Therefore, in this embodiment, incident light and return light from the light source are less likely to penetrate the semiconductor layer 131, making it possible to reduce flicker caused by off-leakage.

In this embodiment, the wiring 124b functioning as the data line 14 is sandwiched between the lower wiring 123b and the upper wiring 125b with respect to the vertical axis of the substrate surface of the element substrate 100a. The wiring 124b functioning as the data line 14 is supplied with a data signal, and therefore may become a noise source due to voltage fluctuations. However, the wirings 123b and 125b sandwiching the wiring 124b are electrically connected via the contact hole Ct35 and are maintained at a constant voltage LCcom over time, and therefore function as a shield wiring.
Therefore, in this embodiment, the influence of noise caused by voltage fluctuations on the wiring 124b can be suppressed.

Second Embodiment
Next, an electro-optical device 100 according to a second embodiment will be described.
The electro-optical device 100 according to the second embodiment differs from the electro-optical device according to the first embodiment in the following respects in the element substrate 100a: Specifically, the main differences between the element substrate 100a of the electro-optical device 100 according to the second embodiment and the first embodiment are the shape of the wiring 122, the shape of the semiconductor layer 131, the shape of the wiring 124b, the elimination of the contact holes Ct45 and Ctd4, and the provision of a new contact hole Ctd6.

34 is a plan view showing the opposing surface of the element substrate 100a of the electro-optical device 100 according to the second embodiment. On the opposing surface of the element substrate 100a, pixel electrodes 126 are provided in a matrix along the X-axis and Y-axis with gaps between them.
One pixel electrode 126 is electrically connected to the drain region via a contact hole Ctd6 provided on the right side of the lower side in a plan view. The contact hole Ctd6 is an opening that exposes the drain region by opening a plurality of interlayer insulating films. The contact hole Ctd6 is filled with a conductive material such as tungsten, as described later.

In FIG. 34, line Dd is an imaginary line that connects, in a plan view, the source region of a transistor 130 described later to point J1 via a contact hole Ctd6, and from point J1 to point J3 along the upward direction of the Y axis.
In the second embodiment, the connection between the gate electrode 123a and the wiring 122 in the transistor 130 and the configuration of the storage capacitor 140 are similar to those in the first embodiment. For this reason, in the second embodiment, cross-sectional views showing the manufacturing process in which the element substrate 100a is broken along the lines Bb and Cc are omitted.
FIG. 35 is a cross-sectional view of the element substrate 100a taken along line Dd.

Figures 28 to 34, including the above Figure 34, are plan views showing the manufacturing process of the element substrate 100a. Note that in the plan views of Figures 28 to 34, various insulating layers and dielectric layers are omitted as appropriate. Also, in Figures 31, 32, and 33, line D-d is omitted to avoid complicating the drawings.

First, as shown in FIGS. 28 and 35, wiring 122 is provided on the upper surface of base material 101.
As in the first embodiment, the wiring 122 is formed for each row along the X-axis in a plan view as shown in Fig. 28 by patterning a first conductive layer made of, for example, tungsten (W) or tungsten silicide (WSi) having light blocking properties and electrical conductivity. In the second embodiment, the wiring 122 is provided with a protrusion 122c for each pixel circuit 50.

Next, as shown in FIGS. 29 and 35, trenches Ta are provided by etching the base material 101 in the same manner as in the first embodiment.
Next, as shown in FIG. 35, a first interlayer insulating film 112 is provided so as to cover the substrate 101 or the wiring 122, and then a semiconductor layer 131 is provided on the upper surface of the first interlayer insulating film 112 or the wiring 122, particularly in the trench Ta, on the upper surface of the first interlayer insulating film 112, and patterned in plan view as shown in FIG. 30.
In the second embodiment, the semiconductor layer 131 has a protruding portion 131d in plan view. The protruding portion 131d overlaps with the protruding portion 122c of the wiring 122 in plan view and is provided to receive the contact hole Ctd6. The semiconductor layer 131 in the second embodiment is similar to that in the first embodiment except for having the protruding portion 131d.

After the semiconductor layer 131 is patterned, a gate insulating film 151 is provided so as to cover the first interlayer insulating film 112 or the semiconductor layer 131, and a part of the gate insulating film 151 is removed by photolithography. The region from which the gate insulating film 151 is removed is the same as in the first embodiment, and is an L-shaped region that is to become the remaining region of the drain region. The photoresist is opened in the L-shaped region, and the gate insulating film 151 is removed in the region corresponding to the opening, exposing the semiconductor layer 131. Using the photoresist as a mask, ions are implanted into the exposed portion of the semiconductor layer 131, and the exposed portion is used as one end of the storage capacitance 140. When viewed in cross section by patterning the dielectric film and the deposited polysilicon film formed after this, dielectric films 152a, 152b and deposited polysilicon films 153a and 153b are formed.
In addition, the dielectric films 152a, 152b and the deposited polysilicon films 153a and 153b are omitted from FIG. 35 to avoid complication, but they are the same as those in FIG.

As shown in FIG. 30, two contact holes Ct23 are provided corresponding to one pixel circuit 50.
On the upper surface of the first interlayer insulating film 112, a gate electrode 123a and a wiring 123b are provided in the same manner as in the first embodiment as shown in FIG. 31 by patterning a second conductive layer having light-shielding and conductive properties, for example.
As a result, the dielectric film 152b is sandwiched between the remaining region of the semiconductor layer 131 excluding a portion of the drain region, the wiring 123b, and the deposited polysilicon film 153b, so that a storage capacitor 140 is formed.
31, the wiring 123b has a protruding portion 123ba that protrudes to the left so as to overlap with the semiconductor layer 131 of each row. The protruding portion 123ba is provided to receive the contact hole Ct35, but does not overlap with the protruding portion 131d of the semiconductor layer 131.

31, the gate electrode 123a is provided in an island shape so as to overlap a narrow portion of the semiconductor layer 131 between the two contact holes Ct23 in a plan view. As a result, the gate electrode 123a is electrically connected to the wiring 122 via the two contact holes Ct23.
In the semiconductor layer 131, LDD regions 131a and 131b are provided by ion implantation using the gate electrode 123a as a mask.
As shown in FIGS. 31 and 35, in the semiconductor layer 131, the left side of the LDD region 131a is a source region, and the right side of the LDD region 131b is a drain region.
Furthermore, a portion of the semiconductor layer 131 that overlaps with the gate electrode 123a in plan view is a channel region 131c.
In this manner, the source region, drain region, LDD regions 131a, 131b and channel region 131c of the transistor 130 are provided.

Next, as shown in FIG. 32 and FIG. 35, a second interlayer insulating film 113 is provided so as to cover the gate insulating film 151, the gate electrode 123a, or the wiring 123b. A contact hole Cts4 is provided in the second interlayer insulating film 113. The source region of the semiconductor layer 131 is exposed by the contact hole Cts4.

On the upper surface of the second interlayer insulating film 113, a wiring 124b is provided by patterning a third conductive layer having light shielding properties and conductivity, such as aluminum.
In the second embodiment, the wiring 124b constitutes the data line 14 in the same manner as in the first embodiment. In addition, the wiring 124b has a protrusion 124bb that protrudes to the right in each row as shown in Fig. 32 when viewed in a plan view. The protrusion 124bb of the wiring 124b is an example of a first protrusion as in the first embodiment, and is electrically connected to the source region of the semiconductor layer 131 via a contact hole Cts4.
The protrusion 124 bb in the second embodiment extends further to the right on the X-axis than the protrusion 124 ba in the first embodiment, that is, extends so as to cover the drain region of the semiconductor layer 131 .

In FIG. 32, a gap Ap3 is generated between a protruding portion 124bb of a wiring 124b in a certain column and a protruding portion 123ba of a wiring 123b in a column located immediately to the right of the certain column.
The gap Ap3 only needs to be provided in a region that overlaps at least the LDD region 131b in plan view.
In FIG. 32, in order to avoid complication, only the wiring 124b including the protruding portion 124bb, the semiconductor layer 131, and the gate electrode 123a are shown, and other wirings including the protruding portion 123ba are omitted.

33 and 35, a third interlayer insulating film 114 is provided so as to cover the wiring 124b including the protruding portion 124bb or the second interlayer insulating film 113. Then, as shown in FIG.
35, a contact hole Ct35 is provided. The contact hole Ct35 is formed in this order through the third interlayer insulating film 114 and the second interlayer insulating film 113. The wiring 123b is exposed through the contact hole Ct35.

A wiring 125b is provided by patterning a fourth conductive layer having light blocking properties and conductivity, such as aluminum, on the upper surface of the third interlayer insulating film 114. Note that in the second embodiment, the wiring 124a in the first embodiment is not provided.
The wiring 125b has a protrusion 125c that protrudes to the right in each row as shown in Fig. 33 when viewed in a plan view. The protrusion 125c of the wiring 125b is an example of a second protrusion, and covers the protrusion 124bb of the wiring 124b in approximately the same shape when viewed in a plan view.
Similarly to the first embodiment, the wiring 125b has a protruding portion 125ba that protrudes to the left in each row and is electrically connected to the wiring 123b via a contact hole Ct35.
As shown in FIG. 33 in plan view, the gap Ap3 occurs between the protruding portion 125c and the protruding portion 125ba.
In FIG. 33, in order to avoid complication, only the wiring 125b including the protruding portions 125ba and 125c and a part of the semiconductor layer 131 are shown, and other wirings are omitted.

Next, as shown in FIG. 35, a fourth interlayer insulating film 115 is provided so as to cover the wiring 125 b or the third interlayer insulating film 114 .
Thereafter, a contact hole Ctd6 is provided. The contact hole Ctd6 is opened in this order through the fourth interlayer insulating film 115, the third interlayer insulating film 114, the second interlayer insulating film 113, and the gate insulating film 151. The drain region is exposed by the contact hole Ctd6.
The contact hole Ctd6 is filled with a conductive material such as tungsten having light blocking properties.
Thereafter, on the upper surface of the fourth interlayer insulating film 115, as shown in the above-described FIGS. 34 and 35, the pixel electrode 126 is provided by patterning a fifth conductive layer that is transparent and conductive.
The pixel electrode 126 is electrically connected to the drain region through a contact hole Ctd6.
In FIG. 34, in order to avoid complication, only the pixel electrode 126 and the wiring 125b are shown, and other wiring is omitted.

According to the second embodiment, as particularly shown in FIG. 35 , the source region, LDD regions 131a, 131b, channel region 131c and a part of the drain region of semiconductor layer 131 are covered with protrusion 124bb of interconnect 124b, and further, protrusion 124bb is covered with protrusion 125c of interconnect 125b having approximately the same shape in a planar view.
In addition, a gap Ap3 is generated in a plan view between the protrusion 125c of the wiring 125b in one column and the protrusion 125ba of the wiring 125b in another column as shown in FIG. 33. However, oblique light incident from the light source through the gap Ap3 is blocked by the light-shielding plug Plg filled in the contact hole Ctd6.
Therefore, in the second embodiment, straight light and oblique light incident from the light source are less likely to penetrate into the semiconductor layer 131, particularly the LDD region 131b.

In addition, in the second embodiment, as in the first embodiment, the LDD regions 131a, 131b and the channel region 131c of the semiconductor layer 131 overlap the wiring 122 in a plan view, so that returning light is less likely to penetrate the semiconductor layer 131.

Therefore, in the second embodiment, as in the first embodiment, the incident light and return light from the light source are less likely to penetrate into the semiconductor layer 131, so flicker caused by off-leakage can be reduced.

In the second embodiment, as in the first embodiment, the wiring 124b functioning as the data line 14 is sandwiched between the wiring 123b and the wiring 125b which are held at a constant voltage and function as shield lines, so that the effects of noise caused by voltage fluctuations in the wiring 124b can be suppressed.

<Additional Notes>
From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

An electro-optical device according to one aspect (aspect 1) includes a transistor having a semiconductor layer and a gate electrode, the semiconductor layer including one source/drain region, the other source/drain region, a channel region located between the one source/drain region and the other source/drain region, and an LDD region located between the other source/drain region and the channel region; a scanning line electrically connected to the gate electrode, extending along a first direction, and having light-shielding properties; a first data line extending along a second direction intersecting the first direction, electrically connected to the one source/drain region, having a first protrusion protruding along the first direction in a planar view, and having light-shielding properties; a first light-shielding member having a gap between itself and the first protrusion in a region overlapping with the LDD region or the other source/drain region in a planar view, the first light-shielding member electrically connected to the other source/drain region; and a second light-shielding member covering the gap between the first light-shielding member and the first protrusion in a planar view, and electrically connected to the first light-shielding member.
According to the first aspect, since the second light shielding member is provided so as to cover the gap between the first light shielding member and the protruding portion in a plan view, incident light is less likely to penetrate into the semiconductor layer, and thus flicker caused by off-leakage can be further reduced.

The electro-optical device according to specific aspect 2 of aspect 1 includes a second data line that extends along the second direction and has light-shielding properties, and a light-shielding wiring that extends along the second direction so as to overlap the second data line in a planar view and has light-shielding properties.

The electro-optical device according to specific aspect 3 of aspect 1 has a main body portion in which the first data line extends along the second direction, and the first protrusion protrudes from the main body portion along the first direction.

An electro-optical device according to another aspect (aspect 4) includes a transistor having a semiconductor layer and a gate electrode, the semiconductor layer including one source/drain region, the other source/drain region, a channel region located between the one source/drain region and the other source/drain region and overlapping with the gate electrode in a planar view, and an LDD region located between the other source/drain region and the channel region; a scanning line electrically connected to the gate electrode, extending along a first direction, and having light-blocking properties; a first data line extending along a second direction intersecting the first direction, electrically connected to the one source/drain region, having a first protrusion that protrudes to one side along the first direction in a planar view and overlaps with the LDD region or the other source/drain region in a planar view, and having light-blocking properties; and a light-blocking wiring extending along the second direction and having light-blocking properties, the scanning line having a first protrusion that protrudes to one side along the first direction in a planar view and covers the first protrusion.
According to the fourth aspect, the first protrusion protruding in one direction from the first data line in the first direction overlaps with the other of the LDD region or the source/drain region in a plan view. This first protrusion is further covered with the second protrusion, so that incident light is less likely to penetrate into the semiconductor layer. This makes it possible to further reduce flicker caused by off-leakage.

The electro-optical device according to a specific aspect 5 of aspect 4 includes a second data line that extends along the second direction so as to overlap the light-shielding wiring in a planar view and has light-shielding properties.

The electro-optical device according to specific aspect 6 of aspect 4 has a main body portion in which the first data lines extend along the second direction, and the first protrusions protrude from the main body portion along the first direction.

In the electro-optical device according to specific aspect 7 of aspect 1 or aspect 4, the gate electrode is provided in an island shape so as to cover a part of the scanning line, and is wider than the line width of the scanning line.

In an electro-optical device according to a specific aspect 8 of aspect 2 or aspect 5, the semiconductor layer overlaps with the scanning line in a planar view from one of the source-drain regions to a portion of the other source-drain region, and the remaining portion of the other source-drain region excluding that portion overlaps with the second data line in a planar view.
According to aspect 8, one source/drain region in the semiconductor layer overlaps with the scanning line in a planar view from one source/drain region to a portion of the other source/drain region, and the remaining portion of the other source/drain region overlaps with the second data line in a planar view, so that the region overlapping with the scanning line and the region overlapping with the second data line are effectively utilized, thereby increasing the aperture ratio.

The electro-optical device according to a specific aspect 9 of aspect 8 includes a capacitance wiring extending along the second direction so as to overlap the second data line and the light-shielding wiring in a planar view, and a storage capacitance having a dielectric film sandwiched between the remaining portion of the other source-drain region and the capacitance wiring.

In the electro-optical device according to a tenth specific example of the ninth example, the light-shielding wiring is electrically connected to the capacitance wiring, and the second data line is disposed between the light-shielding wiring and the capacitance wiring.
According to the tenth aspect, noise caused by the voltage amplitude of the second data line is shielded by the capacitance line and the light-shielding line.

The electronic device according to aspect 11 has the electro-optical device according to aspect 1.

10...projection type display device, 12...scanning line, 14...data line, 14A...first data line, 14B...second data line, 50...pixel circuit, 72...opposing electrode, 74...capacitance line, 100, 100R, 100G, 100B...electro-optical device, 101...substrate, 122...wiring (scanning line), 123a...gate electrode, 123b...wiring (capacitance wiring), 124a...wiring (first light-shielding member), 124b...wiring (de data line), 124ba, 124bb...protrusion (first protrusion), 125a...wiring (second light-shielding member), 125c...protrusion (second protrusion), 125b...wiring (light-shielding wiring), 126...pixel electrode, 130...transistor, 131...semiconductor layer, 131a, 131b...LDD region, 131C...channel region, 140...storage capacitance, 152b...dielectric film, Ap1...gap, Ta...trench.

Claims (11)

a transistor having a semiconductor layer and a gate electrode, the semiconductor layer having one source/drain region, the other source/drain region, a channel region located between the one source/drain region and the other source/drain region, and an LDD region located between the other source/drain region and the channel region;
a scanning line electrically connected to the gate electrode, extending along a first direction, and having a light-shielding property;
a first data line extending along a second direction intersecting the first direction, electrically connected to the one of the source/drain regions, having a first protruding portion protruding along the first direction in a plan view, and having a light-shielding property;
a first light-shielding member that has a gap between itself and the first protrusion in a region that overlaps with the LDD region or the other source/drain region in a plan view, and is electrically connected to the other source/drain region;
a second light blocking member covering a gap between the first light blocking member and the first protrusion in a plan view and electrically connected to the first light blocking member;
An electro-optical device comprising:
a second data line extending along the second direction and having a light blocking property;
a light-shielding wiring extending along the second direction so as to overlap the second data line in a plan view and having a light-shielding property;
The electro-optical device according to claim 1 , comprising:
the first data line has a main body portion extending along the second direction,
The electro-optical device according to claim 1 , wherein the first protrusion protrudes from the main body along the first direction.
a transistor having a semiconductor layer and a gate electrode, the semiconductor layer having one source/drain region, the other source/drain region, a channel region located between the one source/drain region and the other source/drain region and overlapping with the gate electrode in a plan view, and an LDD region located between the other source/drain region and the channel region;
a scanning line electrically connected to the gate electrode, extending along a first direction, and having a light-shielding property;
a first data line extending along a second direction intersecting the first direction, electrically connected to the one of the source/drain regions, protruding to one side along the first direction in a plan view, the first protruding portion overlapping the LDD region or the other of the source/drain regions in a plan view, and having a light-shielding property;
a light-shielding wiring that has a second protruding portion that protrudes in one direction along the first direction in a plan view and covers the first protruding portion, extends along the second direction, and has a light-shielding property;
An electro-optical device comprising:
The electro-optical device according to claim 4 , further comprising: a second data line that extends along the second direction so as to overlap the light-shielding wiring in a plan view and has a light-shielding property.
the first data line has a main body portion extending along the second direction,
The electro-optical device according to claim 4 , wherein the first protrusion protrudes from the main body along the first direction.
The gate electrode is
The electro-optical device according to claim 1 , wherein the scanning lines are provided in an island shape so as to cover a part of the scanning lines, and the island is wider than a line width of the scanning lines.
The semiconductor layer is
a portion of the other source/drain region overlaps with the scanning line in a plan view;
The electro-optical device according to claim 2 , wherein a remainder of the other source/drain region excluding a part of the other source/drain region overlaps with the second data line in a plan view.
a capacitance line extending along the second direction so as to overlap the second data line and the light-shielding line in a plan view;
a storage capacitor having a dielectric film sandwiched between the remaining portion of the other source/drain region and the capacitance wiring;
The electro-optical device according to claim 8 .
the light-shielding wiring is electrically connected to the capacitance wiring,
The electro-optical device according to claim 9 , wherein the second data line is disposed between the light-shielding wiring and the capacitance wiring.
An electronic device having the electro-optical device according to claim 1.

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