JP2024039952A - Semiconductor device and its manufacturing method - Google Patents

Abstract

[Problem] To provide a semiconductor device with an increased carrier lifetime. [Solution] The semiconductor device includes a first semiconductor layer of a first conductivity type containing a first conductivity type impurity, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer and having a lower concentration of the first conductivity type impurity than the first semiconductor layer, and a third semiconductor layer provided within the first semiconductor layer and having a hydrogen concentration of 5 x 1017 atoms/cm3 or more. [Selected Figure] Figure 1

Description

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are used for applications such as power conversion.

JP2019-009148A Patent No. 6662393 International Publication 2013/080417

The problem to be solved by the present invention is to provide a semiconductor device with increased carrier lifetime.

The semiconductor device of the embodiment includes a first semiconductor layer of a first conductivity type that includes an impurity of a first conductivity type, and a first semiconductor layer that is provided on the first semiconductor layer and has a lower concentration of the impurity of the first conductivity type than the first semiconductor layer. , a second semiconductor layer of a first conductivity type, and a third semiconductor layer provided within the first semiconductor layer and having a hydrogen concentration of 5×10 ¹⁷ atoms/cm ³ or more.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another aspect of the first embodiment. 3 is a graph showing impurity concentrations in the semiconductor device of the first embodiment. 7 is a graph showing carrier concentration in the semiconductor device of the first embodiment. 3 is a graph showing the hydrogen concentration and n-type carrier concentration before and after hydrogen plasma treatment in the semiconductor device of the first embodiment. 3 shows DLTS spectrum waveforms before and after hydrogen plasma treatment in the semiconductor device of the first embodiment. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same members and the like are given the same reference numerals, and the description of the members and the like that have been explained once will be omitted as appropriate.

In this specification, in order to indicate the positional relationship of parts, etc., the upper direction of the drawing is referred to as "upper", and the lower direction of the drawing is referred to as "lower". In this specification, the concepts of "upper" and "lower" do not necessarily indicate a relationship with the direction of gravity.

Hereinafter, a case where the first conductivity type is n type and the second conductivity type is p type will be described as an example.

In the following description, the notations n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represent relative levels of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ^- indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ^- indicates that the p-type impurity concentration is relatively lower than p. Note that n ⁺ type and n ⁻ type may be simply referred to as n type, and p ⁺ type and p ⁻ type may simply be referred to as p type.

(First embodiment)
The semiconductor device of the present embodiment includes a first semiconductor layer of a first conductivity type containing impurities of a first conductivity type, and a first semiconductor layer provided on the first semiconductor layer, the concentration of the impurity of the first conductivity type being lower than that of the first semiconductor layer. The semiconductor device includes a second semiconductor layer of a low first conductivity type, and a third semiconductor layer provided within the first semiconductor layer and having a hydrogen concentration of 5×10 ¹⁷ atoms/cm ³ or more.

The semiconductor device of this embodiment includes a first semiconductor region of the second conductivity type provided on the second semiconductor layer, and a second semiconductor region of the first conductivity type provided on the first semiconductor region. a semiconductor region, a first electrode provided in the first semiconductor region via a first insulating film in a trench reaching the second semiconductor layer from above the second semiconductor region, and a first electrode provided on the first electrode. a second insulating film, a second electrode provided on the second semiconductor region and the second insulating film, a fourth semiconductor layer provided under the first semiconductor layer, and a second insulating film provided under the fourth semiconductor layer. The semiconductor device further includes a third electrode provided in the semiconductor layer and electrically connected to the fourth semiconductor layer.

Alternatively, the semiconductor device of the present embodiment includes a first semiconductor region of a second conductivity type provided on a second semiconductor layer, and a second semiconductor region of a first conductivity type provided within the first semiconductor region. a first electrode provided on the first semiconductor region, a first insulating film provided between the first semiconductor region and the first electrode, and a second insulating film provided on the first electrode. a second electrode provided on the second semiconductor region and the second insulating film, a fourth semiconductor layer provided under the first semiconductor layer, and a second electrode provided under the fourth semiconductor layer; The semiconductor device further includes a third electrode electrically connected to the fourth semiconductor layer.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100a of this embodiment. The semiconductor device 100a is a vertical trench IGBT.

The semiconductor device 100a includes a semiconductor substrate 2, a collector electrode 4, a collector layer 6, a first buffer layer 8, a drift layer 10, a second buffer layer 12, an emitter electrode 20, a trench 30, and a gate insulator. It includes a film 40, a gate electrode 42, an emitter region 44, a contact region 46, an interlayer insulating film 48, and a base region 50.

The first buffer layer 8 is an example of a first semiconductor layer. Drift layer 10 is an example of a second semiconductor layer. The second buffer layer 12 is an example of a third semiconductor layer. Base region 50 is an example of a first semiconductor region. Emitter region 44 is an example of a second semiconductor region. The gate insulating film 40 is an example of a first insulating film. The gate electrode 42 is an example of a first electrode. The interlayer insulating film 48 is an example of a second insulating film. Emitter electrode 20 is an example of a second electrode. Collector layer 6 is an example of a fourth semiconductor layer. Collector electrode 4 is an example of a third electrode.

The semiconductor substrate 2 is, for example, a silicon (Si) substrate. However, the semiconductor substrate 2 may also be a substrate containing other semiconductor materials, such as a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. The semiconductor substrate 2 has a first surface 2a and a second surface 2b provided on the first surface 2a and facing the first surface 2a.

Here, when the semiconductor substrate 2 is a Si substrate, as the n-type impurity, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be preferably used. Furthermore, when the semiconductor substrate 2 is a Si substrate, boron (B), for example, can be used as the p-type impurity. Note that in this specification, hydrogen (H) is not included in either "n-type impurity" or "p-type impurity."

In addition, an X direction, a Y direction perpendicularly intersecting the X direction, and a Z direction perpendicularly intersecting the X direction and the Y direction are defined here. The first surface 2a and the second surface 2b are surfaces parallel to the XY plane. The "depth direction" of the semiconductor device 100a, which will be described later, is a direction parallel to the Z direction. FIG. 1 is a schematic cross-sectional view of the semiconductor device 100a in the YZ plane.

The first buffer layer 8 is provided within the semiconductor substrate 2 . The first buffer layer 8 is provided, for example, in parallel to the XY plane. The first buffer layer 8 is provided, for example, to suppress the extension of the depletion layer during switching of the IGBT. The first buffer layer 8 includes, for example, an n ⁺ type semiconductor material. The first buffer layer 8 contains n-type impurities, for example, in an amount of 1×10 ¹⁴ atoms/cm ³ or more and 1×10 ¹⁷ atoms/cm ³ or less. Note that the first buffer layer 8 contains hydrogen, for example, in an amount of 1×10 ¹⁴ atoms/cm ³ or more and 5×10 ¹⁷ atoms/cm ³ or less.

Drift layer 10 is provided within semiconductor substrate 2 . The drift layer 10 is provided, for example, on the first buffer layer 8 in parallel to the XY plane. Drift layer 10 includes, for example, an n ⁻ type semiconductor material. The drift layer 10 contains n-type impurities, for example, in an amount of 1×10 ¹² atoms/cm ³ or more and 1×10 ¹⁵ atoms/cm ³ or less.

Collector layer 6 is provided within semiconductor substrate 2 . For example, the collector layer 6 is provided below the first buffer layer 8 in parallel to the XY plane. Collector layer 6 includes, for example, a p ⁺ type semiconductor material. The collector layer 6 contains p-type impurities, for example, in an amount of 1×10 ¹⁶ atoms/cm ³ or more and 1×10 ¹⁹ atoms/cm ³ or less.

Collector electrode 4 is provided below first surface 2a of semiconductor substrate 2. Collector electrode 4 is provided below collector layer 6 . Collector electrode 4 is electrically connected to collector layer 6 .

The second buffer layer 12 is a region in which the concentration of hydrogen (H) is 5×10 ¹⁷ atoms/cm ³ or more. As will be described later, the second buffer layer 12 is formed by proton irradiation from the first surface 2a side, subsequent hydrogen plasma treatment on the first surface 2a, and subsequent annealing of the semiconductor substrate 2. The second buffer layer 12 is provided, for example, to suppress oscillation of V _ce (emitter-collector voltage) during switching of the IGBT.

The position where the second buffer layer 12 is provided differs depending on the manufacturing process of proton irradiation from the first surface 2a side, subsequent hydrogen plasma treatment on the first surface 2a, and subsequent annealing of the semiconductor substrate 2. For example, the second buffer layer 12 may be provided within the first buffer layer 8, as illustrated as the second buffer layer 12c in FIG. Further, the second buffer layer 12 may be provided over the collector layer 6 and the first buffer layer 8, as illustrated as the second buffer layer 12b in FIG. Further, the second buffer layer 12 may be provided over the collector layer 6, the first buffer layer 8, and the drift layer 10, as illustrated as the second buffer layer 12a in FIG. Further, for example, the second buffer layer 12 may be provided within the collector layer 6. Further, for example, the second buffer layer 12 may be provided within the drift layer 10. Further, for example, the second buffer layer 12 may be provided over the first buffer layer 8 and the drift layer 10. Note that when the second buffer layer 12 is provided within the first buffer layer 8 , the second buffer layer 12 is provided on the collector layer 6 .

Base region 50 is provided within semiconductor substrate 2 . Base region 50 is provided on drift layer 10 . Base region 50 includes, for example, a p-type semiconductor material. The base region 50 contains p-type impurities, for example, in an amount of 1×10 ¹⁶ atoms/cm ³ or more and 1×10 ¹⁸ atoms/cm ³ or less. FIG. 1 shows a base region 50a, a base region 50b, a base region 50c, and a base region 50d.

Emitter region 44 is provided within semiconductor substrate 2 . Emitter region 44 is provided above base region 50 . Emitter region 44 includes, for example, an n ⁺ type semiconductor material. The emitter region 44 is. It contains an n-type impurity, for example, in an amount of 1×10 ¹⁸ atoms/cm ³ or more and 1×10 ²¹ atoms/cm ³ or less. In FIG. 1, emitter region 44a, emitter region 44b, emitter region 44c, emitter region 44d, emitter region 44e, and emitter region 44f are illustrated.

Contact region 46 is provided within semiconductor substrate 2 . Contact region 46 is provided on base region 50 . Contact region 46 includes, for example, a p ⁺ type semiconductor material. The contact region 46 contains a p-type impurity, for example, in an amount of 1×10 ¹⁸ atoms/cm ³ or more and 1×10 ²¹ atoms/cm ³ or less. In FIG. 1, a contact region 46a, a contact region 46b, a contact region 46c, and a contact region 46d are provided. Contact region 46a is provided in contact with emitter region 44a. Contact region 46b is provided between emitter region 44b and emitter region 44c. Contact region 46c is provided between emitter region 44d and emitter region 44e. The contact region 46d is provided in contact with the emitter region 44f.

The gate electrode 42 is provided in the trench 30 reaching the drift layer 10 from above the emitter region 44 with the base region 50 and the gate insulating film 40 in between. The gate electrode 42 is provided in the trench 30 reaching the drift layer 10 from above the emitter region 44 and in the base region 50 with the gate insulating film 40 interposed therebetween. In FIG. 1, a gate electrode 42a, a gate electrode 42b, and a gate electrode 42c are illustrated. FIG. 1 also shows trenches 30a, 30b, and 30c. Further, FIG. 1 shows a gate insulating film 40a, a gate insulating film 40b, and a gate insulating film 40c. Gate electrode 42a is provided in trench 30a so as to face base region 50a and base region 50b with gate insulating film 40a in between. The gate electrode 42b is provided in the trench 30b so as to face the base region 50b and the base region 50c with the gate insulating film 40b interposed therebetween. The gate electrode 42c is provided in the trench 30c so as to face the base region 50c and the base region 50d with the gate insulating film 40c interposed therebetween.

Emitter electrode 20 is provided over emitter region 44 and contact region 46 .

Interlayer insulating film 48 is provided between gate electrode 42 and emitter electrode 20. Interlayer insulating film 48 insulates gate electrode 42 and emitter electrode 20 from each other. FIG. 1 shows an interlayer insulating film 48a, an interlayer insulating film 48b, and an interlayer insulating film 48c. The interlayer insulating film 48a is provided between the gate electrode 42a and the emitter electrode 20. The interlayer insulating film 48b is provided between the gate electrode 42b and the emitter electrode 20. The interlayer insulating film 48c is provided between the gate electrode 42c and the emitter electrode 20.

The gate insulating film 40 and the interlayer insulating film 48 include, for example, an insulator such as silicon oxide.

The collector electrode 4 and the emitter electrode 20 include a conductive material such as Al (aluminum), for example.

Gate electrode 42 includes, for example, a conductive material such as conductive polysilicon containing impurities.

FIG. 2 is a schematic cross-sectional view of a semiconductor device 100b according to another aspect of this embodiment. The semiconductor device 100b is a vertical planar IGBT.

In FIG. 2, a base region 50a and a base region 50b are illustrated.

Emitter region 44 is provided within base region 50 . In FIG. 2, emitter region 44a and emitter region 44b are illustrated. Emitter region 44a is provided within base region 50a. Emitter region 44b is provided within base region 50b.

Gate electrode 42 is provided on base region 50 .

Gate insulating film 40 is provided between gate electrode 42 and base region 50.

Emitter electrode 20 is provided on emitter region 44 and gate electrode 42 . Emitter electrode 20 is electrically connected to emitter region 44 .

Interlayer insulating film 48 is provided between gate electrode 42 and emitter electrode 20.

The semiconductor device 100a shown in FIG. 1 and the semiconductor device 100b shown in FIG. 2 are both preferred embodiments of the semiconductor device 100 of this embodiment.

FIG. 3 is a graph showing the impurity concentration in the semiconductor device 100 of this embodiment. The horizontal axis in FIG. 3 indicates the distance from the collector electrode 4 in a direction parallel to the Z direction. The longer the distance from the collector electrode 4, the closer it is to the second surface 2b.

Further, FIG. 3 shows impurity concentrations of boron ( ¹¹ B), phosphorus ( ³¹ P), and hydrogen ( ¹ H).

Further, FIG. 3 shows that the concentration of hydrogen in the second buffer layer 12 is 5×10 ¹⁷ atoms/cm ³ or more. In the example shown in FIG. 3, the second buffer layer 12 is provided across the collector layer 6 and the first buffer layer 8.

The concentration of hydrogen increases to around 2×10 ¹⁸ atoms/cm ³ as the distance from the collector electrode 4 increases. Here, the distance between the region where the concentration of hydrogen has increased to around 2×10 ¹⁸ atoms/cm ³ and the collector electrode 4 (or first surface 2a) is the projected range of protons. Range: Rp). Further, as the distance from the collector electrode 4 increases, the hydrogen concentration decreases relatively rapidly to around 2×10 ¹⁷ atoms/cm ³ . Thereafter, the hydrogen concentration decreases relatively slowly as the distance from the collector electrode 4 increases.

Note that the change in the hydrogen concentration with respect to the distance from the collector electrode 4 is not limited to that shown in FIG. 3.

FIG. 4 is a graph showing the carrier concentration in the semiconductor device 100 of this embodiment. The horizontal axis in FIG. 4 indicates the distance from the collector electrode 4 in a direction parallel to the Z direction. Figure 4 shows the carrier concentration of holes generated from boron ( ¹¹ B), the carrier concentration of electrons generated from phosphorus ( ³¹ P), and the carrier concentration “N ⁻ ” of electrons generated from hydrogen ( ¹ H). .

The dependence of the carrier concentration of holes generated from boron on the distance from the collector electrode 4 is almost the same as the dependence of the impurity concentration of boron on the distance from the collector electrode 4.

The dependence of the carrier concentration of electrons generated from phosphorus on the distance from the collector electrode 4 is almost the same as the dependence of the impurity concentration of phosphorus on the distance from the collector electrode 4.

The activation rate of hydrogen is lower than the activation rate of boron and the activation rate of phosphorus. The activation rate of hydrogen is about 1%. Therefore, the carrier concentration (N ⁻ ) of electrons generated from hydrogen is lower than the concentration of hydrogen.

Further, the concentration of hydrogen sharply increases to around 2×10 ¹⁸ atoms/cm ³ at a distance corresponding to the projected range of protons. However, the carrier concentration of electrons generated from hydrogen does not show the sharp increase seen in the concentration of hydrogen over a distance corresponding to the projected range of protons.

The carrier concentration (N ⁻ ) of electrons generated from hydrogen increases to around 1×10 ¹⁵ /cm ³ as the distance from the collector electrode increases. The carrier concentration of electrons generated from hydrogen gradually decreases as the distance from the collector electrode increases.

FIG. 5 is a graph showing the hydrogen concentration and n-type carrier concentration before and after hydrogen plasma treatment in the semiconductor device 100 of this embodiment. The n-type carrier concentration is almost the same before and after the hydrogen plasma treatment. On the other hand, after the hydrogen plasma treatment, the hydrogen concentration sharply increases to around 2×10 ¹⁸ atoms/cm ³ at a distance corresponding to the projected range of protons. In other words, the semiconductor device 100 of this embodiment has the second buffer layer 12 in which hydrogen with a low donor contribution rate is concentrated near a distance corresponding to the projected range of protons. That's true. Here, the concentration of hydrogen in the second buffer layer 12 is preferably 500 times or more higher than the n-type carrier concentration (concentration of first conductivity type carriers) in the second buffer layer 12.

Note that the impurity concentration within the semiconductor device 100 can be measured by, for example, secondary ion mass spectroscopy (SIMS).

Furthermore, the carrier concentration within the semiconductor device 100 can be measured by, for example, a spreading resistance analysis (SRA) method.

FIG. 6 shows DLTS (Deep Level Transient Spectroscopy) spectrum waveforms before and after hydrogen plasma treatment in the semiconductor device 100 of this embodiment. Peaks due to the first composite defect, the second composite defect, the third composite defect, and the fourth composite defect are observed.

Here, the measured temperature of the second complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the first complex defect measured by deep level transient spectroscopy. The measured temperature of the third complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the second complex defect measured by deep level transient spectroscopy. The measured temperature of the fourth complex defect measured by deep level transient spectroscopy is lower than the measured temperature of the third complex defect measured by deep level transient spectroscopy.

Note that FIG. 6 shows the absolute value of the signal intensity of the first composite defect before and after the hydrogen plasma treatment.

The first complex defect is a defect containing O (oxygen) and C (carbon). The second complex defect is a defect containing O (oxygen), C (carbon), and H (hydrogen). The third composite defect includes any one of O, C, H, Si, and V (vacancy), and is a defect different from the first composite defect and the second composite defect. The fourth composite defect includes any one of O, C, H, Si, and V (vacancy), and is a defect different from the first composite defect, the second composite defect, and the third composite defect.

The absolute value of the signal strength of the third composite defect and the absolute value of the signal strength of the fourth composite defect after the hydrogen plasma treatment are the same as the absolute value of the signal strength of the third composite defect and the fourth composite defect before the hydrogen plasma treatment. is smaller than the absolute value of the signal strength. This indicates that the amount of third complex defects and the amount of fourth complex defects were reduced by the hydrogen plasma treatment.

Here, the absolute value of the signal intensity of the first complex defect measured by deep level transient spectroscopy is the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy, and the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy is It is preferable that the absolute value of the signal intensity of the fourth composite defect measured by transient spectroscopy is four times or more higher than the sum of .

Furthermore, the absolute value of the signal intensity of the second complex defect measured by deep level transient spectroscopy is the same as the absolute value of the signal intensity of the third complex defect measured by deep level transient spectroscopy. It is preferable that the absolute value of the signal intensity of the fourth composite defect measured by spectroscopy is three times or more higher than the sum of.

Further, the carrier lifetime was measured by μ-PCD (Microwave Photo Conductivity Decay) method. While the carrier lifetime before hydrogen plasma treatment was 239.1 μsec, the carrier lifetime after hydrogen plasma treatment increased to 338.1 μsec. It is considered that the carrier lifetime increased because the hydrogen plasma treatment reduced the amount of third complex defects and the amount of fourth complex defects.

FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment.

The method for manufacturing a semiconductor device of the present embodiment includes starting from the first surface side of a semiconductor substrate having a first surface and a second surface provided on the first surface and opposite to the first surface. Forming a first semiconductor layer of a first conductivity type by implanting impurities, irradiating protons from the first surface side, performing hydrogen plasma treatment on the first surface side, and annealing the semiconductor substrate. Thus, a third semiconductor layer is formed in the first semiconductor layer and has a hydrogen concentration of 5×10 ¹⁷ atoms/cm ³ or more.

First, a semiconductor substrate 2 is prepared. Here, the semiconductor substrate 2 is, for example, an n-type silicon substrate containing phosphorus. Next, an IGBT element structure is formed on the second surface 2b side of the semiconductor substrate 2. That is, the base region 50, emitter region 44, contact region 46, trench 30, gate electrode 42, interlayer insulating film 48, and emitter electrode 20 are formed on the second surface 2b side of the semiconductor substrate 2 (S2).

Next, the first surface 2a of the semiconductor substrate 2 is ground to give the semiconductor substrate 2 a desired thickness (S4).

Next, for example, phosphorus is implanted from the first surface 2a side of the ground semiconductor substrate 2 by, for example, an ion implantation method to form an n-type first buffer layer 8 on the first surface 2a side. Further, from the first surface 2a side of the ground semiconductor substrate 2, for example, boron is implanted into a position shallower than the first buffer layer 8 (on the first surface 2a side) by, for example, an ion implantation method, and the first buffer layer 8 is A collector layer 6 is formed under the layer 8 (S6). The semiconductor substrate 2 between the first buffer layer 8 and the IGBT element structure is used as a drift layer 10.

Next, protons are irradiated from the first surface 2a side of the ground semiconductor substrate 2 (S8). Here, the proton irradiation is performed, for example, by a method using a cyclotron accelerator. The acceleration energy of protons is, for example, about 4 MeV. The amount of protons injected is, for example, 1.5×10 ¹⁴ /cm ² . Note that the proton irradiation may be performed by ion implantation.

Next, hydrogen plasma treatment is performed on the ground first surface 2a side of the semiconductor substrate 2 (S10). Here, the above hydrogen plasma treatment is performed for 5 minutes in an atmosphere at 400° C., for example.

Next, the semiconductor substrate 2 subjected to the above hydrogen plasma treatment is annealed in, for example, N ₂ gas (nitrogen gas) (S12). Here, the above-mentioned annealing is performed, for example, at 400° C. for 120 minutes.

As a result, the second buffer layer 12 is formed.

Next, the collector electrode 4 is formed on the first surface 2a side of the ground semiconductor substrate (S14). Thereby, the semiconductor device 100 of this embodiment is obtained.

Next, the effects of the semiconductor device 100 of this embodiment will be described.

During the IGBT switching process, V _ce sometimes vibrates and oscillates. Therefore, it has been desired to suppress such oscillation. Here, such oscillation is considered to occur because, for example, when the depletion layer spreads from the base region 50 to the drift layer 10 at turn-off of the IGBT, the accumulated carriers are reduced.

Therefore, the semiconductor device of the present embodiment includes a first semiconductor layer of a first conductivity type that contains impurities of a first conductivity type, and a first semiconductor layer that is provided on the first semiconductor layer and that contains impurities of the first conductivity type from the first semiconductor layer. The semiconductor device includes a second semiconductor layer of a first conductivity type having a low concentration, and a third semiconductor layer provided in the first semiconductor layer and having a hydrogen concentration of 5×10 ¹⁷ atoms/cm ³ or more.

FIG. 8 is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device of this embodiment.

FIG. 8A is a diagram schematically showing the hydrogen concentration in the depth direction in a semiconductor device that is a comparative form of this embodiment. Here, in the comparative semiconductor device, after proton irradiation from the first surface 2a side of the semiconductor substrate 2, annealing is performed without performing hydrogen plasma treatment.

By irradiating protons, it is possible to form an n-type semiconductor layer closer to the second surface 2b (deeper) than when using phosphorus, for example. This allows the number of carriers to be increased. However, crystal defects are concentrated and formed at a depth corresponding to the projected range of protons. There was a problem in that the carrier lifetime was shortened due to these crystal defects. Furthermore, even if annealing is performed to reduce crystal defects, there is a problem in that these crystal defects remain.

FIG. 8B is a diagram schematically showing the hydrogen concentration in the depth direction in the semiconductor device 100 of this embodiment. Here, in the semiconductor device 100 of this embodiment, after proton irradiation from the first surface 2a side of the semiconductor substrate 2, hydrogen plasma treatment is performed, and then annealing is performed.

In the semiconductor device 100 of this embodiment, hydrogen is trapped near a depth corresponding to the projected range of protons by hydrogen plasma treatment and subsequent annealing, and the second buffer layer 12 is formed. It is thought that the crystal defects formed by proton irradiation are hydrogen-terminated by hydrogen. The hydrogen concentration of the second buffer layer 12 is 5×10 ¹⁷ atoms/cm ³ or more, which is very high. Therefore, hydrogen termination is sufficiently performed. This greatly reduces carrier traps and increases carrier lifetime. Therefore, it becomes possible to suppress the oscillation of V _ce .

On the other hand, as explained using FIG. 5, hydrogen-terminated hydrogen has a low donor contribution rate and is considered not to contribute much to the n-type carrier concentration. It is preferable that the hydrogen concentration of the second buffer layer 12 is 500 times or more higher than the n-type carrier concentration of the second buffer layer 12. This is because in this case, since the hydrogen concentration is sufficiently high, crystal defects are successfully terminated with hydrogen, and the carrier lifetime is considered to be increased.

Furthermore, it is considered that the amount of the third complex defect and the amount of the fourth complex defect were reduced due to the above-mentioned hydrogen termination of the crystal defect.

The absolute value of the signal intensity measured by deep level transient spectroscopy of the first complex defect is the absolute value of the signal intensity measured by deep level transient spectroscopy of the third complex defect and the depth of the fourth complex defect. The carrier lifetime is decreased by reducing the amount of the third complex defect and the amount of the fourth complex defect so that the absolute value of the signal intensity measured by level transient spectroscopy is more than four times higher than the sum of It is preferable because it increases sufficiently.

The absolute value of the signal intensity measured by deep level transient spectroscopy of the second complex defect is the same as the absolute value of the signal intensity measured by deep level transient spectroscopy of the third complex defect and the depth of the fourth complex defect. The carrier lifetime is reduced by reducing the amount of third complex defects and the amount of fourth complex defects so that the absolute value of the signal intensity measured by level transient spectroscopy is three times higher than the sum of It is preferable because it increases sufficiently.

According to the semiconductor device of this embodiment, it is possible to provide a semiconductor device with increased carrier lifetime.

(Second embodiment)
In the semiconductor device of this embodiment, the third electrode of the semiconductor device of the first embodiment is replaced with a fifth electrode. Furthermore, in the semiconductor device of this embodiment, the fourth semiconductor layer of the semiconductor device of the first embodiment is replaced with a sixth semiconductor layer. Furthermore, in the semiconductor device of this embodiment, the second electrode of the first embodiment is replaced with a fourth electrode. Further, the semiconductor device of the present embodiment does not include the first semiconductor region, the second semiconductor region, the first electrode, the second electrode, the first insulating film, and the second insulating film of the semiconductor device of the first embodiment. The semiconductor device of this embodiment includes a fifth semiconductor layer. Here, the description of content that overlaps with the first embodiment will be omitted.

FIG. 9 is a schematic cross-sectional view of the semiconductor device 200 of this embodiment. The semiconductor device 200 of this embodiment is a PIN diode.

The semiconductor device 200 includes a semiconductor substrate 2, a cathode electrode 54, a cathode layer 56, a first buffer layer 8, a drift layer 10, a second buffer layer 12, an anode layer 62, and an anode electrode 70. Be prepared.

The anode layer 62 is an example of a fifth semiconductor layer. The anode electrode 70 is an example of a fourth electrode. The cathode layer 56 is an example of a sixth semiconductor layer. The cathode electrode 54 is an example of a fifth electrode.

Anode layer 62 is provided within semiconductor substrate 2 . Anode layer 62 is provided on drift layer 10 . Anode layer 62 includes, for example, a p-type semiconductor material. The anode layer 62 contains p-type impurities, for example, in an amount of 1×10 ¹⁶ atoms/cm ³ or more and 1×10 ²¹ atoms/cm ³ or less.

Anode electrode 70 is provided on anode layer 62. Anode electrode 70 is electrically connected to anode layer 62.

Cathode layer 56 is provided within semiconductor substrate 2 . The cathode layer 56 is provided, for example, under the first buffer layer 8 in parallel to the XY plane. Cathode layer 56 includes, for example, an n-type semiconductor material. The cathode layer 56 contains an n-type impurity, for example, in an amount of 1×10 ¹⁹ atoms/cm ³ or more and 1×10 ²¹ atoms/cm ³ or less.

Cathode electrode 54 is provided under semiconductor substrate 2 . Cathode electrode 54 is provided below cathode layer 56. Cathode electrode 54 is electrically connected to cathode layer 56.

The position where the second buffer layer 12 is provided differs depending on the manufacturing process of proton irradiation from the first surface 2a side, subsequent hydrogen plasma treatment on the first surface 2a, and subsequent annealing of the semiconductor substrate 2. For example, the second buffer layer 12 may be provided within the first buffer layer 8, as illustrated as the second buffer layer 12c in FIG. Further, the second buffer layer 12 may be provided over the cathode layer 56 and the first buffer layer 8, as shown as the second buffer layer 12b in FIG. Further, the second buffer layer 12 may be provided over the cathode layer 56, the first buffer layer 8, and the drift layer 10, as illustrated as the second buffer layer 12a in FIG. For example, the second buffer layer 12 may be provided within the cathode layer 56. Further, for example, the second buffer layer 12 may be provided within the drift layer 10. Further, for example, the second buffer layer 12 may be provided over the first buffer layer 8 and the drift layer 10. Note that when the second buffer layer 12 is provided within the first buffer layer 8 , the second buffer layer 12 is provided on the cathode layer 56 .

The anode electrode 70 and the cathode electrode 54 include a conductive material such as Al (aluminum), for example.

The semiconductor device of this embodiment also makes it possible to provide a semiconductor device with increased carrier lifetime.

Although several embodiments and examples of the invention have been described, these embodiments and examples are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

2: Semiconductor substrate 2a: First surface 2b: Second surface 4: Collector electrode (third electrode)
6: Collector layer (fourth semiconductor layer)
8: First buffer layer (first semiconductor layer)
10: Drift layer (second semiconductor layer)
12: Second buffer layer (third semiconductor layer)
20: Emitter electrode (second electrode)
30: Trench 40: Gate insulating film (first insulating film)
42: Gate electrode (first electrode)
44: Emitter region (second semiconductor region)
46: Contact region 48: Interlayer insulating film (second insulating film)
50: Base region (first semiconductor region)
54: Cathode electrode (fifth electrode)
56: Cathode layer (sixth semiconductor layer)
62: Anode layer (fifth semiconductor layer)
70: Anode electrode (4th electrode)
100: Semiconductor device 100a: Semiconductor device 100b: Semiconductor device 200: Semiconductor device

Claims (9)

a first conductivity type first semiconductor layer containing a first conductivity type impurity;
a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower concentration of impurities of the first conductivity type than the first semiconductor layer;
a third semiconductor layer provided in the first semiconductor layer and having a hydrogen concentration of 5×10 ¹⁷ atoms/cm ³ or more;
A semiconductor device comprising: The concentration of hydrogen in the third semiconductor layer is 500 times or more higher than the concentration of carriers of the first conductivity type in the third semiconductor layer.
A semiconductor device according to claim 1. The third semiconductor layer is
a first compound defect;
a second composite defect whose measured temperature is lower as measured by deep level transient spectroscopy than the measured temperature of the first composite defect measured by deep level transient spectroscopy;
a third composite defect whose measured temperature is lower as measured by deep level transient spectroscopy than the measured temperature of the second composite defect measured by deep level transient spectroscopy;
a fourth composite defect whose measured temperature is lower by deep level transient spectroscopy than the measured temperature of the third composite defect measured by deep level transient spectroscopy;
including;
The absolute value of the signal intensity of the first composite defect measured by deep level transient spectroscopy is the same as the absolute value of the signal intensity of the third composite defect measured by deep level transient spectroscopy. The absolute value of the signal intensity of the fourth composite defect measured by spectroscopy is four times or more higher than the sum of
A semiconductor device according to claim 1. The third semiconductor layer is
a first compound defect;
a second composite defect whose measured temperature is lower as measured by deep level transient spectroscopy than the measured temperature of the first composite defect measured by deep level transient spectroscopy;
a third composite defect whose measured temperature is lower as measured by deep level transient spectroscopy than the measured temperature of the second composite defect measured by deep level transient spectroscopy;
a fourth composite defect whose measured temperature is lower as measured by deep level transient spectroscopy than the measured temperature of the third composite defect measured by deep level transient spectroscopy;
including;
The absolute value of the signal intensity of the second composite defect measured by deep level transient spectroscopy is the same as the absolute value of the signal intensity of the third composite defect measured by deep level transient spectroscopy. The absolute value of the signal intensity of the fourth composite defect measured by spectroscopy is three times or more higher than the sum of
A semiconductor device according to claim 1. a first semiconductor region of a second conductivity type provided on the second semiconductor layer;
a second semiconductor region of a first conductivity type provided on the first semiconductor region;
a first electrode provided in the first semiconductor region via a first insulating film in a trench reaching the second semiconductor layer from above the second semiconductor region;
a second insulating film provided on the first electrode;
a second electrode provided on the second semiconductor region and the second insulating film;
a fourth semiconductor layer provided under the first semiconductor layer;
a third electrode provided under the fourth semiconductor layer and electrically connected to the fourth semiconductor layer;
The semiconductor device according to claim 1, further comprising: a first semiconductor region of a second conductivity type provided on the second semiconductor layer;
a second semiconductor region of a first conductivity type provided within the first semiconductor region;
a first electrode provided on the first semiconductor region;
a first insulating film provided between the first semiconductor region and the first electrode;
a second insulating film provided on the first electrode;
a second electrode provided on the second semiconductor region and the second insulating film;
a fourth semiconductor layer provided under the first semiconductor layer;
a third electrode provided under the fourth semiconductor layer and electrically connected to the fourth semiconductor layer;
The semiconductor device according to claim 1, further comprising: The third semiconductor layer is provided across the first semiconductor layer and the fourth semiconductor layer,
The semiconductor device according to claim 5 or claim 6. a fifth semiconductor layer of a second conductivity type provided on the second semiconductor layer;
a fourth electrode provided on the fifth semiconductor layer and electrically connected to the fifth semiconductor layer;
a sixth semiconductor layer provided under the first semiconductor layer;
a fifth electrode provided under the sixth semiconductor layer and electrically connected to the sixth semiconductor layer;
The semiconductor device according to claim 1, further comprising: The third semiconductor layer is provided across the first semiconductor layer and the sixth semiconductor layer,
The semiconductor device according to claim 8.

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