JP2024037259A - semiconductor equipment - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device that has both good assemblability during manufacturing and high breakdown resistance. The present invention includes a first P-type semiconductor layer, a first N-type semiconductor layer disposed on the first P-type semiconductor layer, and a first N-type semiconductor layer disposed on the first N-type semiconductor layer. a second P-type semiconductor layer, an emitter layer 14 disposed on the second P-type semiconductor layer, and a gate electrode 15 disposed on the second P-type semiconductor layer. 18, the periphery of the second P-type semiconductor layer directly under the gate electrode 15 is surrounded by an emitter layer 14, and the gate electrode 15 is located between the center of the thyristor 18 and the outer periphery of the thyristor 18 in plan view. This is a semiconductor device located on the side closer to the [Selection diagram] Figure 1

Description

The present invention relates to a semiconductor device.

In conventional thyristors, the gate electrode is located at the corner of the chip. A gate current is applied to this thyristor from the gate electrode, and the thyristor shifts from OFF to ON at a rate of current increase with a certain slope from around the gate electrode.

Depending on the usage example, a current flows from the anode of the thyristor at a steep rate of current increase due to discharge from a parasitic smoothing capacitor, etc., leading to destruction at locations around the gate electrode where current concentration is likely to occur. This breakdown resistance is called the critical current rise rate (di/dt).

In order to improve this breakdown resistance, a center gate thyristor has been proposed (see, for example, FIG. 2 of Patent Document 1). This center gate means that the gate electrode is arranged at the center of the thyristor in plan view.

When the gate electrode is located at the center of the thyristor chip, the design of the connector becomes more difficult than when the gate electrode is located at the corner of the chip, as the connector connected to the gate electrode must be longer during assembly. Therefore, it is desirable for the gate electrode to be located close to the corner of the chip in terms of manufacturing.

Therefore, there is a need for a semiconductor device that has both good assemblability during manufacturing and high breakdown resistance.

JP2019-160923A

Various aspects of the present invention aim to provide a semiconductor device that has both good assemblability during manufacturing and high breakdown resistance.

Various aspects of the present invention will be explained below.

[1] A first first conductivity type semiconductor layer;
a first second conductivity type semiconductor layer disposed on the first first conductivity type semiconductor layer;
a second first conductivity type semiconductor layer disposed on the first second conductivity type semiconductor layer;
a second second conductivity type semiconductor layer disposed on the second first conductivity type semiconductor layer;
a gate electrode disposed on the second first conductivity type semiconductor layer;
Equipped with a thyristor having
The second first conductivity type semiconductor layer immediately below the gate electrode is surrounded by the second second conductivity type semiconductor layer,
A semiconductor device characterized in that, in plan view, the gate electrode is arranged closer to the outer periphery of the thyristor with respect to the center of the thyristor.

According to the semiconductor device according to the above [1] of one aspect of the present invention, since the gate electrode is arranged on the side closer to the outer periphery of the thyristor with respect to the center of the thyristor in plan view, the connection connected to the gate electrode during assembly There is no need to lengthen the connector (including electrodes, clips, terminals, etc.), and the design of the connector becomes easier. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with conventional center gate thyristors, and to improve the assembling during manufacturing. Further, it is possible to avoid complication of the probe unit of the prober that selects whether the chip is good or bad.
In addition, the second first conductivity type semiconductor layer directly under the gate electrode is surrounded by a second second conductivity type semiconductor layer. Therefore, since the entire outer periphery of the gate electrode or the second first conductivity type semiconductor layer immediately below the gate electrode is in contact with the second second conductivity type semiconductor layer, only a part of the conventional gate electrode is connected to the second conductivity type semiconductor layer. Current concentration can be alleviated compared to a thyristor in contact with a two-conductivity type semiconductor layer. In other words, since the entire outer periphery of the gate electrode is in contact with the second second conductivity type semiconductor layer, the direction in which the gate current flows is not limited, and it is possible to suppress the occurrence of areas where current concentrates on the gate electrode. As a result, current concentration can be alleviated. Therefore, the breakdown resistance of the thyristor can be increased.
According to the above description, it is possible to provide a semiconductor device including a thyristor that has both good assemblability during manufacturing and high breakdown resistance.

[2] In [1] above,
A semiconductor device characterized in that the planar shape of the thyristor is polygonal, circular, or elliptical.

[3] In [2] above,
The semiconductor device is characterized in that the gate electrode is disposed on a side closer to a side of the polygon with respect to the center of the polygon in plan view.

According to the semiconductor device according to the above aspect [3] of the present invention, since the gate electrode is arranged on the side closer to the side of the polygon with respect to the center of the polygon in plan view, it is connected to the gate electrode during assembly. There is no need to make the connector longer, and the design of the connector becomes easier. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with conventional center gate thyristors, and to improve the assembling during manufacturing. Further, it is possible to avoid complication of the probe unit of the prober that selects whether the chip is good or bad.

[4] In [2] above,
The semiconductor device is characterized in that the gate electrode is disposed at a position close to a corner of the polygon with respect to a center of the polygon when viewed in plan.

According to the semiconductor device according to the above aspect [4] of the present invention, by arranging the gate electrode at a position close to the corner of the polygon, there is no need to lengthen the connector connected to the gate electrode during assembly. Connector design also becomes easier. Furthermore, since it becomes possible to shorten the length of the connector, it is expected that internal resistance will be reduced, and gate loss will be reduced.

[5] In any one of the above [1] to [4],
A semiconductor device characterized in that the distance between the center of the gate electrode and the outer periphery of the thyristor is shorter than the distance between the center of the gate electrode and the center of the thyristor in plan view.

According to the semiconductor device according to the above item [5] of one aspect of the present invention, the distance between the center of the gate electrode and the outer periphery of the thyristor is shorter than the distance between the center of the gate electrode and the center of the thyristor. In some cases, the connector (including electrodes, clips, terminals, etc.) connected to the gate electrode can be shortened to some extent, and the design of the connector becomes easier. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with conventional center gate thyristors, and to improve the assembling during manufacturing.

[6] In any one of the above [1] to [4],
A semiconductor device characterized in that the gate electrode has a circular, elliptical, or rectangular planar shape in plan view.

According to various aspects of the present invention, it is possible to provide a semiconductor device that has both good assemblability during manufacturing and high breakdown resistance.

1 is a plan view showing a semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA' shown in FIG. 1. FIG. 2 is a plan view showing a modification of the thyristor 18 shown in FIG. 1. FIG. FIG. 2 is a plan view for explaining the effects of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a plan view showing a conventional semiconductor device.

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the form and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA' shown in FIG.

The semiconductor device according to [1] above according to one aspect of the present invention includes a first first conductivity type semiconductor layer 11 and a first second conductivity type semiconductor layer disposed on the first first conductivity type semiconductor layer 11. type semiconductor layer 12, a second first conductivity type semiconductor layer 13 disposed on the first second conductivity type semiconductor layer 12, and a second first conductivity type semiconductor layer 13 disposed on the second first conductivity type semiconductor layer 13. The thyristor 18 includes a second second conductivity type semiconductor layer 14 and a gate electrode 15 disposed on the second first conductivity type semiconductor layer 13, and the second thyristor 18 is provided directly below the gate electrode 15. The periphery of the first conductivity type semiconductor layer 13 is surrounded by the second second conductivity type semiconductor layer 14, and the gate electrode 15 is located at the outer periphery of the thyristor 18 with respect to the center of the thyristor 18 in plan view. It is placed on the side closest to.

This will be explained in detail below.
This semiconductor device has a thyristor 18 having a rectangular planar shape, and this thyristor 18 has a first first conductivity type semiconductor layer 11 as shown in FIG. The first first conductivity type semiconductor layer 11 is, for example, a first P type semiconductor layer (first P ⁺ type impurity diffusion layer).

A first second conductive type semiconductor layer 12 is arranged on the first first conductive type semiconductor layer (first P type semiconductor layer) 11 . The first second conductivity type semiconductor layer 12 is, for example, a first N-type semiconductor layer (first N ^- type semiconductor layer).

A second first conductivity type semiconductor layer 13 is arranged on the first second conductivity type semiconductor layer (first N type semiconductor layer) 12 . The second first conductivity type semiconductor layer 13 is, for example, a second P type semiconductor layer (second P ⁺ type impurity diffusion layer).

A second second conductive type semiconductor layer 14 is arranged on the second first conductive type semiconductor layer (second P type semiconductor layer) 13 . This second second conductivity type semiconductor layer 14 is an emitter layer. The second second conductive type semiconductor layer 14 is, for example, a second N type semiconductor layer (second N ⁺ type impurity diffusion layer).

A gate electrode 15 is arranged on the second first conductivity type semiconductor layer 13 . The thyristor 18 shown in FIG. 2 includes a first semiconductor layer 11 of the first conductivity type, a first semiconductor layer 12 of the second conductivity type, a second semiconductor layer 13 of the first conductivity type, and a second semiconductor layer of the second conductivity type. (emitter layer) 14.

To explain in detail, as shown in FIG. 2, a first first conductivity type semiconductor layer (first P type semiconductor layer) 11 and a first second conductivity type semiconductor layer (first N type semiconductor layer) 12 are in contact with each other, and the first N-type semiconductor layer 12 and the second first conductivity type semiconductor layer (second P-type semiconductor layer) 13 are in contact with each other. Further, the first P-type semiconductor layer 11 and the second P-type semiconductor layer 13 are electrically separated by an insulating layer (passivation) 31, and the first N-type semiconductor layer 12 and the second second conductive layer The type semiconductor layer (emitter layer) 14 is electrically isolated by an insulating layer 31.

In other words, the insulating layer 31 serves as a passivation for the junction between the first P-type semiconductor layer 11 and the first N-type semiconductor layer 12, and serves as a junction between the first N-type semiconductor layer 12 and the second P-type semiconductor layer 13. This is the passivation of the junction between the emitter electrode (emitter layer) 14 and the gate electrode 15.

As shown in FIGS. 1 and 2, the second first conductivity type semiconductor layer (second P ⁺ type impurity diffusion layer) 13 immediately below the gate electrode 15 is surrounded by a second second conductivity type semiconductor layer. (emitter layer) 14.

As shown in FIG. 1, the planar shape of the thyristor 18 is a polygon (for example, a quadrilateral 19). Note that the planar shape of the thyristor is not limited to a polygon, but may be circular or elliptical. Further, when the planar shape is a polygon, the corners do not need to be sharp and may be curved.

According to this embodiment, since the gate electrode 15 is arranged closer to the outer periphery of the thyristor with respect to the center of the thyristor in plan view, the connectors (electrodes, clips, terminals, etc.) connected to the gate electrode 15 during assembly are also There is no need to lengthen the connector (including the connector), and the design of the connector becomes easier. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with the conventional center gate thyristor, and it is possible to improve the assembling during manufacturing. Further, it is possible to avoid complication of the probe unit of the prober that selects whether the chip is good or bad.
In addition, the periphery of the second first conductivity type semiconductor layer (second P type semiconductor layer) 13 directly under the gate electrode 15 is a second second conductivity type semiconductor layer (second N type emitter layer). type semiconductor layer) 14 (see FIGS. 1 and 2). Therefore, since the entire outer circumference of the gate electrode 15 or the second P-type semiconductor layer 13 directly under the gate electrode 15 is in contact with the emitter layer 14, the current flow is higher than in a conventional thyristor in which only a part of the gate electrode is in contact with the emitter layer. Concentration can be eased. In other words, since the entire outer periphery of the gate electrode 15 is in contact with the emitter layer 14, the direction in which the gate current flows is not limited, and the occurrence of areas where current is concentrated on the gate electrode 15 can be suppressed, and as a result, the current It can relieve concentration. Therefore, the breakdown resistance of the thyristor can be increased.
According to the above description, it is possible to provide a semiconductor device including a thyristor that has both good assemblability during manufacturing and high breakdown resistance.

As shown in FIG. 1, the gate electrode 15 is disposed on the side closer to the side 17 of the polygon (quadrangular) 19 with respect to the center of the polygon (for example, a quadrangle) 19 in plan view. Note that the polygons (quadrilaterals) 19 include those whose corners are not sharp, and also include those whose corners are curved, for example. Further, as long as the gate electrode 15 is placed on the side close to the side 17 of the polygon (quadrangular) 19, it may be placed on the corner 20 as shown in FIG. 1, or on the side 17 as shown in FIG. It may be arranged at the center 21 of. In this embodiment, the polygon 19 is described as a quadrilateral, but other polygons such as pentagons, hexagons, etc. may be used. 3 shows a thyristor 18a that is a modification of the thyristor 18 shown in FIG. 1, and the same parts as in FIG. 1 are given the same reference numerals.

According to this embodiment, since the gate electrode 15 is arranged on the side closer to the side 17 of the rectangle 19 with respect to the center of the rectangle 19 in plan view, it is not necessary to lengthen the connector connected to the gate electrode 15 during assembly. Therefore, the design of the connector becomes easy. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with conventional center gate thyristors, and to improve the assembling during manufacturing. Further, it is possible to avoid complication of the probe unit of the prober that selects whether the chip is good or bad.
In addition, the periphery of the second first conductivity type semiconductor layer (second P type semiconductor layer) 13 directly under the gate electrode 15 is a second second conductivity type semiconductor layer (second N type emitter). (see FIGS. 1 and 2). Therefore, the entire outer periphery of the gate electrode 15 or the second P-type semiconductor layer 13 directly under the gate electrode 15 is in contact with the emitter 14, so current concentration is reduced compared to a conventional thyristor in which only a portion of the gate electrode is in contact with the emitter. It can be relaxed. In other words, since the entire outer periphery of the gate electrode 15 is in contact with the emitter 14, the direction in which the gate current flows is not limited, and the occurrence of areas where current is concentrated on the gate electrode 15 can be suppressed. can be alleviated. Therefore, the breakdown resistance of the thyristor can be increased.
According to the above description, it is possible to provide a semiconductor device including a thyristor that has both good assemblability during manufacturing and high breakdown resistance.

As shown in FIG. 1, the gate electrode 15 is preferably disposed at a position close to the corner 20 of the polygon (quadrangular) 19 with respect to the center of the polygon (quadrangular) 19 in plan view.
In this case as well, effects similar to those described above can be obtained.

Furthermore, by arranging the gate electrode 15 close to the corner 20 of the polygon (quadrangular) 19, assembly is easier than in the semiconductor device shown in FIG. ) by making it possible to further shorten the length of the connector (not shown), which is expected to reduce internal resistance and reduce gate loss.
Further, the distance 16 between the center of the gate electrode 15 and the outer periphery of the thyristor in plan view is preferably shorter than the distance 16a between the center of the gate electrode 15 and the center of the thyristor (see FIGS. 1 and 3). As a result, the connector (including electrodes, clips, terminals, etc.) connected to the gate electrode 15 during assembly can be shortened to some extent, and the design of the connector is also facilitated. Therefore, it is possible to avoid the difficulty of assembling during manufacturing, which is the case with the conventional center gate thyristor, and it is possible to improve the assembling during manufacturing.

As shown in FIG. 1, the distance between the center of the gate electrode 15 and the outer periphery of the thyristor (for example, the distance 16 between the center of the gate electrode 15 and the outer periphery of the thyristor) is the distance between the center of the electrode 15 and the opposite side of the outer periphery of the thyristor 17. It is desirable that the distance be greater than the ratio of the surge current withstand capacity and the current value under the di/dt test conditions. This is to prevent localized locations with weak surge current resistance from occurring. Note that the surge current withstand capacity is, for example, an actual value, and the actual value is a current value that causes the element to break down. Furthermore, the current value under di/dt test conditions is the on-current specified in EIAJ-4521. The current value under the di/dt test conditions may be changed to the current value flowing from a smoothing capacitor or the like in the actual circuit. The current value flowing from a smoothing capacitor or the like in an actual circuit is a discharge current from the smoothing capacitor, and is determined by the capacitance of the capacitor.
Depending on the position of the gate, the current will locally concentrate in the emitter layer 14 surrounded by the corner 20 or the side 19, and the location must not be such that it will break down below the surge withstand capacity. It is determined by the balance between the conditions during the withstand test and the gate area. Note that EIAJ-ED4521 is a standard for ratings, characteristics, and test methods for 3-terminal thyristors, an electronic device item of JEITA (Japan Electronics and Information Technology Industries Association).

As shown in FIGS. 1 and 3, the gate electrode 15 has a circular shape in plan view, but may have an elliptical shape, a rectangular shape, or the like.

Next, the effects of this embodiment will be explained in detail using FIGS. 4 and 5.
An arrow 101 shown in FIGS. 4 and 5 indicates a current path at the time of transition from OFF to ON (at the time of ignition). By making the area of the gate electrode 15 in contact with the emitter layer 14 of the thyristor according to the present embodiment shown in FIG. 4 larger than the area of the gate electrode 15a in contact with the emitter layer 14a of the conventional thyristor shown in FIG. This prevents electric field from concentrating on the area.

The gate electrode 15 only needs to have an area large enough to allow a current to flow as a trigger, and the smaller the area, the better. When the gate electrode 15 shown in FIG. 4, which has the same area as the planar area of the gate electrode 15a shown in FIG. In the thyristor shown in FIG. 4 in which the gate electrode 15 is not arranged at the corner of the emitter layer 14, the effective gate peripheral length in which the current spreads during ON transition (critical time) becomes large. In reality, as shown in FIG. 2, since it is diffused in the depth direction, the area is equivalent to increasing.

On the other hand, the critical current increase rate is generally on the order of A/μs, which causes destruction of the thyristor. The mobility of electrons is expressed in "cm ² /V·s", and the mobility per unit time μs is several mm ² or less. Since it is more effective to secure the entire outer periphery of the gate electrode than the influence of planar expansion on the emitter layer, its position does not have to be in the center, and may be located at a position that emphasizes ease of assembly. . The area around the gate depends on the guaranteed withstand voltage of the thyristor.

In short, when the emitter layer 14 surrounds the gate electrode 15 as shown in FIG. The area becomes larger. Regarding the mobility, the electron mobility is slow at several μm ² /V・s compared to the value of the critical current increase rate di/dt, and even if the gate electrode 15 is located near the corner as shown in FIG. There is no need to worry about carriers losing their destination due to the emitter layer 14 being narrow, and the effects of this embodiment can be achieved if the island-shaped gate is used in a location where it is easy to assemble.

In short, when the emitter layer 14 surrounds the gate electrode 15 as shown in FIG. The area becomes larger. Regarding the mobility, compared to the value of the critical current increase rate di/dt, the electron mobility is about several mm ² /V・s, and even if the gate electrode 15 is located near the corner as shown in FIG. , the corner 20 or the side 19, if a carrier destination can be secured, the effects of this embodiment can be achieved with an island-shaped gate at a location where it is easy to assemble.

As for the unit of mobility, it is sufficient to consider at what speed cm/s electrons and holes move when an electric field of 1 V/cm is applied.
(cm/s)/(V/cm)= ^cm2 /(V・s)

11 First first conductivity type semiconductor layer (first P type semiconductor layer, first P ⁺ type impurity diffusion layer)
12 First second conductivity type semiconductor layer (first N-type semiconductor layer, first N ^- type semiconductor layer)
13 Second first conductivity type semiconductor layer (second P type semiconductor layer, second P ⁺ type impurity diffusion layer)
14 Second second conductivity type semiconductor layer (emitter layer, second N type semiconductor layer, second N ⁺ type impurity diffusion layer distance)
17 Sides of polygon (sides of quadrilateral)
18 Thyristor 19 Polygon (square)
20 corner

Claims (6)

a first first conductivity type semiconductor layer;
a first second conductivity type semiconductor layer disposed on the first first conductivity type semiconductor layer;
a second first conductivity type semiconductor layer disposed on the first second conductivity type semiconductor layer;
a second second conductivity type semiconductor layer disposed on the second first conductivity type semiconductor layer;
a gate electrode disposed on the second first conductivity type semiconductor layer;
Equipped with a thyristor having
The second first conductivity type semiconductor layer immediately below the gate electrode is surrounded by the second second conductivity type semiconductor layer,
A semiconductor device characterized in that, in a plan view, the gate electrode is arranged closer to the outer periphery of the thyristor with respect to the center of the thyristor. In claim 1,
A semiconductor device characterized in that the planar shape of the thyristor is polygonal, circular, or elliptical. In claim 2,
The semiconductor device is characterized in that the gate electrode is disposed on a side closer to a side of the polygon with respect to the center of the polygon in plan view. In claim 2,
The semiconductor device is characterized in that the gate electrode is disposed at a position close to a corner of the polygon with respect to a center of the polygon when viewed in plan. In any one of claims 1 to 4,
A semiconductor device characterized in that the distance between the center of the gate electrode and the outer periphery of the thyristor is shorter than the distance between the center of the gate electrode and the center of the thyristor in plan view. In any one of claims 1 to 4,
A semiconductor device characterized in that the gate electrode has a circular, elliptical, or rectangular planar shape in plan view.

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