JP2024034660A - Semiconductor device, inverter circuit, driving device, vehicle, and elevator - Google Patents

Abstract

To provide a semiconductor device capable of improving a surge current tolerance.SOLUTION: A semiconductor device according to an embodiment includes a semiconductor chip having a transistor region and a diode region, a first conductor, and a second conductor. The semiconductor chip includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and a gate electrode. The transistor region is provided with a third electrode spaced apart from the first electrode and close to the diode region. One end of the first conductor is in contact with the first electrode, and one end of the second conductor is in contact with the third electrode.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

Silicon carbide is expected to be a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties compared to silicon, such as a band gap three times larger, a breakdown electric field strength about ten times greater, and a thermal conductivity about three times greater. By utilizing this characteristic, it is possible to realize, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that has high breakdown voltage, low loss, and can operate at high temperatures.

A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, even when the MOSFET is off, the built-in diode allows a return current to flow.

However, when a return current is caused to flow using a body diode, there is a problem that stacking faults grow in the silicon carbide layer due to the recombination energy of carriers, and the on-resistance of the MOSFET increases. An increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates unipolarly as a built-in diode in a MOSFET, it is possible to suppress the growth of stacking faults in a silicon carbide layer. The reliability of the MOSFET is improved by providing the SBD as a built-in diode in the MOSFET.

A large surge current exceeding the steady state may momentarily flow through the MOSFET. When a large surge current flows, a large surge voltage is applied, heat is generated, and the MOSFET is destroyed. The maximum allowable peak current value ( _IFSM ) of the surge current allowed by the MOSFET is called the surge current withstand capacity. It is desired to improve surge current withstand capability in a MOSFET provided with an SBD.

Patent No. 7004117

An object of the present invention is to provide a semiconductor device with improved surge current resistance.

A semiconductor device according to an embodiment is a semiconductor chip including a plurality of transistor regions and at least one diode region, wherein the plurality of transistor regions include a first surface and a second surface opposite to the first surface. an n-type first silicon carbide region having a plurality of first portions in contact with the first surface; and between the first silicon carbide region and the first surface; A silicon carbide layer including a p-type second silicon carbide region provided and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface. a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the silicon carbide region, and a gate insulating layer provided between the gate electrode and the second silicon carbide region, the at least one diode region facing the first surface. the first n-type silicon carbide region having a plurality of second portions in contact with the first silicon carbide region; and the fourth p-type silicon carbide region provided between the first silicon carbide region and the first surface. the silicon carbide layer including a region, the first electrode in contact with the plurality of second portions and the fourth silicon carbide region, and the second electrode, the first surface The occupied area per unit area of the fourth silicon carbide region projected onto the first surface is larger than the occupied area per unit area of the second silicon carbide region projected onto the first surface, and A first diode region that is one of the diode regions is provided in a first direction with respect to a first transistor region that is one of the plurality of transistor regions and the first transistor region. a second transistor region that is one of the plurality of transistor regions, and the first transistor region is provided on the first surface side of the silicon carbide layer and is connected to the first electrode. a first conductor having one end in contact with the first electrode and applying a voltage to the first electrode; a first conductor having one end in contact with the third electrode; , a second conductor that applies a voltage to the third electrode.

FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment. FIG. 1 is a schematic top view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic top view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic top view of a semiconductor device according to a first embodiment. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. FIG. 3 is a schematic top view of a semiconductor device of a first comparative example. FIG. 3 is a schematic cross-sectional view of a semiconductor device of a first comparative example. FIG. 3 is an equivalent circuit diagram of a semiconductor device of a first comparative example. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view of a semiconductor device of a second comparative example. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view of a modification of the first embodiment. FIG. 3 is a schematic top view of a semiconductor device according to a second embodiment. FIG. 7 is a schematic top view of a semiconductor device according to a third embodiment. FIG. 4 is a schematic diagram of a drive device according to a fourth embodiment. FIG. 3 is a schematic diagram of a vehicle according to a fifth embodiment. FIG. 6 is a schematic diagram of a vehicle according to a sixth embodiment. Schematic diagram of the elevator of the seventh embodiment

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar members will be denoted by the same reference numerals, and the description of the members that have already been explained may be omitted as appropriate.

Furthermore, in the following description, when the notations n ⁺ , n, n ^- and p ⁺ , p, p ^- are used, the above notations represent relative levels of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ^- indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ^- indicates that the p-type impurity concentration is relatively lower than p. Note that n ⁺ type and n ⁻ type may be simply referred to as n type, and p ⁺ type and p ⁻ type may simply be referred to as p type.

The impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). Further, the relative level of impurity concentration can also be determined from the level of carrier concentration determined by scanning capacitance microscopy (SCM), for example. Furthermore, distances such as the depth and thickness of the impurity region can be determined by, for example, SIMS. Also. The depth, thickness, width, spacing, and other distances of impurity regions can be determined, for example, from a composite image of an SCM image and an atomic force microscope (AFM) image.

In this specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region, unless otherwise specified.

(First embodiment)
The semiconductor device of the first embodiment is a semiconductor chip including a plurality of transistor regions and at least one diode region, wherein the plurality of transistor regions include a first surface and a first surface facing the first surface. an n-type first silicon carbide region having a second surface and a plurality of first portions in contact with the first surface; and an n-type first silicon carbide region provided between the first silicon carbide region and the first surface. a silicon carbide layer including a p-type second silicon carbide region and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the first portion, a second silicon carbide region, and a third silicon carbide region; a second electrode in contact with the second surface; and a gate electrode facing the second silicon carbide region. and a gate insulating layer provided between the gate electrode and the second silicon carbide region, the at least one diode region having a plurality of second portions in contact with the first surface. a silicon carbide layer including a first silicon carbide region and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface; and a plurality of second portions. and a first electrode in contact with the fourth silicon carbide region, and a second electrode, and the occupied area per unit area of the fourth silicon carbide region projected onto the first surface is equal to that of the first The first diode region, which is one of the at least one diode regions, is larger than the area occupied per unit area of the second silicon carbide region projected onto the plane, and the first diode region is one of the plurality of transistor regions. and a second transistor region that is one of the plurality of transistor regions provided in the first direction with respect to the first transistor region, and the first transistor region is a semiconductor chip having a third electrode provided on the first surface side of the silicon layer and spaced apart from the first electrode; and a first semiconductor chip having one end in contact with the first electrode and applying a voltage to the first electrode. and a second conductor whose one end is in contact with the third electrode and applies a voltage to the third electrode.

The semiconductor device of the first embodiment is a discrete device 1000. In the discrete device 1000, one MOSFET 100 is mounted with a sealing resin. MOSFET 100 is an example of a semiconductor chip.

MOSFET 100 included in discrete device 1000 is a planar gate type vertical MOSFET using silicon carbide. The MOSFET 100 is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. Furthermore, the MOSFET 100 is a MOSFET that includes an SBD (Shottky Barrier Diode) as a built-in diode. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

FIGS. 1A and 1B are schematic diagrams of the semiconductor device of the first embodiment. FIG. 1(a) is a top view of the discrete device 1000. FIG. 1(b) is a sectional view of KK' in FIG. 1(a).

The discrete device 1000 includes a MOSFET 100, a first bonding wire 110a (first conductor), a second bonding wire 110b, a third bonding wire 110c, a fourth bonding wire 110d (second conductor), and a metal. Bed 120 (first metal layer), first metal lead 130a (second metal layer), second metal lead 130b, third metal lead 130c, fourth metal lead 130d (third metal layer) ), and a sealing resin 145.

MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode pad 22, a gate wiring 24, and a sense electrode pad 25 (third electrode). .

MOSFET 100 is placed on a metal bed 120. MOSFET 100 is connected to metal bed 120.

Metal bed 120 faces drain electrode 14 of MOSFET 100. Metal bed 120 is an example of a first metal layer. Metal bed 120 contacts drain electrode 14 . Metal bed 120 is electrically connected to drain electrode 14 .

Metal bed 120 is metal. The metal bed 120 is, for example, a copper-based alloy or an iron-nickel alloy.

The first metal lead 130a extends in the first direction. The first metal lead 130a is an example of the second metal layer.

The first metal lead 130a is an electrode terminal. The first metal lead 130a has a function of applying voltage to the semiconductor chip 100 from outside the discrete device 1000.

The first metal lead 130a is metal. The first metal lead 130a is, for example, a copper-based alloy or an iron-nickel alloy.

The second metal lead 130b extends in the first direction. The second metal lead 130b is an electrode terminal. The second metal lead 130b has a function of applying voltage to the semiconductor chip 100 from outside the discrete device 1000.

The second metal lead 130b is metal. The second metal lead 130b is made of, for example, a copper-based alloy or an iron-nickel alloy.

Third metal lead 130c extends in the first direction. The third metal lead 130c is an electrode terminal. The third metal lead 130c has a function of applying voltage to the semiconductor chip 100 from outside the discrete device 1000. Third metal lead 130c is connected to metal bed 120.

The third metal lead 130c is metal. The third metal lead 130c is, for example, a copper-based alloy or an iron-nickel alloy.

The fourth metal lead 130d extends in the first direction. The fourth metal lead 130d is an example of the third metal layer.

The fourth metal lead 130d is an electrode terminal. The fourth metal lead 130d has a function of applying voltage to the semiconductor chip 100 from outside the discrete device 1000.

The fourth metal lead 130d is metal. The fourth metal lead 130d is made of, for example, a copper-based alloy or an iron-nickel alloy.

The first bonding wire 110a has one end connected to the source electrode 12 and the other end connected to the first metal lead 130a. The first bonding wire 110a is an example of a first conductor.

The first bonding wire 110a electrically connects the source electrode 12 and the first metal lead 130a. The first bonding wire 110a has a function of applying the voltage applied to the first metal lead 130a to the source electrode 12.

The first bonding wire 110a is metal. The first bonding wire 110a is, for example, aluminum, copper, or gold.

The second bonding wire 110b has one end connected to the source electrode 12 and the other end connected to the first metal lead 130a. The second bonding wire 110b electrically connects the source electrode 12 and the first metal lead 130a. The second bonding wire 110b has a function of applying the voltage applied to the first metal lead 130a to the source electrode 12.

The second bonding wire 110b is metal. The second bonding wire 110b is, for example, aluminum, copper, or gold.

One end of the third bonding wire 110c is connected to the gate electrode pad 22, and the other end is connected to the second metal lead 130b. The third bonding wire 110c electrically connects the gate electrode pad 22 and the second metal lead 130b. The third bonding wire 110c has a function of applying the voltage applied to the second metal lead 130b to the gate electrode pad 22.

The third bonding wire 110c is metal. The third bonding wire 110c is, for example, aluminum, copper, or gold.

The fourth bonding wire 110d has one end connected to the sense electrode pad 25 and the other end connected to the fourth metal lead 130d. The fourth bonding wire 110d is an example of a second conductor.

The fourth bonding wire 110d electrically connects the sense electrode pad 25 and the fourth metal lead 130d. The fourth bonding wire 110d has a function of applying the voltage applied to the fourth metal lead 130d to the sense electrode pad 25.

The fourth bonding wire 110d is metal. The fourth bonding wire 110d is, for example, aluminum, copper, or gold.

The sealing resin 145 covers the MOSFET 100, the first bonding wire 110a, the second bonding wire 110b, the third bonding wire 110c, the fourth bonding wire 110d, and the bed 120. The sealing resin 145 has a function of protecting the MOSFET 100, the first bonding wire 110a, the second bonding wire 110b, the third bonding wire 110c, the fourth bonding wire 110d, and the metal bed 120. The sealing resin 145 is, for example, an epoxy resin.

For example, a source voltage is applied to the first metal lead 130a from outside the MOSFET 100. The first metal lead 130a functions, for example, as a source terminal.

For example, a gate voltage is applied to the second metal lead 130b from outside the MOSFET 100. The second metal lead 130b functions, for example, as a gate terminal.

For example, a drain voltage is applied to the third metal lead 130c from outside the MOSFET 100. The third metal lead 130c functions, for example, as a drain terminal.

For example, a source voltage is applied to the fourth metal lead 130d from outside the MOSFET 100. Furthermore, for example, an ammeter is connected to the fourth metal lead 130d. The fourth metal lead 130d functions, for example, as a current sense terminal.

FIGS. 2A and 2B are schematic top views of the semiconductor device of the first embodiment. FIG. 2(a) is a layout diagram of each region included in the MOSFET 100. FIG. 2(b) is a diagram showing the pattern of electrodes and wiring on the upper surface of the MOSFET 100.

FIG. 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 3 is a cross-sectional view taken along line AA' in FIG. 2(a).

FIG. 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 4 is a sectional view BB' of FIG. 2(a).

FIGS. 5A and 5B are schematic cross-sectional views of the semiconductor device of the first embodiment. FIG. 5(a) is a CC' cross-sectional view of FIG. 2(a). FIG. 5(b) is a DD' cross-sectional view of FIG. 2(a).

As shown in FIG. 2A, the MOSFET 100 includes a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, and a diode region 102a (first transistor region). diode region), a diode region 102b, and a peripheral region 103. The transistor region 101a is an example of a first transistor region. The transistor region 101b is an example of a second transistor region. Diode region 102a is an example of a first diode region.

Hereinafter, the transistor region 101a, the transistor region 101b, the transistor region 101c, and the transistor region 101d may be referred to individually or collectively as simply a transistor region 101. Further, the diode region 102a and the diode region 102b may be referred to individually or collectively as simply the diode region 102.

A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

Peripheral region 103 surrounds transistor region 101 and diode region 102 . In the peripheral region 103, a gate wiring 24 that extends to the gate electrode pad 22 is provided.

For example, a termination structure that improves the breakdown voltage of the MOSFET 100 is provided in the peripheral region 103. A termination structure that improves the breakdown voltage of the MOSFET 100 is, for example, a RESURF or a guard ring.

Diode region 102 is provided between two transistor regions 101. For example, diode region 102a is provided between transistor region 101a and transistor region 101b. The transistor region 101b is provided in a first direction parallel to the first surface P1 with respect to the transistor region 101a.

For example, the diode region 102b is provided between the transistor region 101c and the transistor region 101d. The transistor region 101d is provided in a first direction with respect to the transistor region 101c.

The width of the diode region 102 in the first direction is, for example, 30 μm or more. For example, the width of the diode region 102a in the first direction is 30 μm or more.

MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring 24. , and a sense electrode pad 25.

Silicon carbide layer 10 includes an n ⁺ type drain region 26, an n ⁻ type drift region 28 (first silicon carbide region), a p type body region 30 (second silicon carbide region), and a p type body region 30 (second silicon carbide region). p region 32 (fourth silicon carbide region), n ⁺ type source region 34 (third silicon carbide region), n type first bottom region 36, and n type second bottom region 38. included.

Drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b. Body region 30 includes a low concentration portion 30a and a high concentration portion 30b. P region 32 includes a low concentration portion 32a and a high concentration portion 32b.

Silicon carbide layer 10 is provided between source electrode 12 and drain electrode 14. Silicon carbide layer 10 is provided between gate electrode 18 and drain electrode 14. Silicon carbide layer 10 is single-crystal SiC. Silicon carbide layer 10 is, for example, 4H-SiC.

Silicon carbide layer 10 includes a first surface ("P1" in FIG. 3) and a second surface ("P2" in FIG. 3). The first surface P1 and the second surface P2 face each other. Hereinafter, the first surface may be referred to as the front surface, and the second surface may be referred to as the back surface. Note that hereinafter, "depth" means the depth based on the first surface.

The first plane P1 is, for example, a plane inclined at 0 degrees or more and 8 degrees or less with respect to the (0001) plane. Further, the second plane P2 is, for example, a plane inclined at an angle of 0 degrees or more and 8 degrees or less with respect to the (000-1) plane. The (0001) plane is called a silicon plane. The (000-1) plane is called a carbon plane.

N ⁺ type drain region 26 is provided on the back side of silicon carbide layer 10 . The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 26 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

The n ⁻ type drift region 28 is provided between the drain region 26 and the first surface P1. Drift region 28 is provided between source electrode 12 and drain electrode 14. Drift region 28 is provided between gate electrode 18 and drain electrode 14.

Drift region 28 is provided on drain region 26 . Drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the drain region 26. The n-type impurity concentration of the drift region 28 is, for example, 4×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁷ cm ^{−3 or} less. The thickness of the drift region 28 is, for example, 5 μm or more and 150 μm or less.

Drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b. The first portion 28a is in contact with the first surface P1. First portion 28a is sandwiched between two body regions 30. The first portion 28a functions as an n-type semiconductor region of the SBD. The first portion 28a extends in the second direction, for example.

The second portion 28b is in contact with the first surface P1. Second portion 28b is sandwiched between two p regions 32. The second portion 28b functions as an n-type semiconductor region of the SBD. The second portion 28b extends, for example, in the second direction.

P-type body region 30 is provided between drift region 28 and first surface P1. A portion of body region 30 functions as a channel region of MOSFET 100. Body region 30 functions as a p-type semiconductor region of a pn junction diode.

Body region 30 includes a low concentration portion 30a and a high concentration portion 30b. High concentration portion 30b is provided between low concentration portion 30a and first surface P1. The p-type impurity concentration in the high concentration portion 30b is higher than the p-type impurity concentration in the low concentration portion 30a.

Body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the low concentration portion 30a is, for example, 1×10 ¹⁶ cm ⁻³ or more and 5×10 ¹⁷ cm ⁻³ or less. The p-type impurity concentration of the high concentration portion 30b is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

The depth of the body region 30 is, for example, 0.3 μm or more and 1.0 μm or less.

Body region 30 is fixed at the potential of source electrode 12.

P-type p region 32 is provided between drift region 28 and first surface P1. P region 32 functions as a p-type semiconductor region of a pn junction diode.

P region 32 includes a low concentration portion 32a and a high concentration portion 32b. High concentration portion 32b is provided between low concentration portion 32a and first surface P1. The p-type impurity concentration in the high concentration portion 32b is higher than the p-type impurity concentration in the low concentration portion 32a.

P region 32 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the low concentration portion 32a is, for example, 1×10 ¹⁶ cm ⁻³ or more and 5×10 ¹⁷ cm ⁻³ or less. The p-type impurity concentration of the high concentration portion 32b is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

For example, the p-type impurity concentration of low concentration portion 32a of p region 32 is substantially equal to the p-type impurity concentration of low concentration portion 30a of body region 30.

For example, the p-type impurity concentration of high concentration portion 32b of p region 32 is substantially equal to the p-type impurity concentration of high concentration portion 30b of body region 30.

The width of p region 32 in the first direction is, for example, larger than the width of body region 30 in the first direction. The depth of p region 32 is, for example, 0.3 μm or more and 1.0 μm or less.

P region 32 is fixed at the potential of source electrode 12.

The n ⁺ type source region 34 is provided between the body region 30 and the first surface P1. Source region 34 is provided between low concentration portion 30a of body region 30 and first surface P1. For example, the n ⁺ type source region 34 extends in the second direction.

The source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 34 is higher than the n-type impurity concentration of the drift region 28.

The n-type impurity concentration of the source region 34 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The depth of source region 34 is shallower than the depth of body region 30. The depth of the source region 34 is, for example, 0.1 μm or more and 0.3 μm or less.

An n-type first bottom region 36 is provided between the drift region 28 and the body region 30 . The first bottom region 36 contacts the drift region 28 and the body region 30, for example. The width of the first bottom region 36 in the first direction is, for example, substantially the same as the width of the body region 30 in the first direction.

The first bottom region 36 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the first bottom region 36 is higher than the n-type impurity concentration of the drift region 28 .

The n-type impurity concentration of the first bottom region 36 is, for example, 1×10 ¹⁶ cm ⁻³ or more and 2×10 ¹⁷ cm ^{−3 or} less. The thickness of the first bottom region 36 is, for example, 0.4 μm or more and 1.5 μm or less.

A second bottom region 38 of n-type is provided between drift region 28 and p region 32 . Second bottom region 38 contacts drift region 28 and p region 32, for example. The width of the second bottom region 38 in the first direction is, for example, substantially the same as the width of the p region 32 in the first direction.

The second bottom region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of second bottom region 38 is higher than the n-type impurity concentration of drift region 28 . The n-type impurity concentration of the second bottom region 38 is, for example, substantially the same as the n-type impurity concentration of the first bottom region 36.

The n-type impurity concentration of the second bottom region 38 is, for example, 1×10 ¹⁶ cm ⁻³ or more and 2×10 ¹⁷ cm ^{−3 or} less. The thickness of the second bottom region 38 is, for example, 0.4 μm or more and 1.5 μm or less.

Gate electrode 18 is provided on the first surface P1 side of silicon carbide layer 10. The gate electrode 18 extends in a second direction that is parallel to the first surface P1 and perpendicular to the first direction. A plurality of gate electrodes 18 are arranged in parallel to each other in the first direction. The gate electrode 18 has a so-called stripe shape.

Gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

For example, the gate electrode 18 faces a portion of the body region 30 that is in contact with the first surface P1. For example, the gate electrode 18 faces a portion of the drift region 28 that is in contact with the first surface P1.

Gate insulating layer 16 is provided between gate electrode 18 and body region 30. Gate insulating layer 16 is provided between gate electrode 18 and drift region 28 .

The gate insulating layer 16 is, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be applied to the gate insulating layer 16.

Interlayer insulating layer 20 is provided on gate electrode 18 and silicon carbide layer 10 . Interlayer insulating layer 20 is provided between gate electrode 18 and source electrode 12. The interlayer insulating layer 20 has a function of electrically separating the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

Source electrode 12 is provided on the first surface P1 side of silicon carbide layer 10. Source electrode 12 is in contact with first surface P1.

Source electrode 12 contacts first portion 28 a of drift region 28 , second portion 28 b of drift region 28 , body region 30 , p region 32 , and source region 34 .

Source electrode 12 has a first region 12a above transistor region 101 and a second region 12b above diode region 102.

Source electrode 12 contains metal. The metal forming the source electrode 12 has, for example, a laminated structure of titanium (Ti) and aluminum (Al).

Portions of the source electrode 12 in contact with the body region 30, p region 32, and source region 34 are, for example, metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. For example, metal silicide is not provided in the portion of the source electrode 12 that is in contact with the first portion 28a of the drift region 28 and the second portion 28b of the drift region 28.

The junctions between the body region 30, p region 32, and source region 34 and the source electrode 12 are, for example, ohmic junctions. The junction between the first portion 28a of the drift region 28 and the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

Drain electrode 14 is provided on the second surface P2 side of silicon carbide layer 10. Drain electrode 14 is in contact with second surface P2. Drain electrode 14 contacts drain region 26 .

Drain electrode 14 is, for example, a metal or a metal semiconductor compound. Drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

Gate electrode pad 22 is provided on the first surface P1 side of silicon carbide layer 10. Gate electrode pad 22 is provided on interlayer insulating layer 20 . Gate electrode pad 22 is provided to realize electrical connection between gate electrode 18 and the outside.

Gate wiring 24 is provided on the first surface P1 side of silicon carbide layer 10. Gate wiring 24 is connected to gate electrode pad 22. Gate wiring 24 is electrically connected to gate electrode 18 .

A portion of the gate wiring 24 extends in a first direction parallel to the first surface P1. A portion of the gate wiring 24 extends in a second direction parallel to the first surface P1 and perpendicular to the first direction.

The gate electrode pad 22 and the gate wiring 24 contain metal. The metal forming the gate electrode pad 22 and the gate wiring 24 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The gate electrode pad 22 and the gate wiring 24 are made of the same metal material as the source electrode 12, for example.

The gate wiring 24 between the two source electrodes 12 extends in the first direction. The source electrode 12 is sandwiched between two gate lines 24 extending in the first direction. The source electrode 12 is sandwiched between two gate lines 24 extending in the second direction.

Sense electrode pad 25 is provided on the first surface P1 side of silicon carbide layer 10. The sense electrode pad 25 is provided, for example, only in one transistor region among the plurality of transistor regions 101. The sense electrode pad 25 is provided, for example, in the first transistor region 101a. Sense electrode pad 25 is provided adjacent to diode region 102 .

Sense electrode pad 25 is spaced apart from source electrode 12 . The distance between the sense electrode pad 25 and the source electrode 12 is, for example, smaller than the distance between the sense electrode pad 25 and the gate wiring 24. The minimum distance between the sense electrode pad 25 and the source electrode 12 is, for example, smaller than the minimum distance between the sense electrode pad 25 and the gate wiring 24 wiring.

Sense electrode pad 25 contacts first portion 28 a of drift region 28 , second portion 28 b of drift region 28 , body region 30 , p region 32 , and source region 34 .

The sense electrode pad 25 is provided to detect (sense) a short circuit between the source electrode 12 and the sense electrode pad 25. Furthermore, the sense electrode pad 25 is provided to detect (sense) the amount of on-current flowing through the MOSFET 100.

Sense electrode pad 25 includes metal. The metal forming the sense electrode pad 25 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The sense electrode pad 25 is made of, for example, the same metal material as the source electrode 12, the gate electrode pad 22, and the gate wiring 24.

The area of the sense electrode pad 25 is, for example, 10% or less of the area of the source electrode 12.

As shown in FIG. 3, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 10. A layer 20 is included. Silicon carbide layer 10 of transistor region 101 includes an n ⁺ type drain region 26, an n ⁻ type drift region 28 (first silicon carbide region), and a p type body region 30 (second silicon carbide region). ), an n ⁺ type source region 34 (third silicon carbide region), and an n type first bottom region 36 . Further, the drift region 28 of the transistor region 101 includes a plurality of first portions 28a.

In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. Further, the source electrode 12, the body region 30, the first bottom region 36, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

The first distance (d1 in FIGS. 5(a) and 5(b)) between two adjacent first portions 28a with the body region 30 in between is, for example, 3 μm or more and 30 μm or less. be.

As shown in FIG. 4, diode region 102 includes silicon carbide layer 10, source electrode 12 (first electrode), and drain electrode 14 (second electrode). Silicon carbide layer 10 of diode region 102 includes an n ⁺ type drain region 26, an n ⁻ type drift region 28 (first silicon carbide region), and a p type p region 32 (fourth silicon carbide region). ), and a second bottom region 38 of n-type. Further, the drift region 28 of the diode region 102 includes a plurality of second portions 28b.

In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. Further, the source electrode 12, the p region 32, the second bottom region 38, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

The second distance (d2 in FIGS. 5A and 5B) between two adjacent second portions 28b with the p region 32 in between is, for example, 3 μm or more and 30 μm or less. be. The second distance d2 between two adjacent second portions 28b with the p region 32 in between is, for example, the second distance d2 between two adjacent first portions 28a with the body region 30 in between. is substantially equal to the distance d1 of 1. The first distance d1 and the second distance d2 are distances in the first direction.

FIG. 6 is a schematic top view of the semiconductor device of the first embodiment. FIG. 6 is a diagram showing a pattern of the body region 30 projected onto the first surface P1 and a pattern of the p region 32 projected onto the first surface P1. The pattern of the body region 30 and the pattern of the p region 32 in FIG. 6 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

The occupancy rate per unit area on the first surface P1 of the p region 32 projected onto the first surface P1 is the occupancy rate per unit area on the first surface P1 of the body region 30 projected onto the first surface P1. greater than occupancy. In other words, in a region of a predetermined size, the occupancy rate on the first surface P1 of the p region 32 projected onto the first surface P1 is It is larger than the occupancy rate in P1. The occupancy rate is, for example, the occupancy rate for the transistor region 101 and the diode region 102 projected onto the first surface P1. That is, the occupation ratio of the pn junction diode in the diode region 102 is larger than the occupation ratio of the pn junction diode in the transistor region 101.

The occupancy rate per unit area of the p region 32 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times the occupancy rate per unit area of the body region 30 projected onto the first surface P1. It is as follows.

The unit area is not particularly limited as long as it is a size that allows comparison of the average occupancy of the body region 30 of the transistor region 101 and the average occupancy of the p region 32 of the diode region 102. The unit area is, for example, 30 μm×30 μm=900 μm ² .

Further, the contact area per unit area between source electrode 12 and p region 32 in diode region 102 is larger than the contact area per unit area between source electrode 12 and body region 30 in transistor region 101. That is, the contact resistance per unit area between source electrode 12 and p region 32 in diode region 102 is smaller than the contact resistance per unit area between source electrode 12 and body region 30 in transistor region 101.

FIG. 7 is a schematic top view of the semiconductor device of the first embodiment. FIG. 8 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 8 is a cross-sectional view LL' of FIG. FIG. 7 shows the shape of the sense electrode pad 25 and the source electrode 12 around the sense electrode pad 25.

Sense electrode pad 25 is provided in first transistor region 101a. Sense electrode pad 25 is provided near first diode region 102a. For example, the sense electrode pad 25 is provided adjacent to the first diode region 102a.

Sense electrode pad 25 is spaced apart from source electrode 12 . The sense electrode pad 25 is spaced apart from the first region 12a of the source electrode 12. Furthermore, the sense electrode pad 25 is spaced apart from the second region 12b of the source electrode 12.

The distance (dx in FIG. 7) between the sense electrode pad 25 and the first diode region 102a is, for example, 100 μm or less.

The distance between the sense electrode pad 25 and the source electrode 12 is, for example, 100 μm or less. The distance (dy in FIG. 7) between the sense electrode pad 25 and the first region 12a of the source electrode 12 is, for example, 100 μm or less. Further, the distance (dz in FIG. 7) between the sense electrode pad 25 and the second region 12b of the source electrode 12 is, for example, 100 μm or less.

The distance between the sense electrode pad 25 and the source electrode 12 is, for example, smaller than the distance between the gate wiring 24 and the source electrode 12. The minimum distance between the sense electrode pad 25 and the source electrode 12 is, for example, smaller than the minimum distance between the sense electrode pad 25 and the gate wiring 24 wiring.

Sense electrode pad 25 contacts first portion 28 a of drift region 28 , second portion 28 b of drift region 28 , body region 30 , p region 32 , and source region 34 .

Next, the operation and effects of the semiconductor device of the first embodiment will be explained.

FIGS. 9A and 9B are schematic top views of a semiconductor device of a first comparative example. FIG. 9A is a layout diagram of each region included in the MOSFET 901 of the first comparative example. FIG. 9(b) is a diagram showing the pattern of electrodes and wiring on the upper surface of the MOSFET of the first comparative example. 9(a) and 9(b) are diagrams corresponding to FIG. 2(a) and FIG. 2(b) of the first embodiment.

FIG. 10 is a schematic cross-sectional view of a semiconductor device of a first comparative example. FIG. 10 is a cross-sectional view of GG' in FIG. 9(a). FIG. 10 is a diagram corresponding to FIG. 5(a) of the first embodiment.

The MOSFET of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not include a diode region 102.

Similar to the MOSFET 100 of the first embodiment, a MOSFET and an SBD are provided in the transistor region 101 of the MOSFET 100 of the first comparative example.

FIG. 11 is an equivalent circuit diagram of the semiconductor device of the first comparative example. A pn junction diode and an SBD are connected in parallel to the transistor between the source electrode 12 and the drain electrode 14 as built-in diodes.

For example, consider the case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET 901 is off, a voltage that makes the source electrode 12 positive with respect to the drain electrode 14 may be applied due to a load current caused by an inductive load. In this case, forward current flows through the built-in diode. This state is also called a reverse conduction state.

The forward voltage (Vf) at which a forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, first, a forward current flows through the SBD.

The forward voltage (Vf) of the SBD is, for example, 1.0V. The forward voltage (Vf) of the pn junction diode is, for example, 2.5V.

SBD has unipolar operation. Therefore, even if a forward current flows, stacking faults will not grow in silicon carbide layer 10 due to carrier recombination energy.

FIGS. 12A and 12B are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment. 12(a) and 12(b) are schematic cross-sectional views of a semiconductor device of a first comparative example. 12(a) and 12(b) are diagrams corresponding to FIG. 10.

FIGS. 12(a) and 12(b) are diagrams showing the current flowing through the built-in diode of the MOSFET 901 of the first comparative example. FIG. 12(a) shows a state where forward current flows only through the SBD, and FIG. 12(b) shows a state where forward current flows through the SBD and the pn junction diode.

That is, FIG. 12A shows a state in which the voltage applied between the pn junctions of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Further, FIG. 12(b) shows a state in which the voltage applied between the pn junctions of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

In FIGS. 12(a) and 12(b), dotted arrows indicate currents flowing through the SBD. In FIG. 12(b), the solid arrow indicates the current flowing through the pn junction diode.

As shown in FIG. 12(a), the current flowing through the SBD goes around to the bottom of the body region 30. Therefore, the electrostatic potential wraps around in the drift region 28 facing the bottom of the body region 30 . Due to the wraparound of the electrostatic potential, the voltage applied between body region 30 and drift region 28 is reduced.

Therefore, the forward voltage (Vf) of the pn junction diode is difficult to exceed at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example can be made higher than that in the case where no SBD is provided. Therefore, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in silicon carbide layer 10 due to carrier recombination energy is suppressed.

The forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example depends on the distance between two SBDs adjacent in the first direction. By reducing the distance between two SBDs adjacent in the first direction, the forward voltage (Vf) of the pn junction diode of the MOSFET 901 of the first comparative example can be increased.

A large surge current exceeding the steady state may be instantaneously applied to the MOSFET. The surge current flows from the source electrode 12 toward the drain electrode 14.

When a large surge current flows, a large surge voltage is applied and the MOSFET generates heat, destroying the MOSFET. The maximum allowable peak current value ( _IFSM ) of the surge current allowed by the MOSFET is called the surge current withstand capacity. It is desired to improve surge current withstand capability in a MOSFET provided with an SBD.

When a large surge voltage is applied to MOSFET 901 of the first comparative example, the voltage applied between the pn junctions of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current also flows through the pn junction diode, as shown in FIG. 12(b).

FIG. 13 is a schematic cross-sectional view of a semiconductor device of a second comparative example. FIG. 13 is a diagram corresponding to FIG. 10 of the first comparative example.

The MOSFET 902 of the second comparative example differs from the MOSFET 901 of the first comparative example in that the transistor region does not include an SBD. The built-in diode of MOSFET 902 in the second comparative example is only a pn junction diode.

FIG. 14 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 14 is a diagram showing the voltage-current characteristics of the built-in diodes of MOSFET 901 of the first comparative example and MOSFET 902 of the second comparative example.

As shown in FIG. 14, in the MOSFET 902 of the second comparative example, a current flows through the pn junction diode when a voltage equal to or higher than the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the MOSFET 901 of the first comparative example, current flows through the SBD until the forward voltage Vf1 of the pn junction diode is applied. In the MOSFET 901 of the first comparative example, when a voltage equal to or higher than the forward voltage Vf1 of the pn junction diode is applied, a current flows through the pn junction diode.

Since the MOSFET 901 of the first comparative example operates in a unipolar manner up to the forward voltage Vf1, the slope of current increase is smaller than that of the MOSFET 902 of the second comparative example. Therefore, the maximum allowable peak current value I FSM 1 of the MOSFET 901 of the first comparative example is smaller than the maximum allowable peak current value I _FSM 2 of the MOSFET ₉₀₂ of the second comparative example. In other words, the surge current withstand capacity of MOSFET 901 of the first comparative example is smaller than the surge current withstand capacity of MOSFET 902 of the second comparative example.

FIGS. 15A and 15B are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment. 15(a) and 15(b) are schematic cross-sectional views of the MOSFET 100 of the first embodiment. 15(a) and 15(b) are diagrams corresponding to FIG. 5(a).

15(a) and 15(b) are diagrams showing the current flowing through the built-in diode of the MOSFET 100 of the first embodiment. FIG. 15(a) shows a state where forward current flows only through the SBD, and FIG. 15(b) shows a state where forward current flows through the SBD and the pn junction diode.

That is, FIG. 15A shows a state in which the voltage applied between the pn junctions of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Further, FIG. 15(b) shows a state in which the voltage applied between the pn junctions of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

In FIGS. 15(a) and 15(b), dotted arrows indicate currents flowing through the SBD. In FIG. 15(b), the solid arrow indicates the current flowing through the pn junction diode.

In the diode region 102, the second distance d2 between two adjacent second portions 28b with the p region 32 in between is the same as the second distance d2 between two adjacent second portions 28b with the body region 30 in between in the transistor region 101. 1 and the first distance d1 between the two portions 28a. In other words, the second portions 28b are provided in the diode region 102 at the same intervals as the first portions 28a of the transistor region 101. In other words, SBD regions are provided in the diode region 102 at the same intervals as the transistor region 101.

Therefore, as shown in FIG. 15(a), in the diode region 102, the current flowing through the SBD wraps around to the bottom of the p region 32. Therefore, the forward voltage (Vf) of the pn junction diode is difficult to exceed at the bottom of the p region 32. The forward voltage (Vf) of the pn junction diode in the diode region 102 is increased by providing the SBD region.

When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current also flows through the pn junction diode, as shown in FIG. 15(b).

In the MOSFET 100 of the first embodiment, the occupancy rate per unit area of the p region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of the body region 30 projected onto the first surface P1. It's also big. That is, the occupation ratio of the pn junction diode in the diode region 102 is larger than the occupation ratio of the pn junction diode in the transistor region 101.

Further, the contact area per unit area between source electrode 12 and p region 32 in diode region 102 is larger than the contact area per unit area between source electrode 12 and body region 30 in transistor region 101. That is, the contact resistance per unit area between source electrode 12 and p region 32 in diode region 102 is smaller than the contact resistance per unit area between source electrode 12 and body region 30 in transistor region 101.

Therefore, the current flowing through the pn junction diode in the diode region 102 is larger than the current flowing through the pn junction diode in the transistor region 101.

Furthermore, when a large current flows through the pn junction diode in the diode region 102, carrier propagation and heat propagation occur to the adjacent transistor region 101. Therefore, conductivity modulation of the transistor region 101 adjacent to the diode region 102 is promoted. Therefore, the current flowing through the pn junction diode in the transistor region 101 adjacent to the diode region 102 increases.

FIG. 16 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 15 is a diagram showing the voltage-current characteristics of the built-in diodes of the MOSFET 901 of the first comparative example, the MOSFET 902 of the second comparative example, and the MOSFET 100 of the first embodiment.

As shown in FIG. 16, in the MOSFET 100 of the first embodiment, current flows through the SBD until the forward voltage Vf3 of the pn junction diode is applied. In the MOSFET 100 of the first embodiment, when a voltage equal to or higher than the forward voltage Vf3 of the pn junction diode is applied, a current flows through the pn junction diode.

In the diode region 102 of the MOSFET 100 of the first embodiment, SBD regions are provided at the same intervals as the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET 100 of the first embodiment is equivalent to the forward voltage Vf1 of the pn junction diode of the MOSFET of the first comparative example.

On the other hand, the current after exceeding the forward voltage Vf3 of the pn junction diode in the MOSFET 100 of the first embodiment is higher than the current after exceeding the forward voltage Vf1 of the pn junction diode in the MOSFET 901 of the first comparative example. growing. This is because the current flowing through the pn junction diode in the diode region 102 and the pn junction diode in the transistor region 101 adjacent to the diode region 102 becomes larger than in the MOSFET 901 of the first comparative example.

As the current increases after exceeding the forward voltage Vf3 of the pn junction diode, the maximum allowable peak current value I _FSM 3 of the MOSFET 100 of the first embodiment becomes the maximum allowable peak current of the MOSFET 903 of the third comparative example. The value I _FSM is larger compared to 1. In other words, the surge current withstand capacity of the MOSFET 100 of the first embodiment is greater than the surge current withstand capacity of the MOSFET 901 of the first comparative example.

As described above, the MOSFET 100 of the first embodiment has improved surge current resistance by including the diode region 102 provided between the transistor regions 101.

The occupancy rate per unit area of the p region 32 projected onto the first surface P1 is 1.2 times or more and no more than 3 times the occupancy rate per unit area of the body region 30 projected onto the first surface P1. It is preferable that there be. By exceeding the above lower limit, the surge current withstand capacity is further improved. Moreover, by being less than the above-mentioned upper limit, a decrease in the forward voltage Vf3 is suppressed, and a decrease in reliability is suppressed.

The failure analysis conducted by the inventors has revealed that one of the causes of chip destruction due to surge current is a short circuit between the source electrode 12 and the gate wiring 24. A short circuit between the source electrode 12 and the gate wiring 24 occurs when the source electrode 12 adjacent to the gate wiring 24 melts, flows laterally, and comes into contact with the gate wiring 24 .

It has become clear that a short circuit between the source electrode 12 and the gate wiring 24 is particularly likely to occur between the source electrode 12 and the gate wiring 24 in the diode region 102. That is, it has become clear that a short circuit between the source electrode 12 and the gate wiring 24 is particularly likely to occur between the second region 12b and the gate wiring 24 of the source electrode 12.

The reason why a short circuit is likely to occur between the second region 12b and the gate wiring 24 is that the surge current flowing in the diode region 102 is larger than that in the transistor region 101, so the amount of heat generated is larger. it is conceivable that. In other words, it is thought that this is because the source electrode 12 is more likely to melt as the amount of heat generated increases.

Therefore, for example, a MOSFET whose second region 12b has already melted due to use of the MOSFET can be understood to be a MOSFET with a low surge current withstand capacity. MOSFETs with low surge current resistance have decreased reliability, so it is desirable to replace them before a failure occurs.

17 and 18 are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment. FIG. 17 is a diagram corresponding to FIG. 7. FIG. 18 is a diagram corresponding to FIG. 8.

The MOSFET 100 of the discrete device 1000 of the first embodiment includes a sense electrode pad 25 for detecting a short circuit between the source electrode 12 and the sense electrode pad 25. The sense electrode pad 25 is provided close to the diode region 102 where the source electrode 12 is likely to melt.

For example, in the discrete device 1000, a source voltage is applied to the fourth metal lead 130d connected to the sense electrode pad 25. Then, the current flowing through the fourth metal lead 130d is monitored by an ammeter external to the discrete device 1000.

Consider a case where the second region 12b of the first diode region 102a melts and short-circuits with the sense electrode pad 25, as shown by dotted circles in FIGS. 17 and 18. In this case, the current flowing from the sense electrode pad 25 to the second region 12b increases the current flowing to the fourth metal lead 130d.

Therefore, a short circuit between the second region 12b of the source electrode 12 and the sense electrode pad 25 can be detected. In other words, a decrease in the reliability of the MOSFET 100, that is, a decrease in the reliability of the discrete device 1000 can be detected.

If a decrease in the reliability of the discrete device 1000 is detected, early failure of the discrete device 1000 is predicted. Therefore, for example, the discrete device 1000 is replaced with a new discrete device.

As described above, it is possible to foresee a decrease in reliability of the discrete device 1000.

From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the first diode region 102a (dx in FIG. 7) is preferably 100 μm or less, and preferably 50 μm or less. It is more preferable that the thickness is 10 μm or less.

From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the source electrode 12 is preferably 100 μm or less, more preferably 50 μm or less, and 10 μm or less. is more preferable.

From the viewpoint of early detection of melting of the source electrode 12, the distance (dz in FIG. 7) between the sense electrode pad 25 and the second region 12b of the source electrode 12 is preferably 100 μm or less, and 50 μm or less. It is more preferable that it is below, and more preferably that it is 10 μm or less.

From the viewpoint of early detection of melting of the source electrode 12, the distance between the sense electrode pad 25 and the source electrode 12 is preferably smaller than the distance between the gate wiring 24 and the source electrode 12. Since the distance between the sense electrode pad 25 and the source electrode 12 is shorter than the distance between the gate wiring 24 and the source electrode 12, the source electrode 12 melting can be detected.

Moreover, the MOSFET 100 of the discrete device 1000 of the first embodiment includes the sense electrode pad 25, so that the amount of on-current of the MOSFET 100 can be detected (sense).

From the viewpoint of reducing the amount of on-current flowing through the sense electrode pad 25 and making it easier to detect the amount of on-current using an ammeter, the area of the sense electrode pad 25 is preferably 10% or less of the area of the source electrode 12. , more preferably 5% or less.

(Modified example)
The semiconductor device of the modification of the first embodiment is different from the first embodiment in that the third electrode does not contact the plurality of first portions, the second silicon carbide region, and the third silicon carbide region. The configuration is different from that of a semiconductor device.

FIG. 19 is a schematic cross-sectional view of a modification of the first embodiment. FIG. 19 is a diagram corresponding to FIG. 7 of the first embodiment.

In the MOSFET 101 included in the discrete device of the modification of the first embodiment, the sense electrode pad 25 includes the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, and the p region 32. , and not in contact with the source region 34.

In the semiconductor device of the modification of the first embodiment, no on-current flows through the sense electrode pad 25. Therefore, current flows through the sense electrode pad 25 only when the second region 12b of the first diode region 102a melts and short-circuits with the sense electrode pad 25. Therefore, the accuracy of detecting melting of the source electrode 12 is improved.

As described above, according to the first embodiment and the modified example, a discrete device with improved surge current resistance is realized. Further, according to the first embodiment, a discrete device whose reliability can be predicted to deteriorate is realized.

(Second embodiment)
The semiconductor device of the second embodiment includes a plurality of transistor regions and at least one diode region, and the plurality of transistor regions have a first surface and a second surface opposite to the first surface. a first n-type silicon carbide region having a plurality of first portions in contact with the first surface; and a p-type first silicon carbide region provided between the first silicon carbide region and the first surface. a silicon carbide layer including a second silicon carbide region and a third n-type silicon carbide region provided between the second silicon carbide region and the first surface; a plurality of first portions; a first electrode in contact with the second silicon carbide region and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; a gate insulating layer provided between the second silicon carbide region and the at least one diode region, the n-type first silicon carbide layer has a plurality of second portions in contact with the first surface. a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface; a plurality of second portions and a fourth silicon carbide layer; The occupied area per unit area of the fourth silicon carbide region, which includes a first electrode in contact with the silicon region and a second electrode and is projected onto the first surface, is as follows: a first transistor region that is larger than the area occupied per unit area of the second silicon carbide region and whose first diode region is one of the at least one diode regions and is one of the plurality of transistor regions; The first transistor region is provided between the first transistor region and a second transistor region which is one of the plurality of transistor regions provided in the first direction, and the first transistor region is formed of the first transistor region of the silicon carbide layer. It has a third electrode provided on the side of the surface and spaced apart from the first electrode.

The semiconductor device of the second embodiment has the same configuration as the MOSFET 100 of the first embodiment. The semiconductor device of the second embodiment differs from the first embodiment in that the semiconductor device of the first embodiment is a discrete device, whereas the semiconductor device of the second embodiment is a semiconductor chip. Hereinafter, descriptions of content that overlaps with the first embodiment may be omitted.

20(a) and 20(b) are schematic top views of the semiconductor device of the second embodiment. FIG. 20(a) is a layout diagram of each region included in the MOSFET 200 of the second embodiment. FIG. 20(b) is a diagram showing a pattern of electrodes and wiring on the upper surface of the MOSFET 200.

MOSFET 200 of the second embodiment has the same configuration as MOSFET 100 of the first embodiment. MOSFET 200 is a semiconductor chip. MOSFET 200 is an example of a semiconductor device.

According to the MOSFET 200 of the second embodiment, the surge current withstand capacity is improved like the MOSFET 100 of the first embodiment. Furthermore, for example, by incorporating it into a discrete device like the MOSFET 100 of the first embodiment, it becomes possible to foresee a decrease in reliability.

As described above, according to the second embodiment, a MOSFET with improved surge current resistance is realized. Further, according to the second embodiment, a MOSFET in which a decrease in reliability can be predicted is realized.

(Third embodiment)
The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that it includes eight transistor regions and ten diode regions. Hereinafter, descriptions of content that overlaps with the content of the first embodiment or the second embodiment may be omitted.

21(a) and 21(b) are schematic top views of the semiconductor device of the third embodiment. FIG. 21(a) is a layout diagram of each region included in the MOSFET 300 of the third embodiment. FIG. 21(b) is a diagram showing the pattern of electrodes and wiring on the upper surface of the MOSFET 300.

The MOSFET 300 includes a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a transistor region 101e, a transistor region 101f, a transistor region 101g, a transistor region 101h, and a diode. Region 102a (first diode region), diode region 102b, diode region 102c, diode region 102d, diode region 102e, diode region 102f, diode region 102g, diode region 102h, diode region 102i, diode region 102j, and peripheral region 103 Equipped with. The transistor region 101a is an example of a first transistor region. The transistor region 101b is an example of a second transistor region. Diode region 102a is an example of a first diode region.

According to the MOSFET 300 of the third embodiment, the surge current withstand capacity is improved like the MOSFET 100 of the first embodiment. Furthermore, for example, by incorporating it into a discrete device like the MOSFET 100 of the first embodiment, it becomes possible to foresee a decrease in reliability.

As described above, according to the third embodiment, a MOSFET with improved surge current resistance is realized. Further, according to the third embodiment, a MOSFET whose reliability can be predicted to deteriorate is realized.

(Fourth embodiment)
The inverter circuit and drive device according to the fourth embodiment are the inverter circuit and drive device including the semiconductor device according to the first embodiment.

FIG. 22 is a schematic diagram of the drive device of the fourth embodiment. Drive device 500 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

According to the fourth embodiment, the characteristics of the inverter circuit 150 and the drive device 500 are improved by providing the MOSFET 100 with improved characteristics.

(Fifth embodiment)
The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

FIG. 23 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 600 of the fifth embodiment is a railway vehicle. Vehicle 900 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150. Wheels 90 of vehicle 600 are rotated by motor 140 .

According to the fifth embodiment, the characteristics of the vehicle 600 are improved by providing the MOSFET 100 with improved characteristics.

(Sixth embodiment)
The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

FIG. 24 is a schematic diagram of a vehicle according to the sixth embodiment. Vehicle 700 of the sixth embodiment is an automobile. Vehicle 700 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized.

The motor 140 is driven by the AC voltage output from the inverter circuit 150. Motor 140 rotates wheels 90 of vehicle 700 .

According to the sixth embodiment, the characteristics of the vehicle 700 are improved by providing the MOSFET 100 with improved characteristics.

(Seventh embodiment)
The elevator according to the seventh embodiment is an elevator including the semiconductor device according to the first embodiment.

FIG. 25 is a schematic diagram of an elevator according to the seventh embodiment. The elevator 800 of the seventh embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized.

The motor 140 is driven by the AC voltage output from the inverter circuit 150. The hoist 616 is rotated by the motor 140, and the car 610 is raised and lowered.

According to the seventh embodiment, the characteristics of the elevator 800 are improved by providing the MOSFET 100 with improved characteristics.

In the first to third embodiments, the crystal structure of SiC is 4H-SiC. However, the present invention is applicable to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. It is also possible to apply Further, it is also possible to apply a plane other than the (0001) plane to the surface of silicon carbide layer 10.

In the first to third embodiments, the gate electrode 18 has a so-called stripe shape, but the shape of the gate electrode 18 is not limited to the stripe shape. For example, the shape of the gate electrode 18 may be a lattice shape.

In the first to third embodiments, aluminum (Al) is used as an example of the p-type impurity, but boron (B) can also be used. Further, although nitrogen (N) and phosphorus (P) are illustrated as n-type impurities, arsenic (As), antimony (Sb), etc. can also be applied.

In the first to third embodiments, the conductor is a bonding wire, but the conductor may be a clip used for clip bonding, for example.

In the first embodiment, the semiconductor device is a discrete device, but the semiconductor device may be a module device in which a plurality of semiconductor chips are mounted.

The number of transistor regions 101 and diode regions 102 and the arrangement of transistor regions 101 and diode regions 102 are not limited to those in the first to third embodiments.

Further, in the fourth to seventh embodiments, the configurations including the MOSFET 100 of the first embodiment have been described as an example, but it is also possible to have a configuration including the MOSFETs of the second or third embodiments.

Further, in the fourth to seventh embodiments, the case where the semiconductor device of the present invention is applied to a vehicle or an elevator has been described as an example, but the semiconductor device of the present invention is applied to, for example, a power conditioner of a solar power generation system. It is also possible to do so.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. For example, components of one embodiment may be replaced or modified with components of other embodiments. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

10 Silicon carbide layer 12 Source electrode (first electrode)
14 Drain electrode (second electrode)
16 Gate insulating layer 18 Gate electrode 25 Sense electrode pad (third electrode)
28 Drift region (first silicon carbide region)
28a First portion 28b Second portion 30 Body region (second silicon carbide region)
32 p region (fourth silicon carbide region)
34 Source region (third silicon carbide region)
100 MOSFET (semiconductor chip)
101 Transistor region 101a Transistor region (first transistor region)
101b Transistor region (second transistor region)
102 Diode region 102a Diode region (first diode region)
110a first bonding wire (first conductor)
110d Fourth bonding wire (second conductor)
120 Metal bed (first metal layer)
130a First metal lead (second metal layer)
130d Fourth metal lead (third metal layer)
200 MOSFET (semiconductor device)
300 MOSFET (semiconductor device)
600 Drive device 700 Vehicle 800 Vehicle 900 Elevator 1000 Discrete device (semiconductor device)
P1 First surface P2 Second surface d1 First distance d2 Second distance

Claims (20)

A semiconductor chip including a plurality of transistor regions and at least one diode region,
The plurality of transistor regions are
a first n-type silicon carbide region having a first surface and a second surface opposite to the first surface and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type silicon carbide region provided between the second silicon carbide region and the first surface. a silicon carbide layer comprising a third silicon carbide region of the mold;
a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region;
a second electrode in contact with the second surface;
a gate electrode facing the second silicon carbide region;
a gate insulating layer provided between the gate electrode and the second silicon carbide region,
The at least one diode region is
the first n-type silicon carbide region having a plurality of second portions in contact with the first surface; and the p-type silicon carbide region provided between the first silicon carbide region and the first surface. the silicon carbide layer including a fourth silicon carbide region;
the first electrode in contact with the plurality of second portions and the fourth silicon carbide region;
the second electrode;
The occupied area per unit area of the fourth silicon carbide region projected onto the first surface is greater than the occupied area per unit area of the second silicon carbide region projected onto the first surface. Also big,
A first diode region that is one of the at least one diode region is provided in a first direction with respect to a first transistor region that is one of the plurality of transistor regions and the first transistor region. and a second transistor region that is one of the plurality of transistor regions,
a semiconductor chip in which the first transistor region has a third electrode provided on a side of the first surface of the silicon carbide layer and spaced apart from the first electrode;
a first conductor whose one end is in contact with the first electrode and applies a voltage to the first electrode;
a second conductor whose one end is in contact with the third electrode and applies a voltage to the third electrode;
A semiconductor device comprising: a first metal layer facing the second electrode and electrically connected to the second electrode;
a second metal layer in contact with the other end of the first conductor;
a third metal layer in contact with the other end of the second conductor;
The semiconductor device according to claim 1, further comprising: The semiconductor device according to claim 1, wherein the third electrode is in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region. The semiconductor device according to claim 1, wherein a distance between the third electrode and the at least one diode region is 100 μm or less. The semiconductor device according to claim 1, wherein a distance between the third electrode and the first electrode is 100 μm or less. 2. The semiconductor device according to claim 1, wherein the area of the third electrode is 10% or less of the area of the first electrode. The semiconductor device according to claim 1, wherein the first conductor and the second conductor are bonding wires. The contact area per unit area between the first electrode and the fourth silicon carbide region is larger than the contact area per unit area between the first electrode and the second silicon carbide region. 1. The semiconductor device according to 1. The second distance between two of the plurality of second portions that are adjacent to each other with the fourth silicon carbide region in between is the distance between two of the plurality of second portions that are adjacent to each other with the second silicon carbide region in between. 2. The semiconductor device according to claim 1, wherein the distance is equal to the first distance between the first portions of the semiconductor device. comprising a plurality of transistor regions and at least one diode region,
The plurality of transistor regions are
a first n-type silicon carbide region having a first surface and a second surface opposite to the first surface and having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type silicon carbide region provided between the second silicon carbide region and the first surface. a silicon carbide layer comprising a third silicon carbide region of the mold;
a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region;
a second electrode in contact with the second surface;
a gate electrode facing the second silicon carbide region;
a gate insulating layer provided between the gate electrode and the second silicon carbide region,
The at least one diode region is
the first n-type silicon carbide region having a plurality of second portions in contact with the first surface; and the p-type silicon carbide region provided between the first silicon carbide region and the first surface. the silicon carbide layer including a fourth silicon carbide region;
the first electrode in contact with the plurality of second portions and the fourth silicon carbide region;
the second electrode;
The occupied area per unit area of the fourth silicon carbide region projected onto the first surface is greater than the occupied area per unit area of the second silicon carbide region projected onto the first surface. Also big,
A first diode region that is one of the at least one diode region is provided in a first direction with respect to a first transistor region that is one of the plurality of transistor regions and the first transistor region. and a second transistor region that is one of the plurality of transistor regions,
A semiconductor device in which the first transistor region has a third electrode provided on the first surface side of the silicon carbide layer and spaced apart from the first electrode. 11. The semiconductor device according to claim 10, wherein the third electrode is in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region. 11. The semiconductor device according to claim 10, wherein a distance between the third electrode and the at least one diode region is 100 μm or less. 11. The semiconductor device according to claim 10, wherein a distance between the third electrode and the first electrode is 100 μm or less. 11. The semiconductor device according to claim 10, wherein the area of the third electrode is 10% or less of the area of the first electrode. The contact area per unit area between the first electrode and the fourth silicon carbide region is larger than the contact area per unit area between the first electrode and the second silicon carbide region. 10. The semiconductor device according to 10. The second distance between two of the plurality of second portions that are adjacent to each other with the fourth silicon carbide region in between is the distance between two of the plurality of second portions that are adjacent to each other with the second silicon carbide region in between. 11. The semiconductor device according to claim 10, wherein the distance is equal to the first distance between the first portions of the semiconductor device. An inverter circuit comprising the semiconductor device according to any one of claims 1 to 16. A drive device comprising the semiconductor device according to any one of claims 1 to 16. A vehicle comprising the semiconductor device according to any one of claims 1 to 16. An elevator comprising the semiconductor device according to any one of claims 1 to 16.

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