JP2024020025A - Series capacitor step-down converter, controller circuit therefor, and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a series capacitor step-down converter capable of performing high-efficiency operation.

SOLUTION: A control logic circuit 210 alternately repeats a first state φ1 in which a first switch S1 and a fourth switch S4 are turned on and a second state φ2 in which a second switch S2 and a third switch S3 are turned on with a dead time T_D interposed therebetween. In a second dead time inserted during a transition from the second state φ2 to the first state φ1, a first timing generator 230 monitors a first switching voltage V_SW1 generated at a first switching node SW1 to generate a first timing signal St1 indicating transition from the second dead time to the first state φ1 when the first switching voltage V_SW1 crosses a predetermined upper threshold.

SELECTED DRAWING: Figure 8

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present disclosure relates to series capacitor converters.

A DC/DC converter with a step-down function is used to generate a voltage lower than the input voltage. As a DC/DC converter having a step-down function, there are known types such as buck type, buck-boost type, Cuk type, Zeta type, and Sepic type.

Depending on the application, an interleaved type or series capacitor type, which is a variation of a step-down converter, is used. In the interleaved type, Buck converters are connected in parallel, and the inputs and outputs are connected in common. High efficiency operation is achieved by interleaving a plurality of Buck converters. The interleaved type has the same step-down ratio as a normal buck converter.

A series capacitor type step-down converter can be considered a modification of the interleaved type with a number of phases of two, with the addition of a series capacitor. A series capacitor type step-down converter can have a step-down ratio as small as 1/2 that of an interleaved type, and is therefore suitable for applications that require a small step-down ratio.

Stefano Saggini, Shuai Jiang, Mario Ursino, Chenhao Nan, "A 99% Efficient Dual-Phase Resonant Switched-Capacitor-Buck Converter for 48 V Data Center Bus Conversions", 2019 IEEE Applied Power Electronics Conference and Exposition (APEC)

The present disclosure was made in such a situation, and one of its exemplary objectives is to provide a series capacitor step-down converter capable of highly efficient operation.

Certain aspects of the present disclosure relate to controller circuits for series capacitor buck converters. A series capacitor buck converter includes a couple including an input line and an output line, a first switch having a first end connected to the input line, and a first inductor and a second inductor having respective first ends connected to the output line. a second switch connected between a first switching node, which is a second end of the first inductor, and ground; and a series capacitor connected between a second end of the first switch and the first switching node. a third switch connected between the second end of the first switch and a second switching node, which is the second end of the second inductor; and a fourth switch connected between the second switching node and ground. , and an output capacitor connected to the output line. The controller circuit alternately repeats a first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on, with a dead time in between. A control logic circuit generates a plurality of control signals instructing on/off states of the first switch to the fourth switch, and a second dead time inserted between the transition from the second state to the first state. a first timing generator that monitors a first switching voltage developed at the switching node and asserts a first timing signal instructing turn-on of the first switch when the first switching voltage crosses a predetermined upper threshold; Be prepared.

Note that arbitrary combinations of the above components, and mutual substitution of components and expressions among methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not describe all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. .

According to an aspect of the present disclosure, highly efficient operation can be achieved.

FIG. 1 is a circuit diagram of a series capacitor step-down converter according to an embodiment. FIG. 2 is an equivalent circuit diagram of the series capacitor step-down converter (main circuit) in the first state. FIG. 3 is an equivalent circuit diagram of the series capacitor step-down converter (main circuit) in the second state. FIG. 4 is a current waveform diagram of a series capacitor step-down converter. FIG. 5 is a current waveform diagram of a series capacitor step-down converter. FIG. 6 is a time chart illustrating the operation of the series capacitor step-down converter in consideration of dead time. FIG. 7 is an operational waveform diagram during the dead time during transition from the second state to the first state. FIG. 8 is a block diagram of a series capacitor step-down converter including a controller IC according to an embodiment. FIG. 9 is an operational waveform diagram of the controller IC of FIG. 8. FIG. 10 is a block diagram of a series capacitor step-down converter including a controller IC according to the second embodiment. FIG. 11 is an operational waveform diagram of the controller IC of FIG. 10. FIG. 12 is a diagram illustrating an example of an electronic device including a series capacitor step-down converter.

(Summary of embodiment)
1 provides an overview of some exemplary embodiments of the present disclosure. This Summary is intended to provide a simplified description of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments and as a prelude to the more detailed description that is presented later. It does not limit the size. This summary is not an exhaustive overview of all possible embodiments and is not intended to identify key elements of all embodiments or to delineate the scope of any or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or multiple embodiments (examples or modifications) disclosed in this specification.

A controller circuit of an aspect of the present disclosure controls a series capacitor buck converter. A series capacitor buck converter includes a couple including an input line and an output line, a first switch having a first end connected to the input line, and a first inductor and a second inductor having respective first ends connected to the output line. a second switch connected between a first switching node, which is a second end of the first inductor, and ground; and a series capacitor connected between a second end of the first switch and the first switching node. a third switch connected between the second end of the first switch and a second switching node, which is the second end of the second inductor; and a fourth switch connected between the second switching node and ground. , and an output capacitor connected to the output line. The controller circuit alternately repeats a first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on, with a dead time in between. A control logic circuit generates a plurality of control signals instructing on/off states of the first switch to the fourth switch, and a second dead time inserted between the transition from the second state to the first state. a first timing generator that monitors a first switching voltage developed at the switching node and asserts a first timing signal instructing turn-on of the first switch when the first switching voltage crosses a predetermined upper threshold; Be prepared.

According to this configuration, the first switch can be turned on in a state where the drain-source voltage of the first switch is sufficiently small, and high efficiency operation can be realized.

In one embodiment, the upper threshold Vthh is, where the input voltage of the input line is Vin.
Vin/2×0.7≦Vthh
may be satisfied. Moreover, the upper threshold value Vthh is
Vthh≦Vin/2+0.5
may be satisfied.

In one embodiment, the controller circuit monitors a second switching voltage developed at the second switching node during a first dead time inserted between the transition from the first state to the second state, The third timing generator may further include a third timing generator that asserts a third timing signal instructing turn-on of the third switch when the upper threshold is crossed. Thereby, the third switch can be turned on in a state where the drain-source voltage of the third switch is sufficiently small, and high efficiency operation can be realized.

In one embodiment, the controller circuit monitors the first switching voltage during a first dead time and has a second timing for instructing turn-on of the second switch when the first switching voltage crosses a predetermined lower threshold. The device may further include a second timing generator that asserts the signal. Thereby, the second switch can be turned on in a state where the drain-source voltage of the second switch is sufficiently small, and high efficiency operation can be realized.

In one embodiment, the controller circuit monitors the second switching voltage during the second dead time, and when the second switching voltage crosses a predetermined lower threshold, the controller circuit has a fourth timing for instructing turn-on of the fourth switch. The device may further include a fourth timing generator that asserts the signal. Thereby, the fourth switch can be turned on in a state where the drain-source voltage of the fourth switch is sufficiently small, and high efficiency operation can be realized.

In one embodiment, the control circuit may be monolithically integrated on one semiconductor substrate. "Integration" includes cases where all of the circuit components are formed on a semiconductor substrate, cases where the main components of the circuit are integrated, and some of the components are integrated to adjust the circuit constants. A resistor, a capacitor, etc. may be provided outside the semiconductor substrate. By integrating circuits on one chip, the circuit area can be reduced and the characteristics of circuit elements can be kept uniform.

A series capacitor step-down converter according to one embodiment may include a main circuit of the series capacitor step-down converter and any of the above-described controller circuits that drive the main circuit.

(Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. Identical or equivalent components, members, and processes shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are illustrative rather than limiting the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

In this specification, "a state in which member A is connected to member B" refers to not only a case where member A and member B are physically directly connected, but also a state in which member A and member B are electrically connected. This also includes cases in which they are indirectly connected via other members that do not substantially affect the connection state or impair the functions and effects achieved by their combination.

Similarly, "a state in which member C is connected (provided) between member A and member B" refers to a state in which member A and member C or member B and member C are directly connected. In addition, it also includes cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

In addition, in this specification, the symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors are used as necessary to indicate the respective voltage value, current value, or circuit constant (resistance). value, capacitance value, inductance).

The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification have been enlarged or reduced as appropriate for ease of understanding, and each waveform shown has also been simplified for ease of understanding. exaggerated or emphasized.

FIG. 1 is a circuit diagram of a series capacitor step-down converter 100 according to an embodiment. The series capacitor step-down converter 100 steps down the input voltage Vin supplied to the input line 102 and generates the stepped-down output voltage Vout on the output line 104.

Series capacitor step-down converter 100 includes a main circuit 110 and a controller IC (Integrated Circuit) 200. The controller IC 200 is an ASIC (Application Specific Integrated Circuit) integrated on one semiconductor substrate.

The main circuit 110 includes a first switch S1 to a fourth switch S4, a coupled inductor 112, a series capacitor Cr, and an output capacitor Cout.

The first switch S1 has a first end connected to the input line 102. Coupled inductor 112 is a transformer and includes a first inductor L1 and a second inductor L2 that are magnetically coupled. The first inductor L1 and the second inductor L2 have an equal inductance L and a mutual inductance M. First ends of each of the first inductor L1 and the second inductor L2 are connected between the output line 104 and ground.

The second switch S2 is connected between the second end (first switching node SW1) of the first inductor L1 and ground. A series capacitor Cr is connected between a second end of the first switch S1 and a second end of the first inductor L1. The third switch S3 is connected between the second end of the first switch S1 and the second end of the second inductor L2 (second switching node SW2). The fourth switch S4 is connected between the second end of the second inductor L2 and ground. Output capacitor Cout is connected to output line 104.

In this example, the first switch S1 to the fourth switch S4 are all shown as N-channel MOSFETs, but the present invention is not limited to this, and other transistors may be used. Further, the second switch S2 and the fourth switch S4 on the lower side may be rectifying elements such as diodes.

The controller IC 200 controls the first switch S1 to the fourth switch S4 to generate an output voltage Vout on the output line 104. Specifically, the controller IC 200 alternately repeats the first state φ1 and the second state φ2 at a predetermined switching frequency _fSW with a dead time _TD in between.
First state φ1:
First switch S1=ON
Second switch S2=OFF
Third switch S3=OFF
Fourth switch S4=ON

Second state φ2:
First switch S1=OFF
Second switch S2=ON
Third switch S3=ON
Fourth switch S4=OFF

Dead time _TD :
First switch S1=OFF
Second switch S2=OFF
Third switch S3=OFF
Fourth switch S4=OFF

When the length of each of the first state φ1 and the second state φ2 is T _ON , the switching frequency f _SW is 1/(2×T _ON ). In other words, operating at the switching frequency f _SW means repeating the first state φ1 and the second state φ2 with a length of T _ON =1/(2×f _SW ).

The above is the configuration of the series capacitor step-down converter 100. Next, its operation will be explained.

FIG. 2 is an equivalent circuit diagram of the series capacitor step-down converter 100 (main circuit 110) in the first state φ1. Switches S1 and S4 that are on are shown as mere wiring. Further, the coupled inductor 112 is shown as an equivalent circuit including an excitation inductance Lm and a leakage inductance Lk. The current flowing through the first inductor L1 is referred to as a first coil current I _L1 , and the current flowing through the second inductor L2 is referred to as a second coil current I _L2 .

In the first state φ1, the series capacitor Cr, the first inductor L1 (leakage inductance Lk), and the output capacitor Cout form a series resonant circuit, and a resonant current Ires flows through the first inductor L1 (I _L1 =Ires). Since the sum of the resonant current Ires', which is a replica of the resonant current Ires flowing through the first inductor L1, and the excitation current _Im2 flowing through the excitation inductance Lm flows through the second inductor L2, the second coil current I _L2 is I _L2 =Ires'+ _Im2 .

FIG. 3 is an equivalent circuit diagram of the series capacitor step-down converter 100 (main circuit 110) in the second state φ2. Switches S2 and S3 that are on are shown as mere wiring.

In the second state φ2, the series capacitor Cr, the leakage inductance Lk, and the output capacitor Cout form a series resonant circuit, and a resonant current Ires flows through the second inductor L2 (I _L2 =Ires). Since the sum of the resonant current Ires', which is a replica of the resonant current Ires flowing through the second inductor L2, and the excitation current _Im1 flowing through the excitation inductance Lm flows through the first inductor L1, the first coil current I _L1 is I _L1 =Ires'+ _Im1 .

When the first state φ1 and the second state φ2 are alternately repeated, the voltage across the series capacitor Cr becomes Vin/2 in the steady state, and the remaining Vin/2 is applied to the coupled inductor 112. When the inductances of the first inductor L1 and the second inductor L2 are equal, an output voltage Vout that is 1/4 times as large as Vin is generated on the output line 104.

The conditions for series capacitor step-down converter 100 to perform ZVS (Zero Voltage Switching) are as follows.

・Transition from the first state φ1 to the second state φ2 During the dead time _TD immediately after the first state φ1, when I _L1 ≧0, the current I _L1 flows through the body diode of the second switch S2. , the voltage across the second switch S2 becomes smaller. At this time, when the state changes to the second state φ2, that is, when the second switch S2 is turned on, ZVS of the second switch S2 is established. Note that the currents I _L1 and I _L2 have positive directions toward the output line 104.

Also, during the dead time _TD , when I _L2 <0, the voltage at the connection node between the third switch S3 and the fourth switch S4 increases due to the regenerative current, and the voltage across the third switch S3 decreases. . At this time, when the state changes to the second state φ2, that is, the third switch S3 turns on, ZVS of the third switch S3 is established.

・Transition from the second state φ2 to the first state φ1 During the dead time _TD immediately after the second state φ2, when I _L1 <0, the regenerative current connects the first switch S1 and the second switch S2. The voltage at the node increases, and the voltage across the first switch S1 decreases. At this time, when the state changes to the first state φ1, that is, when the first switch S1 is turned on, ZVS of the first switch S1 is established.

Further, during the dead time, when I _L2 ≧0, the current I _L2 flows through the body diode of the fourth switch S4, and the voltage across the fourth switch S4 becomes small. At this time, when the state changes to the first state φ1, that is, when the fourth switch S4 is turned on, ZVS of the fourth switch S4 is established.

FIG. 4 is a current waveform diagram of the series capacitor step-down converter 100. The switching frequency f _sw matches the resonant frequency f ₀ of the main circuit 110, and the first state φ1 and the second state φ2 transition at the timing when the resonant current Ires becomes zero. Dead time is omitted here. FIG. 4 shows current waveforms when the first switch S1 to the fourth switch S4 are ideal switches, that is, when the first switch S1 to the fourth switch S4 do not include parasitic capacitance.

At the end of the first state φ1, the current I _L1 of the first inductor L1 is positive or zero (I _L1 ≧0), and the current I _L2 of the second inductor L2 is negative (I _L2 <0). The ZVS conditions are met.

Similarly, at the end of the second state φ2, the current I _L1 of the first inductor L1 is negative (I _L1 <0), and the current I _L2 of the second inductor L2 is positive or zero (I _L2 ≧0). Therefore, the above-mentioned ZVS conditions are satisfied.

In this way, the series capacitor step-down converter 100 can satisfy the ZVS condition by switching at the resonant frequency f ₀ and can operate with high efficiency.

FIG. 5 is a current waveform diagram of the series capacitor step-down converter 100. Although FIG. 4 shows a waveform ignoring the parasitic capacitance of the MOSFET, in reality, parasitic capacitance exists. This parasitic capacitance suppresses discontinuity of current across the dead time. The coil currents I _L1 and I _L2 are continuous, and have symmetrical waveforms on the time axis with respect to the dead time in the first state φ1 and the second state φ2.

FIG. 6 is a time chart illustrating the operation of the series capacitor step-down converter 100 in consideration of dead time. FIG. 6 shows the operation when the switching frequency f _SW is equal to the resonant frequency f ₀ , and the length T _ON of the first state φ1 and the second state φ2 is the resonant period T _r (=1/f _r ) is 1/2.

If the switching frequency f _SW can be made to completely match the resonant frequency f ₀ , the ZVS condition will always hold, and high efficiency operation will be possible.

Consider dead time losses. Attention is paid to the dead time T _D2 between the second state φ2 and the first state φ1 in the time chart of FIG.

FIG. 7 is an operational waveform diagram during dead time TD2 during transition from second state φ2 to first state φ1. The voltage V _SW1 is the voltage at the first switching node SW1, and is referred to as a switching voltage V _SW1 .

Before time _t0 , the second state φ2 is reached, in which the first switch S1 is off and the second switch S2 is on. During the second state φ2, the voltage _VSW1 of the first switching node SW1 is 0V.

At time _t0 , the second switch S2 is turned off, resulting in a dead time _TD2 . As described above, when the ZVS condition is satisfied, the first coil current I _L1 is negative (<0) at time t ₀ and flows toward the first switching node SW1. This first coil current I _L1 charges the parasitic capacitances of the first switch S1 and the second switch S2, and the switching voltage V _SW1 increases. Then, when the switching voltage V _SW1 rises to around Vin/2, the first coil current I _L1 begins to flow through the body diode of the first switch S1. While the first coil current I _L1 is flowing through the body diode, the switching voltage V _SW1 is
V _SW1 ≒Vin/2+Vf
becomes. Vf is the forward voltage of the body diode.

If the timing of transition from the dead time T _D2 to the first state φ1 is too early, in other words, if the dead time T _D2 is too short, the first switch S1 will be turned on during the charging period. During the charging period, the drain-source voltage Vds1 of the first switch S1 is large, resulting in hard switching and lower efficiency. Therefore, the timing of transition to the first state φ1 is preferably after the body diode is turned on.

On the other hand, while the first coil current I _L1 is flowing through the body diode, a loss of I _L1 ×Vf occurs in the body diode, so if the dead time T _D2 is too long, the loss increases.

Therefore, in order to achieve high efficiency operation, it is desirable that the length of the dead time T _D2 be close to the boundary between the charging section of the switching node and the conduction section of the body diode. Although the dead time _TD2 when transitioning from the second state φ2 to the first state φ1 has been described here, the same applies to the dead time _TD1 when transitioning from the first state φ1 to the second state φ2.

In the following, switching control capable of highly efficient operation will be described.

(Embodiment 1)
FIG. 8 is a block diagram of a series capacitor step-down converter 100 including a controller IC 200 according to the first embodiment. The controller IC 200 includes a control logic circuit 210, an oscillator 220, a first timing generator 230, a third timing generator 240, and drivers DR1 to DR4. The controller IC 200 includes a first output pin OUT1 to a fourth output pin OUT4, a first voltage detection pin VS1, and a second voltage detection pin VS2. The first output pin OUT1 to the fourth output pin OUT4 are connected to the gates of the first switch S1 to the fourth switch S4. The first voltage detection pin VS1 is connected to the first switching node SW1, and receives the first switching voltage V _SW1 . The second voltage detection pin VS2 is connected to the second switching node SW2, and receives the second switching voltage V _SW2 .

Oscillator 220 has an oscillation frequency that corresponds to the resonance frequency f _r of main circuit 110 and generates clock signal CLK. Clock signal CLK is supplied to control logic circuit 210. The control logic circuit 210 switches between the first state φ1 and the second state φ2 in synchronization with the clock signal CLK. The edge of the clock signal CLK indicates the end timing _t0 of the second state φ2 and the end timing _t2 of the first state φ1.

The first timing generator 230 monitors the first switching voltage V _SW1 at the second dead time T _D2 . Then, when the first switching voltage V _SW1 crosses a predetermined upper threshold voltage Vthh, a first timing signal St1 that triggers turning on the first switch SW1 is asserted. Using the first timing signal St1 as a trigger, the control logic circuit 210 turns on the first switch S1, turns on the fourth switch S4 at the same time or with a time difference, and changes from the second dead time T _D2 to the first state φ1. Transition.

The upper threshold voltage Vthh is set around Vin/2. Preferably, Vthh is Vin/2×0.7≦Vthh≦Vin/2+0.5
may be set within the range of

Similarly, the third timing generator 240 monitors the second switching voltage V _SW2 at the first dead time T _D1 . Then, when the second switching voltage V _SW2 crosses the upper threshold voltage Vthh, the third timing signal St2, which triggers the turn-on of the third switch SW3, is asserted. The control logic circuit 210 uses the third timing signal St2 as a trigger to turn on the third switch S3, and simultaneously or with a time difference therebetween, turns on the second switch S2, and changes from the first dead time T _D1 to the second state φ2. Transition to.

The above is the configuration of the controller IC 200. Next, its operation will be explained.

FIG. 9 is an operational waveform diagram of the controller IC 200 of FIG. 8. At time _t0 when the edge of the clock signal CLK occurs, the second switch S2 and the third switch S3 are turned off, and the second state φ2 transitions to the dead time _TD2 . When the dead time T _D2 begins, the first switching voltage V _SW1 increases. When the first switching voltage _VSW1 crosses the upper threshold Vthh at time _t1 , the timing signal St1 is asserted. In response to this assertion, the control logic circuit 210 turns on the first switch S1 and the fourth switch S4, and transitions to the first state φ1.

At time _t2 when the next edge of clock signal CLK occurs, the first state φ1 transitions to dead time _TD1 . When the dead time T _D1 begins, the second switching voltage V _SW2 increases. When the second switching voltage _VSW2 crosses the upper threshold Vthh at time _t3 , the timing signal St2 is asserted. In response to this assertion, the control logic circuit 210 turns on the second switch S2 and the third switch S3, and transitions to the second state φ2.

The above is the operation of the controller IC 200. According to this controller IC 200, the drain-source voltage is sufficiently small at the timing of turn-on of the first switch S1, resulting in soft switching. Similarly, at the turn-on timing of the second switch S2, the drain-source voltage is sufficiently small, resulting in soft switching. Therefore, highly efficient operation is possible.

(Embodiment 2)
In the first embodiment, the first switch S1 and the fourth switch S4 are simultaneously turned on in response to the assertion of the first timing signal St1, and the second switch S2 and the third switch S4 are turned on simultaneously in response to the assertion of the third timing signal St2. Switch S3 was turned on at the same time. In the second embodiment, the first switch S1 and the fourth switch S4 are turned on at different timings, and the second switch S2 and third switch S3 are turned on at different timings.

FIG. 10 is a block diagram of a series capacitor step-down converter 100A including a controller IC 200A according to the second embodiment.

The controller IC 200A includes a second timing generator 250 and a fourth timing generator 260 in addition to the controller IC 200 of FIG.

The second timing generator 250 monitors the first switching voltage V _SW1 during the first dead time T _D1 , and when the first switching voltage V _SW1 crosses a predetermined lower threshold Vthl, the second timing generator 250 switches the second switch S2. A second timing signal St2 instructing turn-on is asserted.

Further, the fourth timing generator 260 monitors the second switching voltage V _SW2 during the second dead time T _D2 , and turns on the fourth switch S4 when the second switching voltage V _SW2 crosses the lower threshold Vthl. A fourth timing signal St4 is asserted.

During the second dead time T _D2 , the control logic circuit 210 turns on the first switch S1 in response to the assertion of the first timing signal St1, and turns on the fourth switch S4 in response to the assertion of the fourth timing signal St4. do. Furthermore, during the first dead time T _D1 , the control logic circuit 210 turns on the second switch S1 in response to the assertion of the second timing signal St2, and turns on the third switch S3 in response to the assertion of the third timing signal St3. Turn on.

The above is the configuration of the controller IC 200A.

FIG. 11 is an operational waveform diagram of the controller IC 200A of FIG. 10. According to the controller IC 200A of FIG. 10, not only the high-side switches S1 and S3 but also the low-side switches S2 and S4 can be turned on in a state where the drain-source voltage is small, so that efficiency can be improved.

If only the efficiency of the low-side switch is to be improved, the first timing generator 230 and the third timing generator 240 may be omitted from the controller IC 200A of FIG. 10. In that case, the second switch S2 and the third switch S3 may be turned on in response to the second timing signal St2, and the first switch S1 and the fourth switch S4 may be turned on in response to the fourth timing signal St4.

In the embodiment, both the first switching voltage V _SW1 and the second switching voltage V _SW2 are monitored, but only one of them may be monitored.

In the embodiment, a separately excited system in which switching is performed in synchronization with a clock signal generated by an oscillator has been described, but the present disclosure is not limited thereto, and can also be applied to a self-excited controller.

(Application)
FIG. 12 is a diagram illustrating an example of an electronic device 700 including a series capacitor step-down converter 100. A suitable example of the electronic device 700 is a server. Originally, the server was connected to a 12V power line, so the internal circuit 710 is designed to operate at 12V. The internal circuit 710 may include a CPU (Central Processing Unit), a memory, a LAN (Local Area Network) interface circuit, a DC/DC converter that steps down a 12V voltage, and the like.

In recent years, there has been a movement to replace the bus voltage from 12V to 48V in order to reduce the current flowing through electric wires. In this case, a power supply circuit 720 that steps down the 48V power supply voltage to 12V is required. The above-described series capacitor step-down converter 100 with a gain of 1/4 can be suitably used in such a power supply circuit 720.

The electronic device 700 is not limited to a server, and may be an in-vehicle device. Conventional automobile batteries are typically 12V or 24V, but hybrid vehicles may employ a 48V system, and in this case also a power supply circuit is required to convert the 48V battery voltage to 12V. In such a case, the 1/4 series capacitor step-down converter 100 can be suitably used.

In addition, the electronic device 700 may be industrial equipment, OA equipment, or consumer equipment such as audio equipment.

(Additional note)
The technology included in the present disclosure can be understood as follows.

(Item 1)
A controller circuit for a series capacitor buck converter, the controller circuit comprising:
The series capacitor buck converter includes:
an input line and an output line;
a first switch having a first end connected to the input line;
a coupled inductor including a first inductor and a second inductor each having a first end connected to the output line;
a second switch connected between a first switching node, which is a second end of the first inductor, and ground;
a series capacitor connected between a second end of the first switch and the first switching node;
a third switch connected between the second end of the first switch and a second switching node that is the second end of the second inductor;
a fourth switch connected between the second switching node and ground;
an output capacitor connected to the output line;
Equipped with
The controller circuit includes:
A first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on are alternately repeated with a dead time in between. a control logic circuit that generates a plurality of control signals from a first switch to instruct the fourth switch to be on or off;
During a second dead time inserted between the transition from the second state to the first state, a first switching voltage generated at the first switching node is monitored, and the first switching voltage reaches a predetermined upper threshold. a first timing generator that asserts a first timing signal that instructs the first switch to turn on when the first timing signal crosses the first timing signal;
A controller circuit comprising:

(Item 2)
When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The controller circuit according to item 1, which satisfies the following.

(Item 3)
During a first dead time inserted between the transition from the first state to the second state, a second switching voltage generated at the second switching node is monitored, and the second switching voltage reaches a predetermined upper threshold. 2. The controller circuit of item 1, further comprising a third timing generator that asserts a third timing signal instructing turn-on of the third switch when crossed by a third timing signal.

(Item 4)
a second timing signal for monitoring the first switching voltage during the first dead time and asserting a second timing signal instructing to turn on the second switch when the first switching voltage crosses a predetermined lower threshold; 4. The controller circuit according to any of items 1 to 3, further comprising a 2 timing generator.

(Item 5)
A fourth timing signal for monitoring the second switching voltage during the second dead time and asserting a fourth timing signal instructing to turn on the fourth switch when the second switching voltage crosses a predetermined lower threshold. 4. The controller circuit according to any of items 1 to 3, further comprising a 4 timing generator.

(Item 6)
The controller circuit according to any one of items 1 to 5, which is monolithically integrated on one semiconductor substrate.

(Item 7)
The main circuit of a series capacitor buck converter,
the controller circuit according to any one of items 1 to 5, which drives the main circuit;
A series capacitor buck converter comprising:

(Item 8)
A method for controlling a series capacitor buck converter, the method comprising:
The series capacitor buck converter includes:
an input line and an output line;
a first switch having a first end connected to the input line;
a coupled inductor including a first inductor and a second inductor each having a first end connected to the output line;
a second switch connected between a first switching node, which is a second end of the first inductor, and ground;
a series capacitor connected between a second end of the first switch and the first switching node;
a third switch connected between the second end of the first switch and a second switching node that is the second end of the second inductor;
a fourth switch connected between the second switching node and ground;
an output capacitor connected to the output line;
Equipped with
The control method includes:
a step of alternately repeating a first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on, with a dead time in between;
During a second dead time inserted between the transition from the second state to the first state, a first switching voltage generated at the first switching node is monitored, and the first switching voltage reaches a predetermined upper threshold. asserting a first timing signal that, when crossed with a value, instructs the first switch to turn on;
A control method comprising:

(Item 9)
When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The control method described in item 8, which satisfies the following.

(Item 10)
During a first dead time inserted between the transition from the first state to the second state, a second switching voltage generated at the second switching node is monitored, and the second switching voltage reaches a predetermined upper threshold. 9. The control method according to item 8, further comprising the step of asserting a third timing signal that instructs to turn on the third switch when the third timing signal crosses the value.

(Item 11)
The control method according to item 10, wherein the upper threshold is equal to the upper threshold.

(Item 12)
When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The control method according to item 10 or 11, which satisfies the following.

The embodiments are illustrative, and it is understood that there are various modifications to the combinations of the constituent elements and processing processes, and that such modifications are also included in the present disclosure and may constitute the scope of the present invention. It will be understood by those skilled in the art.

100 Series capacitor buck converter 102 Input line 104 Output line 106 Ground line 110 Main circuit 112 Coupled inductor Lk Leakage inductance Lm Exciting inductance L1 First inductor L2 Second inductor Cr Series capacitor S1 First switch S2 Second switch S3 Third switch S4 4th switch Cout Output capacitor 200 Controller IC
210 Control logic circuit DR driver 220 Oscillator 230 First timing generator 240 Third timing generator 250 Second timing generator 260 Fourth timing generator

Claims (12)

A controller circuit for a series capacitor buck converter, the controller circuit comprising:
The series capacitor buck converter includes:
an input line and an output line;
a first switch having a first end connected to the input line;
a coupled inductor including a first inductor and a second inductor each having a first end connected to the output line;
a second switch connected between a first switching node, which is a second end of the first inductor, and ground;
a series capacitor connected between a second end of the first switch and the first switching node;
a third switch connected between the second end of the first switch and a second switching node that is the second end of the second inductor;
a fourth switch connected between the second switching node and ground;
an output capacitor connected to the output line;
Equipped with
The controller circuit includes:
A first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on are alternately repeated with a dead time in between. a control logic circuit that generates a plurality of control signals from a first switch to instruct the fourth switch to be on or off;
During a second dead time inserted between the transition from the second state to the first state, a first switching voltage generated at the first switching node is monitored, and the first switching voltage reaches a predetermined upper threshold. a first timing generator that asserts a first timing signal that instructs the first switch to turn on when the first timing signal crosses the first timing signal;
A controller circuit comprising: When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The controller circuit according to claim 1, which satisfies the following. A second switching voltage generated at the second switching node is monitored during a first dead time inserted between the transition from the first state to the second state, and the second switching voltage is set to the upper threshold. 2. The controller circuit of claim 1, further comprising a third timing generator that asserts a third timing signal instructing turn-on of the third switch when crossed. a second timing signal for monitoring the first switching voltage during the first dead time and asserting a second timing signal instructing to turn on the second switch when the first switching voltage crosses a predetermined lower threshold; 4. A controller circuit according to any one of claims 1 to 3, further comprising a 2 timing generator. A fourth timing signal for monitoring the second switching voltage during the second dead time and asserting a fourth timing signal instructing to turn on the fourth switch when the second switching voltage crosses a predetermined lower threshold. 4. A controller circuit according to any of claims 1 to 3, further comprising a 4 timing generator. 4. The controller circuit according to claim 1, wherein the controller circuit is monolithically integrated on one semiconductor substrate. The main circuit of a series capacitor buck converter,
The controller circuit according to any one of claims 1 to 3, which drives the main circuit;
A series capacitor buck converter comprising: A method for controlling a series capacitor buck converter, the method comprising:
The series capacitor buck converter includes:
an input line and an output line;
a first switch having a first end connected to the input line;
a coupled inductor including a first inductor and a second inductor each having a first end connected to the output line;
a second switch connected between a first switching node, which is a second end of the first inductor, and ground;
a series capacitor connected between a second end of the first switch and the first switching node;
a third switch connected between the second end of the first switch and a second switching node that is the second end of the second inductor;
a fourth switch connected between the second switching node and ground;
an output capacitor connected to the output line;
Equipped with
The control method includes:
a step of alternately repeating a first state in which the first switch and the fourth switch are on, and a second state in which the second switch and the third switch are on, with a dead time in between;
During a second dead time inserted between the transition from the second state to the first state, a first switching voltage generated at the first switching node is monitored, and the first switching voltage reaches a predetermined upper threshold. asserting a first timing signal that, when crossed with a value, instructs the first switch to turn on;
A control method comprising: When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The control method according to claim 8, which satisfies the following. During a first dead time inserted between the transition from the first state to the second state, a second switching voltage generated at the second switching node is monitored, and the second switching voltage reaches a predetermined upper threshold. 9. The control method of claim 8, further comprising asserting a third timing signal that instructs turn-on of the third switch upon crossing a value. The control method according to claim 10, wherein the upper threshold is equal to the upper threshold. When the upper threshold is Vthh and the input voltage of the input line is Vin,
Vin/2×0.7≦Vthh
The control method according to claim 10 or 11, which satisfies the following.

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