JP2024016670A - Inkjet head unit and inkjet printer - Google Patents

Abstract

An object of the present invention is to provide an inkjet head unit that cuts off a power supply line that involves all paths through which a through current generated in a driver IC flows due to latch-up.
[Solution] An inkjet head unit includes a driver IC that drives an actuator, first and second power supply lines that supply different power supplies to the driver IC, and a first fuse of a first fusing current provided in the first power supply line. The power supply device includes a fuse and a second fuse provided in the second power supply line and having a second blowing current smaller than the first blowing current. When a latch-up occurs in the driver IC and a first path through which a through current related to the first power supply line flows and a second path through which a through current related to the second power supply line flows are established, the second fuse blows. simultaneously or with a delay, the first fuse blows to cut off the first path, electrically separating the first power supply line and the second power supply line from the driver IC. do.
[Selection diagram] Figure 2

Description

Embodiments of the present invention relate to an inkjet head unit and an inkjet printer having a protection circuit.

2. Description of the Related Art Inkjet printers that form images by ejecting ink onto a print medium are known as image forming apparatuses. An inkjet printer includes, for example, an inkjet head and a head control unit that controls the inkjet head. An inkjet head includes an actuator having a capacitive load connected to a plurality of capacitive elements, and a driver IC that drives the actuator.
The driver IC includes a logic circuit and a semiconductor switch. The driver IC generates a drive signal from the drive power source by switching the semiconductor switch based on the output of the logic circuit under the control of the head control section, and supplies this drive signal to each capacitive element of the actuator.

Inkjet printers use a driver IC to generate multiple types of drive signals with different potentials and different waveforms in order to improve the quality of ink ejection. Since the driver IC described above is formed by a CMOS process, it often includes parasitic circuits. Therefore, when latch-up occurs, the structure is such that a plurality of through current paths due to parasitic circuits are likely to occur. Inkjet printers instantaneously supply drive signals to drive actuators at high speed. If latch-up occurs due to external noise, etc., and multiple through-current paths are created, even if only the main drive power source is disconnected, it will not be possible to disconnect all through-current paths from other drive power sources. There is a possibility. Therefore, in order to prevent overcurrent from flowing to the driver IC due to latch-up and causing burnout due to heating, a protection circuit including a fuse is installed in the power supply line to cut off the power supply to the driver IC. It is configured so that it can be done.

JP2017-53236A

The fuse of the protection circuit mentioned above is a fuse with a large capacity (rated current) that has a certain tolerance and is connected to the power supply line in order to prevent the fuse from blowing out due to the current flowing through the power supply line during normal operation of the driver IC. provided for each.

When a plurality of through current paths occur due to latch-up, all fuses related to the through current may not blow, depending on the occurrence situation. For example, in an example where fuses of the same capacity are provided on each power supply line to which different potentials are supplied, one fuse with a higher potential blows first, reducing the through current and causing the other fuse to melt. In some cases, the fuse does not blow and the through current path is maintained as it is.

Therefore, it is an object of the present invention to provide an inkjet head and an inkjet printer that have a protection circuit that shuts off power supply lines related to all the paths even if a plurality of paths through which through current flows occur due to latch-up.

An inkjet head unit according to an embodiment includes: an actuator having a capacitive load connected to a plurality of capacitive elements that eject ink; a driver IC that drives the capacitive element of the actuator; a first capacitor provided on a first power supply line that supplies power at a potential; and a second capacitor provided on a second power supply line that supplies power at a second potential smaller than the first potential to the driver IC. a second capacitor, a first fuse with a first blowing current provided in the first power supply line between the first capacitor and the driver IC, and a first fuse with a first blowing current provided between the second capacitor and the driver IC; a second fuse provided in the second power supply line and having a second blowing current smaller than the first blowing current; When a first path through which a through current related to the second power supply line flows and a second path through which a through current related to the second power supply line flows, the second fuse blows to cut off the second path, and simultaneously or The first fuse blows out with a delay to cut off the first path and electrically isolate the first power supply line and the second power supply line with respect to the driver IC.

FIG. 1 is an explanatory diagram showing a configuration example of an inkjet printer according to an embodiment. FIG. 2 is a diagram showing a configuration example of an inkjet head unit and a head control section. FIG. 3 is a diagram showing a configuration example of a driver IC. FIG. 4 is a diagram showing a configuration example of a driver IC and an actuator. FIG. 5 is a diagram showing an example of the configuration of the driver. FIG. 6 is a diagram showing the stacked structure and equivalent circuit of the driver. FIG. 7 is a diagram showing the flow of trigger current generated in the equivalent circuit of the parasitic circuit. FIG. 8 is a diagram showing the flow of through current at the time of latch-up occurring in the equivalent circuit of the parasitic circuit. FIG. 9 is a diagram showing the flow of through current at the time of latch-up occurring in the equivalent circuit of the parasitic circuit when the drive power supply V2 is supplied in addition to the drive power supply V1. FIG. 10 is a diagram showing a line where the fuse blows and a line where the fuse is difficult to blow. FIG. 11 is a diagram showing a blow line where a fuse blows.

An inkjet printer and an inkjet head unit according to a first embodiment will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing a configuration example of an inkjet printer 1 according to an embodiment.

The inkjet printer 1 forms an image on the print medium while conveying the print medium as a recording medium. The inkjet printer 1 includes a control section 11, a display 12, an operation section 13, a communication interface 14, a transport motor 15, a motor drive circuit 16, a pump 17, a pump drive circuit 18, an inkjet head unit 19, a head control section 20, and a power supply 21. Equipped with. Furthermore, the inkjet printer 1 includes a transport mechanism, a paper feed cassette, and a paper ejection tray (not shown).

The control unit 11 includes a processor 22 and a memory 23, and performs various controls on the inkjet printer 1. The processor 22 is an arithmetic element that performs arithmetic processing. The processor 22 performs various processes based on, for example, programs stored in the memory 23 and data used in the programs. The memory 23 rewritably stores programs and data used in the programs.

The display 12 is, for example, a display device such as a liquid crystal display, and displays an image in response to a video signal input from the processor 22 or a graphics controller (not shown) for performing image processing.

The operation unit 13 includes an operation unit that generates an operation signal based on a user's operation. The operation unit 13 is, for example, a touch sensor, a numeric keypad, a power key, a paper feed key, various function keys, a keyboard, or the like. The touch sensor is, for example, a resistive touch sensor, a capacitive touch sensor, or the like. The touch sensor acquires information indicating a specified position within a certain area. Further, the touch sensor may be used as a touch panel that is placed on the top surface of the display 12 and is integrally configured. In this case, the touch sensor generates a signal indicating the touched position on the screen displayed on the display 12.

The communication interface 14 is an interface for communicating with external equipment. In this embodiment, the communication interface 14 is used, for example, to communicate with at least one host PC 2 that transmits print data to the inkjet printer 1. The communication interface 14 communicates with the host PC 2 via a wired or wireless network 24, such as a LAN (Local area network).

By rotating, the conveyance motor 15 serves as a drive source for a conveyance mechanism (not shown) for conveying the print medium. The conveyance mechanism includes a conveyance belt that conveys the print medium, a plurality of rollers (a driving roller and a driven roller) around which the conveyance belt is stretched, a guide, and the like. The conveyance motor 15 rotates a drive roller to move the conveyance belt. The print medium moves along a transport path defined by a guide located near the transport belt.

The motor drive circuit 16 drives the transport motor 15 according to the transport control signal input from the control section 11 . The motor drive circuit 16, the transport motor 15, and the transport mechanism transport a print medium taken out from a paper feed cassette (not shown) to a paper discharge tray (not shown) via an inkjet head unit 19. Note that the paper feed cassette is a cassette that accommodates a plurality of print media. The paper ejection tray is a tray that accommodates print media ejected from the inkjet printer 1.

The pump 17 supplies ink from the ink tank to the ink chamber of the inkjet head unit 19 via an ink supply path. The pump 17 is arranged on an ink supply path consisting of a tube (not shown) that connects an ink tank and an ink chamber (a pressure chamber of a capacitive element to be described later) of the inkjet head unit 19.
Pump drive circuit 18 drives pump 17 according to an ink supply control signal input from processor 22 .

The inkjet head unit 19 forms an image by ejecting ink onto a print medium. The inkjet head unit 19 forms an image by ejecting ink onto a print medium conveyed by a conveyance mechanism based on drive power and control signals supplied from the head control section 20. A plurality of inkjet head units 19 are provided corresponding to each color of ink, for example, cyan, magenta, yellow, and black.

The head control unit 20 operates the inkjet head unit 19 to eject ink from an actuator within the inkjet head unit 19 to form an image on a print medium. The head control section 20 is a circuit that is connected to the control section 11, the power supply 21, and the host PC 2, and controls the inkjet head unit 19. The head control section 20 supplies the inkjet head unit 19 with a plurality of driving power sources having different potentials. Further, the head control unit 20 generates a control signal based on print data input via the communication interface 14 .

The power source [main power source] 21 converts AC power supplied from a commercial power source into DC power (DC voltage DCV). The power supply 21 supplies DC power as a driving power source to each component within the inkjet printer 1 .

The inkjet head unit 19 and head control section 20 will be described with reference to FIG. 2. FIG. 2 is a diagram showing a configuration example of the inkjet head unit 19 and the head control section 20.
The inkjet head unit 19 and the head control section 20 are electrically connected by an I/F cable 35 for transmission. The I/F cable 35 is preferably FFC or FPC. Alternatively, if the connection distance is long, a harness assembly may be used. Thereby, the head control section 20 supplies, through the I/F cable 35, drive power and control signals including a common GND used by the inkjet head unit 19.

First, the head control section 20 will be explained.
The head control unit 20 includes a drive power supply V1 generation circuit 31, a drive power supply V2 generation circuit 32, a logic circuit power supply VDD generation circuit 33, and a control signal generation circuit 34.

The drive power supply V1 generation circuit 31 and the drive power supply V2 generation circuit 32 generate drive power necessary for the operation of the inkjet head unit 19 and the actuator 42 using the DC voltage DCV supplied from the power supply 21. For example, the drive power supply V1 generation circuit 31 uses the DC voltage DCV to generate the drive power supply V1 (first potential power supply) to be supplied to the level shift circuit 52 and driver circuit 53 of the driver IC 43, which will be described later. Further, the drive power supply V2 generating circuit 32 generates the drive power supply V2 (second potential power supply) to be supplied to the driver circuit 53 and the actuator 42 using the DC voltage DCV. In this embodiment, the drive power source V1 and the drive power source V2 have a potential difference, and have a relationship such that the voltage value of the drive power source V1>the voltage value of the drive power source V2. As an example, the drive power supply V2 is set to 50% of the drive power supply V1. Here, when the drive power supply V1 is 30V, the drive power supply V2 is assumed to be 15V.

The logic circuit power supply VDD generation circuit 33 generates the logic circuit power supply VDD to be supplied to the logic circuit 51 and level shift circuit 52 of the driver IC 43.
The control signal generation circuit 34 generates a control signal based on print data input from the host PC 2 via the communication interface 14. This control signal includes a clock signal CK, a reset signal RST, an initialization signal INIT, print data SDI, and the like. The control signal generated by the control signal generation circuit 34 is output to the logic circuit 51 of the driver IC 43, which will be described later.

Next, the inkjet head unit 19 will be explained.
The inkjet head unit 19 includes a head PC board 41, an actuator 42, and a driver IC 43. Furthermore, a heat sink (radiating fin) 46 is attached within the inkjet head unit 19 to radiate heat from the driver IC 43.

The actuator 42 has a capacitive load connected to a plurality of capacitive elements for ejecting ink, as shown in FIG. 4 described later. These capacitive elements include, for example, two piezoelectric members sandwiched between two electrodes formed in a groove. A pressure chamber filled with ink is formed by two piezoelectric members and a nozzle plate (not shown). These piezoelectric members deform the pressure chamber based on the potential difference between the two electrodes, and eject ink from the nozzle provided on the nozzle plate. The driver IC 43 drives a plurality of capacitive elements of the actuator 42.

The head PC board 41 relays the drive power supply V1, drive power supply V2, logic circuit power supply VDD, control signal, and GND potential transmitted from the head control unit 20 through the I/F cable 35 to the driver IC and the actuator 42. The GND potential is a ground potential for drive power supplies V1 and V2, logic circuit power supply VDD, control signals, and the like. Further, the head PC board 41 includes a protection circuit 47, which will be described later, on each power supply line of the drive power source V1 and the drive power source V2. Further, the control signals include a clock signal CK, a reset signal RST, an initialization signal INIT, print data SDI, and the like.

Next, the driver IC 43 will be explained with reference to FIG.
FIG. 3 is a diagram showing an example of the configuration of the driver IC 43. This driver IC 43 includes a logic circuit 51, a level shift circuit 52, and a driver circuit 53. These circuits are formed on a semiconductor chip using a CMOS process. This driver IC 43 is configured in the form of a COF (Chip On Film) package 45. In this COF package 45, a chip of the driver IC 43 is mounted on the surface of a film made of a resin material on which wiring is formed, for example, a polyimide film 44, and the chip is sealed with resin.

The logic circuit 51 operates using the logic circuit power supply VDD generated by the logic circuit power supply VDD generation circuit 33. The logic circuit 51 controls the operation of switching elements of drivers 53a to 53n, which will be described later, in the driver circuit 53 based on input control signals such as a clock signal CK, a reset signal RST, an initialization signal INIT, and print data SDI. Generate a drive signal for Logic circuit 51 outputs these drive signals to level shift circuit 52.

The level shift circuit 52 converts the voltage level of the drive signal input from the logic circuit 51 using the drive power supply V1. The level shift circuit 52 outputs the drive signal whose voltage level has been converted to the driver circuit 53.

The driver circuit 53 will be explained with reference to FIGS. 4 and 5.
FIG. 4 is a diagram showing a configuration example of a driver IC and an actuator. FIG. 5 is a diagram showing an example of the configuration of the driver. The driver circuit 53 is composed of a plurality of drivers 53a to 53n. The number of these drivers 53a to 53n is set by the number of nozzles (or the number of capacitive elements) provided in the actuator 42.

Each driver 53a-53n is connected to one electrode of a series-connected capacitive element in each actuator 42. Each of the drivers 53a to 53n receives drive power supplies V1 and V2, outputs drive signals DRV1 to DRVn, and drives the actuator 42.
When drive signals DRV1 to DRVn are input from the respective drivers 53a to 53n to the electrodes of the capacitive elements, the volume of the pressure chamber changes. As a result, the pressure in the pressure chamber changes, and the ink in the pressure chamber is ejected from the ejection nozzle. As described above, the drivers 53a to 53n are formed using a CMOS process.

In addition, a capacitor C1 (first capacitor) is arranged as a bypass before the driver IC 43 on the power supply line (first power supply line) of the drive power supply V1, and similarly A capacitor C2 (second capacitor) is placed in front of the driver IC 43 on the second power supply line.

In order to drive the actuator 42 at high speed, it is necessary to instantaneously supply drive signals DRV1 to DRVn to each of the drivers 53a to 53n. Therefore, by charging the capacitors C1 and C2 in advance, the drive power supplies V1 and V2 are instantaneously supplied to the drivers 53a to 53n. Ceramic capacitors are suitable for these capacitors C1 and C2, and the capacitance value is determined based on conditions such as assuming the voltage drop due to maximum power from the design value and satisfying the rising and falling requirements of the drive waveform. decide. In this embodiment, the capacitors C1 and C2 preferably have a capacity of about 12 [μF].

In this embodiment, a protection circuit 47 is provided in the power supply line. Specifically, a fuse F1 (first fuse) is provided on the power supply line of the drive power supply V1 between the capacitor C1 and the driver IC 43. Similarly, a fuse F2 (second fuse) is provided on the power supply line of the drive power supply V2 between the capacitor C2 and the driver IC 43. These fuses F1 and F2 function as a protection circuit to cut off the power supply line and prevent the drive power supplies V1 and V2 from being supplied to the driver IC 43 when latch-up occurs in the driver IC 43. Note that the capacitance and blowout timing of the fuses F1 and F2 will be described later.

Next, the drivers 53a to 53n will be explained with reference to FIG. Hereinafter, one driver 53a will be explained as an example.
The driver 53a uses transistors M1 and M3 made up of PMOSFETs and transistors M2 and M4 made up of NMOSFETs. These are constituted by a switch made up of transistors M1 and M2, and a switch made up of transistors M3 and M4. Of these, the transistor M1 constitutes a switch connected to the drive power supply V1, the transistor M2 constitutes a switch connected to GND, and the transistors M3 and M4 constitute a switch connected to the drive power supply V2.

This driver 53a has four output patterns of drive signals DRV. The first pattern is the voltage of the drive power supply V1 (first potential level), the second pattern is the voltage of the drive power supply V2 (second potential level), and the third pattern is the potential level of GND (ground) (voltage 0V). A drive signal DRV of one of different potential levels is output. Furthermore, as a fourth pattern, the driver 53a is placed in a high impedance state in which it does not output any drive signal.

The connection relationship between each of the transistors M1 to M4 will be explained.
In the transistor M1, a drive power supply V1 is applied to the source, a drive signal DRV is output from the drain, and a back gate is connected to the N-well region of the P-type semiconductor substrate. Note that a driving power supply V1 is applied to the N-well region. The transistor M2 has a source connected to GND, a drain outputting a drive signal DRV, and a back gate connected to a P-type semiconductor substrate. Note that the P-type semiconductor substrate is connected to GND.

The transistor M3 has a source applied with the drive power V2, a drain outputting a drive signal DRV, and a back gate connected to the N-well. Note that the driving power supply V1 is applied to the N well. The transistor M4 has a source applied with a driving power supply V2, a drain which outputs a driving signal DRV, and a back gate connected to a P-type substrate. Note that the P-type semiconductor substrate is connected to GND. The drains of the output terminals of the transistors M1 to M4 are connected to the electrodes of the series-connected capacitive elements of the respective actuators. A driving power supply V2 is applied to these series-connected capacitive elements. The drive power supply V2 here is the potential of the common electrode of the actuator.

When the driver 53a configured in this manner outputs the voltage V1 (drive power supply V1) as the first pattern drive signal DRV, it turns on the transistor M1 and turns off the transistors M2, M3, and M4. Similarly, when outputting the voltage V2 (drive power supply V2) as the second pattern drive signal DRV, the transistors M3 and M4 are turned on and the transistors M1 and M2 are turned off. When outputting GND (0V) to the drive signal DRV as the third pattern drive signal DRV, the transistor M2 is turned on and the transistors M1, M3, and M4 are turned off. When the fourth pattern drive signal DRV is set to high impedance, all transistors M1 to M4 are turned off.

The stacked structure and equivalent circuit of the drivers 53a to 53n will be explained with reference to FIG. FIG. 6 is a diagram showing the stacked structure and equivalent circuit of the driver.

An N-well region is formed in the P-type semiconductor substrate. A switching circuit including transistors M1 to M4 is formed on the main surface of the P-type semiconductor substrate. A driving power supply V1 is applied to the N-well, and the P-type semiconductor substrate is connected to GND.

In addition to the switching circuit formed by the transistors M1 and M3 of these PMOSFETs, a parasitic circuit exists in the vertical direction of the PMOSFET, which is the depth direction with respect to the main surface of the P-type semiconductor substrate. This parasitic circuit becomes a PNP transistor having the P type diffusion layer as the emitter, the N well region as the base, and the P type substrate as the collector. Here, the transistors are Q1, Q2, Q3, and Q4.

Similarly, in addition to the switching circuit formed by the NMOSFET transistors M2 and M4, a parasitic circuit exists in the vertical direction. This parasitic circuit becomes an NPN transistor having an N type diffusion layer as an emitter, a P type semiconductor substrate as a base, and an N well region as a collector. Here, transistors Q5, Q6, Q7, and Q8 are assumed. Note that the sheet resistance of the N-well region is Rwell, and the sheet resistance of the P-type semiconductor substrate is Rsub.

Next, with reference to FIGS. 7 and 8, a description will be given of how latch-up occurs using the output terminals DRV of the drivers 53a to 53n as a trigger. Hereinafter, one driver 53a will be explained as an example. FIG. 7 is a diagram showing the flow of trigger current generated in an equivalent circuit of the parasitic circuit shown in FIG. FIG. 8 is a diagram showing the flow of current at the time of latch-up occurring in the equivalent circuit of the parasitic circuit. FIG. 9 is a diagram showing the flow of through current at the time of latch-up occurring in the equivalent circuit of the parasitic circuit when the drive power supply V2 is supplied in addition to the drive power supply V1.

First, generation of the trigger current will be explained with reference to FIG.
When an event occurs in which the voltage of the drive signal DRV outputted from the driver 53a exceeds the drive power supply V1 by 0.6 V or more (for example, noise mixing), the emitter-base of the transistors Q2 and Q4 are biased in the forward direction. Due to the generation of this bias, a through current i1 flows from the output terminal side (drive signal DRV) to the drive power supply V1 terminal side through the bases of transistors Q2 and Q4. At the same time, a through current i2 also flows to the GND side of the P-type semiconductor substrate through the collectors of the transistors Q2 and Q4. When the above-described through current i2 flowing toward the GND side becomes large, the base-emitter of the transistor Q8 is biased in the forward direction.

As shown in FIG. 8, a through current i3 flows to the GND side through the base of the transistor Q8 due to the bias. The flow of this through current i3 forms the first A path. This through current i3 is used as a trigger current, and a through current i4 flowing through the transistor Q1 is also generated. The flow of this through current i4 forms the first B path. A state in which these through currents i3 and i4 flow is a latch-up. Once these through currents i3 and i4 flow and the 1st A path and 1B path are established, even if the voltage on the output end side (drive signal DRV) decreases, the through currents will flow from the drive power supply V1 to GND. Since the first A path and the first B path of the through currents i3 and i4 are maintained, the through currents will continue to flow unless the supply of the drive power source V1 is stopped. Note that the 1A route and the 1B route are collectively referred to as the 1st route.

Furthermore, in the state shown in FIG. 8, if the drive power supply V2 is supplied in addition to the drive power supply V1, as shown in FIG. After the two first A paths and first B paths through which the through current i4 flows are established, the voltage at the base of the transistor Q3 drops and the emitter-base of the transistor Q3 becomes forward biased, and the drive power source V2 is connected to the GND. A second path by the through current i5 flowing through is also established. If the latch-up continues as it is, the through currents i3, i4, and i5 may become overcurrents.

When latch-up occurs in this way and the first path and second path are established by the through currents i3, i4, i5 between the drive power source V1 and the drive power source V2, these through currents i3, i4, i5 become overcurrents. This will destroy or burn out the driver IC.
Therefore, in this embodiment, first, the fuse F2 of the protection circuit 47 provided in the power supply line of the drive power supply V2 which has been generated with a delay is blown. Next, if the fuse F1 installed in the power supply line that supplies the drive power supply V1, which is the cause of maintaining the latch-up, can be blown and the power supply of the drive power supply V1 can be stopped, all causes of the problem can be isolated. (separation), and it is possible to avoid a situation where the driver burns out due to heat generation.

Next, the arrangement relationship between the fuses F1 and F2 in the protection circuit 47 and the capacitors C1 and C2 arranged in the power supply line, and the blowing currents of the fuses F1 and F2 will be explained.
As described above, the capacitor C1 is placed on the front side (upstream side) of the driver IC 43 on the power supply line of the drive power source V1. Similarly, a capacitor C2 is placed on the front side (upstream side) of the driver IC 43 on the power supply line of the drive power source V2. As mentioned above, these capacitors C1 and C2 are used to instantly supply drive power V1 and V2 to the drivers 53a to 53n by charging them in advance in order to drive the actuator 42 at high speed. .

Further, in this embodiment, as shown in FIG. 3, the fuses F1 and F2 are arranged between the capacitors C1 and C2 and the driver IC 43 on the power supply line. In this arrangement, the capacitors C1 and C2, the fuses F1 and F2, and the driver IC 43 are connected in this order when viewed from the head control unit 20 side.

In contrast to this arrangement, for example, the fuses F1 and F2 are arranged on the power supply line before the capacitors C1 and C2. That is, when viewed from the head control section 20 shown in FIG. 1, the fuses F1 and F2, the capacitors C1 and C2, and the driver IC 43 are connected in this order. In the opposite arrangement, when the drive power is normally turned on, charging current flows to the capacitors C1 and C2 after passing through the fuses F1 and F2. In this case, there is a possibility that the Joule integral value flowing to the capacitors C1 and C2 exceeds the value that blows out the fuses F1 and F2. That is, it is not preferable to arrange fuses F1, F2 and capacitors C1, C2 in this order.

Therefore, in this embodiment, as shown in FIG. 3, the fuses F1 and F2 are arranged at a later stage (downstream) than the capacitors C1 and C2. With this arrangement, since the charging current to the capacitors C1 and C2 that occurs when the driving power is turned on does not pass through the fuses F1 and F2, it is possible to avoid blowing out of the fuses F1 and F2 due to the Joule integral value.

Next, with reference to FIGS. 10 and 11, the current flowing through the fuses F1 and F2 and the blowing current will be described. In the following description, the driver 53a among the drivers 53a to 53n will be described as an example. Figure 10 shows the Joule integral value on the vertical axis and the time on the horizontal axis, showing the blowing line L1 where the fuse blows, the line L2 where the fuse is difficult to blow due to inrush current durability, and the Joule integral (I^2*t) curve. 25% or less, indicating a line L3 in which the fuse is difficult to blow.

As a standard for fuses F1 and F2, the current that causes burnout when an overcurrent is passed through the power supply wiring of the driver IC 43 is defined as the burnout current, and a guideline for the current that blows fuses F1 and F2 is set so that the burnout current does not reach this burnout current. This is set as a dangerous current.

In the head control section 20 and inkjet head unit 19 of this embodiment, the burnout current that causes burnout to the driver 53a is 3.5 [A] from experiments, so the dangerous current is set to about 3 [A]. . In addition, regarding the normal drive current, select a fuse that is 25% or less of the Joule integral (I^2*t) curve used for fuse selection, and select a fuse that is below the lines L2 and L3 that are less likely to blow out. use.

Here, the fuse F1 has a rated current of 1.25 [A] and is blown within 5 seconds when 250% of the rated current is passed. In the case of this fuse F1, the design value of the fusing current (first fusing current) is 3.125 [A], and it can be handled without causing burnout.

Next, the dangerous current setting value of fuse F2 is the same as that of fuse F1. However, the normal drive current is set to a smaller value for the drive power supply V2 than for the main drive power supply V1. Therefore, normally, it is considered that there is no problem even if the fuse F2 is selected from the same standard as the fuse F1. However, in consideration of the occurrence of latch-up, selecting the same standard is not necessarily a suitable setting for the following reasons.

In FIG. 9, as described above, when latch-up occurs, a through current path is generated by the drive power supply V1 in the parasitic circuit, and then a new drive power supply is added in the same parasitic circuit with a delay of about 5 [μs]. A through current path is generated due to V2. At this time, if fuse F1 and fuse F2 are of the same standard, first, when fuse F1 is blown, the overcurrent due to through currents i3 and i4 is reduced, so fuse F2 is not blown subsequently. A situation occurs. If this fuse F2 is not blown, the through current i5 continues to flow, and parts related to the path of the through current i5, for example, the switching element of the driver 53a shown in FIG. 5, are damaged due to overcurrent or temperature rise. Otherwise, a situation that may lead to burnout is expected.

Furthermore, it has been confirmed that with the above-mentioned dangerous current setting, if latch-up occurs, the driver 53a will be destroyed if the time is about 30 [μs], but it will not burn out. Therefore, the specifications of the fuse F1 are selected so that the fuse F1 blows out at the blowout position Fa indicated by the circle in FIG.

In addition, the capacitance (charged charge) of the capacitor C1 is set so that the through current flowing in the power supply line becomes the Joule integral value on the fusing line L1 shown in FIG. Set.

Fuse F2 takes into account that the initial value of drive power supply V2 is 50% of the voltage of drive power supply V1, the amount of charge stored in capacitor C2 is small, and there is a delay of 5 [μs] in the flow of current. By selecting a fuse with a small rated current and a low fusing current (second fusing current), it can be blown out at the same time as or before the fuse F1. That is, by adjusting the magnitude of the Joule integral value that leads to the blowing of each of the fuses F1 and F2, the timing of blowing out the fuses F1 and F2 can be adjusted. Basically, the fuse F1 is set to blow after the fuse F2 blows or at the same time. Of course, when selecting fuse standards, it is important to be able to appropriately set the dangerous current that causes fusing and the normal drive current that does not cause fusing, but if both conditions cannot be met, change the capacitance of capacitor C2. You can.

Next, with reference to FIG. 11, a description will be given of the blowout status of the fuse F1 and the fuse F2. FIG. 11 shows the Joule integral value on the vertical axis and the time on the horizontal axis, and shows a blowing line L1 where the fuse F1 blows and a blowing line L4 where the fuse F2 blows.

When the driver IC latches up while the drive power supplies V1 and V2 are being supplied, a through current (overcurrent) path is established in the driver IC by the drive power supplies V1 and V2, respectively. The overcurrent flowing through this through current path destroys or burns out the driver IC.

In order to prevent this, first blow out the fuse F2 placed in the path of the through current caused by the drive power supply V2 that is generated late, and then blow out the fuse F1 to avoid destruction or burnout due to heat generation. It is possible to avoid the danger of In other words, if the fuse F1, which is placed on the power supply line to which the drive power V1 is applied, which causes damage and burnout due to latch-up, can be blown, all causes of the malfunction can be isolated, thereby avoiding danger. can do.

Therefore, as shown in FIG. 11, the fuse F1 of this embodiment is set at a position Fa indicated by a circle as a blowing current, and the fuse F2 is set at a position Fb indicated by a circle as a blowing current. Specifically, the fuse F1 used is one that has a rated current of 1.25 [A] and blows out within 5 seconds when 250% of the rated current flows. In the case of this fuse F1, the design value of the fusing current is 3.125 [A], and it can be handled as a fuse that will not burn out.

First, as an example of setting the blowing current of fuse F1 and fuse F2, fuse F1 has a rated current of 1.25 [A] and will blow within 5 seconds when 250% of the rated current flows. do. The fuse F2 has a rated current of 1 [A] and is blown out within 5 seconds when 250% of the rated current is passed.

The fuse F1 is blown out at a Joule integral value of 0.004 [A^2*sec] 20 [μs] after the latch-up occurs. At this time, the effective value of the current IF1rms[A] is
IF1rms[A]=√(0.004[A^2*sec]/20[μs]),
IF1rms[A]=√(200)=14.1[A],
becomes. Furthermore, the amount of charge q1 [C] discharged from the capacitor C1 is
q1=14.1[A]*20[μs]=282[μC].
The amount of charge q1init[C] discharged from the capacitor C1 charged in the initial state is q1init=12[μF]*30[V]=360[μC].
The fuse F2 generates a through current with a delay of 5 [μs] after the through current is generated by the drive power supply V1, so it actually blows out within 15 [μs] with a Joule integral value of 0.0015 [A^2*sec]. let Therefore, the effective value of current IF2rms[A] is
IF1rms[A]=√(0.0015[A^2*sec]/15[μs]),
IF1rms[A]=√(100)=10[A],
becomes. Furthermore, the amount of charge q2[C] discharged from the capacitor C2 is
q2=10[A]*15[μs]=150[μC].

The amount of charge q2init[C] discharged from the capacitor C2 charged in the initial state is q1init=12[μF]*15[V]=180[μC].
In this way, after the latch-up occurs, the fuse F2 of the power supply line to which the driving power V2 is supplied is blown first, and the fuse F1 of the power supply line to which the driving power V1 is supplied is blown at the same time or with a delay. Fuse it. The above-mentioned delay time (delay time) is a time determined at the time of circuit design, and is appropriately set according to the circuit configuration so that the fuse F1 is blown after the fuse F2 is blown. A first method for determining the delay time is to make fuse F1 more difficult to blow than fuse F2. For example, with respect to a burnout current that burns out a driver IC, a margin is added to the current that is cut off before burnout and is defined as a dangerous current. By selecting a standard for the fuse F1 so that it will blow with this dangerous current, the delay time leading to blowing can be maximized. That is, the delay time is determined by selecting the standard of the fuse F1. Further, as a second method for determining the delay time, the fuse F2 is made easier to blow than the fuse F1. For example, by selecting a fuse 2 that is rated to blow at the minimum value among the standards that do not blow at normal current, blowing can be accelerated. That is, by selecting the standard of the fuse F2, the delay time is determined by timing the fuses F1 and F2 to blow.

In order to carry out such a blowing order, the rated current of the fuse F2 is selected to be lower than the rated current of the fuse F1. With this selection, when a latch-up occurs and a through current flows due to the drive power supply V1, and later a through current flows due to the drive power supply V2, the fuse F2 of the power supply line to which the drive power supply V2 is supplied is first At the same time or with a delay, the fuse F1 of the power supply line to which the drive power V1 is supplied is blown. By such fusing, all causes of the problem can be isolated, and it is possible to avoid the risk of burning out the components of the driver IC 43 including the drivers 53a to 53n due to heat generated by overcurrent due to through current.

In addition, one embodiment of the present invention is presented as an example, and is not intended to limit the scope of the invention. This aspect can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. This one aspect and its modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

DESCRIPTION OF SYMBOLS 1... Inkjet printer, 2... Host PC, 11... Control unit, 12... Display, 13... Operating unit, 14... Communication interface, 15... Conveyance motor, 16... Motor drive circuit, 17... Pump, 18... Pump drive circuit, 19... Inkjet head unit, 20... Head control unit, 21... Power supply, 22... Processor, 23... Memory, 24... Network, 31... Drive power supply V1 generation circuit, 32... Drive power supply V2 generation circuit, 33... Logic circuit power supply VDD Generation circuit, 34... Control signal generation circuit, 35... I/F cable, 41... Head PC board, 42... Actuator, 43... Driver IC, 44... Polyimide film, 45... COF package, 46... Heat sink, 47... Protection circuit , 51...logic circuit, 52...level shift circuit, 53...driver circuit, 53a-53n...driver.

Claims (3)

an actuator having a capacitive load connected to a plurality of capacitive elements that ejects ink;
a driver IC that drives the capacitive element of the actuator;
a first capacitor provided in a first power supply line that supplies power at a first potential to the driver IC;
a second capacitor provided in a second power supply line that supplies power at a second potential lower than the first potential to the driver IC;
a first fuse with a first blowing current provided in the first power supply line between the first capacitor and the driver IC;
a second fuse having a second fusing current smaller than the first fusing current, the second fuse being provided in the second power supply line between the second capacitor and the driver IC;
Equipped with
When a latch-up occurs in the driver IC and a first path through which a through current related to the first power supply line flows and a second path through which a through current related to the second power supply line flows, The second fuse blows to cut off the second path, and the first fuse blows simultaneously or with a delay to cut off the first path, and the first power supply line and the An inkjet head unit electrically separated from a second power supply line. The inkjet head unit according to claim 1, wherein the driver IC has a structure formed by a CMOS process. a transport motor that transports the print medium;
an actuator that discharges ink onto the print medium transported by the transport motor; a head control unit that supplies drive power and control signals to the actuator;
Equipped with
a driver IC that drives a capacitive element of the actuator;
a first capacitor provided in a first power supply line that supplies power at a first potential to the driver IC;
a second capacitor provided on a second power supply line that supplies power to the driver IC with a second potential that is also smaller than the first potential;
a first fuse with a first blowing current provided in the first power supply line between the first capacitor and the driver IC;
a second fuse having a second fusing current smaller than the first fusing current, the second fuse being provided in the second power supply line between the second capacitor and the driver IC;
Equipped with
When a latch-up occurs in the driver IC and a first path through which a through current related to the first power supply line flows and a second path through which a through current related to the second power supply line flows, 2 fuses blow to cut off the second path, the first fuse blows simultaneously or after a set time delay to cut off the first path, and the first power is supplied to the driver IC. An inkjet printer in which the line and the second power supply line are electrically separated.