JP2024006955A - Semiconductor package substrate and substrate with support medium - Google Patents

Abstract

To provide a technology which enables improvement of robustness of a semiconductor package substrate.SOLUTION: A semiconductor package substrate has a first major surface and a second major surface for connecting an external component at both sides in a lamination direction. A build-up layer 12 in which conductor circuit layers 2 and insulator layers 3 are alternately laminated is formed between the first major surface and the second major surface. A first reinforcement layer 1 is installed on the first major surface. A second reinforcement layer 4 is installed on the second major surface. The first reinforcement layer 1 and the second reinforcement layer 4 have two areas, which are a mounting range 11 for joining to the external component and a non-mounting range 19 which is disposed at an outer periphery of the mounting range and is not joined to the external component, in a plan view and also have multiple pairs of stacked vias penetrating from the first reinforcement layer 1 to the second reinforcement layer 4. At least two pairs of stacked vias of the multiple pairs of stacked vias are disposed in the non-mounting range 19.SELECTED DRAWING: Figure 1B

Description

The present invention relates to a semiconductor package substrate such as an interposer substrate and a substrate with a support for mounting a semiconductor device. Examples of other components that are electrically connected (bonded) to the substrate include a motherboard, a semiconductor element, and the like.

The present invention is a technology suitable for the structure of a so-called coreless FC-BGA (Flip Chip-Ball Grid Array) substrate.

In recent years, SiP (System In Package), in which a plurality of different types of semiconductor devices (semiconductor chips) are mounted on an interposer to form one high-performance semiconductor package, has been put into practical use. According to this method, a "semiconductor package substrate" which is a highly functional semiconductor device can be obtained without increasing the process cost.

Further, as a semiconductor device mounted on the above-mentioned SiP, HBM (High Bandwidth Memory), which is a stacked DRAM, tends to be frequently used. In HBM, the pitch of connection terminals is generally narrow, about 55 micrometers, and it is necessary to form connection terminals of the same size on the interposer.

Further, the interposer as described above will be connected to the FC-BGA board. However, the CTE (Coefficient of Thermal Expansion) of the FC-BGA substrate is about 18 ppm/°C, which is higher than the CTE of a semiconductor chip: 3 ppm/°C. Therefore, the interposer is required to have a function of alleviating the CTE mismatch between the semiconductor chip and the FC-BGA substrate.

Furthermore, for convenience in assembly as a semiconductor package, it is desirable to be able to mount the semiconductor device on the FC-BGA substrate after mounting it on the interposer. For this reason, the interposer needs to be able to exist as a single unit independent of the FC-BGA board.

Here, Patent Document 1 describes a technique for suppressing warpage of an interposer. In Patent Document 1, as a method for manufacturing a semiconductor package, a first plate-shaped reinforcing member, a first conductive pattern wiring board laminate, and a second plate-shaped reinforcing member disposed on a second conductive pattern are used. a step of heating the laminate to thermoset the insulating layer; and selectively removing a portion of the first reinforcing member to expose the first conductor pattern. forming an opening for exposing the second conductor pattern by selectively removing a portion of the second reinforcing member; A technique is disclosed that includes a step of connecting a semiconductor element to a conductor pattern.

International Publication No. 2013/065287

However, since the interposer of Patent Document 1 has a structure in which a fiber base material is impregnated with a resin composition, the diameter of the via that can be formed is limited to 50 micrometers. Furthermore, the pitch between vias is also limited to 130 micrometers, making it difficult to mount an HBM, which is a stacked DRAM.

Further, further robustness is desired for the interposer.

Here, as a structure having more robustness than the structure described in Patent Document 1, the inventor has proposed one first main surface and the other second main surface opposite to the one first main surface. For each of these, we considered a structure with a reinforcing layer made of resin material.

However, it has been found that even with this structure, the coreless FC-BGA substrate is not sufficiently robust.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a technique for improving the robustness of a semiconductor package substrate.

According to the first aspect of the present invention, the first main surface and the second main surface are provided on both sides in the stacking direction, and the first main surface and the second main surface are surfaces for connecting to external components, respectively. A build-up layer in which a conductor circuit layer and an insulating layer are alternately laminated is formed between the main surface of the second main surface, a first reinforcing layer is installed on the first main surface, and a build-up layer is formed between the second main surface and the second main surface. A second reinforcing layer is installed on the surface, and the first reinforcing layer and the second reinforcing layer are arranged in a mounting range for joining with the external component and an outer periphery of the mounting range in plan view. and has two areas, the external parts and a non-mounted area that is not joined, and has a plurality of stacked vias penetrating from the first reinforcing layer to the second reinforcing layer, and has a stack of the plurality of sets. A semiconductor package substrate is provided in which at least two or more sets of stacked vias among the vias are arranged in the non-mounting range.

According to a second aspect of the present invention, a solder resist is provided on the main surface side of at least one of the first reinforcing layer and the second reinforcing layer. A side semiconductor package substrate is provided.

According to the third aspect of the present invention, at least one of the first reinforcing layer and the second reinforcing layer is composed of a plurality of layers. A side semiconductor package substrate is provided.

According to a fourth aspect of the present invention, the semiconductor package substrate according to the first aspect and a support for supporting the semiconductor package substrate are provided, and at least the first reinforcing layer or the support is provided on the support. A substrate with a support is provided, on which the second reinforcing layer is formed.

According to a fifth aspect of the present invention, a solder resist is provided on the main surface side of at least one of the first reinforcing layer and the second reinforcing layer. A substrate with side supports is provided.

According to the sixth aspect of the present invention, in the fourth aspect or the fifth aspect, at least one of the first reinforcing layer and the second reinforcing layer is composed of a plurality of layers. A substrate with side supports is provided.

According to the present invention, a technique for improving the robustness of a semiconductor package substrate is provided.

FIG. 1A is a schematic top view of a semiconductor package substrate according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view (A-A' cross-sectional view) showing a semiconductor package substrate according to an embodiment of the present invention. FIG. 1C is a schematic cross-sectional view (B-B' cross-sectional view) showing a semiconductor package substrate according to an embodiment of the present invention. FIG. 2A is a schematic top view of a semiconductor package substrate in which solder is placed on the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 2B is a schematic cross-sectional view (C-C' cross-sectional view) of a semiconductor package substrate in which solder is provided on the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 2C is a schematic cross-sectional view (DD' cross-sectional view) of a semiconductor package substrate in which solder is provided on the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 3A is a schematic top view of the semiconductor package substrate in which solder is installed in the vias in the non-mounting area where the semiconductor chip is not mounted in the semiconductor package substrate of FIGS. 2A, 2B, and 2C. FIG. 3B is a schematic cross-sectional view (EE' cross-sectional view) of the semiconductor package substrate in which solder is installed in the vias in the non-mounting area where the semiconductor chip is not mounted in the semiconductor package substrate of FIGS. 2A, 2B, and 2C. . FIG. 3C is a schematic cross-sectional view (FF' cross-sectional view) of the semiconductor package substrate in which solder is installed in the vias in the non-mounting area where the semiconductor chip is not mounted in the semiconductor package substrate of FIGS. 2A, 2B, and 2C. . FIG. 4A is a schematic top view of a semiconductor package substrate in which the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C has a laminated structure of multiple layers. FIG. 4B is a schematic cross-sectional view (GG' cross-sectional view) of a semiconductor package substrate in which the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C has a laminated structure of multiple layers. FIG. 4C is a schematic cross-sectional view (H-H' cross-sectional view) of a semiconductor package substrate in which the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C has a laminated structure of multiple layers. FIG. 5A is a schematic top view of a semiconductor package substrate in which a copper pillar is installed in the semiconductor chip mounting range of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 5B is a schematic cross-sectional view (II' cross-sectional view) of a semiconductor package substrate in which copper pillars are installed in the semiconductor chip mounting range of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 5C is a schematic cross-sectional view (JJ' cross-sectional view) of a semiconductor package substrate in which copper pillars are installed in the semiconductor chip mounting range of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 6A is a schematic top view of the semiconductor package substrate of FIGS. 5A, 5B, and 5C in which a copper pillar is installed in a non-mounting area where a semiconductor chip is not mounted. FIG. 6B is a schematic cross-sectional view (K-K′ cross-sectional view) of the semiconductor package substrate of FIGS. 5A, 5B, and 5C, in which a copper pillar is installed in a non-mounting area where a semiconductor chip is not mounted. FIG. 6C is a schematic cross-sectional view (L-L' cross-sectional view) of the semiconductor package substrate of FIGS. 5A, 5B, and 5C, in which a copper pillar is installed in a non-mounting area where a semiconductor chip is not mounted. FIG. 7A is a schematic top view of a semiconductor package substrate in which a solder resist is provided on the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 7B is a schematic cross-sectional view (MM′ cross-sectional view) of a semiconductor package substrate in which a solder resist is provided on the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 7C is a schematic cross-sectional view (N-N' cross-sectional view) of a semiconductor package substrate in which a solder resist is provided on the reinforcing layer of the semiconductor package substrate of FIGS. 1A, 1B, and 1C. FIG. 8A is a schematic top view of a semiconductor device in which a semiconductor chip and an FC-BGA substrate are electrically connected to the semiconductor package substrate of FIGS. 2A, 2B, and 2C. FIG. 8B is a schematic cross-sectional view (O-O' cross-sectional view) of a semiconductor device in which a semiconductor chip and an FC-BGA substrate are electrically connected to the semiconductor package substrate of FIGS. 2A, 2B, and 2C. FIG. 8C is a schematic cross-sectional view (PP' cross-sectional view) of a semiconductor device in which a semiconductor chip and an FC-BGA substrate are electrically connected to the semiconductor package substrate of FIGS. 2A, 2B, and 2C. FIG. 9A is a schematic diagram of a part (steps (I) to (V)) of the method for manufacturing a semiconductor package substrate. FIG. 9B is a schematic diagram of part of the method for manufacturing a semiconductor package substrate (steps from (VI) to (IX)). FIG. 9C is a schematic diagram of a part (steps (X) to (XII)) of the method for manufacturing a semiconductor package substrate. FIG. 9D is a schematic diagram of part of the method for manufacturing a semiconductor package substrate (steps (XIII) to (XV)). FIG. 10A is a schematic top view of a semiconductor package substrate of a comparative example. FIG. 10B is a schematic cross-sectional view (QQ' cross-sectional view) of a semiconductor package substrate of a comparative example. FIG. 10C is a schematic cross-sectional view (R-R' cross-sectional view) of a semiconductor package substrate of a comparative example.

Embodiments of the present invention will be described below with reference to the drawings. In order to avoid redundant explanations, the same reference numerals are used in the figures to refer to components that perform the same or similar functions.

Further, the dimensions of each part shown in the description are merely examples, and may be changed as appropriate depending on various conditions such as the purpose of use and the type of measurement sample.

(composition)
An embodiment of the present invention will be described using FIG. 1A, FIG. 1B, and FIG. 1C. The semiconductor package substrate 13 of this embodiment includes a first reinforcing layer 1 made of a resin material, a build-up layer 12 in which a conductive circuit layer 2 and an insulating resin layer (insulating layer) 3 are alternately laminated, and a resin material. It has a layered structure consisting of a second reinforcing layer 4. Further, in the semiconductor package substrate 13 of this embodiment, in order to electrically connect the conductor circuit layers 2, the insulating resin layer 3 is provided with vias 7 and 8, and the vias 7 and 8 are filled with a conductor. ing. Further, in order to electrically connect the semiconductor package substrate 13 and an external device (external component), the first reinforcing layer 1 is provided with vias 5 and 6, and the second reinforcing layer 4 is provided with a via 9. , 10 are provided, and each via 5, 6, 9, 10 is filled with a conductor.

The first reinforcing layer 1 is on the first main surface side that is connected to the motherboard, FC-BGA board 18, etc. The second reinforcing layer 4 is on the second main surface side that is connected to the semiconductor chip 15 and the like.

In plan view, the substrate (second reinforcing layer 4 and first reinforcing layer 1) has two areas: a mounting range 11 for mounting the semiconductor chip 15 and a non-mounting range 19 for mounting the semiconductor chip 15. There are two areas.

In the non-mounting range 19, there are two or more vias 10 that are not electrically connected to the outside. Then, the via 8 is arranged so as to be stacked with the via 10, and the via 6 formed in the first reinforcing layer 1 is further arranged so as to be stacked with the via 8. By stacking the vias 10, 8, and 6 coaxially, a stacked via penetrating from the first reinforcing layer 1 to the second reinforcing layer 4 can be formed. Note that the number of layers of the insulating resin layer 3 and the number of stacks of vias 8 are the same.

A plurality of such stacked vias are arranged in the non-mounting area 19. A stacked via having the same structure may also be arranged in the mounting area 11.

Such a stacked via penetrating from the first reinforcing layer 1 to the second reinforcing layer 4 serves as a stake penetrating the semiconductor package substrate 13. Furthermore, stacked vias extending from the first reinforcing layer 1 to the second reinforcing layer 4 arranged surrounding the semiconductor chip 15 in the non-mounting area 19 where the semiconductor chip 15 is not mounted improve the robustness of the semiconductor package substrate 13. It has the effect of increasing

The plurality of stacked vias arranged in the non-mounting range 19 are preferably arranged so as to surround the mounting range 11.

Here, the conductor circuit layer 2 electrically connected to the via 8 disposed in the non-mounting area 19 may be electrically connected to other vias 8 or vias 7 on the same plane as the via 8. good.

When electrically connecting the semiconductor package substrate 13 and the mounted semiconductor chip 15 (see FIGS. 8A and 8B), solder 16 (see FIGS. 2A and 2B) is generally used. In addition to the vias 9 within the mounting range 11 of the semiconductor chip 15, the solder 16 may also be mounted on the vias 10 within the non-mounting range 19 where the semiconductor chip 15 is not mounted (see FIGS. 3A, 3B, and 3C). ).

Furthermore, when electrically connecting the semiconductor package board 13 and the motherboard or FC-BGA board 18 (see FIGS. 8A, 8B, and 8C), it is common to use solder 17 (see FIGS. 2B and 8C). (see Figure 2C). Solder 17 may be mounted on the vias 5 and 6 within the non-mounting range 19 (see FIG. 3C).

1A, 1B, and 1C are semiconductor package substrates 13 according to aspects of the present invention. This semiconductor package substrate 13 has the following structure. That is, the second reinforcing layer 4 is provided on the side of the so-called build-up layer 12 on which the semiconductor chip is mounted, and the first reinforcing layer 1 is provided on the side of the build-up layer 12 on which the FC-BGA substrate or motherboard is mounted. The second reinforcing layer 4 has vias 9 and 10, and the vias 9 and 10 are filled with a conductor, and the first reinforcing layer 1 has vias 5 and 6, and the vias 5 and 6 are filled with a conductor. is filled with. The vias 8 in the insulating resin layer 3 of the build-up layer 12 are filled with a conductor and provide interlayer electrical connection between the conductive circuit layers 2. Via 10, via 8, and via 6 in the non-mounting area 19 where no semiconductor chip is mounted on the semiconductor package board 13 serve as stacked vias, which serve as stakes penetrating the semiconductor package board 13, thereby increasing the robustness of the semiconductor package board 13. will improve. Each of the reinforcing layers 1 and 4 is made of a resin layer.

In this embodiment, as shown in FIGS. 1A, 1B, and 1C, the stacked vias of the via 10, the via 8, and the via 6 in the non-mounting area 19 are arranged so as to surround the semiconductor chip 15 to be mounted. Therefore, the robustness of the semiconductor package substrate 13 is further improved.

Note that the stacked vias of the vias 10, 8, and 6 may be electrically connected to vias other than the stacked vias via the conductive circuit layer 2. For example, two sets of stacked vias consisting of via 10, via 8, and via 6 may be electrically connected to each other via conductor circuit layer 2. Further, for example, the stacked vias of the vias 10, 8, and 6 may be electrically connected to the vias 5, 7, and 9 in the mounting range 11 via the conductive circuit layer 2.

Further, each exposed surface of the conductor-filled vias 5, 6, 9, and 10 may be coated with gold, nickel, palladium, tin, lead, an organic material, or the like.

The semiconductor package substrate 20 of FIGS. 2A, 2B, and 2C has solder 16 in the via 9 of the second reinforcing layer 4 on the side where the semiconductor chip 15 of the semiconductor package substrate 13 of FIGS. 1A, 1B, and 1C is connected. The structure is shown in which solder 17 is placed in the vias 5 and 6 of the first reinforcing layer 1 on the FC-BGA connection side.

The semiconductor package substrate 23 in FIGS. 3A, 3B, and 3C shows a configuration in which the solder 16 is also placed in the via 10 that exists in the non-mounting area 19 of the second reinforcing layer 4 of the semiconductor package substrate 20.

In the semiconductor package substrate 24 of FIGS. 4A, 4B, and 4C, each of the reinforcing layers 1 and 4 of the second reinforcing layer 4 and the first reinforcing layer 1 of the semiconductor package substrate 13 is composed of a plurality of layers. This shows the configuration.

For example, the second reinforcing layer 4 can be composed of second reinforcing layers 4A and 4B. For example, the first reinforcing layer 1 can be composed of first reinforcing layers 1A and 1B.

The semiconductor package substrate 25 in FIGS. 5A, 5B, and 5C shows a configuration in which copper pillars 21 are arranged in the vias 9 in the mounting range 11 on the semiconductor package substrate 13 in which the semiconductor chip 15 is mounted. The exposed surface of the copper pillar 21 may be coated with gold, nickel, palladium, tin, lead, an organic substance, or the like.

The semiconductor package substrate 26 in FIGS. 6A, 6B, and 6C shows a configuration in which copper pillars 22 are also arranged in the vias 10 located in the non-mounting range 19 of the semiconductor package substrate 25. The exposed surface of the copper pillar 22 may be coated with gold, nickel, palladium, tin, lead, an organic substance, or the like.

The semiconductor package substrate 33 in FIGS. 7A, 7B, and 7C shows a configuration in which solder resists 31 and 32 are disposed on the exposed surfaces of the second reinforcing layer 4 and the first reinforcing layer 1 of the semiconductor package substrate 13. For example, the solder resist 31 disposed on the second reinforcing layer 4 may have an opening such that the via 9 is exposed, or may have an opening such that the via 10 is exposed. Further, for example, the solder resist 32 disposed on the first reinforcing layer 1 has an opening so that the vias 5 and 6 are exposed.

8A, 8B, and 8C show a semiconductor device 27 in which the semiconductor chip 15 and the FC-BGA substrate 18 are electrically connected to the first main surface and the second main surface of the semiconductor package substrate 13. It is a diagram. An underfill material (reinforcing material: not shown) or the like may be applied around the semiconductor chip 15, and an underfill material (reinforcing material: not shown) or the like may be applied between the semiconductor device 27 and the FC-BGA substrate 18. You may. Furthermore, the FC-BGA board 18 may be electrically connected to the motherboard.

Furthermore, a plurality of semiconductor devices 14 may be electrically connected to one FC-BGA substrate 18.

(Production method)
Next, an example of a method for manufacturing the semiconductor package substrate 13 of this embodiment will be described with reference to FIGS. 9A, 9B, 9C, and 9D.

Here, an example of a manufacturing method for the semiconductor package substrate 13 shown in FIGS. 1A, 1B, and 1C will be shown. A series of steps from (I) to (XV) are shown in FIGS. 9A, 9B, 9C, and 9D. Hereinafter, each process will be explained one by one.

(I) A plate-shaped support substrate 30 is prepared. This support substrate is also called a support body.

In the following, an example will be shown where the second reinforcing layer 4 on the second main surface side is formed on the support substrate 30, but instead, the first reinforcing layer 1 on the first main surface side is formed on the support substrate 30. 30 may be formed.

(II) The pillars constituting the vias 9 in the mounting range 11 on which the semiconductor chip 15 is mounted and the pillars constituting the vias 10 in the non-mounting range 19 are formed using photolithography technology (resist coating, exposure, development), electrolytic plating, and resist Formed by peeling. The resist used may be liquid or sheet-like. Exposure may be performed using a stepper or by direct drawing. Development may be done by immersion or showering. Electrolytic plating may be copper or copper alloy. The electrolytic plating apparatus may be of a batch type or a continuous conveyance type.

The diameters of the pillars that make up the vias 9 and the pillars that make up the vias 10 are, for example, 10 micrometers to 50 micrometers. The height of each pillar is, for example, from 20 micrometers to 100 micrometers.

For example, in the example below, each pillar has a diameter of 30 micrometers and a height of 30 micrometers. By setting the diameter of each pillar constituting the vias 9 and 10 to 30 micrometers, it is possible to adapt to HBM connection terminals with a pitch of 55 micrometers.

(III) A reinforcing material constituting the second reinforcing layer 4 is attached to the support substrate 30 so as to cover the pillars constituting the vias 9 and 10. The surface of the support substrate 30 (at least the surface on the reinforcing layer side) is flat.

The thickness of the reinforcing material (reinforcing layer 4) is preferably from 30 micrometers to 110 micrometers, for example. When the thickness is less than 30 micrometers, a sufficient reinforcing effect cannot be obtained. On the other hand, if the thickness is greater than 110 micrometers, the entire substrate becomes too thick and cannot meet the demand for miniaturization. In the following example, the thickness of the second reinforcing layer 4 was set to 40 micrometers.

The method of attaching the reinforcing material forming the second reinforcing layer 4 may be set as appropriate, but in this embodiment, thermocompression bonding is used. The second reinforcing layer 4 may be composed of a plurality of layers by pasting a plurality of reinforcing materials.

(IV) The second reinforcing layer 4 is ground to expose the pillars constituting the vias 9 and 10, so that the thickness of the second reinforcing layer 4 is kept substantially the same at each portion.

The polishing method may be appropriately selected from methods such as CMP (Chemical Mechanical Polisher), grinder grinding, buffing, and the like.

(V) The conductor circuit layer 2 is formed by photolithography technology (resist coating, exposure, development), electrolytic plating, and resist peeling so as to be electrically connected to the exposed surfaces of the pillars that constitute the vias 9 and 10. do.

The resist may be liquid or sheet-like. Exposure may be performed using a stepper or by direct drawing. Development may be done by immersion or showering. Electrolytic plating may be copper or copper alloy. The electrolytic plating apparatus may be of a batch type or a continuous conveyance type.

The thickness of the conductor circuit layer 2 is preferably from 1 micrometer to 10 micrometers, for example. If the thickness is less than 1 micrometer, it will be difficult to ensure conductivity. On the other hand, if the thickness is greater than 10 micrometers, the entire substrate will become too thick and cannot meet the demand for miniaturization. In the following example, the thickness of the conductor circuit layer 2 was 3 micrometers.

(VI) A photosensitive insulating resin is placed on the exposed surfaces of the second reinforcing layer 4 and the conductor circuit layer 2, and by exposing and developing, the vias 29 that become the insulating resin layer 3, vias 7 and 8 are formed. It is formed.

The thickness of the insulating resin layer 3 is preferably from 2 micrometers to 10 micrometers, for example. When the thickness becomes thinner than 2 micrometers, the insulation reliability decreases significantly. On the other hand, if the thickness is greater than 10 micrometers, the entire substrate becomes too thick and cannot meet the demand for miniaturization. In the following example, the thickness of the insulating resin layer 3 was 3 micrometers.

Furthermore, it is desirable that the diameters of the vias 7 and 8 be from 3 micrometers to 20 micrometers, for example. When the diameter is smaller than 3 micrometers, it becomes difficult to fill the inside of the via with conductive material, while when the diameter is larger than 20 micrometers, the via takes up too much space in the substrate, making miniaturization difficult. Unable to meet requests. In the example below, it was set to 15 micrometers.

(VII) Filling the vias 7 and 8 with conductors and forming the second conductor circuit layer 2 are performed by photolithography technology (resist coating, exposure, development), electrolytic plating, and resist peeling.

The resist may be in liquid or sheet form. Exposure may be performed using a stepper or by direct drawing. Development may be done by immersion or showering. Electrolytic plating may be copper or copper alloy. The electrolytic plating apparatus may be of a batch type or a continuous conveyance type.

The thickness of the conductor circuit layer 2 is, for example, 1 micrometer to 10 micrometers. In the following example, the thickness of the conductor circuit layer 2 is, for example, 3 micrometers. Forming the insulating resin layer 3, the vias 7, and the vias 8 using the same method as in (VIII) to (XI) and (VI) is repeated for the desired number of layers. The thickness of each insulating resin layer 3 and the diameter of the vias 7 and 8 are, for example, the same size as VI above.

Then, the buildup layer 12 is formed by the steps (V) to (XI) described above.

Here, the number of buildup layers is, for example, 1 to 10 layers. In this embodiment, there are four layers.

(XII) A reinforcing material that will become the first reinforcing layer 1 is attached so as to cover the third insulating resin layer 3 and the fourth conductive circuit layer 2.

The thickness of the reinforcing material (first reinforcing layer 1) is, for example, from 30 micrometers to 400 micrometers. In the example below, the thickness is, for example, 100 micrometers.

The method of attaching the reinforcing material can be, for example, thermocompression bonding.

(XIII) Vias 28, which will become the vias 5 in the mounting range 11 where the semiconductor chip 15 is mounted and the vias 6 in the non-mounting range 19, are formed in the first reinforcing layer 1 by laser irradiation.

The diameter of the via 28 to be formed is, for example, from 30 micrometers to 400 micrometers. In the examples below, the diameter is, for example, 100 micrometers.

For laser processing, a UV laser or a carbon dioxide laser may be used.

(XIV) Filling the vias 5 and 6 with conductors and forming the conductor circuit layer 34 by photolithography technology (resist coating, exposure, development), electrolytic plating, and resist peeling.

The resist may be in liquid or sheet form. Exposure may be performed using a stepper or by direct drawing. Development may be done by immersion or showering. Electrolytic plating may be copper or copper alloy. The electrolytic plating apparatus may be of a batch type or a continuous conveyance type.

The thickness of the conductive circuit layer 2 is, for example, 1 micrometer to 10 micrometers.
In the example below, the thickness is, for example, 3 micrometers.

(XV) Peel off the support substrate (support body) 30. As a result, the semiconductor package substrate 13 is formed.

Here, the first reinforcing layer 1 and the second reinforcing layer 4 can be formed from prepreg, epoxy mold resin, or the like. Moreover, as the support substrate 30, glass, a metal plate such as copper, a copper-clad laminate, etc. can be used.

As described above, the surface of the support substrate 30 (at least the surface on the reinforcing layer side) is flat. Since the surface of the support substrate 30 is not warped and maintains flatness, in the steps (I) to (XIV), the pillars constituting the vias 9 in the mounting range 11 on which the semiconductor chip 15 is mounted, and the non-mounted The pillars constituting the vias 10 in the range 19 and the conductor circuit layer 2 can be easily formed. After the support substrate 30 is peeled off in the step (XV), the semiconductor package substrate 13 can be mounted on the motherboard or a semiconductor element etc. can be mounted on the semiconductor package substrate 13 in the subsequent process. .

Further, the substrate with support (semiconductor package substrate 13 with support substrate 30) completed in step (XIV) can be transferred to another party as an intermediate product. In that case, the support substrate 30 functions as a support that supports and fixes the entire semiconductor package substrate 13. Since the semiconductor package substrate 13 is supported and fixed by the support substrate 30, the substrate with support can be stably carried and transported. Further, the substrate with a support as an intermediate product can be used by peeling off the support substrate 30 at any location, mounting the semiconductor package substrate 13 after peeling off the support substrate 30 on a motherboard, or mounting the semiconductor package substrate 13 on a motherboard. Semiconductor elements and the like can be mounted on 13.

(others)
The present disclosure can take the following configuration.

(1) Each side in the stacking direction has a first main surface and a second main surface which are surfaces for electrically connecting to external components, and the first main surface and the second main surface A build-up layer consisting of alternating conductor circuit layers and insulating layers is formed between the
A first reinforcing layer is installed on the first main surface, and a second reinforcing layer is installed on the second main surface,
The first reinforcing layer and the second reinforcing layer are arranged in a mounting range for joining with the external component and on the outer periphery of the mounting range in a plan view, and are non-mounting that is not joined to the external component. has two areas with a range,
having a plurality of stacked vias penetrating from the first reinforcing layer to the second reinforcing layer;
At least two or more sets of stacked vias among the plurality of sets of stacked vias are arranged in the non-mounting range;
Semiconductor package substrate.

(2) A support comprising the semiconductor package substrate and a support that supports the semiconductor package substrate, and at least the first reinforcing layer or the second reinforcing layer is formed on the support. Board with body.

(3) A solder resist is provided on the main surface side formed by at least one of the first reinforcing layer and the second reinforcing layer.

(4) At least one of the first reinforcing layer and the second reinforcing layer is composed of a plurality of layers.

Next, an example based on this embodiment will be described.

(Example 1)
A resist was applied to a copper-clad laminate serving as a support substrate (support body). The thickness of the resist was 40 micrometers.

Next, a via with a diameter of 30 micrometers was formed by exposing and developing the resist. For the vias, copper pillars for vias 9 and 10 with a height of 30 micrometers were formed on the copper-clad laminate by electrolytic plating and resist peeling.

Next, a 40 micrometer thick epoxy mold resin was thermocompression bonded to form a second reinforcing layer so as to cover the copper pillar.

Then, the epoxy mold resin was polished using CMP to bring out the top of the copper pillar.

A seed layer was formed by sputtering on the surface of the copper pillar polished by CMP. The seed layer had a two-layer structure of titanium and copper.

Next, a resist with a thickness of 5 micrometers was applied to the sputtered surface. The first conductive circuit layer was patterned by exposing and developing the resist.

Next, a first conductive circuit layer having a thickness of 3 micrometers was formed by electrolytic copper plating, resist peeling, and seed etching.

A first photosensitive insulating resin layer having a thickness of 5 micrometers was applied on the first conductive circuit layer. The first photosensitive insulating resin layer was exposed and developed to form vias with a diameter of 15 micrometers.

Next, a seed layer was formed by sputtering on the first photosensitive insulating resin layer, and a resist having a thickness of 5 micrometers was applied. The seed layer had a two-layer structure of titanium and copper.

Then, the second conductive circuit layer was patterned by exposing and developing the resist.

Next, via electrolytic copper plating, resist peeling, and seed etching were performed to fill vias and form a second conductor circuit layer with a thickness of 3 micrometers. The first conductive circuit layer and the second conductive circuit layer were electrically connected by the vias.

Next, a second photosensitive insulating resin layer with a thickness of 5 micrometers was coated, exposed, and developed on the second conductor circuit layer to form vias with a diameter of 15 micrometers.

Next, a seed layer was formed on the second photosensitive insulating resin layer by sputtering, and a resist with a thickness of 5 micrometers was coated, exposed, and developed to pattern a third conductive circuit layer. The seed layer had a two-layer structure of titanium and copper.

Next, by electrolytic copper plating, resist peeling, and seed etching, vias were filled and a third conductor circuit layer having a thickness of 3 micrometers was formed. The second conductive circuit layer and the third conductive circuit layer were electrically connected by the vias.
A third photosensitive insulating resin layer with a thickness of 5 micrometers was applied, exposed, and developed on the third conductor circuit layer to form vias with a diameter of 15 micrometers.

Next, a seed layer was formed on the third photosensitive insulating resin layer by sputtering, and a resist having a thickness of 20 micrometers was applied, exposed, and developed to pattern a fourth conductive circuit layer. The seed layer had a two-layer structure of titanium and copper.

Next, by electrolytic copper plating, resist peeling, and seed etching, vias were filled and a fourth conductor circuit layer with a thickness of 10 micrometers was formed. The third conductive circuit layer and the fourth conductive circuit layer were electrically connected by the vias.

Next, a prepreg having a thickness of 100 micrometers was thermocompression bonded to the fourth conductor circuit layer, and the copper foil of the prepreg was dissolved and removed.

Next, vias with a diameter of 30 micrometers were formed in the prepreg using a carbon dioxide laser. Then, a seed layer was formed on the prepreg by sputtering. The seed layer had a two-layer structure of titanium and copper.

Next, a dry film resist with a thickness of 30 micrometers is pasted on the seed layer, and vias are filled and pads with a thickness of 15 micrometers are formed by exposure, development, electrolytic plating, dry resist film peeling, and seed etching. did.

Then, the carrier was deponded and the exposed copper foil was dissolved and removed, thereby obtaining a semiconductor package substrate 13 as shown in FIGS. 1A, 1B, and 1C.

In Example 1, on the outer periphery of the semiconductor package substrate 13, a copper pillar in an epoxy mold resin, a first conductive circuit layer, vias in the first photosensitive insulating resin layer, and a second conductive circuit layer are provided. , the vias in the second photosensitive insulating resin layer, the third conductive circuit layer, the vias in the third photosensitive insulating resin layer, the fourth conductive circuit layer, the vias in the prepreg layer, and the thickness By placing a stacked structure of 15 micrometer pads, the robustness of the semiconductor package was improved.

(Comparative example)
Comparative examples were semiconductor package substrates 35 shown in FIGS. 10A, 10B, and 10C. The semiconductor package substrate 35 of the comparative example is a semiconductor package substrate that does not have a stack structure like the present invention on the outer periphery of the substrate. Otherwise, a semiconductor package substrate 35 of a comparative example was manufactured under the same conditions as in Example 1.

(evaluation)
When the coefficient of thermal expansion (CTE) of the semiconductor package substrate 35 of the comparative example and the semiconductor package substrate 13 of Example 1 was measured, the coefficient of thermal expansion (CTE) of the semiconductor package substrate 35 of the comparative example was 15 ppm/°C. On the other hand, the semiconductor package substrate 13 of Example 1 had a concentration of 10 ppm/°C. In this way, the superiority of the robustness of the structure of the semiconductor package substrate 13 based on the present invention was recognized.

1, 1A, 1B...first reinforcing layer, 4,4A,4B...second reinforcing layer, 2...conductor circuit layer, 3...insulating resin layer (insulating layer), 5, 6, 7, 8, 9, 10, 28, 29... Via, 11... Mounting range, 12... Buildup layer, 13... Semiconductor package substrate, 14... Semiconductor device, 15... Semiconductor chip, 16, 17... Solder, 18... FC-BGA board, 19... Non-mounting range, 21, 22... Copper pillar, 30... Support substrate (support body), 31, 32... Solder resist.

Claims (6)

Each side has a first main surface and a second main surface, which are surfaces for connecting to external components, on both sides in the stacking direction, and a conductor is provided between the first main surface and the second main surface. A build-up layer is formed in which circuit layers and insulation layers are laminated alternately.
A first reinforcing layer is installed on the first main surface, and a second reinforcing layer is installed on the second main surface,
The first reinforcing layer and the second reinforcing layer are arranged in a mounting range for joining with the external component and on the outer periphery of the mounting range in a plan view, and are non-mounting that is not joined to the external component. has two areas with a range,
having a plurality of stacked vias penetrating from the first reinforcing layer to the second reinforcing layer;
At least two or more sets of stacked vias among the plurality of sets of stacked vias are arranged in the non-mounting range;
Semiconductor package substrate. 2. The semiconductor package substrate according to claim 1, wherein a solder resist is provided on a main surface formed by at least one of the first reinforcing layer and the second reinforcing layer. 3. The semiconductor package substrate according to claim 1, wherein at least one of the first reinforcing layer and the second reinforcing layer is composed of a plurality of layers. The semiconductor package substrate according to claim 1;
a support for supporting the semiconductor package substrate, and at least the first reinforcing layer or the second reinforcing layer is formed on the support. 5. The substrate with a support according to claim 4, wherein a solder resist is provided on a main surface formed by at least one of the first reinforcing layer and the second reinforcing layer. The substrate with a support according to claim 4 or 5, wherein at least one of the first reinforcing layer and the second reinforcing layer is composed of a plurality of layers.