JP2023545223A - Multi-resolution imager for night vision - Google Patents

Abstract

An image sensor having a set of pixels that make up the image sensor for capturing images. Two or more pixels in the set of pixels each have an architecture that includes a plurality of photodiodes that are configurable to form an individual pixel. The control system can cooperate with multiple photodiodes to form individual pixels. Each of the plurality of photodiodes can have a transfer gate electrically coupled to the photodiode. The common region can hold or transfer charge at least during or after the integration time. A read gate electrically coupled to the common region and the sense node can supply charge from the common region to the sense node through the read gate.

Description

INCORPORATION BY REFERENCE This application incorporates the benefit under 35 U.S.C. 120 of patent application Ser. Claiming priority as a continuation application, the application is based on U.S. Application No. 16/175,662 entitled "Extended dynamic range imaging sensor and operating mode of the same" filed on October 30, 2018. 120 of the U.S. Patent Act and priority as a continuation-in-part application thereof, the application is filed on August 16, 2016, and is based on the patent application “Extended dynamic range imaging sensor and operating mode of the same No. 15/238,063, filed on August 18, 2015, entitled "Extended dynamic range (XDR) CMOS pixels and 119 of U.S. Provisional Patent Application No. 62/206,417 entitled "Operating Mode". All of these applications mentioned herein are herein incorporated by reference in their entirety to the same extent as if each individual document was specifically and individually indicated to be incorporated by reference. .

GOVERNMENT RIGHTS This invention was made with Government support under Other Transaction Agreement W909MY-18-9-0001 awarded by the U.S. Army Contracting Command. Ta. The Government has certain rights in this invention.

BACKGROUND OF THE INVENTION The field of the invention relates generally to imaging devices. More particularly, one embodiment of the present disclosure is directed to a complementary metal oxide semiconductor (“CMOS”) imaging sensor capable of a wide range of operation.

Imaging sensors typically include an array of pixels containing light-sensitive elements known as photodetectors, such as CMOS or charge-coupled device (“CCD”) sensors. Generally, a photodetector accumulates charge in response to incident light during what is known as an integration period.

Previous quad pixel imagers had a sense node that needed to be large enough to allow the four photodiodes to sequentially transfer signal charge directly to the sense node through four transfer gates. This configuration may result in a high capacitance sense node compared to non-quad pixel imagers, in part due to the four sequential transfers and their transfer gates coupled to the sense nodes. Additionally, the sense node must be large to receive charge directly from the photodiode. Therefore, readout noise may be higher than non-quad pixels.

A rolling shutter can take a still image or a single frame of footage, which is captured by taking a snapshot of the entire scene at one moment in time (e.g. global shutter), rather than capturing a pixel is captured by rapidly scanning across multiple rows of the image and then performing a read operation.

summary

Machines, methods, and systems for multi-resolution imagers capable of night vision are discussed. An image sensor has a set of pixels that make up the image sensor for capturing images. Two or more pixels in the set of pixels each have an architecture that includes a plurality of photodiodes that can be formed into individual pixels by a controller. The control system is configured to cooperate with a plurality of photodiodes in each pixel, including a first photodiode and a second photodiode of the plurality of photodiodes. Each photodiode can have a transfer gate electrically coupled to the photodiode. The common region can hold or transfer charge at least during or after the integration time. A read gate electrically coupled to the common region and the sense node can supply charge from the common region to the sense node through the read gate. Thus, the common region can be operated as a charge transfer channel to move charge from the transfer gate output to the sense node. Each pixel includes: 1) a common region electrically coupled to the sense node for retaining or transferring charge received from at least the first photodiode during or after at least the integration time; 2) a common region electrically coupled to the sense node; and 3) any combination of both.

These and other features of the designs provided herein can be better understood with reference to the drawings, description, and claims, all of which constitute disclosure of this patent application.

FIG. 3 illustrates one embodiment of a block diagram of an exemplary pixel that transfers charge to be transferred to a common area through an associated photodiode transfer gate during or after an integration time. a plurality of photodiodes for simultaneous collection and a readout gate electrically coupled to the common area for transferring binned charge from the common area through the readout gate to the sense node during a readout operation. .

FIG. 3 illustrates one embodiment of an exemplary pixel block diagram in which multiple photodiodes simultaneously collect charge during an integration time, which is transferred to multiple common areas through each transfer gate, and then , the charges in each common region are fed through a read gate coupled to the common region to bin them together at the sense node.

1 illustrates one embodiment of a block diagram of an exemplary image sensor having a set of pixels that make up an image sensor for capturing images. FIG.

FIG. 3 illustrates one embodiment of a block diagram of a control system and pixel arrangement for an image sensor having a set of pixels making up the image sensor for capturing images, each pixel being as shown in FIGS. 1-2. It has an architecture that includes multiple photodiodes forming individual pixels similar to the example pixel.

Detailed Discussion As discussed in more detail below, the control system for a pixel and its components determines the manner in which those components operate through sending control signals to change the imaging mode of operation of the components. can be changed. The architecture of the pixel and its components supports an exemplary imaging mode of operation, which is a low light mode that uses a rolling shutter process that incorporates some aspects of the global shutter process. The low light mode, which uses a rolling shutter process with pixels and their components, allows the imager to trade resolution for low light level sensitivity while providing extended dynamic range. Low light mode using a rolling shutter process with pixels and their components uses simultaneous charge binning from multiple photodiodes in rolling shutter mode during the integration time to improve dynamic range and low light Improve level sensitivity. A baseline imager pixel for night vision cameras with reduced readout noise at the lowest light levels and longer detection range uses a pixel and its configuration in which charge from multiple photodiodes is binned simultaneously during the integration time. A low light mode that uses a rolling shutter process with elements can be used. Again, other imaging modes of operation using this pixel architecture are possible and will be discussed later, but the pixel architecture, and how the control system uses a rolling shutter process in low light mode to control those components. We first discuss how to operate to simultaneously bin charges from multiple photodiodes during the integration time.

FIG. 1 shows one embodiment of a block diagram of an exemplary pixel in which charge is to be transferred to a common area through an associated photodiode transfer gate during or after an integration time. a readout gate electrically coupled to the common region for transferring binned charge from the common region through the readout gate to the sense node during a readout operation. have

Each pixel within an image sensor has an architecture that may include multiple photodiodes and other components forming an individual pixel 100.

Pixel 100 is the light "detector" for the image sensor. They can be individual photodiode readouts through a common output stage. Additionally, charge from multiple photodiodes can be read out through this common output stage. The controller allows one photodiode to be in one pixel without binning, but with binning up to, for example, four photodiodes can bin their charge and fit into one pixel. A control signal can be sent to the photodiode so that it can be formed. Thus, without binning, one photodiode and other components that make up pixel 100 can become one pixel in the display. This is what a simple camera would see. Also, the image sensor in an exemplary video camera may be described as a 24 megapixel image sensor. The pixel measure in an image sensor typically refers to the smallest displayable unit, so it refers to the unbinned case, in which each "pixel" is operated to be one photodiode. However, as discussed in the various modes of operation of a more advanced camera or video camera, the controller may manipulate such, for example, 24 megapixels in various ways to form each pixel that detects light. If the controller bins all four photodiodes, the four photodiodes and other components that make up pixel 100 can form one pixel in the display. So basically the four photodiodes become a single pixel in the display. There is a photodiode and a pixel to be displayed. A common output stage does not always define pixels. A pixel is how a photodiode looks in the output to form an image. An imager sensor with N pixels (where N is an individual photodiode) has, for example, the capability of 4:1 or 2:1 charge binning of the photodiodes. The binned group of pixels becomes the displayed pixel.

Again, in the mode of operation controlled by the controller, the plurality of photodiodes making up pixel 100 are read out through a common output stage. For example, a quad pixel has all four photodiodes convert charge to voltage and send it to one signal line through a common output stage. The photodiodes may be binned or unbinned, but all pass through a common output stage. The common output stage can be considered to consist of a sense node SN, a source follower buffer SF, a row selection transistor SEL, and a reset transistor RST integrated with the sense node. All these components are involved in signal readout.

An individual pixel 100 may have a plurality of photodiodes, eg, PD1-PD4, each having an associated transfer gate TG1-TG4 electrically coupled to the photodiode. A plurality of photodiodes PD1-PD4 may form individual pixels 100 that collect photons to generate charge during an integration time and then transfer that charge signal to its own transfer associated with that photodiode. can be induced through gates (TG1 to TG4, respectively). Charges from two or more of the photodiodes PD1-PD4 can essentially be binned together "noise-free" within the common region SR during the integration time phase.

Two or more pixels in the set of pixels each have an architecture that includes a plurality of photodiodes that can be formed into individual pixels 100 by a controller. The control system is configured to cooperate with the plurality of photodiodes in each pixel 100 to include at least a first photodiode PD1 and a second photodiode PD2 of the plurality of photodiodes. The multiple photodiodes are read out through a common output stage that includes a sense node SN. Pixel 100 further includes: 1) a common region SR electrically coupled to sense node SN for retaining or transferring charge received from at least one photodiode during or after at least an integration time; 2) at least 3) one or more readout gates TX electrically coupled to the sense node SN for retaining or transferring charge received from the at least one photodiode during or after the integration time; and 3) at least the integration time. any combination of both 1) and 2) for retaining or transferring charge received from the at least one photodiode during or after the photodiode.

This common region SR is electrically coupled to each transfer gate TG1 to TG4. This common region SR is also coupled to the sense node SN via the read gate TX. One or more common regions SR may be implemented, each of which may i) transfer charge temporarily, such as during one clock cycle (see e.g. FIG. 2), or ii) transfer charge over a number of clock cycles. It is configured to retain a charge for a long duration, such as to be able to store it (see, eg, FIG. 1). The common region SR typically bins/sums charges from multiple photodiodes PD1-PD4 simultaneously during an integration time when in low light mode using a rolling shutter process. The read gate TX is electrically coupled to the common region SR and the sense node SN to supply charge from the common region SR to the sense node SN through the read gate TX during a read operation.

The common region SR is used to bin charge from two or more of photodiodes PD1-PD4 during integration time and to transfer charge during readout operations. In the first case, if the charge passes through the common region SR, the final binning occurs at the sense node SN. When operated in this way, some binning occurs in the common region SR. In the second case, if the charges are stored in the common region SR, all binning occurs in the common region SR. Note that in other modes of operation, the common region SR is also used for single photodiode readout for high resolution. In this case, there is no binning, but the signal follows the same path as when binning multiple diodes. Single pixel readout is different from global shutter. Charge is retained in the common region SR for a fraction of the row time. For global shutter operation, charge is retained in the common region SR for at least the total row time, but more likely for multiple row times.

Sense node SN is used to read charge during read operations. Sense node SN can achieve high conversion gain and lower read noise by converting charge into a voltage signal when sense node SN has a lower capacitance. The size of the sense node SN is such that in this example it is connected to only one read gate TX for all four transfer gates TG1-TG4 in order to lower the noise threshold required during read operations. You can set the size to be large enough to accommodate your needs. Note that the reset of the sense node occurs when the reset gate RST is turned on after reading to complete the read operation.

During a read operation, the charge in the sense node SN is read out using source follower transistor SF and row select transistor SEL to generate a voltage signal on the column bus (which has a current source load). let The read transistor groups that cooperate for a read operation are denoted read gate (TX), source follower (SF), row select (SEL), and reset (RST).

The first step of a read operation may be to transfer the charge held in the common region SR to the sense node SN, in which two separate steps (e.g. 1) transfer gates TG1-TG4 are switched off and then , 2) the read gate TX is turned on).

Charge is thus binned in potential wells, preferably formed by buried channel wells. Charge is transferred from the plurality of photodiodes to a common region SR having its own potential well. In the common region SR, two or more photodiodes can be summed/binned within a well. A second transfer from the potential well to the sense node SN then produces a voltage output. This low-light mode allows for smaller sense nodes, resulting in higher voltage-to-electron charge conversion and therefore lower read noise.

In exemplary low-light operation, at least the top two photodiodes PD1-PD2 and their associated transfer gates TG1-TG2 are sent control signals by the control system to transfer their charge during the integration time. The transfer gates are "switched on" to supply the common region SR simultaneously. In the common region SR, charges from at least these two photodiodes PD1 to PD2 are binned during the integration time. Furthermore, for the lowest noise and most extended range imaging mode of operation, the four photodiodes PD1-PD4 and their A control signal is sent to all of the transfer gates TG1-TG4 associated with to "switch on" simultaneously in order to transfer their respective charges to the common region SR during the integration time. When all four photodiodes simultaneously bin their respective charges in the common area, then only one read operation to the sense node SN occurs to read out the binned charges. In contrast, the noise associated with four sequential read operations would normally be required to obtain the full charge from all four photodiodes PD1-PD4. Thus, noise is reduced by three read operations compared to some other quad-pixel designs. In addition, the common area is provided with a large number of connections from multiple photodiodes PD1-PD4 in order to keep the size dimension of the sense node SN small and also to keep the parasitic transfer gate capacitance that may be present to reduce readout noise small. It holds (possibly stores) the charge and then transfers the binning/summed charge to the sense node SN. The common region SR transferring charge during a read operation allows the sense node SN and its read gate TX to be smaller and have less capacitance. Rather than four transfer gates TG1-TG4, each adding parasitic capacitance to sense node SN, only one readout gate TX (two readout gates in some architectures) is coupled to the area that makes up sense node SN. . The lower capacitance allows for improved noise levels during readout operations, thereby allowing detection in low-light conditions (e.g. moonless nights with only starlight) and reducing usable signals. lower the noise threshold level at which it becomes undetectable.

Structurally, each transfer gate TG1-TG4 has its own channel formed under each of the transfer gates TG1-TG4 to supply charge to the common region. At least a portion of the well forming the common region SR is located below each transfer gate TX when two or more wells are mounted. The potential well is preferably formed by a buried channel well. Each photodiode's transfer gate TG1-TG4, such as a transistor or a metal oxide device, allows control signals to be sent to it from the control system to control the integration time of that particular photodiode and thus its associated photodiode. The diodes, eg PD1-PD4, control how long they collect photons before their associated transfer gates TG1-TG4 transfer the stored charge from the photodiodes to the common region SR.

Note that in one embodiment, the common region SR is constructed with wells constructed to store charge over many cycles. The common area can be a well that stores a charge potential, which can be formed by a virtual gate or a polygate. One of the challenges with the pixel architecture of FIG. 1 is that since the charge is stored in a common area, that area must be large enough to hold the maximum desired charge. This reduces the space available for photodiodes PD1-PD4 and reduces quantum efficiency. Without the idea that this architecture could yield lower noise, this approach may not seem logical. Also, if the common region SR becomes too large, the transfer of charge to the sense node SN may take longer than required/allowed by that mode of operation. Therefore, in one embodiment, the charge capacity of the common region SR is made large enough to allow the required charge transfer time to the sense node SN, and to actually transfer the expected amount of charge. can be set to only the minimum required to support storage.

The common region SR can have a charge channel. The common region SR may have a charge channel from the photodiode output from each of the photodiodes PD1-PD4, the charge channel passing under the transfer gate TG1-TG4 associated with that photodiode and common to the photodiode output. It passes through the well of region SR and reaches the read gate TX. Note that the problem of sense node SN becoming too large can be solved by adding these charge channels from the photodiode output, under the transfer TG gate, through the well, to the readout gate TX. It allows the sense node SN to be separated from the four photodiodes PD1-PD4, but still within the pixel. The addition of a channel extending from the output of the photodiode to the well of the sense node SN to the readout gate ensures that the well is large enough to simultaneously handle the direct transfer of charge from all four photodiodes PD1-PD4. It no longer needs to be. Again, this approach can reduce noise to or near the noise threshold level of imagers that do not use quad-pixel architecture.

The common region SR between the transfer gates TG1-TG4 and the sense node may be a charge binning region with a read gate for holding/storing the charge in the common region SR. The common region SR is a place where charges from the four photodiodes PD1 to PD4 are binned and then transferred to the sense node SN through one read gate TX1. This charge binning region can hold/storage charge for one frame time to enable global shutter operation, and this charge binning region holds charge for less than one row time for rolling shutter operation. You can also do that.

The image sensor containing the pixels has a control system that implements rolling shutter, global shutter, and can operate in various imaging modes of operation. The control system can send control signals to operate the image sensor in a mixed global shutter and rolling shutter mode of operation. In this rolling shutter mode with several global shutter aspects, the control system controls the charge accumulation on multiple photodiodes by sending control signals to collect charge from multiple photodiodes simultaneously, and The integration time is started by sending another signal for transfer to the common region SR through the associated transfer gate TG coupled to the photodiode. The common region SR sums/bins the charges supplied by two or more photodiodes PD1-PD4 during the integration time. During a read operation, the control system sends a control signal to transfer the binned charge in the common region SR to the sense node SN through the read gate TX. An image sensor with a rolling shutter reads out rows of photodiodes within the image sensor on a row-by-row basis instead of all rows being read out simultaneously.

An advantage of the pixel architecture of Figure 1 is that the 4X binned pixels involve a global shutter mode of simultaneous binning of all photodiodes, where all rows are read out simultaneously, or, preferably, an aspect of simultaneous binning of multiple photodiodes. The advantage is that it can operate in either row-by-row or rolling shutter mode, which results in less geometric distortion in the displayed image with respect to moving objects.

The quad pixel architecture may be a CMOS pixel with four photodiodes PD1-PD4 within the pixel 100 on the substrate.

FIG. 2 shows one embodiment of an exemplary pixel block diagram in which multiple photodiodes simultaneously collect charge during an integration time, which is transferred to multiple common areas through each transfer gate; The charges in each common region are then fed through a read gate coupled to that common region to bin together at the sense node. Note that as shown, the common area is actually part of each read gate TX1-TX2. Therefore, the one or more readout gates include at least the first readout gate TX1 and the second readout gate TX2, and are configured to function as a common area. The common region (SR in FIG. 1) is therefore the first common region (TX1 shown in FIG. 2) for transferring the charge from the first photodiode PD1 and the second photodiode PD2 during the integration time. ) and a second common region (TX2 shown in FIG. 2) for transferring charge from the third photodiode PD3 and the fourth photodiode PD4 during the integration time. The readout gates TX1-TX2 act here as conductors leading the charge to the sense nodes. They can only transfer charge, not store charge.

The pixel architecture of FIG. 2 has two readout gates, TX1 and TX2. Each read gate TX1 or TX2 is coupled to two transfer gates TG1-TG2 or TG3-TG4 and then to a sense node SN. Unlike the common region SR of FIG. 2, which can store charge until it is slowly and reliably transferred to the sense node SN, some of the transfer gates TG1-TG4 only temporarily hold charge here. The two read gates TX1 and TX2 serve as charge transfer gates to the sense node SN. The charges from the four photodiodes PD1-PD4 are actually binned within the sense node. Thus, with this architecture, charge binning of two, three or all four photodiodes can be performed simultaneously, but at the sense node SN rather than in the common area. Note that the common region can act as a channel from the associated TG gate outputs TG1-TG4 directly to the sense node SN.

Read gates TX1 and TX2 can be implemented by using poly gates. The small size of readout gates TX1 and TX2 also allows for larger photodiodes PD1-PD4 within a given quad area, resulting in higher quantum efficiency. The area of sense node SN is still much smaller than previous designs. Instead of four transfer gates TG1-TG4, each adding parasitic capacitance to sense node SN, only two small read gates TX are coupled to the area of sense node SN. Redundant capacitance is further reduced by the small size of sense node SN.

In FIG. 2, in one embodiment, the architecture does not require a read gate TX. Alternatively, the architecture may have a common region coupled to a sense node and one or more transfer gates (TGs). The common region may be configured to transfer and move charge to the sense node during the integration time. The common area need not hold charge, but simply transfer charge.

Referring to FIG. 1, an exemplary pixel with multiple photodiodes is divided into multiple common areas through each transfer gate for summation/binning of the charge provided by two or more photodiodes during the integration time. The transferred charges are collected simultaneously and then during a read operation, the binned charges of each common area are provided to the sense node through the read gate.

Pixel 100 has four transfer gates TG1-TG4, each at the edge of its associated photodiode PD1-PD4. A central channel between the upper two transfer gates TG1-TG2 acts as a common region SR1 for storing the charges of the two photodiodes PD1-PD2, and also bins the charges from the two photodiodes PD1-PD2. . Similarly, the central channel between the upper two transfer gates TG3-TG4 acts as a common region SR2 for storing the charges of the two photodiodes PD3-PD4, and also serves as a common region SR2 for storing the charges of the two photodiodes PD3-PD4. binning. All four transfer gates TG1-TG4 are electrically coupled to the read gate TX through their respective channels. Read gate TX is coupled to sense node SN. Sense node SN also has a gain capacitor GC electrically coupled to sense node SN.

In one embodiment, the first storage region SR1 is a well formed by a long, deep central channel between the top two transfer gates TG1-TG2. The second storage region SR2 is a well formed by a long, deep central channel between the bottom two transfer gates TG3-TG4.

The read gate TX1 transfers charges from the first common region SR1 and the second common region SR2 to the sense node SN through the read gate TX1 during a read operation.

FIG. 3 depicts one embodiment of a block diagram of an exemplary image sensor having a set of pixels that make up an image sensor for capturing images. The image sensor has an array 500 comprising columns and rows of pixels. In this example, the image sensor is configured to capture images and has five rows and columns of pixels, including exemplary pixel 100 (rows 1-5).

FIG. 4 shows one embodiment of a block diagram of a control system and pixel arrangement for an image sensor having a set of pixels that make up the image sensor for capturing images, each architecture shown in FIGS. 1-2. The pixel contains a photodiode similar to the exemplary pixel shown in FIG. The control system includes a controller with two or more decoders implemented in analog/ADC circuits, column and row control circuits for each transfer gate of a photodiode in a quad pixel array of pixels 500, a MIM gain capacitor, a readout gate, It may include components such as a reset switch and row select switches, column logic drivers, and timing circuits.

A control system can use more than one decoder. The two or more decoders cooperate with the timer to enable the pixels of the array of pixels 500 to operate in various imaging modes of operation, i) the frame rate, ii) the photodiodes. and iii) the binning of multiple photodiodes per pixel. Again, the control system may configure the plurality of photodiodes to cooperate with the plurality of photodiodes to form a detector for an individual pixel and/or to form a detector for an individual pixel. Configured to form a single photodiode.

The control system in night vision/low light mode may be configured such that the plurality of photodiodes simultaneously collect charge during the integration time and send a first control signal for the associated transfer gate to switch off. . The associated transfer gate, upon receiving the second control signal, then transfers the charge stored in at least two of the plurality of photodiodes to retain the charge for a subsequent readout operation. simultaneously to one or more common regions through their associated transfer gates coupled to their photodiodes. In many architectures, one or more common regions bin the charge provided by two or more photodiodes during the integration time. The read gate is also switched off to keep the charge in the common area until a read operation occurs. The control system then sends a third control signal during a read operation to switch on the read gate, thereby transferring the binned charge of the common area to the sense node through the read gate. The transfer gate may also receive a signal to prevent charge from leaking back into the photodiode. When operating in rolling shutter mode, the control system is configured to perform the above sequence row by row of photodiodes, performing all rows within one time frame of one image frame. The control system may send control signals to the remainder of the set of read transistors (discussed above) and the gain capacitor to terminate the read operation.

The control system is configured to analyze the scene being captured in the image. The control system operates differently on two or more pixels within a row based on imaging conditions of the scene content, such as different light intensities and required frame rates within the scene being captured by multiple image pixels. Select the imaging mode. The controller is
selecting different imaging modes of operation for at least two pixels based on imaging conditions captured within the pixel 100;
By assembling an image using the collected data signals that reflect the accumulated charge and other imaging conditions obtained from multiple pixels through readout.
Capable of operating imaging sensors.

All of the pixel architectures of FIGS. 1-2 may include an additional MIM capacitor GC that allows switchable capacitance to the sense node SN to modify the capacitance and resulting gain.

The control system may be configured to transfer the charge to the common area, store the charge there for longer than a row time, and then read it out by the readout gate TX. The control system may also be configured to transfer charge to the common area to bin the charge to the common area and store a fraction of a row of charge therein. The purpose is completely different.

The image sensor routes wiring/conductor paths for control signals to enable various modes of operation using an exemplary quad pixel/electrical circuit. The controller may control the timing of control signals to each pixel of each row of the imager to implement the envisioned imaging mode of operation, which includes:

1. ) Non-binned photodiode readout of photodiodes PD1-PD4 performed sequentially in sequence. In some cases, the integration times are different due to high resolution. Each transfer gate associated with its own photodiode is switched on in sequence to transfer charge from that photodiode through the associated transfer gate to the common region. For the highest resolution readout mode, the control system sends a signal to collect charge sequentially from a single photodiode during the integration time and uses an associated transfer gate to transfer that charge to a common area. Transfer to potential well. Charge in the common area is then transferred to the sense node using a transfer gate. Alternatively, charge is transferred to the sense node simply by using a transfer gate. Again, the control system repeats this process for the other three photodiodes in turn.

2. ) For the highest sensitivity mode, all four photodiodes sequentially bin their charges in one common area without noise to form a superpixel using a 4X signal. Then, during a read operation, the binned charge stored in the storage region is transferred to the sense node using the read gate.

3. ) Simultaneous or binned photodiode readout of multiple photodiodes, each in one or more storage areas. For example, 1) all of the photodiodes, e.g. PD1-PD4, are binned into one common area at the same time, or 2) each pair, e.g. PD1-PD2 and then e.g. PD3-PD4, are binned into one common area during the integration time. , their respective accumulated charges from their respective integration times are binned together in their common area. If all of the charge from the photodiodes during the integration time is not binned into one common storage area, the binning photodiode readout mode will contain each accumulated charge from each integration time. Multiple photodiodes can be binned together at the sense node. The controller can bin any combination of, eg, two, three, or four photodiodes, eg, PD1-PD4, to collect and read out charge/signal levels. The controller and timer work together to switch on the transfer gates of the binned photodiodes and switch off the readout gates of the common area, all at the same time via a pulse. Binning the charge from multiple photodiodes in a common area and then at the sense node increases the effective exposure, sensitivity, and thus better resolution.

4. ) High frame rate motion imaging mode for motion adaptive signal integration (MASI) and/or short integration time with high gain for motion blur reduction. High frame rate for motion adaptive signal integration (MASI) may be an imaging mode of operation that uses photodiode readout from a pixel 100 with multiple photodiodes. The high frame rate MASI algorithm achieves high dynamic range by combining high frame rate images of different exposures. High frame rate modes may still implement binning, non-binning, and extended dynamic range in a given pixel 100. Note that high frame rates may also exclude a certain amount of rows or even individual pixels from being read out to match the data throughput of the image sensor. Thus, the first decoder can select a subset of rows, such as 60 rows, and have them read out their respective charges from the total number of rows that make up the image sensor, such as 80 rows.

4) Extended dynamic range from low light conditions to clear sky conditions. The extended dynamic range imaging mode of operation may be an imaging mode of operation that uses multiple photodiode readouts from the pixel 100. Dynamic range can be a measure of how well a sensor can measure accurate signals at low light intensities and up to full well volume. Extended dynamic range can be achieved by adjusting the effective integration times of the four photodiodes.

In one embodiment, the quad-pixel design discussed herein can provide a readout noise reduction of two times (or more) when compared to some other conventional designs. In one embodiment, the system is constructed from a quad design, where four 8x8um pixels are read out individually or their charges are combined/binned to form a 16x16um superpixel. Either you do it. A 16x16um pixel collects 4 times more signal for the lowest light levels. This design allows for improved imaging with starlight illumination alone while reducing readout noise by a factor of two.

Although this invention has been described in terms of one or more embodiments, there are many equivalents, alterations, modifications, and modifications other than those expressly described and which fall within the scope of this invention. It should be understood that

Claims (20)

A device,
said image sensor having a set of pixels forming an image sensor for capturing an image;
The two or more pixels in the set of pixels each have an architecture including a plurality of photodiodes configurable to form an individual pixel, the plurality of photodiodes having a common output including a sense node. read out through the stages,
A control system is configured to cooperate with the plurality of photodiodes to configure the plurality of photodiodes to form the individual pixels, the plurality of photodiodes including a first photodiode and a first photodiode. 2 photodiodes,
The first photodiode and the second photodiode each have a transfer gate electrically coupled to the photodiode, and the apparatus further comprises:
1) a common region electrically coupled to the sense node for retaining or transferring charge received from at least the first photodiode during or after at least the integration time; 2) at least after the integration time; 3) one or more readout gates electrically coupled to said sense node for retaining or transferring charge received from at least said first photodiode during or after said integration time; any combination of both 1) and 2) for retaining or transferring charge received from at least the first photodiode during or thereafter. The one or more readout gates include at least a first readout gate and a second readout gate, and are configured to function as the common area, and the common area is configured to act as the common area during the integration time. a first common area for transferring the charge from the first photodiode and the second photodiode and transferring charge from the third photodiode and the fourth photodiode during the integration time; 2. The apparatus of claim 1, wherein the apparatus is divided into: a second common area for; The plurality of photodiodes are configured to collect charge during the integration time, and the common area is configured to retain the charge from the first photodiode and the second photodiode. 2. The method of claim 1, wherein the read gate is configured to supply the retained charge from the common region to the sense node through the read gate during a read operation. The device described. The first photodiode and the second photodiode are connected to each other during the integration time such that the common area bins the charge from the first and second photodiodes during or after at least the integration time. and the control system is configured to send a control signal to operate the image sensor in a rolling shutter mode of operation; Thereby, during the integration time, the plurality of photodiodes simultaneously collect charge, the charge is transferred and binned to the common area through the transfer gate of the associated photodiode, and the readout gate then During the readout operation, the image sensor in the rolling shutter mode of operation is configured to supply the charge from the common area to the sense node through the readout gate, and the image sensor in the rolling shutter mode of operation 4. The apparatus of claim 3, wherein the apparatus is configured to read out rows of photodiodes in the image sensor on a row-by-row basis instead of transferring their respective signals simultaneously. The plurality of photodiodes in the individual pixel include a third photodiode and a fourth photodiode, and the common area is configured such that during the integration time, the first photodiode, the second photodiode 4. The apparatus of claim 3, configured to store the charge from a photodiode, a third photodiode, and a fourth photodiode. the common region is configured to retain or transfer charge at least during or after the integration time;
The one or more readout gates electrically coupled to the common region and the sense node are configured to supply charge from the common region to the sense node through the readout gate. The device according to item 1. The control system sends a first control signal to the plurality of photodiodes to collect charge simultaneously during an integration time, and controls the first and second photodiodes at least during or after the integration time. For binning the charge provided by the diodes, the charge accumulated in at least the first photodiode and the second photodiode of the plurality of photodiodes is divided into the respective ones coupled to the photodiode. the control system is further configured to send a second control signal to the associated transfer gates to simultaneously move through the associated transfer gates to the common area; the control system when operating in rolling shutter mode, the control system being configured to send a third control signal for the read operation to transfer the binned charge through the read gate to the sense node; 2. The apparatus of claim 1, wherein said sequence of said three control signals is configured to perform said sequence of said three control signals row by row of photodiodes, so that all rows are performed within one time frame of one image frame. To reduce the noise threshold required during the read operation, the area of the sense node is set small enough to couple directly to the read gate instead of all the associated transfer gates. ,
2. The control system is configured to cooperate with the plurality of photodiodes to reconfigure the plurality of photodiodes such that each photodiode forms its own individual pixel. equipment. The common area has a charge channel from a photodiode output from the first photodiode and a photodiode output from the second photodiode, the charge channel being electrically coupled to the photodiode. 2. The apparatus of claim 1, wherein the reading gate is reached through the associated transfer gate and through the well of the common area. A method for an image sensor having a control system implementing a rolling shutter, the method comprising:
simultaneously transferring charge from the plurality of photodiodes forming a pixel to a common area through associated transfer gates to binning the charge provided by the two or more photodiodes during an integration time;
then supplying the binned charge from the common region to a sense node through a read gate during a read operation. collecting charge using the plurality of photodiodes during the integration time;
storing and binning the charge from the two or more photodiodes in the common area during the integration time;
then supplying the binned charge from the common region to the sense node through the read gate during the read operation;
11. The method of claim 10, further comprising: sending a control signal to operate the image sensor in a rolling shutter mode of operation, whereby during the integration time, the plurality of photodiodes simultaneously collect charge, the charges are associated with each other; A photodiode transfer gate is moved and binned to the common area, and the readout gate then supplies the charge from the common area to the sense node through the readout gate during the readout operation, and the rolling 12. The method of claim 11, wherein the image sensor in a shutter mode of operation further comprises reading out rows of photodiodes in the image sensor on a photodiode row by row basis instead of all rows being read out simultaneously. the plurality of photodiodes within the individual pixel includes at least four photodiodes;
11. The method of claim 10, comprising moving the charge from all of the plurality of photodiodes to the common area to store the charge during the integration time. further comprising retaining or transferring charge to the common region during or after at least the integration time;
The one or more readout gates are electrically coupled to the common region and the sense node, the readout gate providing charge from the common region to the sense node through the readout gate. The method according to item 10. The one or more readout gates include at least a first readout gate and a second readout gate, and are configured to function as the common area, and the common area is configured to act as the common area during the integration time. a first common area for transferring the charge from the first photodiode and the second photodiode and transferring charge from the third photodiode and the fourth photodiode during the integration time; 11. The method of claim 10, wherein: sending a first control signal to the plurality of photodiodes and their respective associated transfer gates to simultaneously collect charge during an integration time;
Then, during or after at least the integration time, at least the first photodiode and the second photodiode of the plurality of photodiodes are connected to each other for binning the charge provided by the first and second photodiodes of the plurality of photodiodes. sending a second control signal to the associated transfer gates to simultaneously transfer the charge stored on the diodes to the common region through their respective associated transfer gates coupled to the photodiodes; ,
sending a third control signal for the read operation to transfer the binned charge in the common region to the sense node through the read gate;
The control system when operating in rolling shutter mode performs the above sequence of the three control signals row by row of photodiodes such that all rows are performed within one time frame of one image frame. 11. The method of claim 10, comprising: To reduce the noise threshold required during the read operation, the area of the sense node is set small enough to couple directly to the read gate instead of all of the associated transfer gates. ,
11. The control system is configured to cooperate with the plurality of photodiodes to reconfigure the plurality of photodiodes such that each photodiode forms its own individual pixel. the method of. The common area has a charge channel from a photodiode output from a first photodiode and a photodiode output from a second photodiode of the plurality of photodiodes, and the charge channel 11. The method of claim 10, wherein the read gate is reached through a well of the common area through a well of the common area through a bottom of the transfer gate electrically coupled to the transfer gate. A method for an image sensor having a set of pixels constituting the image sensor for capturing an image, the method comprising:
creating two or more pixels in the set of pixels, each having an architecture that includes a plurality of photodiodes configurable to form an individual pixel;
a control system configured to cooperate with the plurality of photodiodes to form the individual pixels, wherein a first photodiode and a second photodiode of the plurality of photodiodes each include: comprising a transfer gate electrically coupled to the photodiode;
1) a common region electrically coupled to the sense node for retaining or transferring charge received from at least the first photodiode during or after at least the integration time; 2) at least after the integration time; 3) one or more readout gates electrically coupled to said sense node for retaining or transferring charge received from at least said first photodiode during or after said integration time; during or after, at least one of: any combination of both 1) and 2) for retaining or transferring charge received from at least the first photodiode. The plurality of photodiodes in the individual pixel include a third photodiode and a fourth photodiode, and the common area is configured such that during the integration time, the first photodiode, the second photodiode 20. The method of claim 19, wherein the method is configured to retain the charge from a second photodiode, the third photodiode, and the fourth photodiode.