JP2023180383A - Semiconductor relay, and semiconductor relay module including the same - Google Patents

Abstract

To provide a semiconductor relay capable of suppressing degradation of output signals due to the structure at the input side.SOLUTION: A semiconductor relay 1 includes at least: a housing 11; first and second input terminals 6 and 7; first and second output terminals 8 and 9; a light-emitting element 2; a light receiving element 51; and first and second MOSFETs 3 and 4. The light-emitting element 2 is placed on a first main surface 7d1, which is the upper surface of the first base 7d, and the light-emitting element 2 is placed on a second main surface 10a of a second base 10. A source electrode 5a of a light-receiving drive element 5 and the second substrate 10 are connected to the same potential. The second substrate 10 is placed between a first MOSFET 3 and a second MOSFET 4, viewed along the first axis. The light-emitting element 2 and the light-receiving driving element 5 are arranged apart from each other when viewed along the first axis.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor relay and a semiconductor relay module including the same.

2. Description of the Related Art Conventionally, semiconductor relays, also called MOSFET output photocouplers and optical MOSFETs, have been known as means for transmitting alternating current signals.

In conventional semiconductor relays, a stub, that is, a signal branch part, is formed inside due to the arrangement of input terminals, output terminals, and conductive members connected to these, and the stub resonates, causing insertion near the resonance frequency. There is a problem in that the loss (Insertion Loss) increases and the usable frequency band becomes narrower.

In order to solve this problem, for example, Patent Document 1 proposes a configuration in which conductor frames on which MOSFETs are placed are arranged on both sides of a conductor frame on which a light receiving element is placed. By arranging each frame in this manner, the length of the stub can be shortened, and it is possible to prevent the usable frequency band from becoming narrower due to the influence of the stub.

Japanese Patent Application Publication No. 2011-082916

However, in the conventional configuration disclosed in Patent Document 1, capacitive coupling and inductive coupling occur due to the structure between signal input and output, and when a high frequency signal is transmitted to the output side, these couplings occur. There was a risk that the signal would leak to the input side through the

Further, in the conventional configuration, the physical length (physical length) of the input terminal connected to the light emitting element for signal input is long, and the electrical length on the input side is correspondingly long. Note that the electrical length is the length based on the propagation speed of electromagnetic waves in the signal transmission medium.In a vacuum, the physical length and the electrical length are the same, but in a general transmission medium, the electrical length is longer than the physical length.

When the electrical length on the input side becomes longer, a corresponding resonance phenomenon occurs in the semiconductor relay, and there is a risk that the high frequency characteristics on the output side will deteriorate.

The present disclosure has been made in view of the above, and an object thereof is to provide a semiconductor relay that can suppress deterioration of an output signal due to the structure on the input side, and a semiconductor relay module equipped with the same.

To achieve the above object, a semiconductor relay according to the present disclosure includes a housing having an upper surface and a lower surface located below the upper surface along a first axis, and a first input terminal and a second input terminal. , a first output terminal and a second output terminal, a light emitting element electrically connected to the first input terminal and the second input terminal, a first surface that receives output light of the light emitting element, and a first surface that receives the output light of the light emitting element; a light-receiving drive element having a second surface located below the first surface along the first axis and a first electrode; a first intermediate electrode electrically connected to the first electrode; a first MOSFET having a first output electrode electrically connected to the first output terminal; a first gate electrode; a second intermediate electrode electrically connected to the first electrode; a second MOSFET having a second output electrode electrically connected to an output terminal and a second gate electrode; a first base body having an upper surface corresponding to the first main surface on which the light emitting element is disposed; and the light receiving drive. at least a connecting conductor having a second main surface on which an element is arranged and connected to the same potential as the first electrode, at least a part of the connecting conductor when viewed along the first axis. , disposed between the first MOSFET and the second MOSFET, and characterized in that the light emitting element and the light receiving driving element are spaced apart from each other when viewed along the first axis.

The semiconductor relay module according to the present disclosure includes at least the semiconductor relay and a circuit board on which first to fourth wirings are respectively formed, and the first wiring and the second wiring are respectively connected to the semiconductor relay. The relay is connected to the first input terminal and the second input terminal, and the third wiring and the fourth wiring are connected to the first output terminal and the second output terminal of the semiconductor relay, respectively. do.

According to the present disclosure, capacitive coupling and inductive coupling between input and output can be reduced, and the electrical length on the input side can be shortened. This allows the high frequency characteristics on the output side to be improved.

FIG. 2 is a perspective view of the semiconductor relay according to the first embodiment, viewed from above. FIG. 3 is a perspective view of the semiconductor relay seen from below. FIG. 3 is a diagram of the semiconductor relay viewed along the first axis. FIG. 3 is a diagram of the semiconductor relay viewed along the second axis. FIG. 3 is a diagram of the semiconductor relay viewed along the third axis. FIG. 3 is a diagram of a first input terminal and a second input terminal on which a light emitting element is mounted, viewed along a third axis. FIG. 3 is an equivalent circuit diagram of a semiconductor relay. FIG. 2 is a perspective view of a semiconductor relay. FIG. 3 is a perspective view of a semiconductor relay according to a comparative example. This is an example of frequency dependence of insertion loss in a transmission signal on the output side of a semiconductor relay. FIG. 7 is a perspective view of a semiconductor relay according to a modification. FIG. 3 is a perspective view of a semiconductor relay according to a second embodiment. FIG. 4 is a schematic diagram illustrating the difference in resonance phenomenon before and after inserting a resistor on the input side. FIG. 3 is a perspective view of a semiconductor relay module according to a third embodiment. FIG. 3 is a diagram of the semiconductor relay module viewed along the second axis. FIG. 3 is a diagram of the semiconductor relay module viewed along a third axis.

Embodiments of the present disclosure will be described below based on the drawings. Note that the following description of preferred embodiments is essentially just an example, and is not intended to limit the present disclosure, its applications, or its uses.

(Embodiment 1)
[1: Configuration of semiconductor relay]
FIG. 1 shows a perspective view of the semiconductor relay according to the first embodiment seen from above, and FIG. 2 shows a perspective view of the semiconductor relay seen from below. 3 to 5 show views of the semiconductor relay along the first to third axes, respectively. FIG. 6 shows a view of the first input terminal and the second input terminal on which the light emitting elements are mounted, viewed along the third axis.

For convenience of explanation, in FIG. 1 and the subsequent drawings, the respective outlines of the housing 11 and the light-shielding portion 11a and light-transmitting portion 11b constituting the housing 11 are shown by broken lines.

In addition, in the following description, the arrangement direction of the first input terminal 6 and the second input terminal 7 may be referred to as the X direction. Further, the virtual axis extending in the X direction may be referred to as a second axis. The X direction (second axis direction) is also the direction in which the first output terminal 8 and the second output terminal 9 are arranged. The direction in which the first input terminal 6 and the first output terminal 8 are arranged is sometimes called the Y direction. Further, the virtual axis extending in the Y direction may be referred to as a third axis. The Y direction (third axis direction) is also the direction in which the second input terminal 7 and the second output terminal 9 are arranged. Further, the Y direction is also the direction in which the light emitting elements 2 and the light receiving driving elements 5 are arranged.

The direction that intersects the X direction and the Y direction is sometimes called the Z direction. Further, the virtual axis extending in the Z direction may be referred to as a first axis. The X direction, Y direction, and Z direction are orthogonal to each other. In the specification of this application, "orthogonal" means that they are orthogonal, including processing tolerances and manufacturing tolerances of each component constituting the semiconductor relay 1, as well as assembly tolerances between components. This does not mean that the objects are orthogonal in a strict sense.

In addition, in the Z direction (first axis direction), the side where the light emitting element 2 is arranged may be referred to as the upper or upper side, and the side where the light receiving drive element 5 is arranged may be referred to as the lower or lower side. Note that the terms "upper" and "lower" in this specification are strictly relative, and do not mean, for example, "upper" or "lower" along the vertical direction.

As shown in FIG. 1, the semiconductor relay 1 includes a light emitting element 2, a light receiving drive element 5, a first MOSFET 3, and a second MOSFET 4. The semiconductor relay 1 also includes a first input terminal 6 , a second input terminal 7 , a first output terminal 8 , a second output terminal 9 , a second base 10 , and a housing 11 .

[1-1: Configuration of light-emitting element, light-receiving drive element, and second base]
The light emitting element 2 is a known LED (Light Emitting Diode) element. As shown in FIGS. 1 and 3 to 6, the cathode electrode (not shown) of the light emitting element 2 is connected and fixed to the first base 7d via a conductive adhesive (not shown) such as silver paste. . The first base 7d is connected to the second input terminal 7.

Further, the anode electrode 2a of the light emitting element 2 is electrically connected to the third base 6d via the wire 12. The third base 6d is connected to the first input terminal 6. The first input terminal 6 and the second input terminal 7, as well as the first base body 7d and the third base body 6d will be described in detail later.

The light receiving drive element 5 includes a light receiving element 51 and a control circuit 52 (both shown in FIG. 7). The light receiving element 51 receives the output light from the light emitting element 2, and is made up of, for example, known photodiodes arranged in an array. As shown in FIG. 3, a source electrode 5a and a drain electrode 5b are formed on the upper surface (first surface) of the light receiving drive element 5. The drain electrodes 5b are provided at two positions spaced apart from each other on the upper surface. Note that a light receiving portion, which is a portion that receives the output light from the light receiving element 51, is also formed on the upper surface of the light receiving driving element 5, but for convenience of explanation, illustration thereof is omitted.

Note that the source electrode 5a corresponds to the cathode electrode 51a (hereinafter sometimes referred to as the first electrode 5a or the first electrode 51a) of the light receiving element 51, and the drain electrode 5b corresponds to the anode electrode 51b of the light receiving element 51. .

The lower surface (second surface) of the light receiving drive element 5 is connected and fixed to the second base 10 via an adhesive (not shown). The second base 10 is a rectangular conductor when viewed along the first axis. Further, the surface on which the light receiving drive element 5 is placed on the second base 10, that is, the upper surface of the second base 10 is referred to as a second main surface 10a. The normal to the second main surface 10a is parallel to the first axis, that is, along the Z direction. However, this does not mean that the normal line is parallel to the first axis in a strict sense.

The second base body 10 protrudes from the side opposite to the first input terminal 6 and the second input terminal 7 among the two side faces facing each other in the Y direction, and has a portion exposed to the outside from the side of the housing 11 (hereinafter referred to as The first externally exposed portions 10b are provided at two positions spaced apart from each other along the second axis on the above-mentioned side surface of the second base 10. . However, the position and number of the first externally exposed portions 10b are not particularly limited to this.

As shown in FIGS. 1 to 3, the source electrode 5a of the light receiving drive element 5, in other words, the cathode electrode 51a (first electrode 51a) of the light receiving element 51 is electrically connected to the second base 10 via the wire 13. has been done. That is, the cathode electrode 51a of the light receiving element 51 is at the same potential as the second base 10. Also, one of the two drain electrodes 5b, 5b of the light receiving drive element 5 is electrically connected to the first gate electrode 3b of the first MOSFET 3, and the other is electrically connected to the second gate electrode 4b of the second MOSFET 4 via the wire 12. It is connected to the.

[1-3: Configuration of first MOSFET and second MOSFET]
As shown in FIGS. 1 and 3, the first MOSFET 3 is a well-known vertical MOSFET, and has a first gate electrode 3b and a first source electrode 3a (hereinafter sometimes referred to as a first intermediate electrode 3a) on its upper surface. However, a first drain electrode (not shown) is formed on each lower surface. The first drain electrode (hereinafter sometimes referred to as the first output electrode) of the first MOSFET 3 is connected to the first output terminal 8 via a conductive adhesive (not shown) such as silver paste. , are electrically connected to the fourth base 8a.

Further, the first source electrode 3a of the first MOSFET 3 is electrically connected to the second base 10 via a wire 12. That is, the first source electrode 3a of the first MOSFET 3 is electrically connected to the source electrode 5a of the light receiving drive element 5 via the second base 10 and the wire 12. In the example shown in FIGS. 1 and 3, the first source electrode 3a of the first MOSFET 3 and the second base 10 are connected by two wires 12, 12 to strengthen the connection.

The second MOSFET 4 is a well-known vertical MOSFET, and has a second gate electrode 4b and a second source electrode 4a (hereinafter sometimes referred to as a second intermediate electrode 4a) on the upper surface, and a second drain electrode (hereinafter referred to as a second intermediate electrode 4a) on the lower surface. (not shown) are formed respectively. The second drain electrode (hereinafter sometimes referred to as the second output electrode) of the second MOSFET 4 is connected to the second output terminal 9 via a conductive adhesive (not shown) such as silver paste. , are electrically connected to the fifth base 9a. The first output terminal 8 and the second output terminal 9 will be explained in detail later.

Further, the second source electrode 4a of the second MOSFET 4 is electrically connected to the second base 10 via the wire 12. That is, the second source electrode 4a of the second MOSFET 4 is electrically connected to the source electrode 5a of the light receiving drive element 5 via the second base 10 and the wire 12. In the example shown in FIGS. 1 and 3, the second source electrode 4a of the second MOSFET 4 and the second base 10 are connected by two wires 12, 12 to strengthen the connection.

[1-4: Configuration of first input terminal and second input terminal]
As shown in FIGS. 1 to 3 and 6, the first input terminal 6 is a conductive member having a first upright portion 6b and a first external connection portion 6a. Further, the first input terminal 6 is formed integrally with the third base 6d, and the third base 6d forms a part of the first input terminal 6. The third base body 6d, the first upright portion 6b, and the first external connection portion 6a are obtained, for example, by punching or bending a single copper plate. However, the method of manufacturing the first input terminal 6 is not particularly limited to this. Note that the surface of the copper plate is plated with another metal film, for example, a metal film containing nickel (not shown). Note that the material of the metal film is not particularly limited to this.

The third base 6d is located inside the housing 11 and is a rectangular conductor when viewed along the first axis. Further, the normal line of the connection surface of the third base 6d with the wire 12 is parallel to the first axis, that is, along the Z direction. However, this does not mean that the normal line is parallel to the first axis in a strict sense.

A wire 12 connected to the anode electrode 2a of the light emitting element 2 is connected to the third base 6d. Further, in the third base body 6d, a first upright portion 6b is connected to a side surface located on the opposite side from the second input terminal 7.

The first upright portion 6b is provided inside the housing 11 so as to extend along the second axis when viewed along the first axis, and is bent midway down along the first axis. Further, the first upright portion 6b is provided with a cutout 6e at a portion facing the second base body 10 when viewed along the first axis. Of both ends of the first upright portion 6b, one end located above along the first axis is connected to the third base 6d, and the other end located below is connected to the first external connection portion 6a.

The first external connection portion 6a is connected to the other end of the first standing portion 6b, and is a substantially rectangular conductor when viewed along the first axis. The lower surface of the first external connection portion 6a is formed to be exposed from the lower surface of the housing 11.

Furthermore, among the two side surfaces of the first external connection portion 6a facing in the X direction, the side surface facing the housing 11 has a portion (hereinafter referred to as A fourth externally exposed portion 6c) is provided.

The second input terminal 7 is a conductive member having a second standing portion 7b and a second external connection portion 7a. Further, the second input terminal 7 is formed integrally with the first base 7d, and the first base 7d forms a part of the second input terminal 7. The materials and manufacturing methods of the first base body 7d and the second input terminal 7 are the same as those of the third base body 6d and the first input terminal 6, so the description thereof will be omitted. Further, since the mutual connection relationship between the first base body 7d, the second upright portion 7b, and the second external connection portion 7a is the same as that of the third base body 6d, the first upright portion 6b, and the first external connection portion 6a, detailed explanation will be given. The explanation will be omitted.

The first base 7d is a rectangular plate-shaped conductor when viewed along the first axis, and the light emitting element 2 is placed on the upper surface of the first base 7d. The upper surface, that is, the surface on which the light emitting element 2 is placed on the first base 7d is referred to as a first main surface 7d1. The normal to the first principal surface 7d1 is parallel to the first axis, that is, along the Z direction. However, this does not mean that the normal line is parallel to the first axis in a strict sense.

When viewed along the first axis, the second upright portion 7b has a portion extending along the second axis and a portion bent downward from the end of the portion. A second external connection portion 7a is connected to the end of the bent portion.

The second external connection portion 7a is a rectangular plate-shaped conductor when viewed along the first axis, and the lower surface of the second external connection portion 7a is formed to be exposed from the lower surface of the housing 11. Of the two side surfaces of the second external connection portion 7a facing in the X direction, the side surface facing the housing 11 has a portion (hereinafter referred to as a fifth portion) that protrudes along the second axis and is exposed to the outside from the side surface of the housing 11. An externally exposed portion 7c) is provided.

In the following description, the first standing portion 6b and the second standing portion 7b may be collectively referred to as an standing portion. Further, the first external connection site 6a and the second external connection site 7a may be collectively referred to as an external connection site. The lower surfaces of each of the first external connection portion 6a and the second external connection portion 7a serve as connection terminals to a circuit board 40 (see FIGS. 14 to 16), which will be described later.

[1-5: Configuration of first output terminal and second output terminal]
As shown in FIGS. 1 to 3, the first output terminal 8 includes a fourth base 8a that is a rectangular plate-shaped conductor when viewed along the first axis. Further, the lower surface of the fourth base 8a is exposed from the lower surface of the housing 11, and serves as a connection terminal with a circuit board 40, which will be described later.

Further, of the two side faces facing each other in the X direction, the fourth base body 8a protrudes from the side opposite to the second MOSFET 4 and the light receiving drive element 5, and has a portion exposed to the outside from the side of the housing 11 (hereinafter referred to as the Note that the number of second externally exposed portions 8b is not particularly limited to those shown in FIGS. 1 to 3.

The second output terminal 9 includes a fifth base 9a that is a rectangular plate-shaped conductor when viewed along the first axis. Further, the lower surface of the fifth base 9a is exposed to the lower surface of the housing 11, and serves as a connection terminal for a circuit board 40, which will be described later.

Further, of the two side faces facing each other in the X direction, the fifth base body 9a protrudes from the side opposite to the first MOSFET 3 and the light receiving drive element 5, and has a portion exposed to the outside from the side of the housing 11 (hereinafter referred to as the Note that the number of third externally exposed portions 9b is not particularly limited to those shown in FIGS. 1 to 3.

[1-6: Housing configuration]
As shown in FIGS. 1 and 2, the housing 11 has an upper surface, a lower surface, and four side surfaces. The lower surface is located below the upper surface along the first axis. Each of the four side surfaces is continuous with the top surface and the bottom surface, and is parallel to the first axis. The normals of the two side surfaces facing each other in the X direction intersect the second axis, and the normals of the two side surfaces facing each other in the Y direction intersect the third axis.

The housing 11 has a light shielding part 11a and a light transmitting part 11b. The light shielding part 11a is made of, for example, an insulating epoxy resin containing a black pigment. However, the material is not particularly limited to this, and any insulating material that blocks light may be used. The light-transmitting part 11b is provided between the light-receiving driving element 5 and the light-emitting element 2, and is sealed by the light-blocking part 11a. Specifically, the light-transmitting part 11b includes the light-emitting element 2, covers the first main surface 7d1 of the first base 7d, extends along the third axis, and is further bent downward to cover the light-receiving drive element 5. It is provided to cover the top surface.

The light transmitting portion 11b is made of, for example, an insulating transparent silicone resin. However, the material is not particularly limited to this, and any insulating material that is transparent to at least the light emitted by the light emitting element 2 may be used. The light-transmitting portion 11b constitutes an optical coupling portion that optically couples the light-receiving element 51 (see FIG. 6) of the light-receiving drive element 5 and the light-emitting element 2.

The housing 11 seals the first input terminal 6, the second input terminal 7, the first to third bases 7d, 10, 6d, the first output terminal 8, and the second output terminal 9, and fixes their respective positions. do. Further, the light emitting element 2 placed on the first base 7d, the first MOSFET 3 placed on the fourth base 8a, the second MOSFET 4 placed on the fifth base 9a, and the second MOSFET 4 placed on the second base 10 are also included. The respective positions of the light receiving driving elements 5 are fixed by the housing 11.

Further, the first input terminal 6 and the second input terminal 7 and the first output terminal 8 and the second output terminal 9 are electrically insulated from each other by the housing 11. Further, the light emitting element 2, the light receiving drive element 5, the first MOSFET 3, and the second MOSFET 4 are electrically insulated from each other by the housing 11. That is, the semiconductor relay 1 shown in this specification is an input/output isolation type semiconductor relay 1 that turns on and off the output signal while electrically insulating the input signal and the output signal.

[1-7: Relationship between the first to fifth substrates]
As described above, the normal to the first main surface 7d1 of the first base 7d is along the first axis. Similarly, the normal to the second main surface 10a of the second base 10 is along the first axis. That is, the normal to the first main surface 7d1 of the first base 7d is parallel to the normal to the second main surface 10a of the second base 10. Note that these two normal lines do not need to be parallel in a strict sense. The two normals may intersect within a predetermined angular range. Further, the first base body 7d is disposed at a distance from the second base body 10 in the Y direction when viewed along the first axis. Further, the first base body 7d is located above the second base body 10 along an axis (second axis or third axis) orthogonal to the first axis. That is, the first main surface 7d1 of the first base 7d is located above the second main surface 10a of the second base 10 when viewed along the axis perpendicular to the first axis.

Further, as shown in FIG. 3, the first base body 7d is spaced apart from the second base body 10 with an interval L0 along the third axis. Further, the distance L0 between the first base 7d and the second base 10 along the third axis is smaller than the distance L1 between the first input terminal 6 and the second base 10 along the third axis. A first input terminal 6 and a second base 10 are arranged. Further, the second input terminal 7 and the second base body 10 are arranged such that the distance L0 is smaller than the distance L2 between the second input terminal 7 and the second base body 10 along the third axis. .

Note that in the following description, the distance L0 may be referred to as the shortest distance L0 between the first base body 7d and the second base body 10. Similarly, the interval L1 may be referred to as the shortest distance L1 between the first input terminal 6 and the second base 10. The distance L2 may be referred to as the shortest distance L2 between the second input terminal 7 and the second base 10.

Further, as shown in FIGS. 4 and 6, the first base body 7d is arranged above the third base body 6d along the first axis. In other words, the upper end of the second input terminal 7 is arranged above the upper end of the first input terminal 6.

The second base 10 is electrically connected to the source electrode 5a of the light receiving drive element 5 via a wire 13. In other words, the second base 10 is connected to the source electrode 5a of the light receiving drive element 5 so as to have the same potential. In the following description, the second base 10 and the wire 13 connecting the source electrode 5a of the light-receiving drive element 5 (the cathode electrode 51a of the light-receiving element 51) and the second base 10 will be collectively referred to as the connection conductor 14. There is.

Further, the second base 10 is electrically connected to the first source electrode 3a (first intermediate electrode 3a) of the first MOSFET 3 via the wire 12. Further, the second base 10 is electrically connected to the second source electrode 4a (second intermediate electrode 4a) of the second MOSFET 4 via the wire 12. In other words, the source electrode 5a of the light receiving drive element 5 is connected to the source electrodes 3a and 4a of the first MOSFET 3 and the second MOSFET 4 so as to have the same potential.

Furthermore, when viewed along the first axis, the second base 10 is disposed between the fourth base 8a and the fifth base 9a, with a space between the fourth base 8a and the fifth base 9a. . In other words, the second base 10 is arranged between the first MOSFET 3 and the second MOSFET 4 when viewed along the first axis. More specifically, when viewed along the first axis, the second base 10 is arranged between the first source electrode 3a of the first MOSFET 3 and the second source electrode 4a of the second MOSFET 4. Note that in the example shown in FIGS. 1A and 1B, the second base body 10 is located above the fourth base body 8a and the fifth base body 9a, with the lower surface of the housing 11 as a reference and along the first axis. That is, the lower surface of the second base 10 is covered by the light shielding part 11a of the housing 11. Further, the second base body 10 is at approximately the same height as the third base body 6d, with the lower surface of the housing 11 as a reference and along the first axis. However, both may be arranged at different heights with respect to the lower surface of the housing 11.

[2: Operation of semiconductor relay]
FIG. 7 shows an equivalent circuit diagram of a semiconductor relay.

When a transmission signal is input between the first input terminal 6 and the second input terminal 7, the light emitting element 2 outputs light of a predetermined wavelength. Light generated by the light emitting element 2 propagates inside the transparent portion 11b and is received by the light receiving element 51.

In the light receiving element 51, a current is generated by photoelectric conversion, and the control circuit 52 operates based on this current. Via the wire 12, a drive signal, which is a voltage signal corresponding to the amount of light from the light emitting element 2, is applied to the first gate electrode 3b of the first MOSFET 3 and the second gate electrode 4b of the second MOSFET 4, respectively.

When the voltage of the drive signal exceeds the respective threshold voltages of the first MOSFET 3 and the second MOSFET 4, the voltages between the source (S) and drain (D) of the first MOSFET 3 and between the source (S) and drain (D) of the second MOSFET 4 are respectively Turns on. Furthermore, conduction is established between the first output terminal 8 and the second output terminal 9 via the first MOSFET 3 and the second MOSFET 4. This allows high frequency signals to be transmitted bidirectionally between the first output terminal 8 and the second output terminal 9.

When the input of the transmission signal stops between the first input terminal 6 and the second input terminal 7, the light emission from the light emitting element 2 also stops. In response, no current is generated in the light receiving element 51, and the control circuit 52 is stopped.

As a result, the voltages of the drive signals applied to the first gate electrode 3b of the first MOSFET 3 and the second gate electrode 4b of the second MOSFET 4 are reduced. When the voltage of the drive signal falls below the threshold voltage described above, the source (S) and drain (D) of the first MOSFET 3 and the source (S) and drain (D) of the second MOSFET 4 are respectively turned off. Further, the first output terminal 8 and the second output terminal 9 are brought into a non-conducting state. As a result, signal transmission is interrupted between the first output terminal 8 and the second output terminal 9.

[3: Effects, etc.]
As described above, the semiconductor relay 1 according to the present embodiment includes at least the housing 11, the first input terminal 6, the second input terminal 7, the first output terminal 8, and the second output terminal 9. Further, the semiconductor relay 1 includes a light emitting element 2, a light receiving drive element 5, a first MOSFET 3, and a second MOSFET 4.

The housing 11 has an upper surface and a lower surface located below the upper surface along the first axis.

The light emitting element 2 is electrically connected to a first input terminal 6 and a second input terminal 7.

The light-receiving driving element 5 includes a light-receiving part, which is a part that receives the output light of the light-emitting element 2, formed on the upper surface (first surface) of the light-receiving driving element 5, and a source electrode 5a (a second part) provided near the light-receiving part. 1 electrode 5a). Further, the light receiving drive element 5 has a drain electrode 5b.

The first MOSFET 3 has a first source electrode 3a (first intermediate electrode 3a) electrically connected to the source electrode 5a of the light receiving drive element 5, and a first drain electrode (first intermediate electrode 3a) electrically connected to the first output terminal 8. (first output electrode) and a first gate electrode 3b.

The second MOSFET 4 has a second source electrode 4a (second intermediate electrode 4a) electrically connected to the source electrode 5a of the light receiving drive element 5, and a second drain electrode (second intermediate electrode 4a) electrically connected to the second output terminal 9. a second output electrode) and a second gate electrode 4b.

Further, the semiconductor relay 1 includes a first base 7d and a connecting conductor 14. The first base 7d has a first main surface 7d1 on which the light emitting element 2 is arranged. Further, the first base 7d is connected to the second input terminal 7. The connecting conductor 14 includes the second base 10 . The second base 10 has a second main surface 10a on which the light receiving element 51 is arranged, and is electrically connected to the source electrode 5a so as to have the same potential as the source electrode 5a of the light receiving drive element 5. There is.

A part of the connection conductor 14, ie, the second base body 10, is arranged between the first MOSFET 3 and the second MOSFET 4 when viewed along the first axis. More specifically, when viewed along the first axis, the second base 10 is arranged between the first source electrode 3a of the first MOSFET 3 and the second source electrode 4a of the second MOSFET 4. From another perspective, when viewed along the first axis, the second base 10 is disposed between the fourth base 8a on which the first MOSFET 3 is placed and the fifth base 9a on which the second MOSFET 4 is placed. There is. Note that even if the wire 13 connecting the source electrode 5a of the light receiving drive element 5 and the second base 10 is disposed between the fourth base 8a and the fifth base 9a when viewed along the first axis, Needless to say, it's a good thing.

Further, the first main surface 7d1 of the first base 7d corresponds to the upper surface of the first base 7d. Further, the light emitting element 2 and the light receiving driving element 5 are arranged apart from each other when viewed along the first axis.

By configuring the semiconductor relay 1 in this way, capacitive coupling and inductive coupling between input and output can be reduced, and the electrical length on the input side can be shortened. This makes it possible to suppress deterioration of high frequency characteristics on the output side. These will be further explained.

FIG. 8 shows a perspective view of a semiconductor relay according to the present embodiment, and FIG. 9 shows a perspective view of a semiconductor relay according to a comparative example. Note that FIGS. 8 and 9 illustrate a conductive path to the light emitting element 2, parasitic capacitance, and parasitic mutual inductance. The parasitic capacitances C1 and C2 and the parasitic mutual inductances M1 and M2 shown in FIGS. 8 and 9 are shown as lumped constants for convenience. Further, the equivalent circuit diagram of the semiconductor relay according to the present embodiment may be illustrated as a distributed constant existing between the first input terminal 6 and the first output terminal 8, between the first input terminal 6 and the second base 10, etc. can.

A semiconductor relay 20 shown in FIG. 9 is a comparative example showing a configuration similar to that disclosed in Patent Document 1, and differs from the semiconductor relay 1 of the present embodiment shown in FIG. 1 in the following points.

First, on the input side, the first base 7d is formed to extend from the upper end of the first input terminal 6 along the third axis. Further, the third base 6d is formed to extend from the upper end of the second input terminal 7 along the third axis. Furthermore, when viewed along the first axis, the first base body 7d and the third base body 6d are provided to extend above the light receiving drive element 5. Further, the light emitting element 2 is connected and fixed to the lower surface of the third base 6d. Note that the anode electrode (not shown) of the light emitting element 2 and the first base 7d are connected by a wire 12.

With these configurations, in the semiconductor relay 20 shown in FIG. 9, the light receiving element 51 is arranged directly below the light emitting element 2 along the first axis. The output light from the light emitting element 2 travels downward and enters the light receiving element 51 as it is.

According to this configuration, as described above, the length of the stub can be shortened, and it is possible to prevent the usable frequency band from becoming narrower due to the influence of the stub. On the other hand, since the first base body 7d and the third base body 6d are provided to extend above the light-receiving driving element 5, a conductive path on the input side, that is, from the first input terminal 6 to the light-emitting element 2 and the wire 12, is provided. The transmission path of the input signal to the second input terminal 7 becomes long. In other words, the electrical length on the input side becomes long. Moreover, in accordance with this, the parasitic mutual inductance M1 due to inductive coupling between the first input terminal 6, the second base 10, and the light receiving drive element 5 increases. Although not shown in FIG. 9, for the same reason, the parasitic mutual inductance due to inductive coupling between the second input terminal 7, the second base 10, and the light receiving drive element 5 also increases.

Furthermore, when viewed along the first axis, the area where the first base body 7d on which the light emitting element 2 is placed and the second base body 10 on which the light receiving drive element 5 is placed face each other and overlap becomes large. Correspondingly, the parasitic capacitance C1 due to capacitive coupling between the first base body 7d, the second base body 10, and the light receiving drive element 5 increases.

When the parasitic mutual inductance M1 and the parasitic capacitance C1 become large between input and output in this way, when transmitting a high frequency signal between the first output terminal 8 and the second output terminal 9, the parasitic mutual inductance M1 and the parasitic capacitance C1 increase. There is a risk that the high frequency signal on the output side may leak to the input side through.

Furthermore, on the input side, when the electrical length becomes long, the resonance frequency decreases and a resonance phenomenon may occur. In this case, the signal transmission characteristics on the output side, in other words, the high frequency characteristics on the output side may deteriorate.

On the other hand, according to the present embodiment, as shown in FIGS. 1 to 3 and 8, the first base body 7d is provided continuously to the second upright portion 7b provided to extend along the second axis. There is. Further, the normal to the first main surface 7d1 of the first base 7d is along the first axis. Further, the normal line to the second main surface 10a of the second base 10 is also along the first axis. Furthermore, when viewed along the first axis, the first base body 7d and the second base body 10 are arranged apart from each other with the shortest distance L0.

That is, when viewed along the first axis, there is no overlap between the first base body 7d and the second base body 10. As a result, the parasitic capacitance C2 due to capacitive coupling between the first base body 7d, the second base body 10, and the light-receiving drive element 5 can be significantly reduced compared to the above-mentioned parasitic capacitance C1.

Furthermore, since the first base body 7d and the third base body 6d can be made smaller in size, the electrical length on the input side can be made shorter than that of the semiconductor relay 20 shown in FIG. As a result, the parasitic mutual inductance M2 due to inductive coupling between the first input terminal 6, the second substrate 10, and the light-receiving drive element 5 can be made lower than the above-mentioned parasitic mutual inductance M1. For the same reason, the parasitic mutual inductance due to inductive coupling between the second input terminal 7, the second base 10, and the light receiving drive element 5 can also be reduced compared to the semiconductor relay 20 shown in FIG. This can suppress leakage of high frequency signals on the output side to the input side and suppress deterioration of high frequency characteristics on the output side.

Furthermore, on the input side, when the electrical length becomes long, the resonance frequency decreases and a resonance phenomenon may occur. In this case, the signal transmission characteristics on the output side, in other words, the high frequency characteristics on the output side may deteriorate.

On the other hand, according to this embodiment, the electrical length on the input side can also be reduced compared to the semiconductor relay 20 shown in FIG. This makes it possible to increase the resonance frequency on the input side.

FIG. 10 shows an example of frequency dependence of insertion loss in a transmission signal on the output side of a semiconductor relay.

As shown in FIG. 10, when the semiconductor relay 1 of this embodiment is operated, the frequency at which the insertion loss starts to increase is shifted to the higher frequency side compared to the semiconductor relay 20 of the comparative example shown in FIG. In other words, it can be seen that deterioration of the high frequency characteristics on the output side of the semiconductor relay 1 is suppressed.

Furthermore, according to the present embodiment, at least a portion of the connection conductor 14 is arranged between the first MOSFET 3 and the second MOSFET 4 when viewed along the first axis. By doing so, it is possible to suppress the formation of stubs in the path from the first output terminal 8 to the second output terminal 9 via the first MOSFET 3, the second base 10, and the second MOSFET 4. This can prevent the frequency band of the output signal transmitted by the semiconductor relay 1 from becoming narrower.

The light emitting element 2 and the light receiving element 51 are arranged apart from each other when viewed along the first axis, and by doing so, the output light from the light emitting element 2 can be reliably received through the light transmitting part 11b. It can be made incident on the element 51.

Note that the normal to the first main surface 7d1 of the first base 7d is preferably parallel to the normal to the second main surface 10a of the second base 10. By doing so, the capacitive coupling between the first base body 7d, the second base body 10, and the light receiving drive element 5 can be made smaller compared to the comparative example.

Further, the first main surface 7d1 of the first base 7d on which the light emitting element 2 is placed corresponds to the upper surface of the first base 7d. The light generated by the light emitting element 2 is emitted isotropically, but most of the light is emitted from the upper surface side where the anode electrode 2a is partially formed. Therefore, by placing the light emitting element 2 on the first main surface 7d1, which is the upper surface of the first base 7d, the light generated by the light emitting element 2 can be made to efficiently enter the light receiving element 51.

Further, the first main surface 7d1 of the first base 7d is located above the second main surface 10a of the second base 10 when viewed along an axis (second axis or third axis) perpendicular to the first axis. It is located. More specifically, the light emitting element 2 is arranged above the light receiving surface of the light receiving drive element 5 on which the light receiving element is formed.

By doing so, compared to the case where the first main surface 7d1 of the first base 7d and the second main surface 10a of the second base 10 are located at the same height with respect to the lower surface of the housing 11, The optical coupling efficiency when the light generated by the light emitting element 2 passes through the light transmitting part 11b and enters the light receiving element 51 of the light receiving driving element 5 can be increased.

Further, the first base body 7d is connected to one end of the second input terminal 7, specifically, to one end of the second upright portion 7b. Furthermore, the shortest distance L0 between the first base 7d and the second base 10 is smaller than the shortest distance L1 between the first input terminal 6 and the second base 10. Further, the shortest distance L0 is smaller than the shortest distance L2 between the second input terminal 7 and the second base 10.

By defining the relationship between the shortest distances L0, L1, and L2 in this way, the main conductive paths between the first input terminal 6 and the second input terminal 7, that is, the first external connection portion 6a and the first standing portion 6b, Furthermore, the second external connection portion 7a and the second upright portion 7b can be moved away from the second base body 10, which is the conductive path on the output side. This makes it possible to increase the optical coupling efficiency between the light-emitting element 2 and the light-receiving element 51, reduce the parasitic capacitance component and parasitic inductance component on the input side, and improve high-frequency characteristics. Therefore, depending on the output light from the light emitting element 2, high frequency signals can be reliably passed and blocked between the first output terminal 8 and the second output terminal 9.

It is preferable that the connection conductor 14, specifically, the second base body 10, has a first externally exposed portion 10b as a portion exposed to the outside of the housing 11. Further, the fourth base 8a has a second externally exposed part 8b as a part exposed to the outside of the housing 11, and the fifth base 9a has a third externally exposed part 9b as a part exposed to the outside of the housing 11. is preferable.

Usually, the first input terminal 6, the third base 6d, the second input terminal 7, and the first base 7d are obtained by processing a single metal plate. On the other hand, when manufacturing a plurality of semiconductor relays 1, it is inefficient to assemble the light emitting elements 2 after dividing the first input terminal 6 and the second input terminal 7 into pieces.

Therefore, first, a metal plate material is processed to create an input terminal prototype in which multiple sets are connected, with each member of the first input terminal 6, third base 6d, second input terminal 7, and first base 7d being connected as one set. Form. In this state, the light emitting elements 2 are connected and fixed to each of the first bases 7d, and further, the anode electrodes 2a of the light emitting elements 2 and the third base 6d are connected with the wires 12. Further, a light transmitting portion 11b made of a light transmitting resin is formed between the light emitting element 2 and the light receiving drive element 5.

A similar process is also performed on the output side. That is, a metal plate material is processed to form an output terminal prototype in which a plurality of sets are connected, each of which includes the first output terminal 8, the second base 10, and the second input terminal 7 as one set. In this state, the light receiving driving element 5, the first MOSFET 3, and the second MOSFET 4 are connected and fixed to the second base 10, the fourth base 8a, and the fifth base 9a, respectively. Furthermore, each part is connected with wires 12 and 13.

After these are formed, the input terminal model and the output terminal model are aligned and arranged, and each element is further sealed by resin injection to form the housing 11. After forming the housing 11, the connection portion with the metal frame is cut, and the plurality of semiconductor relays 1 are each separated into individual pieces.

The first externally exposed portion 10b, the second externally exposed portion 8b, and the third externally exposed portion 9b correspond to connecting portions between the second base 10, the first output terminal 8, and the second output terminal 9 and the metal frame. By forming the second base 10, the first output terminal 8, and the second output terminal 9 so that the first externally exposed portion 10b, the second externally exposed portion 8b, and the third externally exposed portion 9b remain, the semiconductor relay 1 can be easily assembled. Moreover, a large amount of semiconductor relays 1 can be easily manufactured.

For the same reason, it is preferable that the first input terminal 6 and the second input terminal 7 also have a portion exposed to the outside of the housing 11. Specifically, it is preferable that the first external connection part 6a has a fourth externally exposed part 6c, and the second external connection part 7a has a fifth externally exposed part 7c.

The connection conductor 14 includes a second base 10 on which a light receiving element 51 is placed, and the second base 10 includes a fourth base 8a on which the first MOSFET 3 is placed and a fifth base 9a on which the second MOSFET 4 is placed. Preferably, it is placed between. Moreover, it is more preferable that the second base body 10 is arranged between the first source electrode 3a of the first MOSFET 3 and the second source electrode 4a of the second MOSFET 4.

By doing so, a path from the first output terminal 8 to the second output terminal 9 via the first MOSFET 3, the second base 10, and the second MOSFET 4 can be provided in a straight line along the second axis. , the formation of stubs can be reliably suppressed. This can reliably prevent the frequency band of the output signal transmitted by the semiconductor relay 1 from becoming narrower.

Further, the first input terminal 6 and the second input terminal 7 are arranged side by side along the second axis (X direction). The first input terminal 6 has a first upright portion 6b that extends along the second axis inside the housing 11 when viewed along the first axis. When viewed along the first axis, the first upright portion 6b is provided with a cutout 6e at a portion facing the second base body 10.

As mentioned above, the prototypes of the first input terminal 6 and the second input terminal 7 are connected to the same metal frame. Further, a metal frame to which the prototypes are connected is formed by punching a single metal plate. In this state, the original shapes of the first input terminal 6 and the second input terminal 7 are flat, and the distance between the first input terminal 6 and the second input terminal 7 is narrower than before the upright portion is bent. It has become. Therefore, in the process of forming the first input terminal 6 and the second input terminal 7, there is a possibility that the two may come into contact with each other. In order to avoid this, the process of forming the first input terminal 6 and the second input terminal 7 may become complicated.

Therefore, as shown in this embodiment, by providing the notch 6e in the first upright portion 6b, it is possible to prevent the first input terminal 6 and the second input terminal 7 from coming into contact with each other in the process of forming them. , the formation process can be simplified.

Further, by providing the notch 6e in the first upright portion 6b, the width of the first input terminal 6 along the third axis can be partially narrowed. This allows the parasitic mutual inductance M2 and parasitic capacitance C2 to be reduced.

In each of the first input terminal 6 and the second input terminal 7, an upright portion is provided inside the housing 11 so as to extend along the second axis. Further, the upright portion is bent along the first axis halfway from one end connected to the external connection portion to the other end connected to the third base 6d or the first base 7d, and extends upward. It is provided.

The first input terminal 6 and the light emitting element 2 are connected via a wire 12, and as shown in FIG. It is arranged above the upper end of the input terminal 6, that is, the upper surface of the third base 6d.

By providing the standing portions as described above in each of the first input terminal 6 and the second input terminal 7, the length along the second axis, that is, the physical conductive path, can be increased in the first input terminal 6. Can be shortened. Further, the distance between the first input terminal 6 and the second input terminal 7 along the second axis can be narrowed, and the length of the wire 12 connected to the light emitting element 2 can be shortened. In other words, the electrical length on the input side can be shortened. Furthermore, since the length of the wire 12 connected to the light emitting element 2 can be shortened, the parasitic mutual inductance and parasitic capacitance between the wire 12 and the conductor on the output side, such as the second base 10, can be reduced.

Further, by forming the first input terminal 6 and the second input terminal 7 such that the upper end of the second input terminal 7 is arranged above the upper end of the first input terminal 6, the first input terminal In the process of forming the input terminal 6 and the second input terminal 7, it is possible to prevent them from coming into contact with each other, and the formation process can be simplified.

In addition, by providing an upright portion extending upward from the lower surface of the housing 11 so as to be continuous with the external connection portion, the light emitting element 2 can be placed closer to the upper surface of the housing 11. This makes it possible to ensure a distance between the light receiving element 51 and the light emitting element 2, which are located closer to the lower surface of the housing 11. Further, the output light from the light emitting element 2 can be guided to the light receiving element 51 through the light transmitting part 11b.

Further, in each of the first input terminal 6 and the second input terminal 7, an external connection portion is provided so as to extend along the lower surface of the housing 11.

By providing an external connection part that electrically connects to the outside so as to extend along the bottom surface of the housing 11, the semiconductor relay 1 can be connected to, for example, wiring provided on the top surface of the circuit board 40 (see FIGS. 14 to 16). It can be surface mounted.

<Modified example>
FIG. 11 shows a perspective view of a semiconductor relay according to a modification. For convenience of explanation, in FIG. 10 and the subsequent drawings, the same parts as in Embodiment 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The second base body 10 shown in FIG. This is different from the second base body 10 of Embodiment 1 shown in 1 to 5.

By defining the width W2 of the second base body 10 in this way, it is possible to suppress an increase in the characteristic impedance of the transmission line due to the portion of the second base body 10 located at a higher position than the bottom surface of the housing 11. Loss can be reduced.

(Embodiment 2)
FIG. 12 shows a perspective view of a semiconductor relay according to the second embodiment.

The semiconductor relay 30 of this embodiment shown in FIG. 12 has the point that the anode electrode 2a of the light emitting element 2 is connected to the third base 6d via the wire 12 and the chip resistor 15 which is an electronic component as a resistance element. This is different from the semiconductor relay 1 of the first embodiment shown in FIG.

Specifically, the lower surface of the chip resistor 15 is connected and fixed to the upper surface of the third base 6d, and the upper surface of the chip resistor 15 and the anode electrode 2a of the light emitting element 2 are connected by a wire.

According to this embodiment, the electrical length on the input side can be reliably shortened compared to the configuration shown in Embodiment 1. This increases the resonance frequency on the input side and suppresses the occurrence of resonance phenomena. In turn, deterioration of high frequency characteristics on the output side can be suppressed. This will be further explained using FIG. 13.

FIG. 13 shows a schematic diagram illustrating the difference in resonance phenomenon before and after inserting a resistor on the input side.

When a high frequency signal is input between the first input terminal 6 and the second input terminal 7, a standing wave is generated when the electrical length on the input side reaches a predetermined value, as shown on the left side of FIG. , resonance phenomena may occur. Therefore, in order to increase the resonance frequency on the input side, it is necessary to shorten the wavelength of the standing wave.

Therefore, as shown in this embodiment, a resistance element having a resistance value higher than the resistance value of the conductive path is inserted in the middle of the conductive path on the input side so as to be electrically connected in series. By doing so, the vibration of the standing wave is significantly attenuated at the position where the resistance element is inserted. In other words, the insertion position of the resistance element becomes a node of the standing wave. As a result, as shown on the right side of FIG. 13, the wavelength of the standing wave can be shortened, and the resonance frequency on the input side can be increased. As a result, occurrence of resonance phenomena and deterioration of high frequency characteristics on the output side can be suppressed.

As shown on the right side of Figure 13, in order to shorten the wavelength of the standing wave, it is effective to insert a resistance element at the midpoint between the nodes of the standing wave. . In other words, if the resonance phenomenon is occurring in the semiconductor relay 1 before the resistance element is inserted, it will occur not near the ends of the first input terminal 6 or the second input terminal 7, but at the physical intermediate part of each. Preferably, the resistive elements are inserted in series.

Further, as shown in FIG. 12, there is no need to insert the chip resistor 15 as a resistance element in the conductive path connecting the first input terminal 6 and the light emitting element 2. The chip resistor 15 may be connected in series to at least one of the conductive path connecting the first input terminal 6 and the light emitting element 2 and the conductive path connecting the second input terminal 7 and the light emitting element 2.

The resistance value of the chip resistor 15 is preferably higher than the resistance value of the conductive path described above, but the specific value may be changed as appropriate depending on the frequency of the input signal, the resistance value of the conductive path, etc. .

Furthermore, methods other than inserting a resistive element can be used to shorten the electrical length on the input side. For example, the electrical length on the input side can also be shortened by replacing the chip resistor 15 with a chip inductor as an inductor element that provides a higher impedance than the impedance of the conductive path described above in the high frequency region. In this case as well, it is possible to suppress the occurrence of a resonance phenomenon and to suppress deterioration of the high frequency characteristics on the output side.

(Embodiment 3)
14 shows a perspective view of the semiconductor relay module according to Embodiment 3, FIG. 15 shows a view of the semiconductor relay module viewed along the second axis, and FIG. 16 shows the semiconductor relay module viewed along the third axis. A view along the line is shown.

As shown in FIGS. 14 to 16, the semiconductor relay module 100 includes at least a semiconductor relay 1 and a circuit board 40. Since the semiconductor relay 1 has the same configuration as shown in Embodiment 1, detailed explanation will be omitted.

The circuit board 40 is a so-called printed wiring board in which first to fourth wirings 41 to 44 are formed on a dielectric substrate 40a made of a dielectric material having a predetermined dielectric constant.

The first to fourth wirings 41 to 44 are formed by applying copper plating or the like to the upper surface of the dielectric substrate 40a. Further, a conductive via 45 is connected to one end of each of the first to fourth wirings 41 to 44. The conductive via 45 is a via hole that penetrates the dielectric substrate 40a in the thickness direction, and a conductor is embedded in the inner surface of the via hole using copper plating or the like. Note that in order to simplify the manufacturing process of the semiconductor relay module 100, this conductor is preferably formed at the same time as the first to fourth wirings 41 to 44 are formed.

In each of the third wiring 43 and the fourth wiring 44, the first output terminal 8 of the semiconductor relay 1 and the second Output terminals 9 are connected respectively. For connection, a conductive adhesive such as silver paste or cream solder is used.

Further, the first input terminal 6 and the second input terminal 7 of the semiconductor relay 1 are connected to the other ends of the first wiring 41 and the second wiring 42, respectively. For connection, a conductive adhesive such as silver paste or cream solder is used.

On the other hand, each of the first wiring 41 and the second wiring 42 is divided near the other end. In each of the first wiring 41 and the second wiring 42, chip resistors 16 are connected in series as resistance elements so as to connect the divided portions.

Input signals are transmitted to the first wiring 41 and the second wiring 42 from the conductive via 45 connected to the first wiring 41 and the conductive via 45 connected to the second wiring 42 . Furthermore, input signals are transmitted to the first input terminal 6 and the second input terminal 7 of the semiconductor relay 1 . Also, during a period when an input signal with an amplitude greater than a predetermined value is being input, a semiconductor relay is connected between the third wiring 43 to which the first output terminal 8 is connected and the fourth wiring 44 to which the second output terminal 9 is connected. 1 through which a high frequency signal is transmitted. Further, a high frequency signal is transmitted between the conductive via 45 connected to the third wiring 43 and the conductive via 45 connected to the fourth wiring 44. When the amplitude of the input signal becomes less than a predetermined value, a conductive via 45 connected to the third wiring 43 and a conductive via 45 connected to the fourth wiring 44 is connected between the third wiring 43 and the fourth wiring 44. Transmission of high frequency signals is blocked between the two.

According to this embodiment, in the semiconductor relay 1, capacitive coupling and inductive coupling between input and output can be reduced, and the electrical length on the input side can be shortened. Thereby, deterioration of the high frequency characteristics of the output signal transmitted between the third wiring 43 and the fourth wiring 44 can be suppressed.

In addition, in the semiconductor relay module 100 of the present embodiment, in each of the first wiring 41 and the second wiring 42 connected to the second input terminal 7, a Chip resistors 16 are connected in series. More specifically, a chip resistor 16 is inserted as a resistance element having a predetermined resistance value in the vicinity of the connection point with the first input terminal 6 in the first wiring 41 so as to be electrically connected in series. . Further, a chip resistor 16 is inserted as a resistive element having a predetermined resistance value in the vicinity of the connection point with the second input terminal 7 in the second wiring 42 so as to be electrically connected in series.

By doing so, in the second embodiment, as explained using FIG. 13, the wavelength of the standing wave can be shortened and the resonance frequency on the input side can be increased. As a result, occurrence of resonance phenomena and deterioration of high frequency characteristics on the output side can be suppressed.

Note that either one of the resistance elements connected to the first wiring 41 and the resistance element connected to the second wiring 42 may not be connected. Furthermore, if the semiconductor relay 1 and the semiconductor relay module 100 are designed so that the resonance frequency on the input side is higher than a predetermined value, it is not essential to connect the chip resistor 16 as a resistance element, and it is not necessary to connect the chip resistor 16 as a resistance element. good. In that case, the first wiring 41 and the second wiring 42 are not divided and are provided continuously from the conductive via 45 to the first input terminal 6 and the second input terminal 7. Furthermore, a chip inductor can be used instead of the chip resistor 15.

Note that although FIGS. 14 to 16 show the semiconductor relay module 100 in which only the semiconductor relay 1 is mounted on the circuit board 40, other elements may be mounted on the circuit board 40. Moreover, the conductive via 45 penetrating the circuit board 40 does not necessarily have to be provided. A plurality of pad electrodes (not shown) for external connection may be provided on the upper surface of the circuit board 40, and each pad electrode may be connected to the first to fourth wirings 41 to 44.

(Other embodiments)
It is also possible to create a new embodiment by appropriately combining each component shown in Embodiments 1 to 3 and the modified examples. For example, in the semiconductor relay module 100 shown in the third embodiment, the structure of the semiconductor relay 1 may be the structure shown in the second embodiment or the modified example.

Further, in this specification, the relationships among the shortest distance L0, the shortest distance L1, and the shortest distance L2 described above are defined as shown in FIG. 3, but the relationship is not particularly limited thereto. The shortest distance L0 may be the same as the shortest distance L1, or the shortest distance L0 may be the shortest distance L2. As described above, by defining the relationship between the shortest distance L0, the shortest distance L1, and the shortest distance L2 as shown in FIG. 3, the parasitic capacitance component on the input side can be reduced.

In addition, in the present specification, the first output terminal 8 and the second output terminal 9 are connected to the rear surfaces of the fourth base body 8a and the fifth base body 9a exposed from the respective housings 11 to the outside, for example, as shown in FIGS. 14 to 16. Although the third wiring 43 and the fourth wiring 44 are connected to each other, the present invention is not particularly limited thereto. The semiconductor relay 1 may be a surface-mounted relay, and for example, the semiconductor relay 1 may be a surface-mounted relay that protrudes along the lower surface of the housing 11 and is exposed to the outside from the side surface of the housing 11, like the first input terminal 6 and the second input terminal 7. External connection parts may be provided at the first output terminal 8 and the second output terminal 9, respectively.

Further, the first external connection portion 6a of the first input terminal 6 and the second external connection portion 7a of the second input terminal 7 do not need to protrude to the outside from the side surface of the housing 11. That is, the external connection portion only needs to be exposed from at least the bottom surface of the housing 11. By doing so, a surface-mounted semiconductor relay 1 can be realized.

Further, the control circuit 52 may be formed on a separate semiconductor chip from the light receiving element 51. In that case, the control circuit 52 is preferably sealed with the light shielding part 11a of the housing 11.

The semiconductor relay of the present disclosure can suppress deterioration of high frequency characteristics on the output side and is useful as a relay for transmitting high frequency signals.

1 Semiconductor relay 2 Light emitting element 2a Anode electrode 3 First MOSFET
3a First source electrode (first intermediate electrode)
3b First gate electrode 4 Second MOSFET
4a Second source electrode (second intermediate electrode)
4b Second gate electrode 5 Light receiving drive element 5a Source electrode (first electrode)
5b Drain electrode 6 First input terminal 6a First external connection part 6b First upright part 6c Fourth external exposed part 6d Third base 6e Notch 7 Second input terminal 7a Second external connection part 7b Second upright part 7c 5 Externally exposed portion 7d First base 7d1 First main surface 7e Seventh externally exposed portion 8 First output terminal 8a Fourth base 8b Second externally exposed portion 9 Second output terminal 9a Fifth base 9b Third externally exposed portion 10 Second base body 10a Second main surface 10b First externally exposed part 11 Housing 11a Light shielding part 11b Transparent part 12 Wire 13 Wire 14 Connection conductor 15 Chip resistor (resistance element)
16 Chip resistor (resistance element)
20 Semiconductor relay 30 Semiconductor relay 40 Circuit board 40a Dielectric substrates 41 to 44 First to fourth wiring 45 Conductive via 51 Light receiving element 51a Cathode electrode (first electrode)
51b Anode electrode 52 Control circuit 100 Semiconductor relay module

Claims (12)

a housing having an upper surface and a lower surface located below the upper surface along a first axis;
a first input terminal and a second input terminal;
a first output terminal and a second output terminal;
a light emitting element electrically connected to the first input terminal and the second input terminal;
a light receiving driving element having a first surface that receives output light of the light emitting element, a second surface located below the first surface along the first axis, and a first electrode;
a first MOSFET including a first intermediate electrode electrically connected to the first electrode, a first output electrode electrically connected to the first output terminal, and a first gate electrode;
a second MOSFET including a second intermediate electrode electrically connected to the first electrode, a second output electrode electrically connected to the second output terminal, and a second gate electrode;
a first base having an upper surface corresponding to a first main surface on which the light emitting element is arranged;
a connecting conductor having a second main surface on which the light receiving driving element is arranged and connected to the first electrode at the same potential;
comprising at least
At least a portion of the connection conductor is disposed between the first MOSFET and the second MOSFET when viewed along the first axis,
The light emitting element is spaced apart from each other when viewed along the first axis.
semiconductor relay. The normal to the first main surface is parallel to the normal to the second main surface,
The semiconductor relay according to claim 1. The connection conductor includes a second base on which the light receiving driving element is placed and has the second main surface,
The first main surface of the first base is located above the second main surface of the second base when viewed along an axis perpendicular to the first axis.
The semiconductor relay according to claim 1. The connection conductor includes a second base on which the light receiving driving element is placed,
the first base is connected to one end of the second input terminal,
The shortest distance between the first base and the second base is smaller than the shortest distance between the first input terminal and the second base and the shortest distance between the second input terminal and the second base.
The semiconductor relay according to claim 1. the first input terminal and the second input terminal are arranged along a second axis perpendicular to the first axis,
The first input terminal has an upright portion extending along the second axis inside the housing when viewed along the first axis;
The upright portion of the first input terminal is provided with a notch at a portion facing the second base when viewed along the first axis.
The semiconductor relay according to claim 3. the first input terminal and the second input terminal are arranged along a second axis perpendicular to the first axis,
The first input terminal and the second input terminal each have an upright portion extending along the second axis inside the housing when viewed along the first axis,
the first input terminal and the light emitting element are connected via a wire,
the upper end of the second input terminal is located above the upper end of the first input terminal;
The semiconductor relay according to claim 3. The connection conductor has a portion exposed to the outside of the housing.
The semiconductor relay according to claim 1. The connection conductor includes a second base on which the light receiving driving element is placed,
The second base has the second main surface and is disposed between the base on which the first MOSFET is placed and the base on which the second MOSFET is placed.
The semiconductor relay according to claim 1. A resistive element having a predetermined resistance or an inductor having a predetermined impedance in at least one of a conductive path connecting the first input terminal and the light emitting element and a conductive path connecting the second input terminal and the light emitting element. elements are electrically connected in series,
The semiconductor relay according to claim 1. When an axis along the arrangement direction of the light emitting element and the light receiving driving element is a third axis,
The width of the second base along the third axis is wider than the width of the first output terminal along the third axis or the width of the second output terminal along the third axis.
The semiconductor relay according to claim 8. The semiconductor relay according to claim 1;
At least a circuit board on which first to fourth wirings are respectively formed,
The first wiring and the second wiring are connected to the first input terminal and the second input terminal of the semiconductor relay, respectively,
The third wiring and the fourth wiring are connected to the first output terminal and the second output terminal of the semiconductor relay, respectively.
Semiconductor relay module. A resistance element having a predetermined resistance or an inductor element having a predetermined impedance is electrically connected in series near a connection point with the first input terminal in the first wiring.
and/or
A resistance element having a predetermined resistance or an inductor element having a predetermined impedance is electrically connected in series near a connection point with the second input terminal in the second wiring,
The semiconductor relay module according to claim 11.