JP2023176902A - Method for manufacturing semiconductor device - Google Patents

Abstract

To suitably suppress warpage of a compound semiconductor substrate.SOLUTION: A method for manufacturing a semiconductor device (10) includes a first implantation step and a second implantation step. In the first implantation step, a dopant is implanted from a first surface side so that a peak (P1) of a density of the dopant is formed closer to the first surface side than a central portion (50) in a thickness direction of the compound semiconductor substrate. In the second implantation step, an inert impurity is implanted into the compound semiconductor substrate from the first surface side. In the second implantation step, a peak (P2) of the density of the crystal defect is formed closer to a second surface side than the central portion of the compound semiconductor substrate. When the amount of warpage of the compound semiconductor substrate is defined by an assumption that the warpage in which the first surface becomes convex is a positive value, the amount of warpage increases in the first implantation step and the amount of warpage decreases in the second implantation step.SELECTED DRAWING: Figure 5

Description

The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

When a dopant is implanted into a compound semiconductor substrate, crystal defects are formed in the dopant implantation range. As a result, the crystal lattice is distorted within the dopant implantation range, causing warpage in the compound semiconductor substrate. Handling a compound semiconductor substrate in a warped state causes problems such as the exposure device not being able to focus when processing the compound semiconductor substrate, and the compound semiconductor substrate being damaged during transportation.

Patent Document 1 discloses that warping of a compound semiconductor substrate is suppressed by forming a deformation suppressing layer made of a material different from that of the compound semiconductor substrate (e.g., aluminum, titanium, nickel, platinum, etc.) on the surface of the compound semiconductor substrate. A technique for doing so has been disclosed.

JP2017-183730A

In the warpage suppression technique disclosed in Patent Document 1, it is necessary to form a deformation suppression layer made of a material different from that of the compound semiconductor substrate on the surface of the compound semiconductor substrate. Therefore, depending on the structure of the semiconductor device to be manufactured, it may not be possible to form the deformation suppressing layer. Further, the deformation suppressing layer may not be formed due to the problem of metal contamination of the compound semiconductor substrate or semiconductor manufacturing equipment.

In addition, warping of the compound semiconductor substrate is suppressed by injecting impurities into the compound semiconductor substrate from the surface (hereinafter referred to as the second surface) opposite to the surface where the dopant is implanted (hereinafter referred to as the first surface). The technology exists. According to this technique, warpage of the compound semiconductor substrate can be suppressed without causing the problems that occur in Patent Document 1. However, in this method, it is necessary to form a protective film on the first surface to prevent the first surface from coming into contact with the stage etc. during impurity implantation from the second surface side, which increases the processing cost for the compound semiconductor substrate. It gets expensive. Further, during the process of forming and removing the protective film, foreign matter may adhere to the first surface, scratches may occur, etc.

Therefore, this specification proposes a technique that can more suitably suppress warping of a compound semiconductor substrate.

The method for manufacturing a semiconductor device disclosed in this specification includes a first implantation step and a second implantation step. In the first implantation step, an n-type or p-type dopant is implanted from the first surface side into a compound semiconductor substrate having a first surface and a second surface located on the back side of the first surface. In the first implantation step, the dopant is implanted so that a density peak of the dopant is formed closer to the first surface than to a central portion in the thickness direction of the compound semiconductor substrate. In the second implantation step, crystal defects are formed in the compound semiconductor substrate by implanting an inactive impurity into the compound semiconductor substrate from the first surface side. In the second implantation step, the inert impurity is implanted so that a peak density of the crystal defects is formed closer to the second surface than the center of the compound semiconductor substrate. When the amount of warpage of the compound semiconductor substrate is defined by taking the warpage in which the first surface becomes convex as a positive value, the amount of warpage increases in the first implantation step, and the amount of warpage increases in the second implantation step. Decrease.

Note that in the above manufacturing method, either the first injection step or the second injection step may be performed first.

In this manufacturing method, in the first implantation step, the peak of dopant density is formed closer to the first surface than the central portion in the thickness direction of the compound semiconductor substrate, so that the amount of warpage of the compound semiconductor substrate increases. Furthermore, in the second implantation step, the peak of the dopant density is formed closer to the second surface than the central portion in the thickness direction of the compound semiconductor substrate, so that the amount of warpage of the compound semiconductor substrate is reduced. For example, when the first implantation step is performed before the second implantation step, the compound semiconductor substrate is warped so that the first surface becomes convex in the first implantation step, and the compound semiconductor substrate is warped in the second implantation step so that the first surface becomes convex. The compound semiconductor substrate is deformed so as to eliminate the warpage of the semiconductor substrate. Further, for example, if the second implantation step is performed before the first implantation step, the compound semiconductor substrate is warped so that the first surface becomes concave in the second implantation step, and the first implantation step In the step, the compound semiconductor substrate is deformed so as to eliminate the warpage of the compound semiconductor substrate. In this way, the warpage that occurs in the first implantation step and the warp that occurs in the second implantation step cancel each other out, so that the warpage of the compound semiconductor substrate is suppressed. Furthermore, in the second implantation step, an inert impurity is implanted into the compound semiconductor substrate from the first surface side of the compound semiconductor substrate. That is, in both the first implantation step and the second implantation step, implantation is performed from the first surface side. Therefore, the first surface of the compound semiconductor substrate does not come into contact with the stage in the first implantation step and the second implantation step, and there is no need to protect the first surface with a protective film. Therefore, the problem of increased processing cost due to the protective film does not occur. Further, it is possible to prevent foreign matter from adhering to the first surface or from causing scratches on the first surface due to the protective film. Furthermore, since the impurity implanted in the second implantation step is an inactive impurity, even if the inert impurity is implanted from the first surface side to a depth on the second surface side rather than the central part of the compound semiconductor substrate, the compound semiconductor The effect on the characteristics of the substrate is small. Therefore, a semiconductor device can be suitably manufactured.

FIG. 3 is an enlarged cross-sectional view of a switching element. FIG. 3 is an enlarged cross-sectional view of the semiconductor substrate before the first injection step. An explanatory diagram of the first implantation step (a diagram showing an enlarged cross-sectional view of the semiconductor substrate in the first implantation step and a graph showing the density distribution of the p-type dopant implanted into the electric field relaxation region). FIG. 3 is a cross-sectional view showing warpage of the semiconductor substrate after the first implantation step. An explanatory diagram of the second implantation step (an enlarged cross-sectional view of the semiconductor substrate in the second implantation step, a graph showing the density distribution of the p-type dopant implanted into the electric field relaxation region, and a graph showing the density distribution of the p-type dopant implanted into the electric field relaxation region). (Graph showing the density distribution of crystal defects.) FIG. 3 is a cross-sectional view of the semiconductor substrate after the second implantation step. FIG. 7 is an explanatory diagram of a second injection step of a modified example.

FIG. 1 shows a switching element 10 manufactured by the manufacturing method of the embodiment. The switching element 10 is a MOSFET (metal oxide semiconductor field effect transistor). The switching element 10 has a semiconductor substrate 12, a gate insulating film 14, a gate electrode 16, an interlayer insulating film 18, a source electrode 20, and a drain electrode 22. Semiconductor substrate 12 is a so-called compound semiconductor substrate, and is made of silicon carbide (i.e., SiC). Note that the semiconductor substrate 12 may be made of gallium nitride (ie, GaN), gallium oxide (eg, Ga ₃ O ₃ ), or the like. The semiconductor substrate 12 has an upper surface 12a and a lower surface 12b. A plurality of trenches 12c are provided in the upper surface 12a. Gate insulating film 14 covers the inner surface of each trench 12c. The gate electrode 16 is arranged in each trench 12c and is insulated from the semiconductor substrate 12 by the gate insulating film 14. Interlayer insulating film 18 covers the upper surface of each gate electrode 16 . The source electrode 20 covers the upper surface of the interlayer insulating film 18 and the upper surface 12a of the semiconductor substrate 12. Source electrode 20 is insulated from each gate electrode 16 by interlayer insulating film 18 . Drain electrode 22 covers lower surface 12b of semiconductor substrate 12.

The semiconductor substrate 12 has a source layer 30, a body contact layer 32, a body layer 34, an electric field relaxation layer 36, a drift layer 38, a buffer layer 40, and a drain layer 42. Source layer 30 is an n-type layer. Each source layer 30 is in contact with the gate insulating film 14 at the upper end of the side surface of the corresponding trench 12c. Each source layer 30 is in ohmic contact with the source electrode 20. Each body contact layer 32 is a p-type layer. Each body contact layer 32 is in ohmic contact with the source electrode 20 in an area where the source layer 30 is not provided. The body layer 34 is a p-type layer having a lower p-type impurity concentration than the body contact layer 32. The body layer 34 is arranged below the source layer 30 and the body contact layer 32. The body layer 34 is in contact with the gate insulating film 14 below the source layer 30. Each electric field relaxation layer 36 is a p-type layer, and is arranged in a range adjacent to the lower end of each trench 12c. Each electric field relaxation layer 36 is in contact with the gate insulating film 14 at the lower end of the corresponding trench 12c. Drift layer 38 is an n-type layer and is arranged below body layer 34 . The drift layer 38 covers the periphery of each electric field relaxation layer 36. The drift layer 38 is in contact with the gate insulating film 14 on the lower side of the body layer 34. The buffer layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38. Buffer layer 40 is arranged below drift layer 38 . The drain layer 42 is an n-type layer having a higher n-type impurity concentration than the buffer layer 40. Drain layer 42 is arranged below buffer layer 40 . Drain layer 42 is in ohmic contact with drain electrode 22 .

When a voltage equal to or higher than the gate threshold is applied to the gate electrode 16, a channel is formed in the body layer 34 at a position adjacent to the gate insulating film 14, and the source layer 30 and the drift layer 38 are connected by the channel. This turns on the switching element 10. When the voltage applied to the gate electrode 16 is lowered to a voltage below the gate threshold, the channel disappears and the switching element 10 is turned off. When the switching element 10 is turned off, a depletion layer spreads from the electric field relaxation layer 36 to the drift layer 38. The depletion layer spreading from the electric field relaxation layer 36 suppresses electric field concentration at the lower end of the trench 12c.

Next, a method for manufacturing the switching element 10 will be described. FIG. 2 shows the semiconductor substrate 12 before the source layer 30, body contact layer 32, body layer 34, and electric field relaxation layer 36 are formed. The switching element 10 is manufactured from the semiconductor substrate 12 shown in FIG. As shown in FIG. 2, at this point, the drift layer 38 is exposed on the upper surface 12a of the semiconductor substrate 12. Further, at this point, the thickness of the drain layer 42 is thicker than that in FIG. 1, and more than half of the thickness of the semiconductor substrate 12 is constituted by the drain layer 42. Reference numeral 50 in FIG. 2 indicates the central portion of the semiconductor substrate 12 in the thickness direction. Since the drain layer 42 is thick, the central portion 50 is located within the drain layer 42 . The semiconductor substrate 12 is flat before the source layer 30, body contact layer 32, body layer 34, and electric field relaxation layer 36 are formed. That is, no warpage occurs in the semiconductor substrate 12 before the source layer 30, body contact layer 32, body layer 34, and electric field relaxation layer 36 are formed. In this manufacturing method, a first implantation step and a second implantation step are performed on the semiconductor substrate 12.

(First injection step)
In the first implantation step, the source layer 30, A body contact layer 32, a body layer 34, and an electric field relaxation layer 36 are formed. For example, FIG. 3 shows the step of implanting p-type dopants into the field relaxation layer 36. As shown in FIG. 3, in the step of implanting the p-type dopant into the electric field relaxation layer 36, the semiconductor substrate 12 is placed on the stage 62 so that the lower surface 12b of the semiconductor substrate 12 is in contact with the stage 62. Then, a p-type dopant is implanted into the semiconductor substrate 12 from above through the mask 60. Here, the dose amount is controlled to 1×10 ¹³ to 1×10 ¹⁴ cm ⁻² . Furthermore, when the dopant density distribution is measured along the thickness direction of the semiconductor substrate 12, the peak P1 of the density of the p-type dopant injected into the electric field relaxation layer 36 is located above the central portion 50. Control the injection energy to More specifically, the p-type dopant implanted into the electric field relaxation layer 36 is implanted so that the implantation depth D1 (that is, the distance from the upper surface 12a to the depth of the peak P1) is 1 μm or more (for example, 1 to 3 μm). control the energy injected into the Similarly, dopants are implanted into the source layer 30, body contact layer 32, and body layer 34 from the upper surface 12a side. After the dopant implantation into the source layer 30, body contact layer 32, body layer 34, and electric field relaxation layer 36 is completed, the semiconductor substrate 12 is annealed to activate the dopant.

As described above, in the first implantation step, a dopant is implanted into the semiconductor layer closer to the upper surface 12a than the central portion 50. Crystal defects are formed in the semiconductor layer into which the dopant is implanted. That is, the crystallinity of the semiconductor substrate 12 decreases within the dopant implantation range. As a result, the semiconductor layer into which the dopant has been implanted (ie, the semiconductor layer near the top surface 12a) expands. Therefore, as shown in FIG. 4, the semiconductor substrate 12 is warped so that the upper surface 12a becomes convex. In particular, when aluminum is implanted into the electric field relaxation layer 36 with a deep implantation depth, the crystallinity of the semiconductor layer tends to deteriorate, and the semiconductor substrate 12 tends to warp.

Note that, hereinafter, the amount of warpage of the semiconductor substrate 12 is defined as the amount of warp X, where the warp in which the upper surface 12a becomes convex is defined as a positive value, and the warp in which the upper surface 12a becomes concave is defined as a negative value. In the first implantation step, the amount of warpage X of the semiconductor substrate 12 increases.

(Second injection step)
Next, a second injection step is performed. In the second implantation step, as shown in FIG. 5, inert impurity ions are implanted into the semiconductor substrate 12 from the upper surface 12a side. The inactive impurity is an element that is inactive with respect to the semiconductor substrate 12. As the inert impurity, for example, carbon, silicon, hydrogen, helium, argon, etc. can be used. Note that in the case of implanting hydrogen ions (for example, protons or deuterons) or helium ions as inert impurities, a cyclotron can be used as the ion irradiation device. As shown in FIG. 5, in the step of implanting inactive impurities, the semiconductor substrate 12 is placed on the stage 64 so that the lower surface 12b of the semiconductor substrate 12 is in contact with the stage 64. Then, inert impurities are implanted into the entire semiconductor substrate 12 from above. Here, the inert impurity is implanted so that the inert impurity implanted from the upper surface 12a side stops within the drain layer 42 on the lower surface 12b side with respect to the central portion 50. When inert impurities are implanted in this manner, crystal defects are formed at a low density in the semiconductor layer through which the inactive impurities pass, and crystal defects are formed at a high density at positions where the inactive impurities stop. Therefore, as shown in FIG. 5, a peak P2 of crystal defect density is formed in the semiconductor layer closer to the lower surface 12b than the central portion 50. Hereinafter, the region where the peak P2 of crystal defect density is formed will be referred to as a crystal defect region 70. For example, in the second implantation step, the implantation depth of the inert impurity can be controlled so that the distance D2 from the crystal defect region 70 to the lower surface 12b is 0.1 to 5.0 μm. Note that when an aluminum thin film (for example, aluminum foil) is placed between the inert impurity irradiation device and the semiconductor substrate 12, the implantation depth of the inert impurity can be adjusted by adjusting the thickness of the aluminum thin film. can.

As described above, in the second implantation step, a peak P2 of crystal defect density is formed in the semiconductor layer closer to the lower surface 12b than the central portion 50. As a result, the semiconductor layer closer to the lower surface 12b than the central portion 50 expands. Therefore, as shown in FIG. 6, when the second implantation step is performed, the warpage of the semiconductor substrate 12 is alleviated.

In this way, in the first implantation step, the semiconductor substrate 12 is warped so that the upper surface 12a becomes convex, and in the second implantation step, the semiconductor substrate 12 is deformed so that the warp of the semiconductor substrate 12 is alleviated. In other words, the amount of warpage X increases in the first implantation step, and the amount of warpage X decreases in the second implantation step. In this way, the warpage caused in the first implantation step and the warp caused in the second implantation step are offset, so that the semiconductor substrate 12 becomes substantially flat after both the first implantation step and the second implantation step are performed.

Further, in both the first implantation step and the second implantation step, impurities are implanted into the semiconductor substrate 12 from the upper surface 12a side. Therefore, in both the first injection step and the second injection step, it is the lower surface 12b that comes into contact with the stage, and the upper surface 12a does not come into contact with the stage. Therefore, there is no need to protect the upper surface 12a with a protective film, and the semiconductor substrate 12 can be processed at low cost. Further, when a protective film is provided on the upper surface 12a, foreign matter may adhere to the upper surface 12a or scratches may occur during the protective film forming process and the protective film removing process. On the other hand, in the first injection step and the second injection step, since no protective film is provided on the upper surface 12a, the problem of foreign matter or scratches on the upper surface 12a does not occur. Therefore, the switching element 10 can be manufactured with high yield.

Furthermore, in the second implantation step, inert impurities are implanted from the upper surface 12a side to the region near the lower surface 12b. If an n-type or p-type dopant is implanted from the upper surface 12a side to a region near the lower surface 12b, the characteristics of the semiconductor layer within the area through which the dopant passes will be affected, making it difficult to manufacture a switching element with the intended characteristics. Can not do it. On the other hand, in the second implantation step described above, inactive impurities are implanted, so even if the inert impurities are implanted from the upper surface 12a side to the crystal defect region 70, the effect on the characteristics of the semiconductor layer is extremely small. Therefore, even if the second implantation step is performed, it is possible to manufacture the switching element 10 with the intended characteristics.

After the second implantation step is completed, a trench 12c is formed in the upper surface 12a of the semiconductor substrate 12. Next, a gate insulating film 14 and a gate electrode 16 are formed in the trench 12c. Next, an interlayer insulating film 18 is formed. Next, a source electrode 20 is formed. Since the semiconductor substrate 12 is flat, the occurrence of defects due to warpage of the semiconductor substrate 12 is suppressed in these steps and in the transportation step of transporting the semiconductor substrate 12 between these steps.

Next, the lower surface 12b of the semiconductor substrate 12 is polished. This thins the drain layer 42 to the thickness shown in FIG. By polishing the lower surface 12b in this manner, the crystal defect region 70 is removed from the semiconductor substrate 12. Thereafter, the drain electrode 22 is formed on the lower surface 12b, thereby completing the switching element 10 of FIG.

In addition, in the embodiment described above, the second injection process was performed after the first injection process. However, the first implantation step may be performed after the second implantation step. In this case, in the second implantation step, the semiconductor substrate 12 is warped so that the lower surface 12b becomes convex. That is, in the second implantation process, the semiconductor substrate 12 is deformed so that the amount of warpage X decreases to a negative value. In the subsequent first implantation step, the semiconductor substrate 12 is deformed so that the warpage caused in the second implantation step is alleviated. That is, in the first implantation step, the semiconductor substrate 12 is deformed so that the amount of warpage X increases. As a result, the semiconductor substrate 12 becomes flat. In this way, even if the first implantation step is performed after the second implantation step, the semiconductor substrate 12 can be planarized after the first implantation step and the second implantation step are performed. However, if the first implantation step is performed first, the first implantation step can be started in a state where the semiconductor substrate 12 is not warped. It is easy to precisely control the dopant implant range and implant depth for 36.

Furthermore, in the second implantation step described above, inert impurities were implanted so that crystal defect regions 70 were formed within the drain layer 42. However, as shown in FIG. 7, when the thickness of the drain layer 42 is thin and the center portion 50 is present in the drift layer 38, the crystal defect region 70 is placed in the drift layer 38 below the center portion 50. Alternatively, the crystal defect region 70 may be formed within the buffer layer 40. In these cases, crystal defects existing within the crystal defect region 70 function as carrier recombination centers. Therefore, when the diode formed by the pn junction at the interface between the body layer 34 and the drift layer 38 performs a reverse recovery operation, the holes in the drift layer 38 can be eliminated by the crystal defects in the crystal defect region 70. . As a result, the reverse recovery current generated in the diode can be reduced.

Further, in the embodiment described above, the switching element 10 is a MOSFET, but the switching element may be an IGBT (insulated gate bipolar transistor). In this case, if a crystal defect region 70 is formed within the drift layer 38 (for example, see FIG. 7) or within the buffer layer 40, the turn-off speed of the IGBT can be increased.

Further, in the embodiment described above, a method for manufacturing the switching element 10 has been described, but the technology disclosed in this specification may be applied to other semiconductor device manufacturing processes.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings simultaneously achieve multiple objectives, and achieving one of the objectives has technical utility in itself.

10: Switching element, 12: Semiconductor substrate, 16: Gate electrode, 30: Source layer, 34: Body layer, 36: Electric field relaxation layer, 38: Drift layer, 40: Buffer layer, 42: Drain layer, 70: Crystal defect region

Claims (2)

A method for manufacturing a semiconductor device (10), comprising:
An n-type or p-type dopant is implanted from the first surface side into a compound semiconductor substrate (12) having a first surface (12a) and a second surface (12b) located on the back side of the first surface. In the first implantation step, the dopant is implanted so that a density peak (P1) of the dopant is formed closer to the first surface than the center (50) in the thickness direction of the compound semiconductor substrate. 1 injection step,
a second implantation step of forming crystal defects in the compound semiconductor substrate by implanting an inert impurity into the compound semiconductor substrate from the first surface side, the second implantation step forming crystal defects in the compound semiconductor substrate from the central portion of the compound semiconductor substrate; a second implantation step of implanting the inert impurity so that a peak (P2) of the crystal defect density is formed on the second surface side;
has
When the amount of warpage of the compound semiconductor substrate is defined by taking the warpage in which the first surface becomes convex as a positive value, the amount of warpage increases in the first implantation step, and the amount of warpage increases in the second implantation step. Decrease,
Production method. The manufacturing method according to claim 1, wherein the second injection step is performed after the first injection step.

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