JP2023167538A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which can suppress increase of the leakage current and deterioration of the voltage-withstanding or suppress a current collapse phenomenon by suppressing the electric field concentration of an AlGaN layer.SOLUTION: A semiconductor device according to the present invention comprises: an n-type GaN layer 12; a first n-type AlGaN layer 13 which is arranged on the n-type GaN layer 12; a second n-type AlGaN layer 21 which is arranged on the first n-type AlGaN layer 13; a source electrode 15 which is arranged on the first n-type AlGaN layer 13 and located on one side of the second n-type AlGaN layer 21; a drain electrode 16 which is arranged on the first n-type AlGaN layer 13 and located on the other side of the second n-type AlGaN layer 21; a p-type AlGaN layer 22 which is arranged on the second n-type AlGaN layer 21 and located on the source electrode 15 side relative to the center on the second n-type AlGaN layer 21; and a gate electrode 18 which is arranged on the p-type AlGaN layer 22.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device.

A conventional semiconductor device is a polarization junction GaN-based FET as a HEMT (high electron mobility transistor). This polarization junction GaN-based FET includes a buffer layer formed on a Si substrate, a first n-type GaN layer formed on this buffer layer, and an n-type GaN layer formed on this first n-type GaN layer. It has a type AlGaN layer and a second n-type GaN layer formed on this n-type AlGaN layer. A source electrode located on one side of the second n-type GaN layer and a drain electrode located on the other side of the second n-type GaN layer are formed on the n-type AlGaN layer. A p-type GaN layer is formed on the second n-type GaN layer, and a gate electrode is formed on this p-type GaN layer. A technique related to this is disclosed in Patent Document 1.

In the above-mentioned conventional polarization junction GaN-based FET, a first GaN layer, an AlGaN layer, and a second GaN layer are sequentially formed on the buffer layer by an epitaxial growth method. During this epitaxial growth, impurities such as Si and C are mixed into the first GaN layer, AlGaN layer, and second GaN layer to make these layers n-type. This may cause electric field concentration in the n-type AlGaN layer and the n-type GaN layer, resulting in an increase in leakage current and a deterioration in breakdown voltage. Furthermore, making these layers n-type may impede suppression of current collapse.

Therefore, in the above semiconductor device, it is required to suppress electric field concentration between the n-type AlGaN layer and the n-type GaN layer, suppress an increase in leakage current and deterioration of breakdown voltage, and suppress the current collapse phenomenon. .

JP2015-106627A

Various aspects of the present invention aim to provide a semiconductor device that can suppress an increase in leakage current and deterioration of breakdown voltage, as well as a current collapse phenomenon, by suppressing electric field concentration in an AlGaN layer.

Various aspects of the present invention will be explained below.

[1] An n-type GaN layer,
a first n-type AlGaN layer disposed on the n-type GaN layer;
a second n-type AlGaN layer disposed on the first n-type AlGaN layer;
a source electrode disposed on the first n-type AlGaN layer and located on one side of the second n-type AlGaN layer;
a drain electrode disposed on the first n-type AlGaN layer and located on the other side of the second n-type AlGaN layer;
a p-type AlGaN layer disposed on the second n-type AlGaN layer and located closer to the source electrode than the center on the second n-type AlGaN layer;
a gate electrode disposed on the p-type AlGaN layer;
A semiconductor device characterized by having:

[2] An n-type GaN layer,
an n-type AlGaN layer disposed on the n-type GaN layer;
a first p-type AlGaN layer disposed on the n-type AlGaN layer;
a source electrode disposed on the n-type AlGaN layer and located on one side of the first p-type AlGaN layer;
a drain electrode disposed on the n-type AlGaN layer and located on the other side of the first p-type AlGaN layer;
a second p-type AlGaN layer disposed on the first p-type AlGaN layer and located closer to the source electrode than the center on the first p-type AlGaN layer;
a gate electrode disposed on the second p-type AlGaN layer;
A semiconductor device characterized by having:

[3] In [1] above,
A semiconductor device characterized in that the second n-type AlGaN layer has a composition of Al _x Ga _1-X N, where x is 0.01 or more and 0.25 or less.

[4] In [1] or [3] above,
A semiconductor device characterized in that the second n-type AlGaN layer has an Al concentration of 5 atomic % or less.

[5] In [2] above,
A semiconductor device characterized in that the first p-type AlGaN layer has a composition of Al _x Ga _1-x N, where x is 0.01 or more and 0.25 or less.

[6] In [2] or [5] above,
A semiconductor device, wherein the first p-type AlGaN layer has an Al concentration of 5 atomic % or less.

[7] In any one of the above [1], [2], [3] and [5],
the n-type GaN layer is disposed on the buffer layer,
A semiconductor device, wherein the buffer layer is disposed on a substrate.

[8] In [7] above,
A semiconductor device, wherein the substrate is a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, or a Ga ₂ O ₃ substrate.

[9] In [1] above,
A semiconductor device, wherein each of the first n-type AlGaN layer, the second n-type AlGaN layer, and the p-type AlGaN layer has a thickness within a range of 1 nm or more and 60 nm or less.

[10] In [2] or [5] above,
A semiconductor device, wherein each of the n-type AlGaN layer, the first p-type AlGaN layer, and the second p-type AlGaN layer has a thickness within a range of 1 nm or more and 60 nm or less.

According to the semiconductor device of the above item [1] of the present invention, when the first n-type AlGaN layer 13 is stacked on the n-type GaN layer 12, lattice matching is achieved. In other words, the upper atomic arrangement matches the underlying atomic arrangement. Furthermore, since the second n-type AlGaN layer 21 is made of the same material as the first n-type AlGaN layer 13 underlying it in that it is AlGaN, lattice matching occurs when the second n-type AlGaN layer 21 is epitaxially grown. That is, during epitaxial growth, the lattice constants have good matching and distortion is less likely to occur, so surface defects and lattice defects are less likely to occur in the second n-type AlGa 21. This is thought to reduce leakage current when the transistor is off. At the same time, even if the electrons of the two-dimensional electron gas (2DEG), which is a current collapse phenomenon, move beyond the potential barrier to the first n-type AlGaN layer, they are captured by the surface defect level of the second n-type AlGaN layer. It is possible to prevent this from happening.

According to the semiconductor device according to item [2] of the present invention, since the first p-type AlGaN layer has p-type carriers, the balance when the transistor is turned off is improved, so that deterioration of breakdown voltage can be suppressed. Furthermore, since the first p-type AlGaN layer and the underlying n-type AlGaN layer are made of the same AlGaN material, lattice matching occurs when the first p-type AlGaN layer is epitaxially grown. That is, during epitaxial growth, the first p-type AlGaN layer is less likely to have surface defects or lattice defects because the lattice constants have good matching and strain is less likely to occur. This is thought to reduce leakage current when the transistor is off. At the same time, even if the electrons of the two-dimensional electron gas (2DEG), which is a current collapse phenomenon, cross the potential barrier and move to the n-type AlGaN layer, they are captured by the defect levels inherent in the first p-type AlGaN layer a. As a result, the current collapse phenomenon can be suppressed.

According to the semiconductor device of the above item [4] of the present invention, by setting the Al concentration of the second n-type AlGaN layer to 5 atomic % or less, drain-source leakage during off-time can be reduced.

According to the semiconductor device according to item [6] of the present invention, by setting the Al concentration of the first p-type AlGaN layer to 5 atomic % or less, drain-source leakage during off-time can be reduced.

Further, according to various aspects of the present invention, by suppressing electric field concentration in the AlGaN layer, it is possible to provide a semiconductor device in which increase in leakage current and deterioration of breakdown voltage can be suppressed, and current collapse phenomenon can be suppressed. .

1 is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the form and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

This semiconductor device includes an n-type GaN layer 12, a first n-type AlGaN layer 13 disposed on the n-type GaN layer 12, and a second n-type AlGaN layer 13 disposed on the first n-type AlGaN layer 13. an AlGaN layer 21, a source electrode 15 disposed on the first n-type AlGaN layer 13 and located on one side of the second n-type AlGaN layer 21, and a source electrode 15 disposed on the first n-type AlGaN layer 13; A drain electrode 16 located on the other side of the second n-type AlGaN layer 21 and a drain electrode 16 located on the second n-type AlGaN layer 21 and located on the source electrode 15 side from the center on the second n-type AlGaN layer 21. The gate electrode 18 includes a p-type AlGaN layer 22 and a gate electrode 18 disposed on the p-type AlGaN layer 22.

This will be explained in detail below.
The semiconductor device shown in FIG. 1 is a polarization junction GaN-based FET (Field Effect Transistor) as a HEMT (High Electron Mobility Transistor).
The polarization junction GaN-based FET has a substrate 10, which is preferably a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, or a Ga ₂ O ₃ substrate. A buffer layer 11 is formed on the substrate 10. This buffer layer 11 is called a superlattice structure (SLS), and may be formed of, for example, a GaN mixed crystal, so-called AlGaN, InGaN, AlInGaN, or a combination of a plurality thereof. An n-type GaN layer 12 is arranged on the buffer layer 11.

A first n-type AlGaN layer (n-AlGaN1) 13 is arranged on the n-type GaN layer (n-GaN) 12. The thickness of the first n-type AlGaN layer 13 is preferably 1 nm or more and 20 nm or less.

A second n-type AlGaN layer (n-AlGaN2) 21 is arranged on the first n-type AlGaN layer 13. The thickness of the second n-type AlGaN layer 21 is preferably 1 nm or more and 15 nm or less.

Each of the first and second n-type AlGaN layers 13 and 21 is made of TMA (trimethylaluminum: (CH?)?Al), which is a mixed gas containing Al atoms, and TMG (trimethylgallium: Ga(CH ₃ ) ₃ ). By introducing into the chamber, Ga atoms are replaced with Al atoms to form GaN. Note that when only TMG is introduced into the chamber, n-GaN grows.

By polarizing the first n-type AlGaN layer 13 due to the piezo effect, a positive polarization occurs in the first n-type AlGaN layer 13 near the interface between the n-type GaN layer 12 and the first n-type AlGaN layer 13. A fixed charge is induced, and a negative fixed charge is also induced in the first n-type AlGaN layer 13 in the vicinity of the interface between the first n-type AlGaN layer 13 and the second n-type AlGaN layer 21. . Therefore, a two-dimensional hole gas (2DHG) 30 is formed in the second n-type AlGaN layer 21 near the interface between the first n-type AlGaN layer 13 and the second n-type AlGaN layer 21, In addition, a two-dimensional electron gas (2DEG) 31 is formed in the n-type GaN layer 12 near the interface between the n-type GaN layer 12 and the first n-type AlGaN layer 13. The two-dimensional electron gas (2DEG) 31 becomes the channel of the transistor.

A source electrode (S) 15 is arranged on the first n-type AlGaN layer 13 , and this source electrode 15 is located on one side of the second n-type AlGaN layer 21 .

Further, a drain electrode (D) 16 is arranged on the first n-type AlGaN layer 13, and this drain electrode 16 is located on the other side of the second n-type AlGaN layer 21. Note that the source electrode 15 and the drain electrode 16 are preferably made of a laminated film in which a Ni film, an Au film, an Al film, etc. are laminated on a Ti film, for example.

A p-type AlGaN layer (p-AlGaN2) 22 is arranged on the second n-type AlGaN layer 21, and the p-type AlGaN layer 22 extends from the center on the second n-type AlGaN layer 21 toward the source electrode 15. positioned. The thickness of the p-type AlGaN layer 22 is preferably 1 nm or more and 20 nm or less.

The p-type AlGaN layer 22 contains TMA (trimethylaluminum: (CH?)?Al), which is a mixed gas containing Al atoms, as well as TMG (trimethylgallium: Ga(CH ₃ ) ₃ ) and Cp ₂ Mg gas (cyclopentadienyl). It is formed by introducing magnesium gas (C ₁₀ H ₁₀ Mg ₁₀ ) into the chamber.

A gate electrode (G) 18 is disposed on the p-type AlGaN layer 22, and the gate electrode 18 is preferably made of a laminated film in which another metal film is laminated on a Ni film, for example.

According to this embodiment, when the first n-type AlGaN layer 13 is stacked on the n-type GaN layer 12, lattice matching is achieved. In other words, the upper atomic arrangement matches the underlying atomic arrangement. Furthermore, since the second n-type AlGaN layer 21 is made of the same material as the first n-type AlGaN layer 13 underlying it in that it is AlGaN, lattice matching occurs when the second n-type AlGaN layer 21 is epitaxially grown. That is, during epitaxial growth, the lattice constants have good matching and strain is less likely to occur, so surface defects and lattice defects are less likely to occur in the second n-type AlGaN layer 21. This is thought to reduce leakage current when the transistor is off. At the same time, even if the electrons of the two-dimensional electron gas (2DEG) 31, which is a current collapse phenomenon, move to the first n-type AlGaN layer 13 over the potential barrier, the surface defect level of the second n-type AlGaN layer 21 It is possible to suppress the possibility of being captured in the same position.

The composition of the second n-type AlGaN layer 21 shown in FIG. 1 is Al _x Ga _1-x N, where x is preferably 0.01 or more and 0.25 or less. The reason why the Al composition is set in the range of 1 to 25% is that when the Al composition is small, the threshold voltage Vth shifts toward the positive side, which is one of the reasons why the device becomes a normally off N-off device. There are two main ways to turn it off: to reduce the Al composition as much as possible, or to reduce the thickness of the first p-type AlGaN film 21. In the case of a normally off N-off device, it is not necessarily sufficient to make both of them small, but it is preferable to strike a balance. It is thought that if both are made smaller, the amount of 2DEG will decrease, making it difficult to make contact with the first n-type AlGaN layer 13 and making it difficult to form the film thickness (crystal) of the first p-type AlGaN film 21. It will be done. "The film thickness (crystals) becomes difficult to form" means that the film thickness or crystals become such that the necessary physical properties do not function.

The Al concentration of the second n-type AlGaN layer 21 shown in FIG. 1 is preferably 5 atomic % or less. For example, when the composition of the second n-type AlGaN layer 21 is set to Al _0.05 Ga _0.95 N, drain-source leakage during off-state is reduced. The value of IDSS in normally-off devices becomes smaller.

Each of the first n-type AlGaN layer 13, the second n-type AlGaN layer 21, and the p-type AlGaN layer 22 preferably has a thickness within a range of 1 nm or more and 60 nm or less. The reasons why the thickness of the p-type AlGaN layer 22 is set in this range are (1) that it is necessary to have a sufficient amount of holes or electrons to form a p-type layer; (2) ) The thickness is necessary to prevent destruction due to electric field concentration, (3) The thickness is necessary to maintain a correlation with the underlying material to prevent warping and cracking, for example, if the underlying material is thin. However, if the top layer is too thick, warping and cracking will occur, so it is important to maintain a relationship with the underlying layer that can suppress the occurrence of such warping and cracking, and (4) the thickness required to maintain the necessary crystallinity. It is a matter of fact, etc.

A more preferable thickness of the first n-type AlGaN layer 13 is within the range of 1 nm or more and 25 nm or less. As the thickness of the first n-type AlGaN layer 13 becomes smaller, the amount of 2DEG decreases and the threshold voltage Vth shifts to positive, so it is preferably in the range of 1 nm or more and 25 nm or less.

A more preferable thickness of the second n-type AlGaN layer 21 is within the range of 1 nm or more and 30 nm or less. The reason for this is that the second n-type AlGaN layer 21 only needs to have a thickness that does not break due to electric field concentration and can maintain breakdown voltage, and the simulation results show that if the lower limit is 1 nm, it has the necessary functionality. The thickness must be such that it can be manufactured in terms of the manufacturing process.

(Second embodiment)
FIG. 2 is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention, and the same parts as in FIG. 1 are denoted by the same symbols.

This semiconductor device includes an n-type GaN layer 12a, an n-type AlGaN layer 13 disposed on the n-type GaN layer 12a, and a first p-type AlGaN layer 21a disposed on the n-type AlGaN layer 13. , a source electrode 15 disposed on the n-type AlGaN layer 13 and located on one side of the first p-type AlGaN layer 21a; and a source electrode 15 disposed on the n-type AlGaN layer 13 and located on one side of the first p-type AlGaN layer 21a; a drain electrode 16 located on the other side of the layer 21a, and a second electrode located on the first p-type AlGaN layer 21a and located closer to the source electrode 15 than the center on the first p-type AlGaN layer 21a. and a gate electrode 18 disposed on the second p-type AlGaN layer 22.

This will be explained in detail below.
The semiconductor device shown in FIG. 2 is a polarization junction GaN-based FET as a HEMT (high electron mobility transistor).
The polarization junction GaN-based FET has the same substrate 10 and buffer layer 11 as in the first embodiment. An n-type GaN layer 12a is arranged on the buffer layer 11.

An n-type AlGaN layer (n-AlGaN1) 13 is arranged on the n-type GaN layer (n-GaN) 12a. The thickness of the n-type AlGaN layer 13 is preferably 1 nm or more and 20 nm or less.
The methods of forming each of the n-type AlGaN layer 13 and the n-type GaN layer 12a are the same as in the first embodiment.

A first p-type AlGaN layer (p-AlGaN1) 21a is arranged on the n-type AlGaN layer 13. The thickness of the first p-type AlGaN layer 21a is preferably 1 nm or more and 15 nm or less.

By polarizing the n-type AlGaN layer 13 due to the piezo effect, a positive fixed charge is induced in the n-type AlGaN layer 13 near the interface between the n-type GaN layer 12a and the n-type AlGaN layer 13, and Negative fixed charges are induced in the n-type AlGaN layer 13 near the interface between the type AlGaN layer 13 and the first p-type AlGaN layer 21a. Therefore, two-dimensional hole gas (2DHG) 30 is formed in the first p-type AlGaN layer 21a near the interface between the n-type AlGaN layer 13 and the first p-type AlGaN layer 21a, and A two-dimensional electron gas (2DEG) 31 is formed in the n-type GaN layer 12a near the interface between the type GaN layer 12a and the n-type AlGaN layer 13. The two-dimensional electron gas (2DEG) 31 becomes the channel of the transistor.

A source electrode (S) 15 is arranged on the n-type AlGaN layer 13, and this source electrode 15 is located on one side of the first p-type AlGaN layer 21a.

Further, a drain electrode (D) 16 is arranged on the n-type AlGaN layer 13, and this drain electrode 16 is located on the other side of the first p-type AlGaN layer 21a. Note that the source electrode 15 and the drain electrode 16 are preferably made of a laminated film in which a Ni film, an Au film, an Al film, etc. are laminated on a Ti film, for example.

A second p-type AlGaN layer (p-AlGa2) 22 is arranged on the first p-type AlGaN layer 21a, and the second p-type AlGaN layer 22 is located at the center on the first p-type AlGaN layer 21a. It is located closer to the source electrode 15 side. The thickness of the second p-type AlGaN layer 22 is preferably 1 nm or more and 20 nm or less.
The method of forming each of the first p-type AlGaN layer 21a and the second p-type AlGaN layer 22 is the same as that of the p-type AlGaN layer 22 of the first embodiment.

A gate electrode (G) 18 is disposed on the second p-type AlGaN layer 22, and the gate electrode 18 is preferably made of a laminated film in which another metal film is laminated on a Ni film, for example.

According to this embodiment, since the first p-type AlGaN layer 21a has p-type carriers, the balance when the transistor is off is improved, so that deterioration of breakdown voltage can be suppressed. That is, it has a high breakdown voltage.

Moreover, since the first p-type AlGaN layer 21a is made of the same material as the n-type AlGaN layer 13 below it in that it is AlGaN, lattice matching occurs when the first p-type AlGaN layer 21a is epitaxially grown. That is, during epitaxial growth, since the lattice constants have good matching and strain is less likely to occur, surface defects and lattice defects are less likely to occur in the first p-type AlGaN layer 21a. This is thought to reduce leakage current when the transistor is off. At the same time, even if the electrons of the two-dimensional electron gas (2DEG) 31, which is a current collapse phenomenon, move beyond the potential barrier to the n-type AlGaN layer 13, the defect levels inherent in the first p-type AlGaN layer 21a It can prevent you from being captured.

In addition, by using the second n-type GaN layer in the polarization junction GaN-based FET of the prior art as the first p-type AlGaN layer 21a having p-type carriers in this embodiment, when the transistor is in the on state, the high Even if electrons of the two-dimensional electron gas (2DEG) 31 accelerated by voltage move to the n-type AlGaN layer 13 over the potential barrier, the electrons are neutralized with holes in the first p-type AlGaN layer 21a. Therefore, it is thought that it is possible to suppress the lower part of the n-type AlGaN layer 13 from being negatively charged. Therefore, depletion of electrons in the channel of the two-dimensional electron gas (2DEG) 31 directly under the n-type AlGaN layer 13 can be suppressed. As a result, it is possible to suppress an increase in channel resistance, a decrease in drain current, and an increase in on-resistance. Therefore, it becomes possible to suppress the current collapse phenomenon. In other words, the first p-type AlGaN layer 21a is considered to have a function of balancing the polarization due to the piezo effect of the n-type AlGaN layer 13. With the above explanation, a low-loss GaN-based FET can be realized.

The composition of the first p-type AlGaN layer 21a shown in FIG. 2 is Al _x Ga _1-x N, where x is preferably 0.01 or more and 0.25 or less. The reason why the Al composition is set in the range of 1 to 25% is that when the Al composition is small, the threshold voltage Vth shifts toward the positive side, which is one of the reasons why the device becomes a normally off N-off device. There are two main ways to turn it off: to reduce the Al composition as much as possible, or to reduce the thickness of the first p-type AlGaN film 21a. In the case of a normally off N-off device, it is not necessarily sufficient to make both of them small, but it is preferable to strike a balance. It is thought that if both are made smaller, the amount of 2DEG decreases, making it difficult to make contact with the n-type AlGaN layer 13 and making it difficult to form the film thickness (crystal) of the first p-type AlGaN film 21a. "The film thickness (crystals) becomes difficult to form" means that the film thickness or crystals become such that the necessary physical properties do not function.

The Al concentration of the first p-type AlGaN layer 21a shown in FIG. 2 is preferably 5 atomic % or less. For example, when the composition of the first n-type AlGaN layer 21a is set to Al _0.05 Ga _0.95 N, drain-source leakage during off-state is reduced. The value of IDSS in normally-off devices becomes smaller.

Each of the n-type AlGaN layer 13, the first p-type AlGaN layer 21a, and the second p-type AlGaN layer 22 preferably has a thickness within a range of 1 nm or more and 60 nm or less. The reason why the thickness of each of the first p-type AlGaN layer 21a and the second p-type AlGaN layer 22 is set in such a range is that (1) the amount of holes or electrons sufficient to form a p-type is (2) Thickness necessary to prevent damage due to electric field concentration; (3) Thickness necessary to maintain correlation with the underlying material to prevent warping and cracking. For example, if the base is thin and the top is thick, warping and cracks will occur, so it is important to maintain a correlation with the base that can suppress the occurrence of warps and cracks (4 ) The thickness is necessary to maintain the necessary crystallinity, etc.

A more preferable thickness of the n-type AlGaN layer 13 is 1 nm or more and 25 nm or less. As the thickness of the n-type AlGaN layer 13 becomes smaller, the amount of 2DEG decreases and the threshold voltage Vth shifts to the positive side, so a range of 1 nm or more and 25 nm or less is preferable.
A more preferable thickness of the first p-type AlGaN layer 21a is 1 nm or more and 30 nm or less.

10 Substrate 11 Buffer layer 12 N-type GaN layer (n-GaN)
12a n-type GaN layer 12a
13 First n-type AlGaN layer, n-type AlGaN layer (n-AlGaN1)
15 Source electrode (S)
16 Drain electrode (D)
18 Gate electrode (G)
21 Second n-type AlGaN layer (n-AlGaN2)
21a First p-type AlGaN layer (p-AlGaN1)
22 p-type AlGaN layer, second p-type AlGaN layer (p-AlGaN2)

Claims (10)

an n-type GaN layer;
a first n-type AlGaN layer disposed on the n-type GaN layer;
a second n-type AlGaN layer disposed on the first n-type AlGaN layer;
a source electrode disposed on the first n-type AlGaN layer and located on one side of the second n-type AlGaN layer;
a drain electrode disposed on the first n-type AlGaN layer and located on the other side of the second n-type AlGaN layer;
a p-type AlGaN layer disposed on the second n-type AlGaN layer and located closer to the source electrode than the center on the second n-type AlGaN layer;
a gate electrode disposed on the p-type AlGaN layer;
A semiconductor device characterized by having: an n-type GaN layer;
an n-type AlGaN layer disposed on the n-type GaN layer;
a first p-type AlGaN layer disposed on the n-type AlGaN layer;
a source electrode disposed on the n-type AlGaN layer and located on one side of the first p-type AlGaN layer;
a drain electrode disposed on the n-type AlGaN layer and located on the other side of the first p-type AlGaN layer;
a second p-type AlGaN layer disposed on the first p-type AlGaN layer and located closer to the source electrode than the center on the first p-type AlGaN layer;
a gate electrode disposed on the second p-type AlGaN layer;
A semiconductor device characterized by having: In claim 1,
A semiconductor device characterized in that the second n-type AlGaN layer has a composition of Al _x Ga _1-X N, where x is 0.01 or more and 0.25 or less. In claim 1 or 3,
A semiconductor device characterized in that the second n-type AlGaN layer has an Al concentration of 5 atomic % or less. In claim 2,
A semiconductor device characterized in that the first p-type AlGaN layer has a composition of Al _x Ga _1-x N, where x is 0.01 or more and 0.25 or less. In claim 2 or 5,
A semiconductor device, wherein the first p-type AlGaN layer has an Al concentration of 5 atomic % or less. In any one of claims 1, 2, 3 and 5,
the n-type GaN layer is disposed on the buffer layer,
A semiconductor device, wherein the buffer layer is disposed on a substrate. In claim 7,
A semiconductor device, wherein the substrate is a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, or a Ga ₂ O ₃ substrate. In claim 1 or 3,
A semiconductor device, wherein each of the first n-type AlGaN layer, the second n-type AlGaN layer, and the p-type AlGaN layer has a thickness within a range of 1 nm or more and 60 nm or less. In claim 2 or 5,
A semiconductor device, wherein each of the n-type AlGaN layer, the first p-type AlGaN layer, and the second p-type AlGaN layer has a thickness within a range of 1 nm or more and 60 nm or less.

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