JP2023161414A - Dc/dc converter - Google Patents

Abstract

To provide a technique of maintaining an average voltage of the charge/discharge capacitor at half the voltage at a high voltage end without measuring the voltage of the charge/discharge capacitor with regard to a switched capacitor type DC-DC converter having a reactor and the charge/discharge capacitor.SOLUTION: A converter has a series connection of two diodes and two switching elements. A charge/discharge capacitor is connected between a connection point of two diodes and a connection point of two switching elements. A controller is configured to (1) determine a duty of a gate signal to be provided to each switching element based on a target voltage ratio, and (2) correct the duty of at least one of the first and second switching elements so as to reduce difference between an amount of change in a reactor current while the first switching element is turned on and the second switching element is turned off and the amount of change while the first switching element is turned off and the second switching element is turned on.SELECTED DRAWING: Figure 1

Description

The technology disclosed in this specification relates to a switched capacitor type DC-DC converter using a reactor and a switching element. In particular, it relates to a DC-DC converter that includes a capacitor (charge/discharge capacitor) that assists the function of a reactor.

The above DC-DC converter is disclosed in Patent Document 1. The DC-DC converter disclosed in Patent Document 1 includes four switching elements, a reactor, and a charge/discharge capacitor. The four switching elements are connected in series between the high voltage end of the DC-DC converter and ground. For convenience of explanation, the four switching elements will be referred to as first, second, third, and fourth switching elements from the high voltage end side to the ground side.

The reactor is connected between the connection point of the second/third switching element and the low voltage end of the DC-DC converter. The charge/discharge capacitor is connected between the connection point of the first/second switching element and the connection point of the third/fourth switching element.

In the DC-DC converter disclosed in Patent Document 1, a charging/discharging capacitor assists the function of a reactor. By employing a charging/discharging capacitor, the voltage applied to the reactor can be reduced, and as a result, the reactor can be made smaller. In order to use the charge/discharge capacitor effectively, it is important to maintain the average voltage across the charge/discharge capacitor at half the voltage at the high voltage end. Therefore, the DC-DC converter of Patent Document 1 is equipped with a voltage sensor that measures the voltage of the charging/discharging capacitor, and the measured value of the voltage sensor is equal to the target voltage of the charging/discharging capacitor (half of the target voltage at the high voltage end). Feedback control is performed to follow. Hereinafter, for convenience of explanation, the voltage across the charging/discharging capacitor will be referred to as a capacitor voltage.

International Publication No. 2016/125682

The present specification provides a technique that can maintain the average capacitor voltage at half the voltage at the high voltage end in the above-mentioned DC-DC converter without measuring the voltage across the charging/discharging capacitor.

The DC-DC converter of Patent Document 1 has a step-up operation in which the voltage applied to the low voltage end is boosted and output from the high voltage end, and a voltage applied to the high voltage end is stepped down and output from the low voltage end. Both voltage step-down operations can be performed. That is, the DC-DC converter of Patent Document 1 is a so-called bidirectional DC-DC converter. The first/second switching elements contribute to the step-down operation, and the third/fourth switching elements contribute to the step-up operation. The technology disclosed in this specification can be applied to any of boost converters, buck converters, and bidirectional converters.

A first aspect of the DC-DC converter disclosed herein is a boost converter. The DC-DC converter consists of a high voltage end, a low voltage end, a ground, two diodes (first/second diodes), two switching elements (first/second switching elements), a reactor, and a charge/discharge capacitor. , a controller. The first diode, the second diode, the first switching element, and the second switching element are connected in series in this order from the high voltage end to the ground. The reactor is connected between the connection point between the second diode and the first switching element and the low voltage end. The charge/discharge capacitor is connected between a connection point between the first diode and the second diode and a connection point between the first switching element and the second switching element. The first diode and the second diode are connected so that current flows from the ground side to the high voltage end side.

A controller controls the first/second switching elements. The controller performs the following two processes. (1) The controller determines the duty of the gate signal given to each switching element based on the target voltage ratio (target value of the voltage ratio between the low voltage end and the high voltage end). (2) The controller determines the amount of change in reactor current while the first switching element is on and the second switching element is off, and the amount of change in reactor current while the first switching element is off and the second switching element is on. The duty of the gate signal of at least one of the first switching element and the second switching element is corrected so that the difference with the amount of change in the current becomes small.

By the process (2) above, the capacitor voltage is held at half the voltage at the high voltage end. In the above DC-DC converter, when the first switching element is on and the second switching element is off, current flows in the order of the reactor, the first switching element, the charging/discharging capacitor, the first diode, and the high voltage terminal. At this time, the charge/discharge capacitor discharges. For convenience of explanation, this state will be referred to as the first mode. Further, in the DC-DC converter, when the first switching element is off and the second switching element is on, current flows in the order of the reactor, the second diode, the charging/discharging capacitor, the second switching element, and the ground. At this time, the charging/discharging capacitor is charged. This state is called the second mode.

In the second mode, the charge/discharge capacitor is charged, and in the first mode, the charge/discharge capacitor is discharged. The voltage at the low voltage end is represented by the symbol VL, the voltage at the high voltage end is represented by the symbol VH, and the voltage applied to the reactor is represented by the symbol VR. Further, the capacitor voltage is represented by the symbol VC. In the first mode, VR=VL+VC-VH, and in the second mode, VR=VL-VC. Here, if the capacitor voltage VC is half of the high voltage end voltage VH, VR = (1/2) VH in both the first mode and the second mode, and the period of the first mode and the second mode are The amount of change in reactor current becomes equal during the period. Conversely, if the duty ratio of the switching element is adjusted so that the amount of change in the reactor current is equal between the first mode period and the second mode period, the average capacitor voltage VC will be half of the high voltage end voltage VH. is maintained.

The above DC-DC converter can maintain the average capacitor voltage at half the voltage at the high voltage end without having a voltage sensor that measures the voltage across the charging/discharging capacitor.

Note that in the case of boost operation, the input voltage (voltage on the low voltage end side) is known. Therefore, the "target voltage ratio" is equivalent to the "target voltage at the high voltage end" (="voltage applied to the low voltage end" x "target voltage ratio"). Therefore, the "target voltage ratio" may be rephrased as the "target voltage at the high voltage end."

In the above DC-DC converter, if the third switching element is connected in anti-parallel to the first diode and the fourth switching element is connected in anti-parallel to the second diode, it becomes a bidirectional DC-DC converter. Become. In the case of step-down operation, by correcting the duty so that the difference between the amount of change in reactor current in the first mode and the amount of change in reactor current in the second mode is small, the average capacitor voltage is equal to the voltage at the high voltage end. This reduces the voltage by half, realizing efficient step-down operation.

When the technology disclosed in this specification is applied to a step-down converter, the following configuration is achieved. The DC-DC converter includes a first switching element, a second switching element, a first diode, a second diode, a reactor, a charging/discharging capacitor, and a controller connected in series between a high voltage terminal and the ground. Be prepared. The first switching element, the second switching element, the first diode, and the second diode are connected in series in this order from the high voltage end toward the ground. The first/second diodes are connected so that current flows from the ground side to the high voltage end side. The reactor is connected between the low voltage end and the connection point between the second switching element and the first diode. The charging/discharging capacitor is connected between the connection point of the first/second switching element and the connection point of the first/second diode. The controller performs the following two processes. (1) The controller determines the duty of each gate signal based on the target voltage ratio between the low voltage end and the high voltage end. (2) The controller determines the amount of change in reactor current while the first switching element is on and the second switching element is off (first mode period), and the amount of change in the reactor current while the first switching element is off and the second switching element is off. The duty of the gate signal of at least one of the first switching element and the second switching element is corrected so that the difference with the amount of change in the reactor current while it is on (period of the second mode) is small. Through the process (2), the average capacitor voltage is maintained at half the voltage at the high voltage end, based on the same principle as in the step-up converter described above.

Details and further improvements of the technology disclosed in this specification will be explained in the following "Detailed Description of the Invention".

FIG. 2 is a circuit diagram of a DC-DC converter according to a first embodiment. FIG. 3 is a diagram showing a current path in a first mode. FIG. 7 is a diagram showing a current path in a second mode. FIG. 7 is a diagram showing a current path in a third mode. FIG. 7 is a diagram showing a current path in a fourth mode. 5 is a timing chart showing the relationship between switching operation and reactor current. This is an example of temporal changes in reactor voltage VR, reactor current IR, and capacitor voltage VC (when the reactor current changes in the first and second modes are balanced) This is another example of time changes in reactor voltage VR, reactor current IR, and capacitor voltage VC (when the amount of change in reactor current in the first/second mode is unbalanced) It is a timing chart of a switching operation when a fourth mode occurs. It is a control block diagram of a controller. This is another example of temporal changes in reactor voltage VR, reactor current IR, and capacitor voltage VC (when the sign of the amount of change in reactor current is reversed) FIG. 2 is a circuit diagram of a DC-DC converter according to a second embodiment. FIG. 7 is a diagram showing a current path in the first mode in the third embodiment. FIG. 7 is a diagram showing a current path in the second mode in the third embodiment. FIG. 7 is a diagram showing a current path in a third mode in a third embodiment. FIG. 7 is a diagram showing a current path in a fourth mode in a third embodiment. FIG. 3 is a circuit diagram of a DC-DC converter according to a third embodiment. FIG. 7 is a control block diagram of a controller of a DC-DC converter according to a third embodiment.

(First Embodiment) FIG. 1 shows a circuit diagram of a DC-DC converter 2 according to a first embodiment. Hereinafter, for convenience of explanation, "DC-DC converter" will be simply referred to as "converter." Converter 2 in FIG. 2 is a boost converter that can boost the voltage applied to low voltage terminal 3 (and ground 5) and output it from high voltage terminal 4 (and ground 5). In the example of FIG. 1, converter 2 boosts the voltage of power supply 90 connected to low voltage terminal 3 and supplies it to load 91 connected to high voltage terminal 4. The load 91 is, for example, an electric motor.

The converter 2 includes two diodes (a first diode 12a and a second diode 12b) connected in series between a high voltage terminal 4 and a ground 5, and two switching elements (a first switching element 11a and a second diode 12b). 2 switching elements 11b). When the two diodes are collectively referred to without distinction, they are referred to as diodes 12, and when the two switching elements are collectively referred to, they are referred to as the switching element 11. The two switching elements 11 are power conversion transistors. Transistors for power conversion are sometimes called power transistors.

Four semiconductor elements (two diodes 12 and two switching elements 11) are connected in series between high voltage terminal 4 and ground 5. The first diode 12a, the second diode 12b, the first switching element 11a, and the second switching element 11b are connected in this order from the high voltage terminal 4 side to the ground 5 side. The two diodes 12 are connected in such a direction that current flows from the ground 5 side to the high voltage end 4 side.

The two switching elements 11 allow current to flow from the high voltage end 4 side to the ground 5 side when on, and allow current to flow from the high voltage end 4 side to the ground 5 side when off. cut off the flow. A free wheel diode 18 is connected to each of the two switching elements 11, which always allows current to flow from the ground 5 side to the high voltage end 4 side, and always blocks current flow in the opposite direction. . The function of the free wheel diode 18 may be included in the switching element 11 in some cases.

Converter 2 further includes a reactor 15, a charging/discharging capacitor 16, and smoothing capacitors 6 and 7. The reactor 15 is connected between the connection point between the second diode 12b and the first switching element 11a and the low voltage end 3. The charging/discharging capacitor 16 is connected between the connection point of the first/second diodes 12a/12b and the connection point of the first/second switching elements 11a/11b. Smoothing capacitor 6 is connected between low voltage end 3 and ground 5, and smoothing capacitor 7 is connected between high voltage end 4 and ground 5.

Furthermore, converter 2 includes a current sensor 21 and voltage sensors 22 and 23. Current sensor 21 measures the current flowing through reactor 15. The voltage sensor 22 measures the voltage at the low voltage end 3, and the voltage sensor 23 measures the voltage at the high voltage end 4. Controller 100 of converter 2 obtains the voltage ratio between low voltage end 3 and high voltage end 4 from the measured values of voltage sensors 22 and 23. The controller 100 drives the two switching elements 11 so that the voltage ratio between the low voltage end 3 and the high voltage end 4 follows the target voltage ratio. Each switching element 11 is driven by a PWM signal having a predetermined duty. The PWM signal that drives the switching element 11 may be referred to as a gate signal in this specification.

The configuration and basic operation of the circuit shown in FIG. 1 are well known. The controller 100 generates a gate signal so that the voltage ratio between the voltage at the low voltage end 3 and the voltage at the high voltage end 4 follows the target voltage ratio. By employing a charging/discharging capacitor 16 that assists the function of the reactor 15, the DC-DC converter 2 can realize a large voltage ratio with a small reactor. Even if a smaller reactor (smaller inductance) is used, a booster circuit can be realized with the same amount of change in reactor current as in the configuration using only the reactor 15.

The states and current paths of the two switching elements 11 will be described with reference to FIGS. 2 to 5. In converter 2, four current paths are realized depending on the states of two switching elements 11. The four current paths are referred to as a first mode, a second mode, a third mode, and a fourth mode.

First mode (FIG. 2): In the first mode, the first switching element 11a is turned on and the second switching element 11b is turned off. In the first mode, the output current of the power supply 90 passes through the reactor 15, the first switching element 11a, the charge/discharge capacitor 16, and the first diode 12a, and reaches the high voltage terminal 4. In the second mode, which will be described later, energy is accumulated in the reactor 15 and electric charge is accumulated in the charging/discharging capacitor 16. Energy is stored in the reactor 15 in the third mode. In the first mode, the energy stored in the reactor 15 pushes up the voltage at the high voltage end 4, and the charge/discharge capacitor 16 discharges, further pushing up the voltage at the high voltage end 4.

Second mode (FIG. 3): In the second mode, the first switching element 11a is turned off and the second switching element 11b is turned on. In the second mode, the output current of the power supply 90 flows to the ground 5 (or the smoothing capacitor 6) through the reactor 15, the second diode 12b, the charging/discharging capacitor 16, and the second switching element 11b. In the second mode, the current flows to the lower voltage ground 5. At this time, the charging/discharging capacitor 16 is charged.

Although details will be described later, in the second mode, depending on the voltage of the charging/discharging capacitor 16, energy may be stored in the reactor 15 or energy may be released from the reactor 15. If the potential of the charging/discharging capacitor 16 is lower than the potential of the reactor 15, energy is also stored in the reactor 15 in the second mode. If the potential of the charging/discharging capacitor 16 is higher than the potential of the reactor 15, a current is pushed out to the charging/discharging capacitor 16 by the energy of the reactor 15 in the second mode. As a result, the energy of the reactor 15 decreases.

Third mode (FIG. 4): In the third mode, the first/second switching elements 11a/11b are turned on. In the third mode, the output current of the power supply 90 flows to the ground 5 (or smoothing capacitor 6) through the reactor 15, the first switching element 11a, and the second switching element 11b. Even in the third mode, current flows from the reactor 15 to the ground 5, and at this time, energy is stored in the reactor 15.

Fourth mode (FIG. 5): In the fourth mode, the first/second switching elements 11a/11b are turned off. In the fourth mode, the output current of the power supply 90 passes through the reactor 15 and the first/second diodes 12a/12b and reaches the high voltage terminal 4. The energy stored in the reactor 15 in the second mode or the third mode pushes a current toward the high voltage end 4, and the voltage at the high voltage end 4 increases.

Either the third mode or the fourth mode is realized depending on the duty of the gate signal. That is, the converter 2 repeats the first/third/second/third modes in this order, or repeats the first/fourth/second/fourth modes in this order. Which pattern appears depends on the duty.

FIG. 6 shows an example of the relationship between the switching operations of the two switching elements 11 and the reactor current IR. FIG. 6 shows patterns of first/third/second/third modes. Symbols SW1/SW2 in the figure mean first/second switching elements, respectively.

The first switching element 11a is turned on at time T1, and the first switching element 11a is turned off at time T4. The time from time T1 to time T4 corresponds to duty D1 of the first switching element 11a. The duty D1 corresponds to the on time of the first switching element 11a.

The second switching element 11b is kept on until time T2. The second switching element 11b is turned off at time T2. The second switching element 11b remains off from time T2 to time T3. The second switching element 11b is turned on at time T3 and turned off at time T6. The time from time T3 to time T6 corresponds to duty D2 of the second switching element 11b. Duty D2 corresponds to the on time of the second switching element 11b.

The first switching element 11a is kept off from time T4 to time T5, and is turned on again at time T5. The second switching element 11b is kept off from time T6 to time T7, and is turned on again at time T7. After that, the same pattern is repeated.

During the period from time T2 to time T3, the first switching element 11a is on and the second switching element 11b is off. This period corresponds to the first mode. Between time T4 and time T5, the first switching element 11a is off and the second switching element 11b is on. This period corresponds to the second mode. Both the first and second switching elements 11a/11b are turned on from time T1 to time T2, from time T3 to time T4, from time T5 to time T6, and from time T7 to time T8. These periods correspond to the third mode.

As mentioned above, in the first mode, the energy of the reactor 15 is released. Therefore, in the first mode, reactor current IR decreases. In FIG. 6, the amount of change in reactor current IR in the first mode is represented by the symbol dI1 (amount of change in reactor current dI1).

In the third mode following the first mode, one end of the reactor 15 (the end on the switching element side) is directly connected to the ground 5, so a current flows through the reactor 15 at once and energy is accumulated. Therefore, reactor current IR increases during the third mode.

In the example of FIG. 6, in the second mode, the energy of the reactor 15 is used to charge the charging/discharging capacitor 16. Therefore, the reactor current IR also decreases between time T3 and time T4. In FIG. 6, the amount of change in reactor current IR in the second mode is represented by the symbol dI2 (amount of change in reactor current dI2).

FIG. 6 shows an ideal state in which the duty D1 for the first switching element 11a and the duty D2 for the second switching element 11b are equal, and the amount of change dI1 in the reactor current in the first mode and the amount of change in the second mode dI2 are equal (the amount of change in reactor current dI1 and dI2 are balanced). The relationship between the reactor current/voltage and the voltage of the charge/discharge capacitor 16 at this time is shown in FIG. The voltage of the charging/discharging capacitor 16 is represented by the symbol VC (capacitor voltage VC).

As shown in FIG. 7, in an ideal state, the amount of change dI1 in the reactor current in the first mode (the mode in which the charging/discharging capacitor 16 is discharged) and the amount of change dI1 in the reactor current in the second mode (the mode in which the charging/discharging capacitor 16 is charged) The amount of change dI2 in the reactor current is balanced. At this time, the capacitor voltage VC fluctuates due to charging and discharging, but the average thereof is equal to 1/2 of the high voltage end voltage VH. Although the high voltage end voltage VH is shown as 600 [V] in FIG. 7, this is just an example, and the high voltage end voltage VH depends on the characteristics of the converter 2 and the output voltage of the power supply 90.

FIG. 8 shows an example of changes over time in the capacitor voltage, etc. when the amount of change dI1 in the reactor current in the first mode and the amount of change dI2 in the second mode are unbalanced. Hereinafter, the amount of change dI1/dI2 in the reactor current may be simply expressed as the amount of current change dI1/dI2.

FIG. 8 shows a case where the amount of current change dI1 in the first mode (during capacitor discharging) is larger than the amount of current change dI2 in the second mode (during capacitor charging). Since the amount of current change dI1 in the first mode (when discharging the capacitor) is larger than the amount of change in reactor current dI2 in the second mode (when charging the capacitor), the capacitor voltage VC becomes low. At this time, the average of the capacitor voltage VC becomes lower than half of the high voltage end voltage VH. In this case, in order to match the charge balance of the charging/discharging capacitor 16, a current flows to the capacitor voltage VC in the third mode.

Conversely, when the amount of current change dI2 in the second mode is larger than the amount of current change dI1 in the first mode, the average of the capacitor voltage VC becomes larger than half of the high voltage end voltage VH. In this case, in order to match the charge balance of the charging/discharging capacitor 16, a current flows from the capacitor voltage VC to the ground 5 in the third mode.

In this way, when the current variation amounts dI1 and dI2 in the reactor 15 are unbalanced, a current flows to the charging/discharging capacitor 16 in the third mode. The current at this time has a larger peak value (amount of change in current) than during balance, and loss increases accordingly. That is, the voltage conversion efficiency of converter 2 decreases. In other words, the voltage conversion efficiency of the converter 2 is maximized when the reactor current changes dI1 and dI2 are equal. If the gate signals of the first/second switching elements 11a and 11b are generated so that the current change amounts dI1 and dI2 are equal, the loss of the converter 2 is reduced and efficient boosting operation is realized.

In the case of FIG. 6, when the duty D1 of the first switching element 11a is increased, the period of the second mode is shortened. The period of the first mode is relatively longer than the period of the second mode. The relatively longer period of the first mode means that the discharge period of the charging/discharging capacitor 16 becomes longer. When the duty D of the second switching element 11b is increased, the period of the first mode becomes shorter. The period of the second mode is relatively longer than the period of the first mode. A longer period of the second mode means that the charging time of the charging/discharging capacitor 16 becomes longer. In this way, there is a certain relationship (proportional relationship) between the duty of the first/second switching element 11a/11b and the charging/discharging time in the first/second mode.

In the case of the example in FIG. 6, when the current change amount dI1 is larger than the current change amount dI2, the difference between the current change amounts dI1 and dI2 becomes smaller by decreasing the duty D1 or increasing the duty D2. Conversely, when the current change amount dI1 is smaller than the current change amount dI2, the difference between the current change amounts dI1 and dI2 becomes smaller by increasing the duty D1 or decreasing the duty D2. In this way, in order to reduce the difference between the current variation amounts dI1 and dI2, it is sufficient to adjust at least one of the duties D1 and D2.

In the example of FIG. 6, there is a state in which the first and second switching elements 11a and 11b are both on (third mode), but a state in which both the first and second switching elements 11a and 11b are off (in the case of FIG. 4th mode) does not exist. If the duties D1/D2 of the first/second switching elements 11a and 11b are both small, a fourth mode period occurs. FIG. 9 shows a timing chart of the switching elements when the fourth mode exists.

In the example of FIG. 9, the first switching element 11a is turned on during the period from time T1 to time T2 and from time T5 to time T6. In other periods, the first switching element 11a is off. on the other hand. The second switching element 11b is off during the period from time T3 to time T4 and from time T7 to time T8, and the second switching element 11b is off during the other periods.

During the period from time T1 to time T2 and from time T5 to time T6, the first switching element 11a is on and the second switching element 11b is off. That is, these periods correspond to the first mode. During the period from time T3 to time T4 and from time T7 to time T8, the first switching element 11a is turned off and the second switching element 11b is turned on. These periods correspond to the second mode.

In the period from time T2 to time T3, the period from time T4 to time T5, and the period from time T6 to time T7, both the first and second switching elements 11a and 11b are turned off. These periods correspond to the fourth mode (see FIG. 5). In the example of FIG. 9, the period of the first mode corresponds to the duty D1 of the first switching element 11a, and the period of the second mode corresponds to the duty D2 of the second switching element 11b.

Although illustration is omitted, in the example of FIG. 9 as well, the charge/discharge capacitor 16 is discharged during the first mode period, and the charge/discharge capacitor 16 is charged during the second mode period. If the duty D1 of the first switching element 11a is lengthened, the time for discharging the charge/discharge capacitor 16 will be lengthened, and if the duty D2 of the second switching element 11b is lengthened, the time for charging the charge/discharge capacitor 16 will be lengthened.

Even in the case of the example in FIG. 9, if the current change amount dI1 is larger than the current change amount dI2, the difference between the current change amounts dI1 and dI2 becomes smaller by decreasing the duty D1 or increasing the duty D2. Conversely, when the current change amount dI1 is smaller than the current change amount dI2, the difference between the current change amounts dI1 and dI2 becomes smaller by increasing the duty D1 or decreasing the duty D2. In this way, in order to reduce the difference between the current variation amounts dI1 and dI2, it is sufficient to adjust at least one of the duties D1 and D2.

The controller 100 can reduce the difference between the amount of current change dI1 of the reactor in the first mode and the amount of current change dI2 in the second mode by performing the following process. That is, controller 100 can operate converter 2 with high voltage conversion efficiency by performing the following processing.

(1) The controller 100 determines the duty of each gate signal based on the target voltage ratio of the voltage at the low voltage end 3 and the voltage at the high voltage end 4. (2) The controller 100 determines the amount of change dI1 in the reactor current while the first switching element 11a is on and the second switching element 11b is off (first mode period), and the amount of change dI1 in the reactor current when the first switching element 11a is off and the second switching element 11b is off (first mode period). The duty of the gate signal of at least one of the first switching element 11a and the second switching element 11b is set so that the difference with the amount of change dI2 of the reactor current while the second switching element 11b is on (second mode period) is small. Correct.

By performing the processes (1) and (2) above, converter 2 can efficiently convert voltage. Note that a known control law may be employed to determine the duty of the first/second switching elements 11a/11b so that the target voltage ratio is achieved.

FIG. 10 shows a block diagram of an example of a controller 100 that implements the processes (1) and (2) above. The symbol VHref in FIG. 10 is the target voltage of the high voltage end 4. The target voltage VHref of the high voltage end 4 is expressed as “VHref=VL×Vratio” using the voltage VL of the low voltage end 3 and the target voltage ratio Vratio of the converter 2. That is, target voltage VHref is substantially equivalent to target voltage ratio Vratio of converter 2.

The actual high voltage end voltage VH is measured by the voltage sensor 23. The difference calculator 101 calculates the difference (voltage difference) between the target voltage VHref and the actual high voltage end voltage VH. The target voltage VHref and the voltage difference are input to the first control block 102 which derives the target duty Dt. The target voltage VHref is inputted to the first control block 102 as a feedforward value, and the voltage difference (VHref−VH) is inputted as a feedback value.

The first control block 102 calculates the target duty Dt according to conventional control rules such as PI control and PID control. The target duty Dt is added to a duty offset Doff (described later) by an adder 107. The target duty Dt to which the duty offset Doff is added is referred to as the first post-correction duty Dtm1. The first corrected duty Dtm1 is input to the comparator 105. The first carrier signal output from the first carrier generator 104 is also input to the comparator 105 . The comparator 105 outputs the comparison result between the first corrected duty Dtm1 and the first carrier signal as the gate signal GS1 of the first switching element 11a. This gate signal GS1 includes the aforementioned duty D1 (a parameter that specifies the ON time of the first switching element 11a).

On the other hand, the subtracter 117 subtracts the duty offset Doff from the target duty Dt. The target duty Dt with the duty offset Doff subtracted is referred to as a second post-correction duty Dtm2. The second corrected duty Dtm2 is input to the comparator 115. The second carrier signal output from the second carrier generator 114 is also input to the comparator 115 . Note that the second carrier signal is an inverted version of the first carrier signal. The comparator 115 outputs the comparison result between the second corrected duty Dtm2 and the second carrier signal as the gate signal GS2 of the second switching element 11b. The gate signal GS2 includes the aforementioned duty D2 (a parameter that specifies the on-time of the second switching element 11b).

The offset generation module 120 will be explained. The offset generation module 120 generates the duty offset Doff described above. The reactor current IR measured by the current sensor 21 is input to the change amount acquisition section 121. The gate signals of the first/second switching elements 11a/11b are also input to the change amount acquisition unit 121.

As shown in FIGS. 6 and 9, the period of the first mode and the period of the second mode are specified from the switching time charts (ie, gate signals) of the first/second switching elements 11a/11b. The change amount acquisition unit 121 identifies the periods of the first mode and the second mode from the gate signal, and identifies the amount of current change dI1/dI2 in each period from the data of the measurement value of the current sensor 21 during those periods. .

The current change amount dI1/dT2 is sent to the second control block 122. In the second control block 122, a duty offset Doff is calculated based on the difference between the amount of current change dI1/dT2. Most simply, the duty offset Doff may be a value obtained by multiplying the difference between the current change amounts dI1/dI2 by a gain. The second control block 122 may also calculate the duty offset Doff using the PI control law, PID control law, etc. for the difference between the current change amount dI1/dT2.

As described above, the duty offset Doff is added to the target duty Dt by the adder 107 and subtracted from the target duty Dt by the subtracter 117.

The points of the control block in FIG. 10 will be explained. For convenience of explanation, the gate signal for the first switching element 11a will be referred to as a first gate signal, and the gate signal for the second switching element 11b will be referred to as a second gate signal.

A signal obtained by inverting the first carrier signal is the second carrier signal. When there is no duty offset Doff, the comparison result between the target duty Dt and the first carrier signal becomes the first gate signal, and the comparison result between the target duty Dt and the second carrier signal becomes the second gate signal. That is, if there is no duty offset Doff, the first gate signal and the second gate signal have the same duty and a phase difference of 180 degrees.

Before the duty is compared with the carrier signal, the first gate signal adds the duty offset Doff to the target duty Dt, and the second gate signal subtracts the duty offset Doff from the target duty Dt. With this process, when the duty of the first gate signal increases due to the duty offset Doff, the duty of the second gate signal decreases. Conversely, when the duty of the first gate signal becomes smaller due to the duty offset Doff, the duty of the second gate signal becomes larger. With this process, the difference between the amount of change dI1/dI2 in the reactor current can be reduced without changing the total duty of the first gate signal and the second gate signal. Since the total duty of the first gate signal and the second gate signal does not change, the voltage ratio of the converter 2 is maintained.

Note that the first gate signal may be generated only with the target duty Dt, and only the second gate signal may be generated by adding or subtracting the duty offset Doff to the target duty Dt. Alternatively, the second gate signal may be generated using only the target duty Dt, and the duty offset Doff may be added to or subtracted from the target duty Dt only for the first gate signal.
That is, the controller 100 corrects the duty of the gate signal of at least one of the first switching element 11a and the second switching element 11b so that the difference between the current differences dI1/dI2 becomes smaller. In this case, although the realized voltage ratio fluctuates somewhat, due to the feedback effect of the first control block 102, the actual voltage ratio converges to the target voltage ratio.

As explained above, the converter 2 of the first embodiment can maintain the average of the capacitor voltage VC at half of the voltage VH at the high voltage end 4 without measuring the capacitor voltage VC.

It will be explained that in the second mode, the sign of the amount of change dI2 in the reactor current may be reversed. As described above, in the second mode, depending on the voltage of the charging/discharging capacitor 16, energy may be stored in the reactor 15 or energy may be released from the reactor 15. In the case of FIG. 8, the potential of the charging/discharging capacitor 16 is higher than the potential of the reactor 15. As a result, in the second mode, the energy of the reactor 15 pushes a current toward the charging/discharging capacitor 16. In the second mode, the reactor current decreases.

FIG. 11 shows changes in voltage/current of the reactor when the potential of the reactor 15 is higher than the potential of the charging/discharging capacitor 16 in the second mode. In the example of FIG. 11, the reactor voltage takes a positive value during the entire period of the second mode. As a result, the reactor current increases in the second mode. In the example of FIG. 11, the increase and decrease of the reactor current is opposite to that of the example of FIG.

The magnitude relationship of the reactor current at the start and end of the second mode may be reversed. Therefore, when calculating the difference between the amount of change dI1 in the reactor current during the period of the first mode and the amount of change dI2 during the period of the second mode, the absolute value of the amount of change is not used, but the amount of change including the positive and negative signs is calculated. Calculate the difference based on.

(Second Embodiment) FIG. 12 shows a DC-DC converter (converter 2a) of a second embodiment. Converter 2a is a step-down converter. A power source 90 is connected to the high voltage end 4, and a load 91 is connected to the low voltage end 3. Converter 2 a steps down the voltage applied to high voltage terminal 4 and outputs it from low voltage terminal 3 .

The converter 2a corresponds to a configuration in which the first/second switching elements 11a/11b and the first/second diodes 12a/12b of the converter 2 of the first embodiment are replaced. In FIG. 12, the switching elements connected between one end of the reactor 15 and the high voltage end 4 are referred to as a first switching element 11a and a second switching element 11b. Further, the diodes connected between one end of the reactor 15 and the ground 5 are referred to as a first diode 12a and a second diode 12b.

The features of converter 2a will be explained below. The converter 2a includes a low voltage end 3, a high voltage end 4, a ground 5, first/second switching elements 11a/11b, first/second diodes 12a/12b, a reactor 15, a charging/discharging capacitor 16, and a controller 100. . The first/second switching elements 11a/11b and the first/second diodes 12a/12b are connected in series in this order from the high voltage terminal 4 toward the ground 5. The first/second diodes 12a and 12b are connected so that current flows from the ground 5 side to the high voltage end 4 side. The first/second switching elements 11a/11b allow current to flow from the high voltage end 4 side to the ground 5 side when turned on. The first/second switching elements 11a/11b cut off current flowing from the high voltage terminal 4 side to the ground 5 side when turned off. A free wheel diode 18 is connected in antiparallel to each of the first/second switching elements 11a/11b.

The reactor 15 is connected between the connection point between the second switching element 11b and the first diode 12a and the low voltage end 3. The charging/discharging capacitor 16 is connected between the connection point of the first/second switching element 11a/11b and the connection point of the first/second diode 12a/12b. The controller 100 generates gate signals to be applied to each of the first switching element 11a and the second switching element 11b. The controller 100 executes the following process. (1) The controller 100 determines the duty of each gate signal based on the target voltage ratio of the voltage at the low voltage end 3 and the voltage at the high voltage end 4. (2) The controller 100 determines the amount of change dI1 in the reactor current while the first switching element 11a is on and the second switching element 11b is off (first mode), and the amount of change dI1 in the reactor current while the first switching element 11a is off and the second switching element 11b is off (first mode). The duty of the gate signal of at least one of the first/second switching elements 11a/11b is corrected so that the difference with the amount of change dI2 of the reactor current while the switching element 11b is on (second mode) is small. .

FIG. 13 shows the current path in the first mode. The first mode is a state when the first switching element 11a is on and the second switching element 11b is off. In the first mode of step-down operation, the output current of the power supply 90 passes through the first switching element 11a, the charging/discharging capacitor 16, the first diode 12a, and the reactor 15, and reaches the low voltage terminal 3. At this time, the charging/discharging capacitor 16 is charged. Energy is also accumulated in the reactor 15.

FIG. 14 shows the current path in the second mode. The second mode is a state when the first switching element 11a is off and the second switching element 11b is on. In the second mode of step-down operation, the current discharged from the charging/discharging capacitor 16 passes through the second switching element 11b and the reactor 15 and reaches the low voltage terminal 3. At this time, the charging/discharging capacitor 16 is discharged. Further, the reactor 15 may release energy, or may accumulate energy by discharging the charging/discharging capacitor 16.

FIG. 15 shows the current path in the third mode. The third mode is a state when both the first and second switching elements 11a/11b are on. In the third mode of step-down operation, the output current of the power supply 90 passes through the first/second switching elements 11a/11b and the reactor 15, and reaches the low voltage terminal 3. At this time, energy is stored in the reactor 15 by the power of the power source 90.

FIG. 16 shows the current path in the fourth mode. The fourth mode is a state when both the first and second switching elements 11a/11b are off. In the fourth mode of step-down operation, the power supply 90 is completely cut off from the low voltage terminal 3. At this time, an induced electromotive force is generated by the energy of the reactor 15, and a current flows from the reactor 15 to the low voltage end 3.

In the case of step-down operation, the charge/discharge capacitor 16 is charged in the first mode, and discharged in the second mode. If the amount of change in reactor current dI1 in the first mode is equal to the amount of change in reactor current dI2 in the second mode, the amount of charge of the charge/discharge capacitor 16 in the first mode and the amount of discharge of the charge/discharge capacitor 16 in the second mode are equal. be equal. As a result, the amount of current change generated in the reactor 15 is minimized. That is, voltage is converted most efficiently.

(Third Embodiment) FIG. 17 shows a circuit diagram of a DC-DC converter 2b (converter 2b) of a third embodiment. The converter 2b has a configuration in which a third switching element 11c and a fourth switching element 11d are added to the converter 2 of the first embodiment. The third switching element 11c is connected in antiparallel to the first diode 12a, and the fourth switching element 11d is connected in antiparallel to the second diode 12b. In other words, the third/fourth switching elements 11c/11d allow current to flow from the high voltage end 4 side to the ground 5 side when they are on, and from the high voltage end 4 side to the ground when they are off. The current flowing to the side of 5 is cut off.

Note that the first diode 12a and the third switching element 11c may be realized by one semiconductor element. Similarly, the second diode 12b and the fourth switching element 11d may be realized by one semiconductor element.

Controller 200 of converter 2b generates gate signals for first/second switching elements 11a/11b, as in the first embodiment. The controller 200 generates a signal obtained by inverting the gate signal of the first switching element 11a as a gate signal of the fourth switching element 11d. Further, the controller 200 generates a signal obtained by inverting the gate signal of the second switching element 11b as the gate signal of the third switching element 11c.

Converter 2b is a so-called bidirectional DC-DC converter. The converter 2b automatically switches between boost operation and step-down operation depending on the target voltage ratio of the voltage at the low voltage end 3 and the voltage at the high voltage end 4, and the realized voltage ratio. If the actual voltage ratio is lower than the target voltage ratio, converter 2b operates to increase the voltage at the high voltage end (that is, a step-up operation is performed). If the actual voltage ratio is higher than the target voltage ratio, converter 2b operates to increase the voltage at the low voltage end (that is, a step-down operation is performed). Converter 2b is employed, for example, in electric vehicles. A battery 90 is connected to the low voltage end 3, a DC end of an inverter is connected to the high voltage end 4, and an electric motor for running is connected to the AC end of the inverter. That is, the load 91 in FIG. 17 is an electric motor.

When accelerating the automobile, the output voltage of the battery 90 is boosted and output from the high voltage terminal 4. During deceleration, the motor generates regenerative power. The regenerated power (alternating current) generated by the motor is converted into direct current by an inverter and applied to the high voltage end 4 of converter 2b. At this time, the ratio between the voltage at the low voltage end 3 (voltage of the battery 90) and the voltage at the high voltage end 4 becomes larger than the target voltage ratio. In this case, converter 2 b steps down the voltage (regenerated power voltage) applied to high voltage end 4 and outputs it from low voltage end 3 . The battery 90 is charged with the voltage output from the low voltage terminal 3.

The converter 2b adjusts the gate signals of the first to fourth switching elements 11a to 11d so that the difference between the amount of change dI1 in the reactor current in the first mode and the amount of change dI2 in the second mode becomes small both during step-up and step-down. Determine the duty of As a result, in converter 2a, the average of capacitor voltage VC is maintained at half of voltage VH at high voltage end 4, and the loss in converter 2b is reduced. The way the current flows during the step-down operation is as described in the second embodiment.

FIG. 18 shows a control block diagram of the controller 200 of the converter 2b of the third embodiment. The controller 200 is obtained by adding a multiplier 223 and inverters 206 and 216 to the controller 100 (see FIG. 10) of the converter 2 of the first embodiment.

Multiplier 223 multiplies duty offset Doff by a positive or negative sign depending on the direction of reactor current IR. For example, when a current flowing from the low voltage end 3 to the reactor 15 is defined as a positive value, and a current in the opposite direction (direction from the reactor 15 to the low voltage end 3) is defined as a negative value, the current flows from the reactor 15 to the low voltage end. 3, the multiplier 223 inverts the sign of the duty offset Doff. This is because, as mentioned earlier, in the case of step-up operation, the charge/discharge capacitor 16 is discharged in the first mode and charged in the second mode, whereas in the case of step-down operation, the charge/discharge capacitor 16 is charged. This is because the discharge is reversed. That is, in the case of voltage step-down operation, the charging/discharging capacitor 16 is charged in the first mode, and the charging/discharging capacitor 16 is discharged in the second mode.

The inverter 206 inverts the gate signal GS1 for the first switching element 11a. A signal obtained by inverting the gate signal GS1 becomes the gate signal GS4 for the fourth switching element 11d. The inverter 216 inverts the gate signal GS2 for the second switching element 11b. A signal obtained by inverting the gate signal GS2 becomes the gate signal GS4 for the third switching element 11c.

Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of the objectives has technical utility in itself.

2, 2a, 2b: DC-DC converter 3: Low voltage end 4: High voltage end 5: Ground 6, 7: Smoothing capacitor 11a-11d: Switching element 12a, 12b: Diode 15: Reactor 16: Charge/discharge capacitor 18: Freewheeling diode 21: Current sensor 22, 23: Voltage sensor 90: Power source (battery) 91: Load 100, 200: Controller 101: Differentiator 102: First control block 104, 114: Carrier generator 105, 115: Comparator 107 : Adder 117: Subtractor 120: Offset generation module 121: Change amount acquisition unit 122: Second control block 223: Multiplier 206, 216: Inverter

Claims (3)

low voltage end,
high voltage end,
Grand and
A first diode, a second diode, a first switching element, and a second switching element are connected in series between the high voltage end and the ground, and are connected in this order from the high voltage end to the ground. A first diode, a second diode, a first switching element, a second switching element,
a reactor connected between a connection point between the second diode and the first switching element and a low voltage end;
a charging/discharging capacitor connected between a connection point between the first diode and the second diode and a connection point between the first switching element and the second switching element;
a controller that generates a gate signal to be applied to each of the first switching element and the second switching element;
It is equipped with
The first diode and the second diode are connected so that a current flows from the ground side to the high voltage end side,
The controller includes:
(1) determining the duty of each gate signal based on a target voltage ratio of the voltage at the low voltage end and the voltage at the high voltage end;
(2) The amount of change in the reactor current flowing through the reactor while the first switching element is on and the second switching element is off, and the amount of change in the reactor current flowing through the reactor while the first switching element is off and the second switching element is on. The DC-DC converter corrects a duty of a gate signal of at least one of the first switching element and the second switching element so that a difference between the amount of change in the reactor current and the amount of change in the reactor current during the current switching is reduced. The DC-DC converter according to claim 1, further comprising a third switching element connected in antiparallel to the first diode, and a fourth switching element connected in antiparallel to the second diode. . low voltage end,
high voltage end,
Grand and
A first switching element, a second switching element, a first diode, and a second diode are connected in series between the high voltage end and the ground, and are connected in this order from the high voltage end to the ground. A first switching element, a second switching element, a first diode, a second diode,
a reactor connected between a connection point between the second switching element and the first diode and a low voltage end;
a charging/discharging capacitor connected between a connection point between the first switching element and the second switching element and a connection point between the first diode and the second diode;
a controller that generates a gate signal to be applied to each of the first switching element and the second switching element;
It is equipped with
The first diode and the second diode are connected so that a current flows from the ground side to the high voltage end side,
The controller includes:
(1) determining the duty of each gate signal based on a target voltage ratio of the voltage at the low voltage end and the voltage at the high voltage end;
(2) The amount of change in the reactor current flowing through the reactor while the first switching element is on and the second switching element is off, and the amount of change in the reactor current flowing through the reactor while the first switching element is off and the second switching element is on. The DC-DC converter corrects a duty of a gate signal of at least one of the first switching element and the second switching element so that a difference between the amount of change in the reactor current and the amount of change in the reactor current during the current switching is reduced.

Images