JP2023150807A - Method for measuring thermal resistance of semiconductor element and device for measuring thermal resistance of semiconductor element - Google Patents

Abstract

To provide a method for measuring the thermal resistance of a semiconductor element and a device for measuring the thermal resistance of a semiconductor element with which it is possible to measure the thermal resistance of each of a plurality of semiconductor elements.SOLUTION: The method for measuring the thermal resistance of a semiconductor element comprises a first thermal resistance measurement process (step S11) in which an Si-FET 113 provided to a semiconductor module 11 is controlled to an unsaturated state and a GaN-FET 111 provided to the semiconductor module 11 and connected in series to the Si-FET 113 is controlled to a saturated state, and the thermal resistance of the Si-FET 113 is measured; and a second thermal resistance measurement process (step S15) in which the Si-FET 113 and the GaN-FET 111 are controlled to a saturate state, and the thermal resistance of the GaN-FET 111 is measured.SELECTED DRAWING: Figure 4

Description

The present invention relates to a method for measuring thermal resistance of a semiconductor element and an apparatus for measuring thermal resistance of a semiconductor element.

In measuring the thermal resistance of a semiconductor element, it is widely known to measure the thermal resistance by, for example, applying a voltage to the semiconductor element itself to cause it to self-heat (for example, see Patent Document 1).

JP 2017-135868 Publication

However, in semiconductor modules in which multiple semiconductor elements are arranged close together and thermally coupled, it is difficult to measure the thermal resistance of each semiconductor element individually because each semiconductor element generates its own heat. There is a problem.

An object of the present invention is to provide a method for measuring thermal resistance of a semiconductor element and a thermal resistance measuring apparatus for a semiconductor element, which are capable of individually measuring the thermal resistance of each of a plurality of semiconductor elements.

In order to achieve the above object, a method for measuring thermal resistance of a semiconductor element according to one aspect of the present invention controls a first voltage-controlled semiconductor element of an enhancement type provided in a semiconductor module to an unsaturated state, and A second voltage-controlled semiconductor device of the depletion type, which is provided in the device and connected in series to the first voltage-controlled semiconductor device, is controlled to a saturated state, and the thermal resistance of the first voltage-controlled semiconductor device is measured. a thermal resistance measurement step; and a second thermal resistance measurement of controlling the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element to a saturated state and measuring the thermal resistance of the second voltage-controlled semiconductor element. and a process.

Further, in order to achieve the above object, a thermal resistance measuring device for a semiconductor element according to one aspect of the present invention provides a voltage between a control terminal provided in a first voltage-controlled semiconductor element of an enhancement type and a carrier inflow side terminal. one of the semiconductor modules having a terminal-to-terminal variable power source that applies a voltage, and a depletion type second voltage-controlled semiconductor element connected in series to the first voltage-controlled semiconductor element and the first voltage-controlled semiconductor element. and a terminal-to-terminal variable power supply that applies a voltage between the terminal and the other terminal, and the terminal-to-terminal variable power supply is configured to provide the first voltage-controlled semiconductor element with a thermal resistance of the first voltage-controlled semiconductor element. When measuring the thermal resistance of the second voltage-controlled semiconductor device by applying a voltage that can control the semiconductor device to an unsaturated state between the control terminal and the carrier inflow side terminal, the first voltage-controlled semiconductor device A voltage that can control the element and the second voltage-controlled semiconductor element into a saturated state is applied between the control terminal and the carrier inflow side terminal, and the variable power supply between the two terminals is configured to control the second voltage-controlled semiconductor element. When measuring the thermal resistance of the semiconductor module, a voltage is applied between the one terminal and the other terminal of the semiconductor module, and the second voltage-controlled semiconductor element is controlled from the one terminal to the saturated state. A current is passed through.

According to one aspect of the present invention, the thermal resistance of each of a plurality of semiconductor elements can be measured.

1 is a circuit diagram showing an example of a schematic configuration of a thermal resistance measuring device for a semiconductor element according to an embodiment of the present invention. 1 is a plan view schematically showing an example of a schematic configuration of a semiconductor device included in a thermal resistance measuring apparatus for a semiconductor element according to an embodiment of the present invention. 1 is a cross-sectional view schematically showing an example of a schematic configuration of a semiconductor device included in a thermal resistance measuring apparatus for a semiconductor element according to an embodiment of the present invention. 1 is a flowchart illustrating an example of the flow of a method for measuring thermal resistance of a semiconductor device according to an embodiment of the present invention. 1 is a flowchart showing an example of the flow of a first thermal resistance measuring step in a method for measuring thermal resistance of a semiconductor element according to an embodiment of the present invention. FIG. 6 is a diagram for explaining various voltages and currents supplied to a semiconductor module in a first thermal resistance measuring step in a method for measuring thermal resistance of a semiconductor element according to an embodiment of the present invention. It is a flowchart which shows an example of the flow of the second thermal resistance measuring process in the thermal resistance measuring method of a semiconductor element according to one embodiment of the present invention. FIG. 6 is a diagram for explaining various voltages and currents supplied to a semiconductor module in a second thermal resistance measuring step in a method for measuring thermal resistance of a semiconductor element according to an embodiment of the present invention.

A method for measuring thermal resistance of a semiconductor element and an apparatus for measuring thermal resistance of a semiconductor element according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8.

(Semiconductor element thermal resistance measuring device)
A schematic configuration of a thermal resistance measuring device for a semiconductor element according to this embodiment will be described using FIGS. 1 to 3. FIG. FIG. 1 is a diagram showing an example of a schematic configuration of a thermal resistance measuring device (hereinafter sometimes abbreviated as "thermal resistance measuring device") 1 for a semiconductor element according to the present embodiment.

As shown in FIG. 1, the thermal resistance measuring device 1 according to the present embodiment includes a field effect transistor (Field Effect Transistor) having a semiconductor substrate 113a (not shown in FIG. 1, see FIG. 3) made of silicon (Si). A variable power supply 13 (an example of a variable power supply between terminals) that applies a voltage between a gate electrode g3 (an example of a control terminal) and a source electrode s3 (an example of a carrier inflow side terminal) provided in the FET) 113 is provided. . Hereinafter, a field effect transistor having a semiconductor substrate made of silicon will be referred to as a "Si-FET." The Si-FET 113 is, for example, an N-type FET. The Si-FET 113 corresponds to an example of an enhancement-type first voltage-controlled semiconductor element.

The thermal resistance measuring device 1 also measures a drain terminal D (an example of one terminal) and a source terminal S (an example of the other terminal) of a semiconductor module 11 having a Si-FET 113 and a GaN-FET 111 connected in series with the Si-FET 113. A variable power supply 15 (an example of a variable power supply between both terminals) that applies a voltage between the two terminals is provided. The GaN-FET 111 is a field effect transistor having a semiconductor substrate 111a (not shown in FIG. 1, see FIG. 3) made of gallium nitride (GaN). Hereinafter, a field effect transistor having a semiconductor substrate made of gallium nitride will be referred to as a "GaN-FET." The GaN-FET 111 is, for example, an N-type FET. The GaN-FET 111 corresponds to an example of a depletion type second voltage controlled semiconductor element.

The positive electrode side of the variable power supply 13 is connected to the gate terminal G of the semiconductor module 11. The gate terminal G of the semiconductor module is connected to the gate electrode g3 of the Si-FET 113. Therefore, the positive electrode side of the variable power supply 13 is connected to the gate electrode g3 of the Si-FET 113 via the gate terminal G of the semiconductor module 11. The negative electrode side of the variable power supply 13 is connected to the source terminal S of the semiconductor module 11. The source terminal S of the semiconductor module 11 is connected to the source electrode s3 of the Si-FET 113. Therefore, the negative electrode side of the variable power supply 13 is connected to the source electrode s3 of the Si-FET 113 via the source terminal S of the semiconductor module 11.

The positive electrode side of the variable power supply 15 is connected to the drain terminal D of the semiconductor module 11. A drain terminal D of the semiconductor module 11 is connected to a drain electrode d1 of the GaN-FET 111. Therefore, the positive electrode side of the variable power supply 15 is connected to the drain electrode d1 of the GaN-FET 111 via the drain terminal D of the semiconductor module 11.
The negative electrode side of the variable power source 15 is connected to the source terminal S of the semiconductor module 11 and the negative electrode side of the variable power source 13. The source terminal S of the semiconductor module 11 is connected to the source electrode s3 of the Si-FET 113. Therefore, the negative electrode side of the variable power supply 15 is connected to the source electrode s3 of the Si-FET 113 via the source terminal S of the semiconductor module 11.

As shown in FIG. 1, the semiconductor module 11 includes a GaN-FET 111 and a Si-FET 113 connected in series between the positive and negative sides of the variable power supply 13. A source electrode s1 of the GaN-FET 111 is connected to a drain electrode d3 of the Si-FET 113. The gate electrode g1 of the GaN-FET 111 is connected to the source electrode s3 of the Si-FET 113. Therefore, the gate electrode g1 of the GaN-FET 111 is connected to the source terminal S of the semiconductor module 11, the negative electrode side of the variable power source 13, and the negative electrode side of the variable power source 15 via the source electrode s3 of the Si-FET 113.

Here, the configuration of the semiconductor module 11 will be explained with reference to FIG. 1 and FIGS. 2 and 3. FIG. 2 is a schematic plan view showing an example of a schematic configuration of the semiconductor module 11. As shown in FIG. FIG. 3 is a schematic cross-sectional view showing an example of the schematic configuration of the GaN-FET 111 and Si-FET 113 portion of the semiconductor module 11 taken along the line AA shown in FIG.

As shown in FIG. 2, the Si-FET 113 and the GaN-FET 111 are arranged in an overlapping manner. Si-FET 113 is placed above GaN-FET 111. The gate terminal G, drain terminal D, and source terminal S of the semiconductor module 11 have a wiring pattern of a predetermined shape, and are arranged surrounding the GaN-FET 111.

As shown in FIG. 3, the GaN-FET 111 is placed on a case 115 provided in the semiconductor module 11. The GaN-FET 111 is thermally and mechanically bonded to the case 115 by a thermally conductive bonding agent 117. GaN-FET 111 has a semiconductor substrate 111a. The surface of the semiconductor substrate 111a on the case 115 side is bonded to the case 115 via a heat conductive bonding agent 117.

The GaN-FET 111 has two gate electrodes g1, a source electrode s1, and a drain electrode d1 (not shown in FIG. 3, see FIG. )have. In this way, the GaN-FET 111 has a horizontal structure in which the gate electrode g1, the source electrode s1, and the drain electrode d1 are formed on one surface of the semiconductor substrate 111a.

As shown in FIG. 2, the semiconductor substrate 111a has a rectangular shape when viewed from the axial direction perpendicular to the surface on which the gate electrode g1, source electrode s1, and drain electrode d1 are formed (hereinafter referred to as "planar view"). have. The drain electrode d1 is disposed near one long side of the semiconductor substrate 111a and extends along the long side. The drain electrode d1 has a plurality of square electrode pads (six in this embodiment), and has a shape in which adjacent electrode pads are connected to each other by a wiring pattern. The two gate electrodes g1 are arranged near the other long side of the semiconductor substrate 111a. One of the two gate electrodes g1 is arranged near one short side of the semiconductor substrate 111a, and the other of the two gate electrodes g1 is arranged near the other short side of the semiconductor substrate 111a. The source electrode s1 is located approximately at the center of the semiconductor substrate 111a, sandwiched between the two gate electrodes g1, and placed adjacent to the drain electrode d1.

As shown in FIG. 2, the Si-FET 113 is placed on the source electrode s1 of the GaN-FET 111. Returning to FIG. 3, the Si-FET 113 is electrically and physically (thermally) bonded to the GaN-FET 111 by a conductive bonding agent 119 formed on the source electrode s1. The Si-FET 113 includes a semiconductor substrate 113a made of Si, a drain electrode d3 formed on the surface of the semiconductor substrate 111a on the GaN-FET 111 side, and a source electrode s3 and a gate electrode g3 formed on the back side of the surface. have. In this way, the Si-FET 113 has a structure in which the source electrode s3 and the drain electrode d3 are formed on the two surfaces of the semiconductor substrate 111a.

The drain electrode d3 of the Si-FET 113 and the source electrode s1 of the GaN-FET 111 are electrically connected by a conductive bonding agent 119. Thereby, the Si-FET 113 and the GaN-FET 111 are connected in series.

Returning to FIG. 2, the gate electrode g3 of the Si-FET 113 is connected to the gate terminal G of the semiconductor module 11 by a bonding wire BW1. The source electrode s3 of the Si-FET 113 is connected to the source terminal S of the semiconductor module 11 by a plurality of (four in this embodiment) bonding wires BW2. Each of the two gate electrodes g1 of the GaN-FET 111 is connected to the source terminal S of the semiconductor module 11 by a bonding wire BW3. Thereby, the two gate electrodes g1 of the GaN-FET 111 are connected to the source electrode s3 of the Si-FET 113 via the bonding wire BW3, the source terminal S, and the bonding wire BW2. The drain electrode d1 of the GaN-FET 111 is connected to the drain terminal D of the semiconductor module 11 by a plurality of (six in this embodiment) bonding wires BW4. The bonding wire BW4 is bonded to the electrode pad of the drain electrode d1 formed in a square shape.

In this way, the semiconductor module 11 has a chip-on-chip structure in which the Si-FET 113 is placed on the GaN-FET 111. Therefore, they are thermally coupled. Further, the semiconductor module 11 has a configuration in which a GaN-FET 111 and a Si-FET 113 are connected in series (cascade connection). Therefore, if current is simply passed through this series-connected circuit, each of the GaN-FET 111 and Si-FET 113 will generate heat, and as described above, they are also thermally coupled, so the heat generation will be reduced. , the heat generation of each FET cannot be detected individually. Therefore, the thermal resistance of each FET cannot be calculated individually.

Therefore, in the thermal resistance measuring device 1 according to the present embodiment, the variable power supply 13 applies a voltage that can control the Si-FET 113 to an unsaturated state to the gate electrode g3 and the source electrode s3 when measuring the thermal resistance of the Si-FET 113. When measuring the thermal resistance of the GaN-FET 111, a voltage that can control the Si-FET 113 and the GaN-FET 111 into a saturated state is applied between the gate electrode g3 and the source electrode s3. Furthermore, in the thermal resistance measuring device 1 according to the present embodiment, the variable power supply 15 applies a voltage between the drain terminal D and the source terminal S of the semiconductor module 11, and also applies a voltage between the drain terminal D and the source terminal S when measuring the thermal resistance of the GaN-FET 111. A current is passed from the terminal D to the GaN-FET 111 which is controlled to be in a saturated state.

In this way, the thermal resistance measuring device 1 changes the voltage applied to the semiconductor module 11 from the variable power supplies 13 and 15 as appropriate, and measures the thermal resistance of the Si-FET 113 and the thermal resistance of the GaN-FET 111. The thermal resistance of the Si-FET 113 and the thermal resistance of the GaN-FET 111 are individually measured by appropriately changing the operating states of the Si-FET 113 and the GaN-FET 111 depending on the case.

In this embodiment, the "unsaturated state" means a state in which the FET operates in a linear region in the IV characteristics (characteristics of drain-source current with respect to drain-source voltage) of the FET. That is, "unsaturated state" means a state in which the FET operates in a region where the drain-source current changes depending on the drain-source voltage. Furthermore, in the present embodiment, "saturated state" means a state in which the FET operates in a saturated region in the IV characteristics of the FET. That is, the "saturated state" means a state in which the FET operates in a region where the drain-source current does not depend on the drain-source voltage but changes depending on the gate-source voltage. In both the "unsaturated state" and the "saturated state", the FET is in the on state. However, when the gate-source voltages are the same, a larger drain-source current flows in the "saturated state" than in the "unsaturated state."

The thermal resistance measuring device 1 includes a control section 17. The control unit 17 controls the variable power supplies 13 and 15 to measure the voltage between the gate electrode g3 and the source electrode s3, and measures the voltage between the GaN-FET 111 and the Si-FET 113 based on the amount of heat generated by each of the GaN-FET 111 and the Si-FET 113. - Calculate the thermal resistance of each FET 113.

(Method for measuring thermal resistance of semiconductor elements)
A method for measuring thermal resistance of a semiconductor element according to this embodiment will be explained using FIGS. 4 to 8. FIG. 4 is a front gate showing an example of the flow of a method for measuring thermal resistance of a semiconductor element (hereinafter sometimes abbreviated as "thermal resistance measuring method") according to this embodiment.

As shown in FIG. 4, in the thermal resistance measuring method according to this embodiment, first, in step S11, a first thermal resistance measuring step is executed, and the process moves to step S13. In the first thermal resistance measurement step of step S11, the Si-FET 113 (an example of an enhancement type first voltage-controlled semiconductor element, see FIG. 6) provided in the semiconductor module 11 (see FIG. 6) is controlled to an unsaturated state. Then, the GaN-FET 111 (an example of a depletion-type second voltage-controlled semiconductor element, see FIG. 6) provided in the semiconductor module 11 and connected in series to the Si-FET 113 is controlled to a saturated state, and the Si-FET 113 Measure the thermal resistance of

Here, specific processing of the first thermal resistance measurement step (step S11) will be explained using FIGS. 5 and 6. FIG. 5 is a flowchart showing an example of the flow of the first thermal resistance measurement step. FIG. 6 is a diagram for explaining various voltages and currents supplied to the semiconductor module 11 by the variable power supplies 13 and 15 in the first thermal resistance measurement step. FIG. 6(a) is a diagram for explaining the first voltage measurement step before heat generation and the first voltage measurement step during heat generation (both details will be described later) in the first thermal resistance measurement step, and FIG. 6(b) FIG. 2 is a diagram for explaining a first heat generation step (details will be described later).

As shown in FIG. 5, in the first thermal resistance measurement process, first, in step S111, a first pre-heat generation voltage measurement process is executed, and the process moves to step S113. In the first pre-heat generation voltage measurement step of step S111, before the Si-FET 113 is made to generate heat in the first heat generation step (details will be described later), the gate electrode g3 (an example of a control terminal) provided on the Si-FET 113 and the source electrode The inter-terminal voltage Vgsm1 between s3 (an example of carrier inflow side terminals) is measured with the Si-FET 113 controlled to be in an unsaturated state. That is, in the first pre-heat generation voltage measurement step, the inter-terminal voltage Vgsm1 is measured while the Si-FET 113 is controlled to operate in the linear region of the IV characteristic. More specifically, in the first pre-heat generation voltage measurement step, the first measurement voltage Vmp1 is set at a voltage value that can control the GaN-FET 111 to a saturated state and the Si-FET 113 to an unsaturated state. The voltage is applied between a drain terminal D and a source terminal S provided in the semiconductor module 11. In other words, the first measurement voltage Vmp1 is such that the voltage at which the GaN-FET 111 is saturated is applied to the drain terminal d1 and the source terminal s1, and the voltage at which the Si-FET 113 is unsaturated is applied to the drain terminal d3 and the source terminal s3. Set to the applied voltage value. Furthermore, in the first pre-heat generation voltage measurement step, a first measurement current is set to an amount of current that can flow through both the GaN-FET 111 controlled to be saturated and the Si-FET 113 controlled to be unsaturated. Imp1 is caused to flow from the drain terminal D to the semiconductor module 11, and the inter-terminal voltage Vgsp1 between the gate electrode g3 and source electrode s3 of the Si-FET 113 is measured. In the first pre-heating voltage measurement process, a current exceeding the allowable value flows through the GaN-FET 111 and the Si-FET 113, so that at least one of the GaN-FET 111 and the Si-FET 113 operates within the rated range. The generation of heat that would not otherwise occur (hereinafter referred to as "abnormal heat generation") is prevented from occurring.

As shown in FIG. 6(a), in the first pre-heat generation voltage measurement step of step S111, the control unit 17 included in the thermal resistance measuring device 1 controls the variable power supply 15 to control the first measurement voltage Vmp1. is applied between the drain terminal D and source terminal S of the semiconductor module 11, and the first measuring current Imp1 is supplied from the drain terminal D to the semiconductor module 11. The first measurement current Imp1 is set to a current value that can be passed even when the Si-FET 113 is in an unsaturated state (in other words, a value smaller than the current value in a saturated state). As a result, the first measurement current Imp1 becomes a current amount that does not cause abnormal heat generation in the Si-FET 113. The first measurement voltage Vmp1 and the first measurement current Imp1 may be determined, for example, based on the electrical characteristics (current-voltage characteristics, etc.) described in the data sheet of the Si-FET 113, or may be determined based on actual measured values. may also be determined.

In the first pre-heat generation voltage measurement step, the GaN-FET 111 is controlled to be in a saturated state. Therefore, the first measuring current Imp1 supplied from the drain terminal D of the semiconductor module 11 is input to the drain electrode d3 of the Si-FET 113 through the GaN-FET 111. The control unit 17 measures the current output from the source terminal S of the semiconductor module 11 having the GaN-FET 111 in the saturated state and the Si-FET 113 in the unsaturated state, and this current becomes the first measurement current Imp1. Adjust the variable power supply 13 as follows. In the first pre-heat generation voltage measurement step, the control unit 17 controls the output voltage of the variable power supply 13 such that the current output from the source terminal S of the semiconductor module 11 has the same current value as the first measurement current Imp1, that is, the output voltage of the Si-FET 113. The inter-terminal voltage Vgsp1 between the gate electrode g3 and the source electrode s3 is measured and stored.

Returning to FIG. 5, in step S113, a first heat generation process is executed, and the process moves to step S115. In the first heat generation step of step S113, the Si-FET 113 controlled to be in an unsaturated state is caused to generate heat. Generally, in a FET, the resistance in an unsaturated state, which is controlled in a linear region, is larger than the on-resistance in a saturated state. Therefore, in the first heat generation step, heat generation from the Si-FET 113 operating in an unsaturated state becomes dominant to the extent that heat generation from the GaN-FET 111 operating in a saturated region can be ignored. In the first heat generation step of step S113, a voltage having the same voltage value as the inter-terminal voltage Vgsp1 measured in the first pre-heat generation voltage measurement step (step S111) is applied between the gate electrode g3 and source electrode s3 of the Si-FET 113. do. In addition, in the first heat generation step of step S113, the first heat generation voltage Vph1 that can generate heat in the Si-FET 113 controlled in the unsaturated state with the GaN-FET 111 controlled in the saturated state is applied to the drain of the semiconductor module 11. It is applied between terminal D and source terminal S. Furthermore, in the first heat generation step of step S113, a first heat generation current Iph1 having a larger current amount than the first measurement current Imp1 is passed from the drain terminal D to the semiconductor module 11 to cause the Si-FET 113 to generate heat. The first heating current Iph1 is set to, for example, a current amount that is within the allowable range for the GaN-FET 111 that is controlled to be in a saturated state, and is beyond the allowable range for the Si-FET 113 that is controlled to be in an unsaturated state. Therefore, the Si-FET 113 generates a larger amount of heat than the GaN-FET 111.

As shown in FIG. 6(b), in the first heat generation step of step S113, the control unit 17 applies the inter-terminal voltage Vgsp1 measured in step S111 to the gate electrode g3 and source electrode s3 of the Si-FET 113. Then, the variable power supply 15 is controlled so that the first heat generation voltage Vph1 and the first heat generation current Iph1 that can generate heat to an extent that does not damage the semiconductor module 11 flow. The first heat generation voltage Vph1 (that is, the drain-source voltage of the semiconductor module 11), the first heat generation current Iph1 (that is, the drain current of the semiconductor module 11), and the on-resistance of the GaN-FET 111 in a completely on state (saturated state) Using Rong, the power consumption TG1 of the GaN-FET 111 in the first heat generation step of step S113 can be expressed by the following formula (1), and the power consumption TS1 of the Si-FET 113 can be expressed by the following formula (2). It can be expressed as
TG1=Iph1 ² ×Rong...(1)
TS1=Iph1×Vph1-TG1...(2)

For example, if the first heat generation voltage Vph1 is 20 [V], the first heat generation current Iph1 is 2 [A], and the on-resistance Rong is 35 [mΩ], the heat generation TG1 of the GaN-FET 111 is 0.14 [W] (=2 ² × 35 × 10 ⁻³ ), and the heat generation TS1 of the Si-FET 113 is 39.86 [W] (=2 × 20−0.14). Therefore, the power consumption TS1 of the Si-FET 113 is approximately 280 times the heat generation TG1 of the GaN-FET 111. Since the heat generated by the semiconductor module 11 is obtained by adding up the heat generated TG1 of the GaN-FET 111 and the generated heat TS1 of the Si-FET 113, the generated heat generated by the semiconductor module 11 in the first heat generation step of step S113 is consumed by the Si-FET 113. The heat generated by the electric power becomes dominant, and the heat generated by the semiconductor module 11 can be regarded as the heat generated by the power consumption of the Si-FET 113.

Returning to FIG. 5, in step S115, the first heating voltage measurement step is executed, the first thermal resistance measurement step is completed, and the process moves to step S13 (see FIG. 4). In the first heating voltage measurement step of step S115, after the first heating step (step S113), the terminal voltage Vgsm1 of the Si-FET 113 that continues to generate heat in an unsaturated state (the voltage between the gate electrode g3 and The voltage between the source electrodes s3) is measured. More specifically, in the first heating voltage measurement step of step S115, the first measurement voltage Vmp1 is applied between the drain terminal D and the source terminal S of the semiconductor module 11. Furthermore, in the first heating voltage measurement step of step S115, the first measurement current Imp1 is caused to flow from the drain terminal D to the semiconductor module 11 to measure the inter-terminal voltage Vgsm1. In the first voltage measurement step during heat generation, the inter-terminal voltage Vgsm1 is measured after the temperature rise due to heat generation of the Si-FET 113 is stabilized.

As shown in FIG. 6A, in the first voltage measurement step during heat generation in step S115, the control unit 17 uses the same first measurement voltage Vmp1 and first measurement voltage as in the first pre-heat generation voltage measurement step in step S111. The variable power supply 15 is controlled so that the current Imp1 is used. Thereby, the variable power supply 15 applies the first measurement voltage Vmp1 between the drain terminal D and the source terminal S of the semiconductor module 11, and supplies the first measurement current Imp1 from the drain terminal D to the semiconductor module 11. . In the first heating voltage measurement process, the control unit 17 controls the output voltage of the variable power supply 13 such that the current output from the source terminal S of the semiconductor module 11 has the same current value as the first measurement current Imp1, that is, the output voltage of the Si-FET 113. The inter-terminal voltage Vgsm1 between the gate electrode g3 and the source electrode s3 is measured and stored. Note that in FIG. 6A, the inter-terminal voltage Vgsm1 in the first heating voltage measurement step is shown in parentheses.

Returning to FIG. 4, in step S13, a first thermal resistance calculation step is executed, and the process moves to step S15. In the first thermal resistance calculation step of step S15, the terminal-to-terminal voltage Vgsp1 measured in the first pre-heat generation voltage measurement step (step S111), and the terminal-to-terminal voltage Vgsm1 measured in the first heat generation voltage measurement step (step S115). The thermal resistance of the Si-FET 113 is calculated based on the temperature characteristic coefficient Ks [mV/° C.] of the Si-FET 113. The temperature characteristic coefficient of the Si-FET 113 is calculated from the temperature characteristic of the drain-source voltage of a Si-FET formed in the same manner as the Si-FET 113, which is actually measured using, for example, a constant temperature bath, and is calculated by the control unit 17. remembered.

In a FET, even if the current between the drain and the source is the same, the voltage between the gate and the source changes as the temperature changes. Furthermore, the FET has a unique temperature characteristic coefficient that represents the relationship between the gate-source voltage and temperature change. For this reason, the control unit 17 controls the inter-terminal voltage Vgsp1 measured in the first pre-heat generation voltage measurement step (step S111) and the inter-terminal voltage Vgsm1 measured in the first heat generation voltage measurement step (step S115). By dividing the terminal voltage difference ΔVgs, which is the difference, by the temperature characteristic coefficient Ks, the temperature difference ΔT1 before and after heat generation of the Si-FET 113 is calculated. Furthermore, the control unit 17 controls the temperature difference depending on the magnitude of the load applied to the semiconductor module 11 (power obtained by multiplying the first heat generation voltage Vph1 and the first heat generation current Iph1) to generate heat in the Si-FET 113. By dividing ΔT1, the thermal resistance value Rth_S [° C./W] of the Si-FET 113 is calculated. As described above, in the method for measuring thermal resistance of a semiconductor device according to the present embodiment, the thermal resistance of the Si-FET 113 of the GaN-FET 111 and the Si-FET 113 connected in series is determined by executing the processes of step S11 and step S15. The value Rth_S can be measured.

As shown in FIG. 4, in step S15, a second thermal resistance measurement process is performed, and the process moves to step S17. In the second thermal resistance measurement step of step S15, the Si-FET 113 and the GaN-FET 111 are controlled to be in a saturated state, and the thermal resistance of the GaN-FET 111 is measured.

Here, specific processing of the second thermal resistance measurement step (step S15) will be explained using FIGS. 7 and 8. FIG. 7 is a flowchart showing an example of the flow of the second thermal resistance measurement step. FIG. 8 is a diagram for explaining various voltages and currents supplied to the semiconductor module 11 by the variable power supplies 13 and 15 in the second thermal resistance measurement step. FIG. 8(a) shows the state in the second pre-heating voltage measuring step and the second heating voltage measuring step (both details will be described later) in the second thermal resistance measuring step, and FIG. The state at the second exothermic step (details will be described later) is shown.

As shown in FIG. 5, in the second thermal resistance measurement step, first, in step S151, a second pre-heat generation voltage measurement step is executed, and the process moves to step S153. In the second pre-heat generation voltage measurement step of step S151, before the GaN-FET 111 is made to generate heat in the second heat generation step (details will be described later), the semiconductor module 11 is controlled to have the Si-FET 113 and the GaN-FET 111 saturated. A voltage Vdsm2 between the drain terminal D and the source terminal S is measured. More specifically, in the second pre-heat generation voltage measurement step of step S151, the Si-FET 113 and the GaN-FET 111 are controlled to be in a saturated state. Furthermore, in the second pre-heat generation voltage measurement step of step S151, a second measurement current Imp2 of a current amount that does not cause abnormal heat generation in the Si-FET 113 and the GaN-FET 111 is passed from the drain terminal D to the semiconductor module 11 to both terminals. The voltage Vdsp2 (ie, the voltage between the gate and source of the semiconductor module 11) is measured.

As shown in FIG. 8(a), in the second pre-heat generation voltage measurement step of step S151, the control unit 17 included in the thermal resistance measuring device 1 controls the variable power supply 13 to bring the Si-FET 113 into the saturated state. An inter-terminal voltage Vgsp2 is applied between the gate electrode g3 and the source electrode s3 of the Si-FET 113. Since the source electrode s3 of the Si-FET 113 is, for example, 0 [V], the depletion type GaN-FET 111 is also in the on state. After controlling the Si-FET 113 and the GaN-FET 111 to turn on, the control unit 17 controls the variable power supply 15 to supply the second measurement current Imp2 from the drain terminal D to the semiconductor module 11. The second measurement current Imp2 is a current amount that does not cause abnormal heat generation in the Si-FET 113 and the GaN-FET 111. The second measurement current Imp2 is determined based on, for example, the designed values of the electrical characteristics (on resistance, etc.) of the Si-FET 113 and the GaN-FET 111. In the second pre-heat generation voltage measurement step, the control unit 17 increases the voltage of the variable power supply 15 and increases the second measurement current Imp2, so that a second current of the set amount is supplied from the source terminal S of the semiconductor module 11. The voltage Vdsp2 between both terminals (that is, the voltage between the drain and source of the semiconductor module 11) when the measurement current Imp2 is supplied is measured and stored.

Returning to FIG. 7, in step S153, a second heat generation process is performed, and the process moves to step S155. In the second heat generation step of step S153, the GaN-FET 111 is caused to generate heat while the Si-FET 113 and the GaN-FET 111 are controlled to be in a saturated state. More specifically, in the second heat generation step of step S153, the voltage Vdsp2 between the drain terminal D and source terminal S of the semiconductor module 11 measured in the second pre-heat generation voltage measurement step (step S151) is Apply the same voltage value. Furthermore, in the second heat generation step of step S153, it is possible to heat the GaN-FET 111 while controlling the Si-FET 113 and the GaN-FET 111 to a saturated state, and the current amount is lower than the second measurement current Imp2. A large second heating current Iph2 is passed from the drain terminal D to the semiconductor module 11 to cause the GaN-FET 111 to generate heat.

As shown in FIG. 8(b), in the second heat generation process of step S153, the control unit 17 applies the voltage Vdsp2 between both terminals measured in step S151 between the drain terminal D and the source terminal S of the semiconductor module 11. At the same time, the variable power source 15 is controlled so that the second heating current Iph2 that can generate heat to an extent that does not damage the semiconductor module 11 flows. The voltage between both terminals Vdsp2 (that is, the drain-source voltage of the semiconductor module 11), the second heating current Iph2 (that is, the drain-source current of the semiconductor module 11), the on-resistance Rong and Si- of the GaN-FET 111 in the saturated state Using the on-resistance Rons of the FET 113 in the saturated state, the heat generation TG2 of the GaN-FET 111 in the second heat generation step of step S153 can be expressed by the following equation (3), and the heat generation TS2 of the Si-FET 113 can be expressed as follows. It can be expressed by equation (4).
TG2=Iph2 ² ×Rong...(3)
TS2= ^Iph22 ×Rons...(4)

For example, if the second heating current Iph2 is 50 [A], the on-resistance Rong of the GaN-FET 111 is 35 [mΩ], and the on-resistance Rons of the Si-FET 113 is 3 [mΩ], then the heat generation TG2 of the GaN-FET 111 is is 87.5 [W] (=50 ² ×35 × 10 ⁻³ ), and the heat generation TS2 of the Si-FET 113 is 7.5 [W] (=50 ² ×3 × 10 ⁻³ ). Therefore, the heat generation TG2 of the GaN-FET 111 is approximately 12 times the heat generation TS2 of the Si-FET 113. Since the heat generation of the semiconductor module 11 is obtained by adding up the heat generation TG2 of the GaN-FET 111 and the heat generation TS2 of the Si-FET 113, the heat generation of the semiconductor module 11 in the second heat generation process of step S153 is dominated by the heat generation of the GaN-FET 111. Therefore, the heat generated by the semiconductor module 11 can be regarded as the heat generated by the GaN-FET 111.

Returning to FIG. 7, in step S155, the second heating voltage measurement step is executed, the second thermal resistance measurement step is completed, and the process moves to step S17 (see FIG. 4). In the second heating voltage measurement step of step S155, the voltage Vdsm2 between both terminals of the semiconductor module 11 is measured while the GaN-FET 111 continues to generate heat in a saturated state after the second heating step (step S153). More specifically, in the second heating voltage measurement step of step S155, the second measurement current Imp2 is caused to flow from the drain terminal D to the semiconductor module 11 while the Si-FET 113 and the GaN-FET 111 are controlled to be in a saturated state. and measure the voltage Vdsm2 between both terminals.

As shown in FIG. 8(a), in the second voltage measurement step during heat generation in step S155, the control unit 17 sets the same voltage between the two terminals Vdsp2 in the second voltage measurement step before heat generation in step S151 to The variable power source 13 is controlled to be applied between the gate electrode g3 and the source electrode s3 of the FET 113, and the variable power source 15 is controlled so that the second measurement current Imp2 is the same as that in the second pre-heating voltage measurement step of step S151. control. As a result, the second measurement current Imp2 is supplied from the drain terminal D to the semiconductor module 11 while the Si-FET 113 and the GaN-FET 111 are controlled to a saturated state and the GaN-FET 111 generates heat. The control unit 17 measures and stores the inter-terminal voltage Vdsm2 between the drain terminal D and the source terminal S of the semiconductor module 11 in the second heating voltage measuring step. In addition, in FIG. 8(a), the voltage Vdsm2 between both terminals in the second heating voltage measurement step is shown in parentheses.

Returning to FIG. 7, in step S17, a second thermal resistance calculation step is executed, and the processing of the thermal resistance measuring method is completed. In the second thermal resistance calculation step of step S17, the voltage between both terminals Vdsp2 measured in the second voltage measurement step before heating (step S151), and the voltage Vdsp2 between both terminals measured in the second voltage measurement step during heating (step S155). The thermal resistance of the GaN-FET 111 is calculated based on the voltage Vdsm2 and the temperature characteristic coefficient Kg [mV/° C.] of the GaN-FET 111. The temperature characteristic coefficient of the GaN-FET 111 is calculated from the temperature characteristic of the drain-source voltage of a GaN-FET formed in the same way as the GaN-FET 111, which is actually measured using, for example, a constant temperature bath, and is calculated by the control unit 17. remembered.

The control unit 17 calculates the difference between the terminal-to-terminal voltage Vdsp2 measured in the second pre-heat generation voltage measurement step (step S151) and the terminal-to-terminal voltage Vdsm2 measured in the second heat generation voltage measurement step (step S155). By dividing the voltage difference ΔVds between both terminals by the temperature characteristic coefficient Kg, the temperature difference ΔT2 before and after heat generation of the GaN-FET 111 is calculated. Furthermore, the control unit 17 adjusts the temperature difference ΔT2 based on the magnitude of the load applied to the semiconductor module 11 to cause the GaN-FET 111 to generate heat (the power obtained by multiplying the voltage between both terminals Vdsp2 and the second heating current Iph2). By dividing, the thermal resistance value Rth_G [° C./W] of the GaN-FET 111 is calculated. As described above, in the method for measuring thermal resistance of a semiconductor device according to the present embodiment, the thermal resistance of GaN-FET 111 of GaN-FET 111 and Si-FET 113 connected in series is determined by executing the processes of step S15 and step S17. The value Rth_G can be measured.

As described above, in the method for measuring thermal resistance of a semiconductor device according to the present embodiment, the thermal resistance of each of the Si-FET 113 and the GaN-FET 111 connected in series is measured in steps S11 and S13, and in steps S15 and S17. The thermal resistance measurement process is carried out in two stages.

(Method for measuring thermal resistance of semiconductor elements and effects of thermal resistance measuring device)
Generally, the thermal resistance of a single FET is measured based on the drain-source voltage before and after heat generation, which is measured while the FET is controlled to a saturated state. However, the thermal resistance of a semiconductor module having a chip-on-chip structure (a structure in which two types of chips are combined) cannot be measured using this method. For example, a GaN-FET using GaN, which has better switching performance than Si, is a normally-on device. A normally-on device is a device that is turned on without applying a voltage between its gate and source. Normally-on devices are turned off by applying a negative voltage between the gate and source, but to maintain the safety of the power device, the current is cut off at zero bias when no voltage is applied to the gate. There is a need. Therefore, the GaN-FET is normally-off by being cascade-connected with the Si-FET, which is a normally-off type device in which current is cut off at zero bias. In such a cascade type GaN-FET, the accurate thermal resistance of two types of chips connected in cascade cannot be measured by the general thermal resistance measurement method applied to the above-mentioned single FET.

For devices such as cascade-type GaN-FETs in which normally-on devices and normally-off devices are cascade-connected (hereinafter referred to as "cascade-type devices"), the general method applied to the above-mentioned single FET is used. The thermal resistance measurement method cannot measure the thermal resistance of two chips. In order to measure the thermal resistance of two chips, a measurement current is applied to the cascade type device with only the device to be measured out of the normally on device and the normally off device generating heat. It is necessary to measure the voltage between terminals (for example, the voltage between drain and source). If the above-mentioned general thermal resistance measurement method applied to a single FET is applied to a cascade type GaN-FET, the measurement current will always flow through the GaN-FET, which will cause heat generation in the GaN-FET with high on-resistance. Become dominant. Therefore, even if it is possible to measure the thermal resistance of a GaN-FET, it is not possible to measure the thermal resistance of a Si-FET.

Therefore, in the thermal resistance measuring method and thermal resistance measuring apparatus of a semiconductor element according to the present embodiment, the on-resistance of the normally-on device and the normally-off device provided in the cascade type device are different. The thermal resistance of a device can be accurately measured.

As described above, the thermal resistance measuring device 1 of a semiconductor element according to the present embodiment is configured to set the Si-FET 113 in an unsaturated state and the GaN-FET 111 provided in the semiconductor module 11 which is a cascade type device. -FET 111 can be controlled to saturation. The thermal resistance measuring device 1 measures the voltage between the terminals of the Si-FET 113 (that is, the voltage between the gate electrode g3 and the source electrode s3) before and after (that is, before and during heating) the semiconductor module 11 controlled in this way generates heat. Based on this measurement result, the thermal resistance of the Si-FET 113 can be calculated (step S11 and step S13). Further, the thermal resistance measuring device 1 can control the Si-FET 113 and the GaN-FET 111 to a saturated state. The thermal resistance measuring device 1 measures the voltage between both terminals of the semiconductor module 11 (that is, the drain-source voltage between the drain terminal D and the source terminal S) before and after the semiconductor module 11 generates heat, and measures this voltage. The thermal resistance of the GaN-FET 111 can be calculated based on the measurement results (step S15 and step S17).

As described above, the thermal resistance measuring method and thermal resistance measuring apparatus 1 of a semiconductor element according to the present embodiment measure the thermal resistance of each of two semiconductor chips (for example, two semiconductor chips having a chip-on-chip structure) of a cascade type power device. can be measured.

As explained above, the method for measuring thermal resistance of a semiconductor element according to the present embodiment controls the Si-FET 113 provided in the semiconductor module 11 to be in an unsaturated state, and connects the Si-FET 113 provided in the semiconductor module 11 in series. A first thermal resistance measurement step (step S11) in which the Si-FET 113 and GaN-FET 111 are controlled to a saturated state and the thermal resistance of the Si-FET 113 is measured; A second thermal resistance measuring step (step S15) is provided to measure the thermal resistance of the FET 111.

The thermal resistance measuring device 1 of a semiconductor device according to the present embodiment also includes a variable power supply 13 that applies a voltage between the gate electrode g3 and the source electrode s3 provided in the Si-FET 113, and A variable power source 15 applies a voltage between a drain terminal D and a source terminal S of a semiconductor module 11 having a GaN-FET 111 connected in series, and the variable power source 13 measures the thermal resistance of the Si-FET 113. When measuring the thermal resistance of the GaN-FET 111, a voltage that can control the Si-FET 113 into an unsaturated state is applied between the gate electrode g3 and the source electrode s3, and when the thermal resistance of the GaN-FET 111 is measured, the Si-FET 113 and the GaN-FET 111 are brought into a saturated state. A controllable voltage is applied between the gate electrode g3 and the source electrode s3, and the variable power supply 15 applies a voltage between the drain terminal D and the source terminal S of the semiconductor module 11 when measuring the thermal resistance of the GaN-FET 111. is applied, and a current is caused to flow from the drain terminal D to the GaN-FET 111 which is controlled to be in a saturated state.

Thereby, the thermal resistance measuring method and thermal resistance measuring device 1 of a semiconductor element according to the present embodiment can measure the thermal resistance of each of a plurality of semiconductor elements (Si-FET 113 and GaN-FET 111 in this embodiment). .

The present invention is not limited to the above embodiments, and various modifications are possible.
The method for measuring thermal resistance of a semiconductor element according to the above embodiment includes a first thermal resistance measuring step (step S11) and a first thermal resistance calculating step (step S13) as separate steps, and a second thermal resistance measuring step (step S13). Although step S15) and the second thermal resistance calculation step (step S17) are provided as separate steps, the present invention is not limited thereto. For example, in the method for measuring thermal resistance of a semiconductor element, the first thermal resistance calculation step may be included in the first thermal resistance measurement step, and the second thermal resistance calculation step may be included in the second thermal resistance measurement step.

In the method for measuring thermal resistance of a semiconductor element according to the above embodiment, the thermal resistance of the GaN-FET 111 is measured after measuring the thermal resistance of the Si-FET 113, but the present invention is not limited to this. In the method for measuring the thermal resistance of a semiconductor element, the thermal resistance of the Si-FET 113 may be measured after the thermal resistance of the GaN-FET 111 is measured.

In the above embodiment, Si-FET and GaN-FET are exemplified as voltage-controlled semiconductor elements, but the same effects as in this embodiment can be obtained even with other voltage-controlled semiconductor elements such as IGBT. . Further, in the above embodiment, a GaN-FET is exemplified as a depletion type (normally-on type) element, and a Si-FET is exemplified as an enhancement type (normally-off type) element, but other depletion type The same effects as in this embodiment can be obtained even with elements and enhancement type elements.

1 Thermal resistance measuring device 11 Semiconductor modules 13, 15 Variable power supply 17 Control unit 111 GaN-FET
111a, 113a Semiconductor substrate 113 Si-FET
115 Case 117 Heat conductive bonding agent 119 Conductive bonding agent BW1, BW2, BW3, BW4 Bonding wire D Drain terminal d1, d3 Drain electrode G Gate terminal g1, g3 Gate electrode GaN Gallium nitride Im1 First measurement current Imp1 First measurement Current Imp2 Second measurement current Iph1 First heating current Iph2 Second heating current Kg, Ks Temperature characteristic coefficient Rong, Rons On-resistance Rth_G, Rth_S Thermal resistance value S Source terminals s1, s3 Source electrodes TG1, TG2, TS1 , TS2 Heat generation Vdsm2, Vdsp2 Voltage between both terminals Vgsm1, Vgsp1, Vgsp2 Voltage between terminals Vmp1 Voltage for first measurement Vph1 Voltage for first heat generation ΔT1 Temperature difference ΔT2 Temperature difference ΔVds Voltage difference between both terminals ΔVgs Voltage difference between terminals

Claims (12)

a depletion type second voltage provided in the semiconductor module and controlling a first enhancement type voltage controlled semiconductor element provided in the semiconductor module to an unsaturated state and connected in series to the first voltage controlled semiconductor element provided in the semiconductor module; a first thermal resistance measurement step of controlling the control type semiconductor element to a saturated state and measuring the thermal resistance of the first voltage control type semiconductor element;
a second thermal resistance measuring step of controlling the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element to a saturated state and measuring the thermal resistance of the second voltage-controlled semiconductor element. Thermal resistance measurement method. The first thermal resistance measuring step includes:
a first heat generation step of causing the first voltage-controlled semiconductor element controlled to the unsaturated state to generate heat;
Before causing the first voltage-controlled semiconductor element to generate heat in the first heat generation step, the inter-terminal voltage between the control terminal provided on the first voltage-controlled semiconductor element and the carrier inflow side terminal is set to the unsaturated level. a first pre-heat generation voltage measurement step of measuring in a controlled state;
and a first heating voltage measurement step of measuring the voltage between the terminals of the first voltage-controlled semiconductor element that continues to generate heat in the unsaturated state after the first heating step. Method for measuring thermal resistance of semiconductor devices. Based on the terminal-to-terminal voltage measured in the first pre-heat generation voltage measurement step, the terminal-to-terminal voltage measured in the first heat generation voltage measurement step, and the temperature characteristic coefficient of the first voltage-controlled semiconductor element. 3. The method for measuring thermal resistance of a semiconductor device according to claim 2, further comprising a first thermal resistance calculation step of calculating a thermal resistance of the first voltage-controlled semiconductor device. In the first pre-heat generation voltage measurement step,
Applying a first measurement voltage to the semiconductor module with a voltage value capable of controlling the second voltage-controlled semiconductor element to the saturated state and controlling the first voltage-controlled semiconductor element to the unsaturated state. Apply between one terminal and the other terminal provided,
The heat of the semiconductor element according to claim 2 or 3, wherein the voltage between the terminals is measured by flowing a first measuring current of a current amount that does not cause the first voltage-controlled semiconductor element to generate heat from the one terminal to the semiconductor module. How to measure resistance. In the first exothermic step,
Applying a voltage having the same voltage value as the inter-terminal voltage measured in the first pre-heating voltage measurement step between the control terminal and the carrier inflow side terminal of the first voltage-controlled semiconductor element;
A first heat generating voltage that can cause the first voltage controlled semiconductor element controlled to the unsaturated state to generate heat while the second voltage controlled semiconductor element is controlled to the saturated state is applied to the first voltage of the semiconductor module. applying between one terminal and the other terminal,
The heat of the semiconductor element according to claim 4, wherein a first heat generating current having a larger current amount than the first measurement current is passed from the one terminal to the semiconductor module to cause the first voltage controlled semiconductor element to generate heat. How to measure resistance. In the first heating voltage measurement step,
Applying the first measurement voltage between the one terminal and the other terminal of the semiconductor module,
6. The method for measuring thermal resistance of a semiconductor element according to claim 4, wherein the voltage between the terminals is measured by flowing the first measurement current from the one terminal to the semiconductor module. The second thermal resistance measurement step includes:
a second heating step of causing the second voltage-controlled semiconductor element to generate heat while the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element are controlled to the saturated state;
Before causing the second voltage-controlled semiconductor element to generate heat in the second heat generation step, the semiconductor module is heated while the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element are controlled to the saturated state. a second pre-heating voltage measurement step of measuring the voltage between one terminal and the other terminal;
and a second heating voltage measuring step of measuring the voltage between both terminals of the semiconductor module while the second voltage-controlled semiconductor element continues to generate heat in the saturated state after the second heating step. The method for measuring thermal resistance of a semiconductor device according to any one of claims 1 to 6. The voltage between the terminals measured in the second voltage measurement step before heating, the voltage between the terminals measured in the second voltage measurement step during heating, and the temperature characteristic coefficient of the second voltage-controlled semiconductor element. The method for measuring thermal resistance of a semiconductor device according to claim 7, further comprising a second thermal resistance calculation step of calculating the thermal resistance of the second voltage-controlled semiconductor device based on the second voltage-controlled semiconductor device. In the second pre-heat generation voltage measurement step,
controlling the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element to the saturated state;
A second measuring current of an amount that does not cause abnormal heat generation in the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element is passed from the one terminal to the semiconductor module to measure the voltage between the two terminals. The method for measuring thermal resistance of a semiconductor element according to claim 7 or 8. In the second exothermic step,
Applying a voltage between the one terminal and the other terminal of the semiconductor module with the same voltage value as the voltage between the two terminals measured in the second pre-heating voltage measurement step,
It is possible to cause the second voltage-controlled semiconductor element to generate heat while the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element are controlled to the saturated state, and the second measurement current 10. The method for measuring thermal resistance of a semiconductor element according to claim 9, wherein a second heating current having a larger current amount than the first terminal is passed through the semiconductor module from the one terminal to cause the second voltage-controlled semiconductor element to generate heat. In the second heating voltage measurement step,
With the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element controlled to the saturated state, the second measurement current is caused to flow from the one terminal to the semiconductor module to increase the voltage between the two terminals. The method for measuring thermal resistance of a semiconductor element according to claim 9 or 10. a terminal-to-terminal variable power source that applies a voltage between a control terminal and a carrier inflow side terminal provided in an enhancement-type first voltage-controlled semiconductor element;
voltage between one terminal and the other terminal of a semiconductor module having the first voltage-controlled semiconductor element and a second voltage-controlled semiconductor element of a depletion type connected in series to the first voltage-controlled semiconductor element; Equipped with a variable power supply between both terminals that applies
The inter-terminal variable power supply supplies a voltage that can control the first voltage-controlled semiconductor element to an unsaturated state when measuring the thermal resistance of the first voltage-controlled semiconductor element to the control terminal and the carrier inflow side terminal. the voltage that can be applied to the first voltage-controlled semiconductor element and the second voltage-controlled semiconductor element to a saturated state when measuring the thermal resistance of the second voltage-controlled semiconductor element; applying between the terminal and the carrier inflow side terminal;
The terminal-to-terminal variable power supply applies a voltage between the one terminal and the other terminal of the semiconductor module when measuring the thermal resistance of the second voltage-controlled semiconductor element, and also applies voltage between the one terminal and the other terminal of the semiconductor module. A thermal resistance measuring device for a semiconductor device, wherein a current is caused to flow through the second voltage-controlled semiconductor device controlled to the saturated state.

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