JP2023146620A - nitride semiconductor device - Google Patents

Abstract

To realize excellent on-resistance-temperature characteristics by reducing temperature dependency of an on-resistance of a nitride semiconductor HEMT.SOLUTION: A nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 disposed on the substrate 12, an electron transit layer 16 disposed on the buffer layer 14, and an electron supply layer 20 disposed on the electron transit layer 16. The electron transit layer 16 includes a plurality of superlattice layers 16A in which superlattice layers 16A of a first nitride semiconductor layer 16A1 composed of AlN and a second nitride semiconductor layer 16A2 including GaN are repeatedly laminated. The second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A among the plurality of superlattice layers 16A is provided as an uppermost layer of the electron transit layer 16. The electron supply layer 20 is composed of a third nitride semiconductor layer having a larger bandgap than that of each of the superlattice layers 16A.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to a nitride semiconductor device.

Currently, high electron mobility transistors (HEMTs) using Group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMT uses a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMT are recognized as devices that enable lower on-resistance and higher speed/higher frequency operation than typical silicon (Si) power devices.

For example, a nitride semiconductor HEMT includes an electron transit layer made of a gallium nitride (GaN) layer and an electron supply layer made of an aluminum gallium nitride (AlGaN) layer. 2DEG is formed in the electron transit layer near the interface of the heterojunction between the electron transit layer and the electron supply layer. Further, in the case of a normally-off type HEMT, for example, a semiconductor layer (for example, a p-type GaN layer) containing an acceptor type impurity is provided on the electron transit layer directly under the gate electrode. In this configuration, the channel directly under the p-type GaN layer disappears due to a depletion layer extending downward from the p-type GaN layer, thereby realizing normally-off. Patent Document 1 discloses such a normally-off type nitride semiconductor HEMT.

JP 2017-73506 Publication

Generally, in a nitride semiconductor HEMT in which the electron transit layer is made of a GaN layer and the electron supply layer is made of an AlGaN layer, the on-resistance has a large temperature dependence, and the on-resistance increases as the temperature rises. . This is because lattice scattering due to thermal energy increases in the GaN crystal of the electron transport layer, thereby decreasing the mobility of 2DEG used as a channel. For example, in some HEMT products, the on-resistance increases approximately twice as much at a temperature of 150° C. as compared to room temperature. In particular, in a HEMT structure that requires a relatively high breakdown voltage (for example, 650V breakdown voltage), the on-resistance is also high, which increases conduction loss and heat generation during HEMT operation.

Further, in nitride semiconductor HEMTs, it is required to further reduce the chip size from the viewpoint of reducing chip cost. For this reason, it is difficult to increase the chip area in order to obtain a sufficient heat dissipation area, and as a result, it may be difficult to sufficiently dissipate the Joule heat generated when a large current flows through the small chip. Therefore, in a nitride semiconductor HEMT where the on-resistance increases in a positive correlation with temperature and the temperature dependence of the on-resistance is large, the on-resistance increases significantly as the chip temperature rises, which further increases the chip temperature. It is possible that there will be an increase. Therefore, there is still room for improvement in reducing the temperature dependence of the on-resistance of a nitride semiconductor HEMT and achieving good on-resistance-temperature characteristics.

A nitride semiconductor device according to one aspect of the present disclosure includes a plurality of superlattice layers in which superlattice layers of a first nitride semiconductor layer made of AlN and a second nitride semiconductor layer containing GaN are stacked repeatedly. an electron transit layer in which the second nitride semiconductor layer of the uppermost superlattice layer among the plurality of superlattice layers is provided as the uppermost layer of the electron transit layer; and the uppermost layer. In order to generate a two-dimensional electron gas in the second nitride semiconductor layer of the superlattice layer, an electron supply layer is formed of a third nitride semiconductor layer having a larger band gap than each of the plurality of superlattice layers. a gate layer formed of a fourth nitride semiconductor layer disposed on a part of the electron supply layer and containing acceptor-type impurities; a gate electrode disposed on the gate layer; A source electrode and a drain electrode are electrically connected to the dimensional electron gas.

A nitride semiconductor device according to one embodiment of the present disclosure can reduce temperature dependence of on-resistance in a nitride semiconductor HEMT and achieve good on-resistance-temperature characteristics.

FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the first embodiment. FIG. 2 schematically shows an exemplary structure of a buffer layer, an electron transport layer (multiple superlattice layers), a spacer layer, and an electron supply layer formed by epitaxial growth on the substrate of the nitride semiconductor device of FIG. FIG. FIG. 3 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment.

Hereinafter, some embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. It should be noted that components shown in the drawings may be partially enlarged for ease of understanding and clarity, and are not necessarily drawn to scale. Further, in order to facilitate understanding, hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the disclosure and should not be considered as limiting the disclosure.

The following detailed description includes devices, systems, and methods that embody example embodiments of the present disclosure. This detailed description is illustrative in nature and is not intended to limit the embodiments of the disclosure or the application and uses of such embodiments.

[First embodiment]
FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to the first embodiment. FIG. 2 is a diagram showing an exemplary stacked structure of several nitride semiconductor layers of the nitride semiconductor device 10 of FIG. 1.

[Overall structure of nitride semiconductor device]
First, the overall structure of nitride semiconductor device 10 will be described with reference to FIGS. 1 and 2. The nitride semiconductor device 10 may be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor such as gallium nitride (GaN), for example. The nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 20 formed on the electron transit layer 16. including.

Although not shown in FIG. 1 to simplify the illustration, the nitride semiconductor device 10 may include a nucleation layer 13 (see FIG. 2) between the substrate 12 and the buffer layer 14. Although not shown in FIG. 1, the nitride semiconductor device 10 may include a spacer layer 18 (see FIG. 2) between the electron transit layer 16 and the electron supply layer 20.

Substrate 12 may be formed of silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), GaN, sapphire, or other substrate material. For example, the substrate 12 is a Si substrate. The thickness of the substrate 12 may be, for example, 200 μm or more and 1500 μm or less. Note that the Z direction of mutually orthogonal XYZ axes shown in the drawings (for example, FIG. 1) is a direction that is orthogonal to the main surface of the substrate 12. The term "planar view" used in this specification refers to viewing the nitride semiconductor device 10 from above along the Z direction, unless explicitly stated otherwise.

The nucleation layer 13 (see FIG. 2) is formed on the substrate 12 by a nitride semiconductor layer. The nucleation layer 13 may be, for example, an AlN layer having a thickness of 100 nm or more and 500 mm or less. Buffer layer 14 is provided on nucleation layer 13 and may be formed of any material that can alleviate the lattice mismatch between substrate 12 and electron transport layer 16. For example, buffer layer 14 includes one or more nitride semiconductor layers. For example, buffer layer 14 may include at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 14 may be formed by a single AlN layer, a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. can be formed.

In one example, as shown in FIG. 2, the buffer layer 14 includes a first buffer layer 14A, a second buffer layer 14B, and a third buffer layer 14C, which are sequentially stacked on the substrate 12. The first buffer layer 14A may be an AlN layer having a thickness of, for example, 200 nm or more and 500 nm or less. The second buffer layer 14B may be a GaN layer having a thickness of, for example, 500 nm or more and 1000 nm or less. The third buffer layer 14C may be a graded AlGaN layer having a thickness of, for example, 400 nm or more and 1000 nm or less. In this case, the graded AlGaN layer may be composed of three layers of AlGaN in which the Al composition increases stepwise from a position close to the second buffer layer 14B to 25%, 50%, and 75%. Note that in order to suppress leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make it semi-insulating. In that case, the impurity is, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4×10 ¹⁶ cm ⁻³ or more.

The electron transit layer 16 includes a plurality of superlattice layers 16A in which superlattice layers 16A of a first nitride semiconductor layer 16A1 made of AlN and a second nitride semiconductor layer 16A2 containing GaN are repeatedly stacked. Although not necessarily limited, the electron transit layer 16 may include a base layer 16B provided on the buffer layer 14 and made of a nitride semiconductor layer. The base layer 16B is provided to improve the crystal quality of the electron transit layer 16 by forming the electron transit layer 16 with a sufficient thickness. The base layer 16B may be a GaN layer having a thickness of, for example, 100 nm or more and 1000 nm or less. When the electron transit layer 16 includes the base layer 16B, the plurality of superlattice layers 16A are provided on the base layer 16B. The second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A among the plurality of superlattice layers 16A is provided as the uppermost layer of the electron transit layer 16.

In the first embodiment, the first nitride semiconductor layer 16A1 is an AlN layer, and the second nitride semiconductor layer 16A2 is, for example, a GaN layer. The number of superlattice layers 16A can be determined, for example, in consideration of the relationship between the thickness of the electron transport layer 16 (the total thickness of the plurality of superlattice layers 16A) and the breakdown voltage of the nitride semiconductor HEMT. By increasing the number of superlattice layers 16A, the breakdown voltage of the nitride semiconductor HEMT can be improved. In one example, the number of superlattice layers 16A is 10 or more and 100 or less, preferably 10 or more and 40 or less, and in the first embodiment, for example, about 30. In the first embodiment, the nitride semiconductor HEMT is configured to have a breakdown voltage of, for example, 600V or more, preferably 650V or more.

In each superlattice layer 16A, the second nitride semiconductor layer 16A2 may have a thickness greater than the thickness of the first nitride semiconductor layer 16A1. For example, in the first embodiment, the thickness of the second nitride semiconductor layer 16A2 (GaN layer) may be twice or more the thickness of the first nitride semiconductor layer 16A1 (AlN layer). The thickness of the first nitride semiconductor layer 16A1 may be, for example, 1 nm or more and 3 nm or less, and the thickness of the second nitride semiconductor layer 16A2 may be, for example, 2 nm or more and 6 nm or less. The total thickness of the plurality of superlattice layers 16A may be, for example, 30 nm or more and 900 nm or less. When the electron transit layer 16 includes the base layer 16B along with the plurality of superlattice layers 16A, the electron transit layer 16 may have a thickness of, for example, 0.5 μm or less and 2 μm or less.

In the first embodiment, since the second nitride semiconductor layer 16A2, which is a GaN layer, is formed with a larger thickness than the first nitride semiconductor layer 16A1, which is an AlN layer, each superlattice layer 16A is made of Al The layer is composed mainly of GaN. As a result, it is possible to configure a plurality of superlattice layers 16A that take advantage of the characteristics of GaN. This point will be explained later.

Note that in order to suppress leakage current in the electron transit layer 16, impurities may be introduced into a part of the electron transit layer 16 to make the area other than the surface layer region of the electron transit layer 16 semi-insulating. In that case, the impurity is, for example, C, and the concentration of the impurity may be, for example, 1×10 ¹⁹ cm ⁻³ or more in peak concentration.

The electron supply layer 20 is constituted by a third nitride semiconductor layer having a larger band gap than each superlattice layer 16A of the electron transit layer 16. For example, the electron supply layer 20 may be an AlGaN layer. In a nitride semiconductor layer containing Al, the band gap increases as the Al composition increases. For example, in the first embodiment, the electron supply layer 20 is an AlGaN layer, and each superlattice layer 16A of the electron transit layer 16 includes an AlN layer (first nitride semiconductor layer 16A1) and a GaN layer (second nitride semiconductor layer 16A1). It has a superlattice structure with layer 16A2). In this case, the electron supply layer 20 and each A superlattice layer 16A is configured. The Al composition of the electron supply layer 20 is not necessarily limited to this range, but is, for example, 25% or more and 50% or less, preferably 40% or more and 50% or less. The Al composition of each superlattice layer 16A of the electron transit layer 16 may be set based on the Al composition of the electron supply layer 20. The electron supply layer 20 may have a thickness of, for example, 10 nm or more and 20 nm or less.

The second nitride semiconductor layer 16A2, which is the uppermost layer of the electron transit layer 16, and the electron supply layer 20 are made of nitride semiconductors having different lattice constants. Therefore, the junction between the nitride semiconductor (for example, GaN) that constitutes the second nitride semiconductor layer 16A2, which is the uppermost layer of the electron transport layer 16, and the nitride semiconductor (for example, AlGaN) that constitutes the electron supply layer 20 is formed using a spacer. This is a lattice-mismatched junction via layer 18 (see FIG. 2). The uppermost layer is formed through the spacer layer 18 by spontaneous polarization of the second nitride semiconductor layer 16A2 (electron transit layer 16) and the electron supply layer 20, and piezoelectric polarization caused by stress applied to the heterojunction of the electron supply layer 20. The energy level of the conduction band of the uppermost second nitride semiconductor layer 16A2 near the heterojunction interface between the second nitride semiconductor layer 16A2 and the electron supply layer 20 is lower than the Fermi level. As a result, a position close to the heterojunction interface between the uppermost second nitride semiconductor layer 16A2 and the electron supply layer 20 via the spacer layer 18 (for example, several nm from the upper surface of the uppermost second nitride semiconductor layer 16A2) A two-dimensional electron gas (2DEG) 22 (see FIG. 1) spreads within the electron transit layer 16 (the uppermost second nitride semiconductor layer 16A2) at a distance of about 1000 nm.

As shown in FIG. 2, the spacer layer 18 is disposed between the second nitride semiconductor layer 16A2, which is the uppermost layer of the electron transit layer 16, and the electron supply layer 20. The spacer layer 18 is constituted by a nitride semiconductor layer (corresponding to the fifth nitride semiconductor layer) containing AlN. In the first embodiment, the spacer layer 18 is, for example, an AlN layer. By inserting the spacer layer 18 at the heterojunction interface between the uppermost second nitride semiconductor layer 16A2 (GaN layer in the first embodiment) and the electron supply layer 20 (AlGaN layer in the first embodiment), the 2DEG 22 is Mobility can be improved.

The spacer layer 18 containing AlN has an Al composition higher than that of each superlattice layer 16A (superlattice structure of the first nitride semiconductor layer 16A1 and the second nitride semiconductor layer 16A2). Further, the Al composition of the spacer layer 18 is larger than that of the electron supply layer 20. Although the Al composition of the spacer layer 18 is not necessarily limited to this range, it is, for example, 80% or more. The spacer layer 18 may have a thickness equal to or less than the thickness of the first nitride semiconductor layer 16A1 of each superlattice layer 16A. The thickness of the spacer layer 18 may be, for example, 1 nm or more and 3 nm or less.

Nitride semiconductor device 10 further includes a gate layer 24 disposed on a portion of electron supply layer 20 and a gate electrode 26 disposed on gate layer 24.
The gate layer 24 is constituted by a nitride semiconductor layer (corresponding to the fourth nitride semiconductor layer) containing acceptor type impurities. Gate layer 24 may be comprised of any material with a smaller bandgap than electron supply layer 20. For example, when the electron supply layer 20 is an AlGaN layer, the gate layer 24 may be a GaN layer doped with acceptor type impurities, that is, a p-type GaN layer. The acceptor type impurity may include, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C). The acceptor type impurity may have a maximum concentration of, for example, 7×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

The gate electrode 26 is disposed on part or all of the upper surface of the gate layer 24 and forms a Schottky junction with the gate layer 24. The gate electrode 26 is constituted by one or more metal layers, and may be, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 26 may be composed of a first metal layer (for example, a Ti layer) and a second metal layer (for example, a TiN layer) provided on the first metal layer. The gate electrode 26 may have a thickness of, for example, 50 nm or more and 300 nm or less. In a configuration in which a nitride semiconductor layer containing acceptor type impurities is provided as the gate layer 24 directly under the gate electrode 26, the channel (2DEG 22) of the electron transport layer 16 disappears due to the presence of the acceptor type impurities contained in the gate layer 24. In this way, a normally-off type nitride semiconductor HEMT is realized.

Nitride semiconductor device 10 further includes a passivation layer 28 covering electron supply layer 20, gate layer 24, and gate electrode 26. The passivation layer 28 is made of, for example, a silicon nitride (SiN) film, a silicon dioxide (SiO ₂ ) film, a silicon oxynitride (SiON) film, an alumina (Al ₂ O ₃ ) film, an AlN film, and an aluminum oxynitride (AlON) film. It is composed of a single film of any one of these or a composite film containing any combination of two or more thereof.

Passivation layer 28 includes a source side opening 28A that exposes the top surface of electron supply layer 20 as source connection region 20A, and a drain side opening 28B that exposes the top surface of electron supply layer 20 as drain connection region 20B. The gate layer 24 is located between the source side opening 28A and the drain side opening 28B.

Nitride semiconductor device 10 further includes a source electrode 32 and a drain electrode 34 electrically connected to 2DEG 22.
The source electrode 32 is in contact with the source connection region 20A of the electron supply layer 20 through the source side opening 28A of the passivation layer 28, and is in ohmic contact with the 2DEG 22 directly under the electron supply layer 20. The drain electrode 34 is in contact with the drain connection region 20B of the electron supply layer 20 via the drain side opening 28B of the passivation layer 28, and is in ohmic contact with the 2DEG 22 directly under the electron supply layer 20.

The source electrode 32 and the drain electrode 34 are constituted by one or more metal layers using at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer, for example. For example, source electrode 32 and drain electrode 34 are formed of the same material.

The gate layer 24 may include a ridge portion 24A, and a source side extension portion 24B and a drain side extension portion 24C extending in opposite directions from both sides of the ridge portion 24A. In the first embodiment, the gate layer 24 has a step structure formed by a ridge portion 24A, a source side extension portion 24B, and a drain side extension portion 24C.

The ridge portion 24A corresponds to a relatively thick portion of the gate layer 24. The gate electrode 26 is located on the upper surface of the ridge portion 24A. The ridge portion 24A may have a rectangular or trapezoidal shape in a cross section taken along the XZ plane in FIG. The ridge portion 24A may have a thickness of, for example, 100 nm or more and 200 nm or less. Note that the thickness of the ridge portion 24A is the distance from the top surface of the ridge portion 24A to the bottom surface (the bottom surface of the gate layer 24 in contact with the electron supply layer 20). The thickness of this ridge portion 24A (gate layer 24) can be determined in consideration of various parameters such as gate breakdown voltage.

The source-side extension portion 24B extends from the ridge portion 24A toward the source-side opening 28A of the passivation layer 28 (in the −X direction in FIG. 1). The drain side extension portion 24C extends from the ridge portion 24A toward the drain side opening 28B of the passivation layer 28 (in the +X direction in FIG. 1). In the example of FIG. 1, the drain side extension part 24C extends longer from the ridge part 24A than the source side extension part 24B. However, the source side extension part 24B and the drain side extension part 24C may have the same length. The source side extension portion 24B may have a length of, for example, 0.2 μm or more and 0.3 μm or less in the direction from the ridge portion 24A toward the source side opening 28A. The drain side extension portion 24C may have a length of, for example, 0.2 μm or more and 0.6 μm or less in the direction from the ridge portion 24A toward the drain side opening 28B. The source side extension part 24B and the drain side extension part 24C may have a thickness of, for example, 5 nm or more and 30 nm or less.

A portion of the source electrode 32 is filled in the source side opening 28A of the passivation layer 28, and a portion of the drain electrode 34 is filled in the drain side opening 28B of the passivation layer 28.

Although the source electrode 32 is not necessarily limited to this configuration, it may include a source electrode section 32A and a source field plate section 32B continuous with the source electrode section 32A. The source electrode portion 32A includes a filling region that fills the source side opening 28A, and an upper region that is formed integrally with the filling region and is located around the source side opening 28A in plan view. The source field plate section 32B is formed integrally with the upper region of the source electrode section 32A, and includes the entire gate layer 24 (i.e., the ridge section 24A, the source side extension section 24B, and the drain side extension section) in a plan view. 24C) on the passivation layer 28.

The source field plate portion 32B has an end portion 32C near the drain electrode 34. This end portion 32C is located between the drain electrode 34 and the drain side extension portion 24C in plan view. The source field plate portion 32B extends the depletion layer toward the 2DEG 22 directly below the source field plate portion 32B when a high voltage is applied between the source and drain while the gate-source voltage is 0V. It plays a role of alleviating electric field concentration near the end of the gate electrode 26 and near the end of the gate layer 24.

[Relationship between on-resistance and on-resistance-temperature characteristics of nitride semiconductor HEMT]
As shown in FIG. 2, the electron transit layer 16 includes a plurality of superlattice layers in which a superlattice structure (superlattice layer 16A) of a first nitride semiconductor layer 16A1 and a second nitride semiconductor layer A2 is repeatedly stacked. Contains 16A. As described above, the first nitride semiconductor layer 16A1 is an AlN layer, and the second nitride semiconductor layer 16A2 is, for example, a GaN layer in the first embodiment. Therefore, each superlattice layer 16A can be regarded as a layer containing Al and mainly composed of GaN. By employing such a superlattice layer 16A as the electron transit layer 16, it is possible to obtain the advantages when the electron transit layer 16 is composed of an AlGaN layer, and also obtain the advantages when the electron transit layer 16 is composed of a GaN layer. be able to. This point will be explained below. Note that for ease of understanding, components similar to those in FIG. 1 will be described below using the same reference numerals.

Generally, in a nitride semiconductor HEMT in which the electron transit layer 16 is made of a GaN layer and the electron supply layer 20 is made of an AlGaN layer, the on-resistance is highly temperature dependent, and the on-resistance decreases as the temperature rises. To increase. This is because when the electron transit layer 16 is composed of only a GaN layer, lattice scattering due to thermal energy increases in the GaN crystal of the electron transit layer 16, and the mobility of the 2DEG 22 used as a channel decreases. caused by.

Such temperature dependence of on-resistance can be solved by using an AlGaN layer having an Al composition smaller than that of the AlGaN layer used for the electron supply layer 20, that is, an AlGaN layer with a low Al composition for the electron transport layer 16. This can be improved by When the electron transit layer 16 is composed of an AlGaN layer with a low Al composition and the electron supply layer 20 is composed of an AlGaN layer with a high Al composition, the electron transit layer 16 is composed of a GaN layer and the electron supply layer 20 is composed of a GaN layer. The temperature dependence of the on-resistance can be reduced compared to the case where the transistor is composed of an AlGaN layer. This is because when an AlGaN layer with a low Al composition is used for the electron transit layer 16, lattice scattering due to thermal energy occurs in the AlGaN crystal of the electron transit layer 16 (GaN (compared to the case where a layer is used). Therefore, by using an AlGaN layer for the electron transit layer 16, the on-resistance-temperature characteristics of the nitride semiconductor HEMT can be improved.

On the other hand, the GaN layer is superior to the AlGaN layer in terms of crystal quality. Therefore, in a nitride semiconductor HEMT using a GaN layer for the electron transit layer 16, a smaller normalized on-resistance can be obtained compared to one using an AlGaN layer for the electron transit layer 16. This is because the GaN layer, which has excellent crystal quality, has smaller scattering factors (less lattice scattering) than the AlGaN layer, thereby suppressing a decrease in the mobility of the 2DEG 22. Note that the normalized on-resistance refers to the on-resistance per unit area. Therefore, in a nitride semiconductor HEMT using a GaN layer for the electron transit layer 16, the normalized on-resistance can be lowered and the current density can be increased compared to one using an AlGaN layer for the electron transit layer 16.

In consideration of the above, in the first embodiment, a plurality of superlattice layers in which the superlattice layer 16A of the first nitride semiconductor layer 16A1, which is an AlN layer, and the second nitride semiconductor layer A2, which is a GaN layer, are repeatedly laminated. Layer 16A is applied to electron transport layer 16. In a nitride semiconductor HEMT using such an electron transit layer 16, in addition to the effect of reducing the temperature dependence of on-resistance obtained when using an AlGaN layer for the electron transit layer 16, a GaN layer is used for the electron transit layer 16. It is possible to obtain the effect of reducing the normalized on-resistance that can be obtained when using.

[Function of nitride semiconductor device]
Next, the operation of the nitride semiconductor device 10 will be explained.
The electron transport layer 16 includes a plurality of superlattice layers 16A. Each superlattice layer 16A has a superlattice structure of a first nitride semiconductor layer 16A1 made of AlN and a second nitride semiconductor layer 16A2 containing GaN, and in the first embodiment, an AlN layer and a GaN layer are used. It has a superlattice structure. The second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A is provided as the uppermost layer of the electron transit layer 16, and 2DEG22 is generated in the second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A.

In this configuration, lattice scattering in each superlattice layer 16A at high temperatures is reduced (as in the case where the electron transport layer 16 is composed of an AlGaN layer), thereby suppressing a decrease in the mobility of the 2DEG 22. This reduces the temperature dependence of the on-resistance of the nitride semiconductor HEMT (nitride semiconductor device 10), thereby improving the on-resistance-temperature characteristics, compared to the case where the electron transit layer 16 is composed of a GaN layer. be able to.

Further, in the electron transit layer 16 using the superlattice layer 16A of an AlN layer and a GaN layer, the same crystal quality as in the case where the electron transit layer 16 is composed of a GaN layer is maintained at the location where the 2DEG 22 occurs. Therefore, in the electron transit layer 16 using the superlattice layer 16A, the normalized on-resistance is reduced by reducing scattering factors compared to the case where the electron transit layer 16 is composed of an AlGaN layer.

As a result, by using the superlattice layer 16A for the electron transit layer 16, the normalized on-resistance can be reduced in the same way as when the electron transit layer 16 is composed of a GaN layer, while the electron transit layer 16 is made of a GaN layer. It is possible to reduce the temperature dependence of the on-resistance and achieve good on-resistance-temperature characteristics compared to the case where the on-resistance is configured.

The nitride semiconductor device 10 of the first embodiment has the following advantages.
(1-1) The electron transport layer 16 of the nitride semiconductor device 10 is formed by repeatedly stacking a superlattice layer 16A of a first nitride semiconductor layer 16A1 made of AlN and a second nitride semiconductor layer 16A2 containing GaN. The superlattice layer 16A includes a plurality of superlattice layers 16A. In a nitride semiconductor HEMT in which the electron transit layer 16 is composed of such a superlattice layer 16A, the temperature dependence of the on-resistance is reduced compared to the case where the electron transit layer 16 is composed of a GaN layer, and good on-state performance is achieved. It is possible to realize resistance-temperature characteristics. Furthermore, the normalized on-resistance can be reduced similarly to the case where the electron transit layer 16 is composed of a GaN layer.

(1-2) The number of layers of the superlattice layer 16A is 10 or more and 100 or less. By increasing the number of superlattice layers 16A, the breakdown voltage of the nitride semiconductor HEMT can be improved. Therefore, by increasing the number of superlattice layers 16A while obtaining the advantage (1-1) above, a desired breakdown voltage (for example, 650V breakdown voltage) required for a nitride semiconductor HEMT can be achieved.

(1-3) The thickness of the second nitride semiconductor layer 16A2 is greater than the thickness of the first nitride semiconductor layer 16A1. According to this configuration, the superlattice layer 16A can be configured as a layer that makes better use of the characteristics of the second nitride semiconductor layer 16A2 containing GaN. For example, the second nitride semiconductor layer 16A2 may be a GaN layer. In this case, the superlattice layer 16A is composed mainly of GaN while containing Al. Thereby, the electron transit layer 16 can be configured by the superlattice layer 16A that takes advantage of the characteristics of GaN.

(1-4) The electron transit layer 16 may include a base layer 16B made of a GaN layer. With this configuration, the electron transit layer 16 including the plurality of superlattice layers 16A can be formed with a sufficient thickness, so that the crystal quality of the electron transit layer 16 can be improved.

(1-5) The nitride semiconductor device 10 includes a spacer layer 18 disposed between the electron supply layer 20 and the second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A. The spacer layer 18 is made of a nitride semiconductor layer containing AlN. By providing such a spacer layer 18, the mobility of the 2DEG 22 can be improved and the on-resistance of the nitride semiconductor HEMT can be reduced.

(1-6) The Al composition of the spacer layer 18 is greater than or equal to the Al composition of each superlattice layer 16A. With this configuration, 2DEG 22 can be more stably generated in the second nitride semiconductor layer 16A2 of the uppermost superlattice layer 16A.

(1-7) The thickness of the spacer layer 18 is equal to or less than the thickness of the first nitride semiconductor layer 16A1 of each superlattice layer 16A. With this configuration, it is possible to suppress an increase in ohmic resistance due to the thickness of the spacer layer 18 existing between the 2DEG 22 and the source electrode 32 and between the 2DEG 22 and the drain electrode 34.

(1-8) The electron supply layer 20 may be an AlGaN layer. In this case, the Al composition of the spacer layer 18 is larger than that of the electron supply layer 20. With this configuration, the effect of using the spacer layer 18, that is, the effect of improving the mobility of the 2DEG 22 can be further enhanced.

(1-9) Spacer layer 18 may be an AlN layer. In this case, the spacer layer 18 can be configured with the same configuration as the first nitride semiconductor layer 16A1 (ie, AlN layer) of each superlattice layer 16A. With this configuration, the manufacturing process of the nitride semiconductor device 10 including the spacer layer 18 can be facilitated.

(1-10) Nucleation layer 13, buffer layer 14, electron transport layer 16 (base layer 16B and plurality of superlattice layers 16A), spacer layer 18, electron supply layer 20, and gate layer 24 are arranged on substrate 12. They can be formed sequentially by epitaxial growth. In this case, by using a relatively inexpensive silicon substrate as the substrate 12, the nitride semiconductor device 10 can be manufactured at low cost.

[Second embodiment]
FIG. 3 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10A according to the second embodiment. In FIG. 3, the same components as those of the nitride semiconductor device 10 according to the first embodiment are given the same reference numerals. In the following, descriptions of components similar to those in the first embodiment will be omitted, and components different from those in the first embodiment will be described.

As shown in FIG. 3, in the nitride semiconductor device 10A according to the second embodiment, the electron supply layer 20 has a first opening 20C communicating with the source side opening 28A of the passivation layer 28, and a first opening 20C communicating with the source side opening 28A of the passivation layer 28. A second opening 20D that communicates with the drain side opening 28B is included. Note that, like the first embodiment, the nitride semiconductor device 10 according to the second embodiment also has a spacer layer 18 between the electron transit layer 16 and the electron supply layer 20, as shown in FIG. However, the spacer layer 18 is not shown in FIG. 3 to simplify the illustration.

In the second embodiment, the first opening 20C of the electron supply layer 20 exposes the upper surface of the spacer layer 18 (see FIG. 2) as the source connection region 18A, while the second opening 20D of the electron supply layer 20 exposes the upper surface of the spacer layer 18 (see FIG. 2). The upper surface of spacer layer 18 (see FIG. 2) is exposed as drain connection region 18B. Therefore, the source electrode 32 (source electrode part 32A in the example of FIG. 3) is in contact with the spacer layer 18 (see FIG. 2) via the first opening 20C of the electron supply layer 20, and the drain electrode 34 is in contact with the spacer layer 18 (see FIG. 2). The supply layer 20 is in contact with the spacer layer 18 (see FIG. 2) through the second opening 20D. The source electrode 32 and the drain electrode 34 are in ohmic contact with the 2DEG 22. In the second embodiment, the source electrode 32 and the drain electrode 34 may be made of an electrode material containing gold (Au), for example, four layers including a Ti layer, an AlCu layer, a Ti layer, and an Au layer.

The nitride semiconductor device 10A of the second embodiment has the following advantages in addition to the advantages (1-1) to (1-10) of the first embodiment.
(2-1) In the second embodiment, the electron supply layer 20 exposed in the source-side opening 28A and drain-side opening 28B of the passivation layer 28 is removed. Therefore, compared to the first embodiment in which the source electrode 32 is in ohmic contact with the 2DEG 22 via the electron supply layer 20 and the spacer layer 18, in the second embodiment, the source electrode 32 is in ohmic contact with the 2DEG 22 via the spacer layer 18 only. Ohmic contact. Similarly, compared to the first embodiment in which the drain electrode 34 is in ohmic contact with the 2DEG 22 via the electron supply layer 20 and the spacer layer 18, in the second embodiment, the drain electrode 34 is in ohmic contact with the 2DEG 22 via the spacer layer 18 only. Ohmic contact. Thereby, the ohmic resistance between the 2DEG 22 and the source electrode 32 and the ohmic resistance between the 2DEG 22 and the drain electrode 34 can be reduced.

(2-2) The source electrode 32 and the drain electrode 34 may be made of an electrode material containing Au (for example, four layers of a Ti layer, an AlCu layer, a Ti layer, and an Au layer). When a nitride semiconductor HEMT is put into practical use, for example, as a communication device for RF (Radio Frequency), it is desirable to reduce the ohmic resistance as described above. In this case, by using an electrode material containing Au for the source electrode 32 and the drain electrode 34, the ohmic resistance can be reduced. Therefore, in addition to the above advantage (2-1), the nitride semiconductor HEMT of the second embodiment can have a configuration suitable for an RF communication device.

[Example of change]
Each of the above embodiments can be modified and implemented as follows. Moreover, each of the above embodiments and each of the following modified examples can be implemented in combination with each other within a technically consistent range.

- In each of the above embodiments, the nitride semiconductor device 10 is configured as a nitride semiconductor HEMT, but is not limited to a nitride semiconductor HEMT, and may be configured as a nitride semiconductor diode. For example, on the substrate 12, a nucleation layer 13, a buffer layer 14, a base layer 16B (optional) of the electron transit layer 16, a plurality of superlattice layers 16A of the electron transit layer 16, a spacer layer 18 (optional) The nitride semiconductor layer structure shown in FIG. 2 in which the electron supply layer 20 and electron supply layer 20 are sequentially formed by epitaxial growth may be adopted as a nitride semiconductor diode. The advantages of the structure of the present disclosure are obtained by employing a plurality of superlattice layers 16A in the electron transit layer 16 in the nitride semiconductor layer structure of FIG.

- In each of the above embodiments, the nitride semiconductor device 10 is configured as a normally-off type nitride semiconductor HEMT, but may be configured as a normally-on type nitride semiconductor HEMT.

- In the electron transit layer 16 having a superlattice structure, the second nitride semiconductor layer 16A2 containing GaN is not limited to a GaN layer, and may be, for example, an AlGaN layer. Also in this case, the Al composition of the electron supply layer 20 (for example, AlGaN layer) is different from that of each superlattice layer 16A (in this modification, the first nitride semiconductor layer 16A1 of the AlN layer and the second nitride semiconductor layer 16A2 of the AlGaN layer). It is set to have a larger band gap than the Al composition of the superlattice structure (with a superlattice structure). Note that, as explained in the first embodiment, GaN is superior to AlGaN in terms of crystal quality, so from the viewpoint of maintaining good on-resistance-temperature characteristics, it is preferable to use GaN in the second nitride semiconductor layer 16A2. Good to use.

- The electron transit layer 16 may be composed only of the plurality of superlattice layers 16A. That is, the base layer 16B is not essential and may be omitted from the electron transport layer 16.
- The spacer layer 18, ie, the fifth nitride semiconductor layer containing AlN, is not limited to an AlN layer, and may be, for example, an AlGaN layer. In this case as well, the relationship in Al composition between the spacer layer 18 and each superlattice layer 16A and the relationship in Al composition between the spacer layer 18 and the electron supply layer 20 are as explained in the first embodiment. Relationships are maintained.

- In each of the above embodiments, the spacer layer 18 may be omitted.
- As used in this disclosure, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "the first layer is formed on the second layer" refers to the fact that in some embodiments the first layer may be directly disposed on the second layer in contact with the second layer, but in other embodiments. It is contemplated that the first layer may be placed above the second layer without contacting the second layer. That is, the term "on" does not exclude structures in which other layers are formed between the first layer and the second layer. For example, in each of the above embodiments in which the electron supply layer 20 is formed on the electron transit layer 16, an intermediate layer (for example, each of the above It also includes a structure in which a spacer layer 18) as in the embodiment is located.

- The Z-axis direction used in the present disclosure does not necessarily need to be a vertical direction, nor does it need to completely coincide with the vertical direction. Accordingly, in various structures according to the present disclosure (e.g., the structure shown in FIG. 1), "upper" and "lower" in the Z-axis direction described herein are "upper" and "lower" in the vertical direction. Not limited to one thing. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

・“Vertical”, “horizontal”, “above”, “downward”, “above”, “bottom”, “front”, “backward”, “lateral”, “left”, “right” used in this disclosure , "front", "back", etc., are dependent upon the particular orientation of the device described and illustrated. Various alternative orientations may be envisioned in this disclosure, and therefore, these directional terms should not be construed narrowly.

[Additional notes]
The technical ideas that can be grasped from each of the above embodiments and modifications are described below. Note that the reference numerals of the constituent elements of the embodiment corresponding to the constituent elements described in each supplementary note are shown in parentheses. The symbols are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the symbols.

(Appendix A1)
Includes a plurality of superlattice layers (16A) in which superlattice layers (16A) of a first nitride semiconductor layer (16A1) made of AlN and a second nitride semiconductor layer (16A2) containing GaN are stacked repeatedly. In the electron transit layer (16), the second nitride semiconductor layer (16A2) of the uppermost superlattice layer (16A) among the plurality of superlattice layers (16A) is the electron transit layer (16). the electron transit layer (16) provided as the top layer;
In order to generate a two-dimensional electron gas (22) in the second nitride semiconductor layer (16A2) of the uppermost superlattice layer (16A), a second nitride semiconductor layer (16A2) having a larger band gap than each superlattice layer (16A) is used. an electron supply layer (20) constituted by a trinitride semiconductor layer;
a gate layer (24) disposed on a portion of the electron supply layer (20) and constituted by a fourth nitride semiconductor layer containing acceptor type impurities;
a gate electrode (26) disposed on the gate layer (24);
a source electrode (32) and a drain electrode (34) electrically connected to the two-dimensional electron gas (22);
A nitride semiconductor device (10; 10A) comprising:

(Appendix A2)
The nitride semiconductor device (10; 10A) according to appendix A1, wherein the number of layers of the plurality of superlattice layers (16A) is 10 or more and 100 or less.

(Appendix A3)
The nitride semiconductor device (10; 10A) according to appendix A1 or A2, wherein the second nitride semiconductor layer (16A2) is thicker than the first nitride semiconductor layer (16A1).

(Appendix A4)
The thickness of the first nitride semiconductor layer (16A1) is 1 nm or more and 3 nm or less,
The nitride semiconductor device (10; 10A) according to appendix A3, wherein the second nitride semiconductor layer (16A2) has a thickness of 2 nm or more and 6 nm or less.

(Appendix A5)
further comprising a spacer layer (18) disposed between the electron supply layer (20) and the second nitride semiconductor layer (16A2) of the uppermost superlattice layer (16A),
The nitride semiconductor device (10; 10A) according to any one of appendices A1 to A4, wherein the spacer layer (18) is constituted by a fifth nitride semiconductor layer containing AlN.

(Appendix A6)
The nitride semiconductor device (10; 10A) according to appendix A5, wherein the Al composition of the spacer layer (18) is greater than or equal to the Al composition of each of the superlattice layers (16A).

(Appendix A7)
The nitride semiconductor device (10; 10A) according to appendix A5 or A6, wherein the spacer layer (18) has a thickness equal to or less than the first nitride semiconductor layer (16A1).

(Appendix A8)
The nitride semiconductor device (10; 10A) according to any one of appendices A5 to A7, wherein the spacer layer (18) is an AlN layer or an AlGaN layer.

(Appendix A9)
The source electrode (32) is in contact with the spacer layer (18) through the first opening (20C) of the electron supply layer (20), and the drain electrode (34) is in contact with the spacer layer (18) through the first opening (20C) of the electron supply layer (20). The nitride semiconductor device (10A) according to any one of appendices A5 to A8, which is in contact with the spacer layer (18) through the second opening (20D) of 20).

(Appendix A10)
The nitride semiconductor device (10A) according to Appendix A9, wherein the source electrode (32) and the drain electrode (34) contain Au.

(Appendix A11)
The electron supply layer (20) includes a base layer (16B) formed of a GaN layer under a plurality of superlattice layers (16A), and is a nitride according to any one of Appendices A5 to A10. Semiconductor device (10; 10A).

(Appendix A12)
The electron supply layer (20) is an AlGaN layer,
The nitride semiconductor device (10; 10A) according to any one of appendices A5 to A11, wherein the spacer layer (18) has a larger Al composition than the electron supply layer (20).

(Appendix A13)
The Al composition of the electron supply layer (20) is 25% or more and 50% or less,
The nitride semiconductor device (10; 10A) according to appendix A12, wherein the spacer layer (18) has an Al composition of 80% or more.

(Appendix A14)
The nitride semiconductor device (10; 10A) according to any one of appendices A1 to A13, wherein the second nitride semiconductor layer (16A2) is a GaN layer or an AlGaN layer.

(Appendix A15)
The electron supply layer (20) is an AlGaN layer,
The nitride semiconductor device (10; 10A).

(Appendix A16)
The electron transit layer (16) is formed on a silicon substrate (12) with a buffer layer (14) interposed therebetween, in the nitride semiconductor device (10) according to any one of appendices A1 to A15; 10A).

(Appendix B1)
a substrate (12);
a buffer layer (14) disposed on the substrate;
an electron transit layer (16) disposed on the buffer layer;
an electron supply layer (20) disposed on the electron transit layer (16),
The electron transit layer (16) is a plurality of superlattice layers (16A) in which a first nitride semiconductor layer (16A1) made of AlN and a second nitride semiconductor layer (16A2) containing GaN are repeatedly laminated. including a superlattice layer (16A) of
The second nitride semiconductor layer (16A2) of the uppermost superlattice layer (16A) among the plurality of superlattice layers (16A) is provided as the uppermost layer of the electron transport layer (16),
A nitride semiconductor device (10; 10A), wherein the electron supply layer (20) is constituted by a third nitride semiconductor layer having a larger band gap than each of the plurality of superlattice layers (16A).

(Appendix B2)
further comprising a spacer layer (18) disposed between the electron supply layer (20) and the second nitride semiconductor layer (16A2) of the uppermost superlattice layer (16A),
The nitride semiconductor device (10:10A) according to appendix B1, wherein the spacer layer (18) is constituted by a nitride semiconductor layer containing AlN.

The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible beyond those listed for the purpose of describing the techniques of the present disclosure. This disclosure is intended to cover all alternatives, variations, and modifications falling within the scope of this disclosure, including the claims.

DESCRIPTION OF SYMBOLS 10, 10A...Nitride semiconductor device 12...Substrate 14...Buffer layer 16...Electron transit layer 16A...Superlattice layer 16A1...First nitride semiconductor layer 16A2...Second nitride semiconductor layer 18...Spacer layer 20...Electron supply layer 20C...First opening 20D...Second opening 22...Two-dimensional electron gas (2DEG)
24... Gate layer 26... Gate electrode 32... Source electrode 34... Drain electrode

Claims (17)

An electron transport layer including a plurality of superlattice layers in which superlattice layers of a first nitride semiconductor layer made of AlN and a second nitride semiconductor layer containing GaN are stacked repeatedly, the plurality of superlattice layers being stacked repeatedly. the electron transit layer in which the second nitride semiconductor layer of the uppermost superlattice layer among the layers is provided as the uppermost layer of the electron transit layer;
In order to generate two-dimensional electron gas in the second nitride semiconductor layer of the uppermost superlattice layer, an electron supply layer constituted by a third nitride semiconductor layer having a larger band gap than each of the superlattice layers. and,
a gate layer disposed on a portion of the electron supply layer and configured with a fourth nitride semiconductor layer containing acceptor type impurities;
a gate electrode disposed on the gate layer;
a source electrode and a drain electrode electrically connected to the two-dimensional electron gas;
A nitride semiconductor device comprising: The nitride semiconductor device according to claim 1, wherein the number of the plurality of superlattice layers is 10 or more and 100 or less. 3. The nitride semiconductor device according to claim 1, wherein the second nitride semiconductor layer has a thickness greater than the first nitride semiconductor layer. The thickness of the first nitride semiconductor layer is 1 nm or more and 3 nm or less,
The nitride semiconductor device according to claim 3, wherein the second nitride semiconductor layer has a thickness of 2 nm or more and 6 nm or less. further comprising a spacer layer disposed between the electron supply layer and the second nitride semiconductor layer of the uppermost superlattice layer,
The nitride semiconductor device according to any one of claims 1 to 4, wherein the spacer layer is constituted by a fifth nitride semiconductor layer containing AlN. 6. The nitride semiconductor device according to claim 5, wherein the Al composition of the spacer layer is greater than or equal to the Al composition of each of the superlattice layers. 7. The nitride semiconductor device according to claim 5, wherein the spacer layer has a thickness less than or equal to the first nitride semiconductor layer. The nitride semiconductor device according to claim 5, wherein the spacer layer is an AlN layer or an AlGaN layer. The source electrode is in contact with the spacer layer through a first opening of the electron supply layer, and the drain electrode is in contact with the spacer layer through a second opening of the electron supply layer. The nitride semiconductor device according to any one of claims 5 to 8. The nitride semiconductor device according to claim 9, wherein the source electrode and the drain electrode contain Au. The electron supply layer is an AlGaN layer,
The nitride semiconductor device according to any one of claims 5 to 10, wherein the spacer layer has a larger Al composition than the electron supply layer. The Al composition of the electron supply layer is 25% or more and 50% or less,
The nitride semiconductor device according to claim 11, wherein the spacer layer has an Al composition of 80% or more. The nitride semiconductor device according to claim 1, wherein the second nitride semiconductor layer is a GaN layer or an AlGaN layer. The electron supply layer is an AlGaN layer,
14. The nitride semiconductor device according to claim 1, wherein the gate layer is a GaN layer containing at least one of Mg and Zn as the acceptor type impurity. The nitride semiconductor device according to claim 1, wherein the electron transit layer is formed on a silicon substrate with a buffer layer interposed therebetween. A substrate and
a buffer layer disposed on the substrate;
an electron transport layer disposed on the buffer layer;
an electron supply layer disposed on the electron transit layer,
The electron transport layer includes a plurality of superlattice layers in which superlattice layers of a first nitride semiconductor layer made of AlN and a second nitride semiconductor layer containing GaN are stacked repeatedly,
The second nitride semiconductor layer of the uppermost superlattice layer among the plurality of superlattice layers is provided as the uppermost layer of the electron transport layer,
A nitride semiconductor device, wherein the electron supply layer is constituted by a third nitride semiconductor layer having a larger band gap than each of the plurality of superlattice layers. further comprising a spacer layer disposed between the electron supply layer and the second nitride semiconductor layer of the uppermost superlattice layer,
17. The nitride semiconductor device according to claim 16, wherein the spacer layer is constituted by a nitride semiconductor layer containing AlN.

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