JP2023143612A - Reference potential generation circuit and semiconductor storage device - Google Patents

Abstract

To provide a reference potential generation circuit and a semiconductor storage device capable of generating a reference potential of a sense amplifier that can reduce influence of temperature, increase a read margin, and operate with high reliability.SOLUTION: A reference potential generation circuit of the embodiment includes an original reference potential generation unit for generating an original reference potential and a reference potential correction unit for lowering the original reference potential according to the temperature rising and outputting the potential to a sense amplifier as a reference potential.SELECTED DRAWING: Figure 2

Description

Embodiments of the present invention relate to a reference potential generation circuit and a semiconductor memory device.

In a semiconductor memory device, when reading data, the sense amplifier is activated after the bit line reaches a potential sufficient to determine the output of the sense amplifier. At this time, the reference potential of the sense amplifier is set so as to absorb variations in the characteristics of the transistors used in the sense amplifier and to reliably determine the level of the read signal.

Japanese Patent Application Publication No. 2012-113769

By the way, the change in the potential of the read signal varies depending on the temperature such as the ambient temperature. Assuming that the reference potential of the sense amplifier is the same and the value of the memory cell is "0", the read margin ( The lower the temperature, the smaller the data read margin (difference between the level of the signal being read and the level of the reference signal used for judgment) becomes smaller, and if the value of the memory cell is "1". .

One embodiment of the present invention provides a reference potential generation circuit and a semiconductor memory device that can generate a reference potential for a sense amplifier that can reduce the influence of temperature, increase the read margin, and operate with high reliability. With the goal.

The reference potential generation circuit of the embodiment includes an original reference potential generation section that generates an original reference potential, and a reference potential correction section that lowers the original reference potential as the temperature rises and outputs it as a reference potential to a sense amplifier. Be prepared.

FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment. FIG. 2 is an explanatory diagram of an example of the configuration of main parts of the sense amplifier circuit. FIG. 3 is an explanatory diagram of conventional problems. FIG. 4 is an explanatory diagram of the operation of the embodiment.

A semiconductor memory device according to an embodiment will be described in detail below with reference to the drawings.
Note that the present invention is not limited to these embodiments.

FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment.
The semiconductor device 10 is configured as a NOR flash memory, and as shown in FIG. A control circuit 17 is provided.

The memory cell array 11 includes a plurality of memory cells MC arranged in a grid pattern.
Further, the memory cell array includes a plurality of word lines WL, a plurality of source lines SL, and a plurality of bit lines BL.

In FIG. 1, for ease of understanding, only one memory cell MC in a selected state is shown, and only the word line WL, source line SL, and bit line BL corresponding to the memory cell are shown.

Here, the memory cell MC includes a memory cell transistor TR whose source terminal is connected to the source line SL, whose gate terminal is connected to the word line WL, and whose drain terminal is connected to the bit line BL.

Under the control of the control circuit 17, the row decoder 12 enables the word line WL corresponding to the memory cell MC to be read.
Under the control of the control circuit 17, the column decoder 13 enables the source line SL and bit line BL corresponding to the memory cell MC to be read.

The reference potential generation circuit 14 generates and supplies a reference potential to the sense amplifier circuit 15.
The sense amplifier circuit 15 compares the potential of the bit line corresponding to the selected memory cell MC with a reference potential at a predetermined timing, determines the data of the memory cell MC, and transmits the determination result to the data output circuit. Output to 16.

Data output circuit 16 outputs read data DOUT based on the output of sense amplifier circuit 15.
The control circuit 17 includes a row decoder so as to write, read, or erase data in the corresponding memory cell MC based on a clock signal CLK, command data CMD, and address data ADD from a host device (for example, MPU, not shown). 12, controls the column decoder 13 and sense amplifier circuit 15;

Next, the configuration of the sense amplifier circuit 15 will be explained.
FIG. 2 is an explanatory diagram of an example of the configuration of main parts of the sense amplifier circuit.
The sense amplifier circuit 15 includes a sense amplifier 151, a sense timing generation circuit 152, a reference current generation circuit 153, and a reference potential generation circuit 154.

In this case, the sense amplifier 151 and the sense timing generation circuit 152 are respectively provided corresponding to a plurality of blocks BLK.
In this case, the sense timing generation circuit 152 can also be shared by a plurality of sense amplifiers 151.

In the above configuration, the reference current generation circuit 153 generates the reference current control potential IREF and outputs it to the sense timing generation circuit 152 and the reference potential generation circuit 154.
The reference potential generation circuit 154 generates a reference potential Vref corresponding to the ambient temperature based on the reference current control potential IREF, and outputs it to the inverting input terminal of the sense amplifier 151.

The sense timing generation circuit 152 has one or more delay circuits (not shown), and enables the sense amplifier 151 at a timing corresponding to the current value of the reference current control potential IREF input from the reference current generation circuit 153. Outputs sense amplifier enable signal SAE.

As a result, the sense amplifier 151 receives the input signal IN from the bit line BL of each block BLK to the non-inverting input terminal, receives the reference potential Vref to the inverting input terminal, and receives the input signal IN from the sense timing generation circuit 152. When the enable signal SAE is in the enabled state and the input signal IN is at a voltage higher than the reference potential Vref, the output signal OUT at "H" level is output.

Furthermore, when the sense amplifier enable signal SAE from the sense timing generation circuit 152 is in an enabled state and the input signal IN is at a voltage lower than the reference potential Vref, the sense amplifier 151 outputs an output signal OUT at the "L" level. do.

The reference current generation circuit 153 is roughly divided into a current value setting section 153A, a current mirror 153B, and a current source 153C.

The current value setting units 153A are connected in parallel (n is an integer of 2 or more), and set the gate terminal to the “H” level or “L” level based on the trimming information read from the fuse or flash memory. Accordingly, N-channel MOS transistors TT1 to TTn for trimming whose number of parallel connections is variable are provided.

The current mirror 153B has a source terminal connected to a high potential side power supply VDD, a drain terminal connected to a current setting section 153A, a P channel MOS transistor PM1 whose drain terminal and gate terminal are connected, and a P channel MOS transistor PM1 whose source terminal is connected to a high potential side. The P-channel MOS transistor PM2 is connected to the power supply VDD, has a drain terminal connected to the current source 153C, and has a gate terminal connected to the gate terminal of the P-channel MOS transistor.

The current source 153C includes an N-channel MOS transistor whose drain terminal and gate terminal are connected (diode-connected).

In the above configuration, the trimming N-channel MOS transistors TT1 to TTn are set so that the drain-source current in the on state has a positive temperature coefficient, and the higher the temperature, the larger the drain-source current. It's supposed to be.

The current flowing through the P-channel MOS transistor PM1 flows through all of the trimming N-channel MOS transistors whose gates are set to the "H" level among the trimming N-channel MOS transistors TT1 to TTn of the current value setting section 153A. The current value is proportional to the current value of the current.

Therefore, the current value of the current flowing through the P-channel MOS transistor PM2, that is, the current value of the current of the reference current control potential IREF, also changes when the gate of the trimming N-channel MOS transistors TT1 to TTn of the current value setting section 153A is "H". The current value is proportional to the current value of the current flowing through the entire trimming N-channel MOS transistor set to the "level."
Here, the reference current control potential IREF functions as a control signal.

As a result, in the current value setting unit 153A, after trimming, a reference current proportional to the number of trimming N-channel MOS transistors TT connected in parallel flows between the drain terminal and the source terminal of the P-channel MOS transistor PM1 of the current mirror 153B. flows.

As a result, a current proportional to the number of trimming N-channel MOS transistors TT connected in parallel after trimming flows between the drain terminal and source terminal of the P-channel MOS transistor PM2, and the reference current control potential IREF which functions as a control signal flows. It will be outputted to the sense timing generation circuit 152 as a signal.

The sense timing generation circuit 152 is configured to change the sense timing according to the reference current control potential IREF, and the larger the reference current control potential is, the earlier the sense timing is, and the smaller the reference current control potential IREF is, the faster the sense timing is. Become slow. Trimming is set for each chip and the reference current control potential IREF is adjusted so that the sense timing is constant regardless of process variations.

As a result, the sense timing generation circuit 152 receives the reference current control potential IREF in which process variations have been absorbed, and enables the sense amplifier enable signal at a timing corresponding to the current value of the reference current control potential IREF. .

Next, the configuration of the reference potential generation circuit 154 will be explained.
The reference potential generation circuit 154 includes an original reference voltage generation unit 154A that generates and outputs the original reference potential Vref0, and a sense amplifier 151 that performs temperature compensation on the original reference potential Vref0 based on the reference current control potential IREF and uses it as a reference potential Vref. The reference voltage correction unit 154B outputs the output to the inverting input terminal of the reference voltage correction unit 154B.
The original reference voltage generation unit 154A includes a resistor R1 having one end connected to the high potential side power supply VDD, and a resistor R2 having one end connected to the other end of the resistor R1 and the other end connected to the low potential side power supply VSS. The differential voltage between the voltage of the high potential side power supply VDD and the voltage of the low potential side power supply VSS is divided and outputted as the original reference potential Vref0.
The reference voltage correction unit 154B has a drain terminal connected to the connection point between the resistor R1 and the resistor R2, a source terminal connected to the low potential side power supply VSS, and a gate terminal connected to the gate terminal of the N-channel MOS transistor constituting the current source 153C. It has an N-channel MOS transistor NM1 whose terminals are connected.

In this case, a reference current control potential IREF as a control signal is supplied to the gate terminal of the N-channel MOS transistor NM1, and a bias voltage corresponding to the reference current control potential IREF is applied.
As a result, the N-channel MOS transistor NM1 enters an on state corresponding to the bias voltage, pulls down the original reference potential Vref0, and outputs it to the inverting input terminal of the sense amplifier 151 as a desired reference potential Vref.

Next, the operation of the embodiment will be explained.
First, prior to the operation of the embodiment, conventional problems will be explained.
FIG. 3 is an explanatory diagram of conventional problems.
In conventional sense amplifiers, the input reference potential is constant.

By the way, when reading from a flash memory that supports a wide temperature range (for example, −40 to 175° C.), the fluctuation state of the read voltage differs depending on the value stored in the memory cell and the temperature.

More specifically, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is high, the memory cell transistor TR remains in the off state even if the word line WL goes to "H" level. Therefore, the potential of the bit line BL remains approximately at the power supply potential.

However, due to the leakage current of the memory cell transistor TR, the potential of the bit line BL gradually decreases, albeit slightly.
In general, the leakage current of memory cell transistor TR tends to increase as the temperature increases. Therefore, as the temperature increases, as shown in FIG. 3, the potential of the bit line BL decreases faster when reading a value=0 stored in the memory cell MC.

Therefore, as the operating temperature range becomes higher, there is a possibility that the data read margin MG0 with respect to the reference potential Vref becomes insufficient, and there is a possibility that the read data may be erroneous.

On the other hand, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is low, when the word line WL becomes high level, the memory cell transistor TR turns on, and the voltage from the bit line BL to the source line SL is turned on. An on-current flows, and the potential of the bit line BL gradually decreases.

In general, the on-current of the memory cell transistor TR tends to decrease as the temperature decreases, so as the temperature decreases, the potential of the bit line BL decreases when reading the value = 1 stored in the memory cell MC, as shown in FIG. is delayed.

Therefore, as the operating temperature range becomes lower, there is a possibility that the data read margin MG1 with respect to the reference potential Vref becomes insufficient, and there is a possibility that the read data may be erroneous.

Next, the operation of the embodiment will be explained with reference to FIG. 2 again.
FIG. 4 is an explanatory diagram of the operation of the embodiment.
In this case, the reference potential Vref output from the reference potential generation section 154 is configured to decrease as the temperature increases.
That is, as shown in FIG. 4, the reference potential VrefH at a predetermined high temperature is lower than the reference potential VrefL at a predetermined low temperature.

More specifically, the drain-source current in the ON state of the trimming N-channel MOS transistors TT1 to TTn is such that the higher the temperature, the larger the drain-source current becomes, and the drain-source current becomes larger than the predetermined reference temperature. , in the case of high temperature, the current value becomes higher than the current value at the predetermined reference temperature.

Therefore, the current value of the current flowing through P-channel MOS transistor PM2, that is, the current value of the reference current control potential IREF, is also higher than the predetermined reference temperature, and in the case of a higher temperature than the current value at the predetermined reference temperature. This results in a high current value.

In parallel with this, the original reference voltage generation unit 154A of the reference potential generation circuit 154 divides the voltage corresponding to the difference potential between the high potential side power supply VDD and the low potential side power supply VSS, and generates the original reference potential Vref0. Generate and output.

At this time, the reference voltage correction unit 154B performs temperature compensation based on the voltage corresponding to the reference current control potential IREF to correct the reference potential Vref.

That is, the current value of the current of the reference current control potential IREF is higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and when the current value is lower than the predetermined reference temperature. The current value is lower than the current value at a predetermined reference temperature.

As a result, the on-resistance of the N-channel MOS transistor constituting the reference voltage correction section 154B becomes lower than the on-resistance at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature. When the temperature is lower than that, the on-resistance becomes higher than the on-resistance at a predetermined reference temperature.

The reference potential Vref outputted to the inverting input terminal of the sense amplifier 151 is a reference potential VrefH at a high temperature, which is lower than the reference potential at a predetermined reference temperature when the temperature is high, and the reference potential VrefH when the temperature is low. Vref is a reference potential VrefL (>VrefH) at a low temperature, which is higher than the reference potential at a predetermined reference temperature.

Therefore, when reading the value=0 stored in the memory cell and the temperature is high, the reference potential Vref=the reference potential VrefH.
As a result, as shown in the signal waveform HT0 in FIG. 4, even if the read voltage is greatly reduced due to the current flowing between the drain and source of the transistor that constitutes the memory cell to be read, the vertical line in FIG. At the timing when the sense amplifier enable signal SAE shown by the broken line is in the enabled state, a sufficiently large data read margin MGH0 from the reference potential VrefH can be ensured, and the read data will not be erroneous.
However, if the reference potential VrefH is too low, when reading the value 1 stored in the memory cell at a high temperature, the data read margin MGH1 decreases, and there is a risk that the read data will be erroneous.
For this reason, in this embodiment, the on-resistance of the N-channel MOS transistor NM1 constituting the reference voltage correction section 154B is set to an appropriate value so that the data read margin MGH1 does not fall below the data read margin MGH0. ing.

Further, when reading the value=1 stored in the memory cell and the temperature is low, the reference potential Vref=the reference potential VrefL.
As a result, as shown in the signal waveform LT1 in FIG. 4, even if the drop in read voltage due to the current flowing between the drain and source of the transistor constituting the memory cell to be read becomes small, the data from the reference potential VrefL is A sufficiently large read margin MGL1 can be secured, and the read data will not be erroneous.

As described above, according to the present embodiment, when the temperature rises depending on the ambient temperature, the reference potential Vref is lowered and the value stored in the memory cell is determined to be 0. Therefore, a sufficiently large data read margin MGH0 can be secured.
Furthermore, when the temperature becomes low depending on the ambient temperature, the reference potential Vref is raised to ensure a sufficiently large data read margin MGL1 when determining whether the value stored in the memory cell is 1.
Therefore, the optimum reference potential Vref can be set according to the ambient temperature, and stable and reliable determination can be made.
However, if the reference potential VrefL is too high, there is a risk that the data read margin MGL0 will decrease and the read data will be erroneous when reading the value = 0 stored in the memory cell at a low temperature.
Therefore, in the present embodiment, the on-resistance of the N-channel MOS transistor NM1 constituting the reference voltage correction section 154B is set to an appropriate value, so that the data read margin MGL0 does not fall below the data read margin MGL1. ing.

In the above description, the current value setting unit 153A has a configuration including n trimming N-channel MOS transistors TT1 to TTn connected in parallel (n is an integer of 2 or more), but A plurality of resistors or a plurality of resistors with different resistance values (for example, resistance values r, 2r, 4r, 8r, etc.) are connected in parallel, and the combined resistance value of the resistors connected to the current mirror circuit 153B is determined by trimming. It is also possible to configure the current value to be set by changing the current value.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

10 Semiconductor storage device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Reference potential generation circuit 15 Sense amplifier circuit 16 Data output circuit 17 Control circuit 151 Sense amplifier 152 Sense timing generation circuit 153 Reference current generation circuit 153A Current value setting section 153B Current mirror 153C Current source 154 Reference potential generation circuit 154A Reference voltage generation section 154B Reference voltage correction section BLK block BL, BL0 to BLk Bit line IN Input signal IREF Reference current control potential (control signal)
HT0, HT1 signal waveform (at high temperature)
LT0, LT1 Signal waveform (at low temperature) MGL Data read margin MgH Data read margin MT Memory cell NM1 N-channel MOS transistor (pull-down transistor)
OUT Output signal SAE Sense amplifier enable signal TT1 to TTn N-channel MOS transistor for trimming VDD High potential side power supply VSS Low potential side power supply Vref Reference potential VrefH Reference potential (at high temperature)
VrefL Reference potential (at low temperature)
WL, WL0 to WL63 Word line

Claims (15)

an original reference potential generation unit that generates an original reference potential;
a reference potential correction unit that lowers the original reference potential as the temperature rises and outputs it to the sense amplifier as a reference potential;
A reference potential generation circuit equipped with The reference potential correction unit receives a control signal that changes as the temperature rises, and lowers the original reference potential based on the control signal.
The reference potential generation circuit according to claim 1. A reference current control potential for controlling enable timing of the sense amplifier is applied to the reference potential correction unit as the control signal.
The reference potential generation circuit according to claim 2. The reference potential correction unit sets the enable timing to be a timing corresponding to a current value of a current accompanying application of the reference current control potential.
The reference potential generation circuit according to claim 3. The current value of the current accompanying the application of the reference current control potential is higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and is higher than the current value at the predetermined reference temperature when the temperature is lower than the predetermined reference temperature. , lower than the current value at a predetermined reference temperature,
The reference potential generation circuit according to claim 4. The reference potential correction section sets the reference potential to a high-temperature reference potential lower than the reference potential at the predetermined reference temperature when the temperature is higher than a predetermined reference temperature, and sets the reference potential to a reference potential at a high temperature that is lower than the reference potential at the predetermined reference temperature, and when the temperature is lower than the reference temperature. sets the reference potential to be a reference potential at a low temperature that is higher than the reference potential at the reference temperature;
The reference potential generation circuit according to claim 1. The reference potential correction unit includes a MOS transistor to which the reference current control potential is applied as a bias voltage to a gate terminal, and the original reference potential is pulled down to the reference potential.
The reference potential generation circuit according to claim 3. memory cells that store data;
a bit line that transmits a signal read from the memory cell;
a sense amplifier circuit that detects data stored in the memory cell based on a signal transmitted on the bit line,
The sense amplifier circuit is
a sense amplifier that compares the signal transmitted on the bit line with a reference potential and outputs a data detection signal;
a reference current generation circuit that generates and outputs a reference current control potential;
a sense timing generation circuit that controls, based on the reference current control potential, a timing at which a sense amplifier enable signal for enabling the sense amplifier is output from an output terminal;
a reference potential generation circuit having an original reference potential generation unit that generates an original reference potential; and a reference potential correction unit that lowers the original reference potential as the temperature rises and outputs it as the reference potential;
Semiconductor storage device. The reference potential correction unit lowers the original reference potential as the temperature rises based on the reference current control potential.
The semiconductor memory device according to claim 8. The reference current generation circuit includes a current value setting section that makes the set current value variable by trimming;
a current mirror circuit that duplicates a current corresponding to the set current value set by a current value setting section and outputs it as the reference current control potential;
9. The semiconductor memory device according to claim 8, comprising: A reference current control potential for controlling enable timing of the sense amplifier is applied as a control signal to the reference potential correction section.
The semiconductor memory device according to claim 9. The reference potential correction unit sets the enable timing to be a timing corresponding to a current value of a current accompanying application of the reference current control potential.
The semiconductor memory device according to claim 11. The current value of the current accompanying the application of the reference current control potential is higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and is higher than the current value at the predetermined reference temperature when the temperature is lower than the predetermined reference temperature. , lower than the current value at a predetermined reference temperature,
The semiconductor memory device according to claim 12. The reference potential correction section sets the reference potential to a high-temperature reference potential lower than the reference potential at the predetermined reference temperature when the temperature is higher than a predetermined reference temperature, and sets the reference potential to a reference potential at a high temperature that is lower than the reference potential at the predetermined reference temperature, and when the temperature is lower than the reference temperature. sets the reference potential to be a reference potential at a low temperature that is higher than the reference potential at the reference temperature;
The semiconductor memory device according to claim 8. The reference potential correction unit includes a MOS transistor to which the reference current control potential is applied as a bias voltage to a gate terminal, and the original reference potential is pulled down to the reference potential.
The semiconductor memory device according to claim 8.

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