JP2023141490A - ESD protection circuit and semiconductor device - Google Patents

Abstract

To provide an ESD protection circuit that can reduce the layout area, reduce a leakage current, and prevent malfunctions.SOLUTION: An ESD protection circuit 100 connected between a VDD terminal and a VSS terminal in parallel with an internal circuit C that operates at a specified operating voltage includes an NMOS transistor 110 in which an N-type high concentration drain region 114a is connected to the VDD terminal, and a gate 116 is in a floating state, and a high concentration source region 114b is connected to the VSS terminal, and a threshold voltage and a trigger voltage Vtrig of a parasitic bipolar transistor of the NMOS transistor 110 are higher than the operating voltage and lower than the breakdown voltage of the internal circuit C.SELECTED DRAWING: Figure 2A

Description

The present invention relates to an ESD protection circuit and a semiconductor device.

Semiconductor integrated circuits are susceptible to electrostatic discharge (ESD) and may be easily destroyed. For this reason, semiconductor integrated circuits often include an ESD protection circuit to protect internal circuits from electrostatic discharge.

This ESD protection circuit operates only when a surge voltage due to electrostatic discharge is applied to a power supply line, etc., and quickly removes the surge current from the grounding wire without destroying itself before the surge current flows to the internal circuit. etc. to protect internal circuits.
Specifically, if the source of the electrostatic discharge is the human body, the ESD protection circuit will ground the surge current of several amps before the surge voltage of several thousand volts due to the electrostatic discharge reaches the breakdown voltage of the internal circuitry. Performs the action of flowing electrical potential.

Examples of such ESD protection circuits include a diode-type ESD protection circuit that utilizes a breakdown phenomenon, and a GG (Gate Grounded)-MOS (Metal-Oxide-Semiconductor)-type ESD protection circuit that utilizes a snapback operation using a parasitic bipolar transistor. , a capacitively coupled MOS type ESD protection circuit in which a MOS transistor is turned on when a voltage with a short rise time is applied.

As an example of a capacitively coupled MOS type ESD protection circuit, the drain and source terminals of a MOS transistor are connected between each terminal (V _DD terminal, input terminal or output terminal, etc.) except the V _SS terminal and the V _SS terminal. A GG-MOS type ESD protection circuit has been proposed in which the gate terminal is connected to each terminal other than the V _SS terminal via a capacitor (see, for example, Patent Document 1).
In this capacitively coupled MOS type ESD protection circuit, the capacitor between each pad except the V _SS terminal and the gate terminal functions as a high-pass filter, so when static electricity is discharged to each pad except the V _SS terminal, the rise time The high frequency component of the short surge voltage passes through the capacitor and reaches the gate terminal. Then, the potential of the gate changes and the MOS transistor turns on, and a surge current flows to the _VSS terminal side, thereby protecting the internal circuit from electrostatic discharge.

Japanese Patent Application Publication No. 2000-269437

One aspect of the present invention is to provide an ESD protection circuit that can reduce the layout area, reduce leakage current, and prevent malfunctions.

The ESD protection circuit in one embodiment of the invention includes:
An ESD protection circuit connected in parallel with a protected circuit operating at a predetermined operating voltage between a first terminal and a second terminal,
an NMOS transistor having a drain connected to the first terminal, a gate in a floating state, and a source connected to the second terminal;
In the NMOS transistor, an avalanche breakdown voltage of a parasitic diode and a trigger voltage of a parasitic bipolar transistor are higher than the operating voltage and lower than a breakdown voltage of the protected circuit.

According to one aspect of the present invention, it is possible to provide an ESD protection circuit that can reduce the layout area, reduce leakage current, and prevent malfunctions.

FIG. 1 is a circuit diagram showing an ESD protection circuit and a semiconductor device in one embodiment of the present invention. FIG. 2A is a schematic cross-sectional view showing an example of the structure of the NMOS transistor in this embodiment. FIG. 2B is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. FIG. 2C is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. FIG. 2D is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. FIG. 2E is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. FIG. 2F is a graph showing an example of current-voltage characteristics of the ESD protection circuit in this embodiment. FIG. 3A is a schematic cross-sectional view showing another example of the structure of the NMOS transistor in this embodiment. FIG. 3B is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3C is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3D is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3E is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3F is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3G is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 3H is a schematic cross-sectional view showing still another example of the NMOS transistor in this embodiment. FIG. 4A is a circuit diagram showing an example of a conventional diode type ESD protection circuit. FIG. 4B is a graph showing an example of current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. FIG. 5A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit. FIG. 5B is a graph comparing the current-voltage characteristics of a conventional diode type ESD protection circuit and a conventional GG-MOS type ESD protection circuit. FIG. 5C is a graph comparing the current-voltage characteristics of a conventional diode type ESD protection circuit and a conventional GG-MOS type ESD protection circuit when reducing leakage current is considered. FIG. 5D is a graph comparing the current-voltage characteristics of a conventional diode type ESD protection circuit and a conventional GG-MOS type ESD protection circuit when reducing leakage current is not considered. FIG. 6A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit. FIG. 6B is a graph showing an example of current-voltage characteristics (by rise time of surge voltage) of a conventional capacitively coupled MOS type ESD protection circuit.

The present invention does not connect the gate to a low potential terminal such as ground potential as in the conventional GG-MOS type ESD protection circuit, but connects the gate to a high potential terminal from which static electricity is discharged. This is based on the knowledge that it can be protected.
As a result, in one embodiment of the present invention, the layout area can be made smaller than that of a conventional diode type ESD protection circuit, and the leakage current can be reduced more than that of a GG-MOS type ESD protection circuit. Such malfunctions can be prevented.

First, as conventional techniques, a diode type ESD protection circuit, a GG-MOS type ESD protection circuit, and a capacitively coupled MOS type ESD protection circuit will be described with reference to FIGS. 4A to 6B.
Below, the voltage and current due to electrostatic discharge may be simply referred to as "surge voltage" and "surge current."

FIG. 4A is a circuit diagram showing an example of a conventional diode type ESD protection circuit.
As shown in FIG. 4A, this diode type ESD protection circuit 500 is a circuit in which a diode 510 is connected between the V _DD terminal and the V _SS terminal. When a surge voltage is applied to the V _DD terminal, the diode-type ESD protection circuit 500 protects the internal circuit C from electrostatic discharge by causing a surge current to flow through the diode 510 using a breakdown phenomenon.
The diode 510 can adjust the breakdown voltage by adjusting the impurity concentration of the PN junction, so it can easily correspond to the operating voltages of various semiconductor integrated circuits, has a simple structure, has little variation in characteristics, and has an insulating film. Since it is not used, the insulating film will not be destroyed.

FIG. 4B is a graph showing an example of current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. In this graph, the horizontal axis is the voltage at the V _DD terminal, and the vertical axis is the surge current flowing through the diode type ESD protection circuit. Further, the solid line shows the current-voltage characteristics of a diode with a large junction area, and the dotted line shows the current-voltage characteristics of a diode with a small junction area.
Note that not only the graph in FIG. 4B but also the graphs in FIGS. 5B, 5C, 5D, and 6B show that when 2,000V static electricity charged to the human body is applied to the VDD terminal, the so-called 2,000V HBM ( Human Body Model). In order to prevent the internal circuit from being destroyed by the 2,000V HBM, the ESD protection circuit connected in parallel with the internal circuit must prevent the surge current of approximately 1 ampere from flowing into the _VSS terminal before the surge current flows into the internal circuit. It needs to flow.

In the current-voltage characteristics shown by the dotted line in Figure 4B, since the junction area of the diode is small and the resistance value of the parasitic resistance is high, the surge voltage rises to the breakdown voltage of the internal circuit before a 1-amp surge current flows to the _VSS terminal. It reaches . On the other hand, in the current-voltage characteristics shown by the solid line in Figure 5A, the junction area of the diode is large and the resistance value of the parasitic resistance is low, so the surge current of 1 ampere can be reduced to V before the surge voltage reaches the breakdown voltage of the internal circuit. It can be passed to the _SS terminal.
Therefore, in order for the diode-type ESD protection circuit to protect the internal circuit from the 2,000V HBM, the junction area of the diode must be increased, resulting in an increase in the layout area of the semiconductor integrated circuit.

In terms of reducing the layout area of a semiconductor integrated circuit, a GG-MOS type ESD protection circuit using snapback operation is more advantageous than a diode type ESD protection circuit.

Next, a conventional GG-MOS type ESD protection circuit will be explained.

FIG. 5A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit.
As shown in FIG. 5A, the GG-MOS type ESD protection circuit 600 has the drain and source terminals of the MOS transistor 610 connected to the V _DD terminal and the V _SS terminal, respectively, and the gate terminal connected to the V _SS terminal. This is the circuit where

FIG. 5B is a graph comparing the current-voltage characteristics of a conventional diode type ESD protection circuit and a conventional GG-MOS type ESD protection circuit. In this graph, the horizontal axis is the voltage at the V _DD terminal, and the vertical axis is the surge current flowing through each ESD protection circuit. Further, the solid line shows the current-voltage characteristics of a GG-MOS type ESD protection circuit with a small layout area, and the dotted line shows the current-voltage characteristics of a diode-type ESD protection circuit with a small layout area similar to the dotted line in FIG. 4B. That is, in FIG. 5B, the layout area of the conventional GG-MOS type ESD protection circuit is similar to the layout area of the conventional diode type ESD protection circuit.

In the current-voltage characteristics of the GG-MOS type ESD protection circuit shown by the solid line in FIG. 5B, when a surge voltage is applied, after avalanche breakdown occurs in the parasitic diode in the MOS transistor 610, the V _DD terminal voltage becomes The trigger voltage is reached. Here, the trigger voltage is the trigger voltage of the parasitic bipolar transistor, and is the voltage at which the parasitic bipolar transistor is switched from off to on. When the parasitic bipolar transistor turns on, the number of current paths flowing from the drain to the source increases compared to when it is off, so the same current can flow with less drain voltage, and the voltage drops after reaching the trigger voltage, as shown in Figure 5B. (snapback movement) is seen.
This snapback operation allows the conventional GG-MOS type ESD protection circuit to pass one ampere of surge current to the V _SS terminal before the surge voltage reaches the breakdown voltage of the internal circuitry.

The leakage current and breakdown voltage of this GG-MOS type ESD protection circuit are influenced by multiple parameters such as the gate length of the MOS transistor, the gate insulating film thickness, the channel impurity concentration, and the impurity concentration of the low concentration region near the drain. Although it is more complicated than the diode type because of the small size, it is possible to finely adjust the characteristics to desired characteristics by adjusting the concentration of impurities implanted near the drain region.

However, when the operating voltage of the internal circuit is about 2V, it becomes difficult to adjust the diode type or GG-MOS type.
Generally, in an internal circuit whose operating voltage is about 2V, it is necessary to lower the minimum operating voltage, and in order to improve the on-off ratio of the MOS transistor used in the internal circuit, the gate insulating film thickness of the MOS transistor in the internal circuit must be is set to 4 nm to 5 nm. When the gate insulating film is a thin silicon oxide film as described above, the intrinsic breakdown voltage slightly exceeds 10 MV/cm, so the intrinsic breakdown voltage of the gate insulating film of the MOS transistor in the internal circuit is often about 5.5V. Therefore, the ESD protection circuit must perform a protection operation when the V _DD terminal voltage is within the range of 2V to 5.5V.
In a diode type ESD protection circuit or a GG-MOS type ESD protection circuit, when trying to keep the protection operation within the above range, the leakage current at an operating voltage of 2V increases as shown in FIG. 5D. Conversely, when trying to suppress the leakage current, the protection operation is not completed within the above range as shown in Figure 5C, and the voltage exceeds 5.5V before a surge current of 1 ampere flows, destroying the internal circuit. Ru.

In this way, in diode-type ESD protection circuits and GG-MOS type ESD protection circuits, when the operating voltage of the internal circuit approaches 2V, ESD occurs due to the trade-off relationship between leakage current and protection operating voltage (i.e., off-current and on-voltage). Protective function cannot be fulfilled.
A capacitively coupled MOS type ESD protection circuit that eliminates this trade-off will be described below.

FIG. 6A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit. FIG. 6B is a graph showing an example of current-voltage characteristics (by rise time of surge voltage) of a conventional capacitively coupled MOS type ESD protection circuit.

As shown in FIG. 6A, the capacitively coupled MOS type ESD protection circuit 700 is similar to the GG-MOS type in that the drain and source terminals of the MOS transistor 710 are connected to the V _DD terminal and the V _SS terminal, respectively. However, the difference is that the gate is connected to the V _DD terminal via a capacitor 720 and also connected to the V _SS terminal via a resistive element 730. Furthermore, the threshold voltage of the MOS transistor 710 is set to 2V or less.

In the capacitively coupled MOS type ESD protection circuit 700, when the rise time of the surge voltage is long, the potential of the capacitively coupled gate is difficult to fluctuate, and the ESD protection circuit does not allow current to flow. That is, in this case, the capacitively coupled MOS type ESD protection circuit 700 has a current-voltage characteristic as shown by the solid line in FIG. 6B and can reduce leakage current without performing a protective operation in the range of 2V to 5.5V. On the other hand, when the rise time of the surge voltage is short, the potential of the capacitively coupled gate fluctuates, and the MOS transistor 710, which is set to a threshold voltage of 2V or less, performs a protective operation by allowing current to flow through the channel, and the surge current discharge.

In this way, the capacitively coupled MOS type ESD protection circuit 700 eliminates the trade-off between the diode type ESD protection circuit and the GG-MOS type ESD protection circuit by switching the on and off characteristics through capacitive coupling.

However, capacitively coupled MOS type ESD protection circuits will malfunction if used for terminals that operate by inputting or outputting signals with a short rise time equivalent to electrostatic discharge, so they are only used for a limited number of terminals. I can't.
Furthermore, since a high voltage is applied to the gate of the capacitively coupled MOS type ESD protection circuit during operation, avalanche breakdown, which causes the operation of a parasitic bipolar transistor, is less likely to occur. Therefore, the current-voltage characteristics of the capacitively coupled MOS type ESD protection circuit, as shown by the solid line in Figure 6B, are similar to those of the diode type ESD protection circuit shown by the dotted line in Figure 4B, and a large current If you try to make it flow, you will have to increase the layout area as shown by the solid line in FIG. 4B.

Therefore, in order to solve the above problems, the present invention has been made as follows.
The ESD protection circuit in one embodiment of the present invention is connected between a first terminal and a second terminal in parallel with a protected circuit that operates at a predetermined operating voltage, and includes an NMOS transistor. This NMOS transistor has a drain connected to a first terminal, a gate in a floating state, and a source connected to a second terminal, and the avalanche breakdown voltage of the parasitic diode and the trigger voltage of the parasitic bipolar transistor are Higher than the operating voltage of the protection circuit and lower than the breakdown voltage of the protected circuit.
As a result, this ESD protection circuit can have a smaller layout area than conventional diode-type or capacitively coupled MOS-type ESD protection circuits, and can reduce leakage current more than diode-type or GG-MOS type ESD protection circuits. It does not malfunction like a MOS type ESD protection circuit and can also be used as a terminal for inputting/outputting a voltage with a short rise time.
Note that the predetermined operating voltage is a predetermined voltage at which the protected circuit can operate, and is in the range from the minimum operating voltage to the maximum operating voltage of the protected circuit.

Embodiments of the present invention will be described in detail below with reference to the drawings.
In addition, in the drawings, the same components are given the same reference numerals, and redundant explanations may be omitted.
Furthermore, in the drawings, the X direction, Y direction, and Z direction are orthogonal to each other. The direction including the X direction and the direction opposite to the X direction (-X direction) is referred to as the "X-axis direction", and the direction including the Y direction and the direction opposite to the Y direction (-Y direction) is referred to as the "X-axis direction". The "Y-axis direction" is referred to as the "Z-axis direction" (height direction, thickness direction), and the direction including the Z direction and the direction opposite to the Z direction (-Z direction) is referred to as the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the Z-direction side surface of each film may be referred to as a "surface."
The drawings are schematic and the proportions of width, length and depth are not as shown in the drawings.

(Example of embodiment)
FIG. 1 is a circuit diagram showing an ESD protection circuit and a semiconductor device in one embodiment of the present invention.
As shown in FIG. 1, in the semiconductor device 10, an internal circuit C is connected between a V _DD terminal as a first terminal and a V _SS terminal as a second terminal.
The internal circuit C operates with an operating voltage applied between the V _DD terminal and the V _SS terminal at ground potential.
The ESD protection circuit 100 is connected in parallel with an internal circuit C, which is a circuit to be protected from destruction due to electrostatic discharge.
The ESD protection circuit 100 includes an NMOS (N-channel MOS) transistor 110 having a drain 110D electrically connected to a _VDD terminal, a gate 110G in a floating state, and a source 110S electrically connected to a _VSS terminal. be.
The operating voltage of the internal circuit C changes depending on the purpose, but in this embodiment, the operating voltage is 2V, and 2V is applied to the _VDD terminal.
Generally, when the operating voltage of the internal circuit is 2V, the intrinsic breakdown voltage of the gate insulating film of the MOS transistor included in the internal circuit is about 5.5V. Therefore, if an ESD protection circuit does not exist, when static electricity is discharged to the V _DD terminal, a voltage of 5.5 V or more will be applied to the gate insulating film of the MOS transistor included in the internal circuit, resulting in destruction.
In other words, the ESD protection circuit 100 performs a protective operation before the voltage of the V _DD terminal becomes 5.5 V or more, and does not perform a protective operation when 2 V, which is the operating voltage of the internal circuit C, is applied to the V _DD terminal. Just do it like this. Furthermore, the thickness of the insulating film may be set so that the intrinsic breakdown voltage of the gate insulating film of the NMOS transistor 110 is also 5.5V.

FIG. 2A is a schematic cross-sectional view showing an example of the structure of the NMOS transistor in this embodiment.
As shown in FIG. 2A, the structure of the NMOS transistor 110 is such that a P-type well region 112, which is a P-type low concentration region, is formed in a semiconductor substrate 111, and a P-type medium concentration region is formed on the P-type well region 112. A region 113a is formed.
In this embodiment, the P-type medium concentration region 113a is formed on the P-type well region 112, but the present invention is not limited to this, and instead of forming the P-type medium concentration region 113a, a low concentration P-type well region 113a is formed on the P-type well region 112. 112 may have a medium concentration.

A gate insulating film 115 is laminated on the upper surface of this P-type medium concentration region 113a, and a gate electrode 116 is further laminated on the gate insulating film 115.
Above the P-type medium concentration region 113a, an N-type high concentration drain region 114a and an N-type high concentration source region 114b are formed so as to sandwich the gate electrode 116 when viewed in plan. In this way, the P-type medium concentration region 113a is also provided in the channel region between the N-type high concentration drain region 114a and the N-type high concentration source region 114b. Further, a well electrode 114c is formed as a P-type high concentration region above the P-type medium concentration region 113a at a position spaced apart from the N-type high concentration source region 114b.
In this embodiment, the N-type high concentration source region 114b and the well electrode 114c are separated from each other, but the present invention is not limited to this, and the N-type high concentration source region 114b and the well electrode 114c may be brought into contact with each other like a butting contact. Good too.
The N-type heavily doped drain region 114a is connected to the V _DD terminal, the gate electrode 116 is in a floating state, and the N-type heavily doped source region 114b and well electrode 114c are connected to the V _SS terminal.

Generally, the well region of the ESD protection circuit is often formed at the same time as the well region of the internal circuit in the same process, so in addition to the P-type well region 112, the P-type medium concentration region 113a is formed as in this embodiment. That's not necessarily common.

By adjusting the impurity concentration of this P-type medium concentration region 113a, it is possible to adjust the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar.
As described above, the ESD protection circuit 100 performs a protective operation before the voltage at the _VDD terminal becomes 5.5V or higher, and performs protection when 2V, which is the operating voltage of the internal circuit C, is applied to the _VDD terminal. Since it is necessary not to operate, the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar can be set to 2V or more and 5V by adjusting the impurity concentration of the P-type medium concentration region 113a. Adjust to .5V or less.

Here, the operating principle when positive static electricity flows into the _VDD terminal of an IC whose internal circuit C has an operating voltage of 2V will be described.

The gate electrode of this NMOS transistor 110 is in a floating state, and if there is a voltage difference between the V _DD and V _SS terminals, leakage current due to the punch-through phenomenon tends to flow, so a voltage exceeding the operating voltage of 2 V is applied to the V _DD terminal. It is necessary to prevent the punch-through phenomenon from occurring. Further, it is preferable to adjust this punch-through phenomenon so that it does not exceed 5.5V, which is the breakdown voltage of the internal circuit C.
This adjustment is performed by adjusting the impurity concentration of the P-type medium concentration region 113a, that is, by adjusting the threshold value of the NMOS transistor 110. Further, this punch-through current can also be adjusted by increasing the gate length of the NMOS transistor 110.
The above adjustment suppresses the leakage current when 2V is applied as the operating voltage to the V _DD terminal, and when a surge voltage of 2 V or more is applied to the V _DD terminal, the punch-through phenomenon causes the leakage current of the NMOS transistor 110 to be suppressed. A surge current is caused to flow from the N-type heavily doped drain region 114a to the N-type heavily doped source region 114b via the channel region (protection operation 1).

However, if this protective operation 1 is used alone, the current-voltage characteristic will be similar to "the case of an input voltage with a short rise time" shown by the solid line in FIG. 6B, and the internal circuit C cannot be protected in a small area. In order to protect the internal circuit C, it is necessary to widen the gate width of the gate electrode 116 to allow a larger surge current to flow, but as a result, the layout area becomes larger and leakage current also becomes larger.
In the case of the conventional GG-MOS type ESD protection circuit, since the gate electrode is connected to the _VSS terminal, the electric field near the semiconductor surface between the gate and drain becomes strong, causing surface breakdown, which causes The trapped carriers induce parasitic bipolar behavior. On the other hand, in this embodiment, since the gate electrode is in a floating state, operation of a parasitic bipolar transistor due to surface breakdown cannot be expected as in a GG-MOS type ESD protection circuit. Since avalanche breakdown occurs in the parasitic diode formed by the junction between the P-type medium concentration region 113a and the N-type high concentration drain region 114a, the operation of the parasitic bipolar transistor can be induced.

The avalanche breakdown voltage of this parasitic diode and the trigger voltage of the parasitic bipolar transistor induced to operate thereby are also adjusted by the impurity concentration of the P-type medium concentration region 113a, similar to the threshold voltage.
Similarly to the threshold value, the avalanche breakdown voltage of the parasitic diode is adjusted to 2V or more so that when the operating voltage of the internal circuit C, 2V, is applied to the _VDD terminal, the leakage current is below the desired leakage current. The trigger voltage of the parasitic bipolar transistor that is induced to operate thereby naturally becomes 2V or higher. Further, in order to protect the internal circuit C from the ESD surge applied from the _VDD terminal, the trigger voltage of the parasitic bipolar is adjusted to be 5.5V or less. At this time, if the trigger voltage of the parasitic bipolar exceeds 5.5 V when the avalanche breakdown voltage of the parasitic diode is set to 2 V or more, shorten the gate length of the NMOS transistor 110 and lower only the trigger voltage of the parasitic bipolar. adjust. Also, since the gate electrode is not connected to the V _SS terminal like in the GG-MOS type ESD protection circuit, it is easier to lower the trigger voltage for parasitic bipolar operation than in the GG-MOS type ESD protection circuit, making it easier to protect the internal circuit. There is also an advantage.

By operating this parasitic bipolar, apart from the surge current flowing into the channel region from the N-type heavily doped drain region 114a to the N-type heavily doped source region 114b in protection operation 1, a portion deeper than the channel region (in the -Z direction) A large amount of surge current can flow through the parasitic bipolar region (protection operation 2).

In other words, there are two paths for the surge current: a current path that flows through the channel region (protective action 1) and a current path that flows through the parasitic bipolar region deeper than the channel region (in the -Z direction) (protective action 2). Therefore, it is possible to further reduce the area than the GG-MOS type ESD protection circuit, which is advantageous in terms of area among conventional technologies.

In the structure of the NMOS transistor 110, since the channel region is the P-type medium concentration region 113a, the threshold voltage and the breakdown voltage of the parasitic diode can be adjusted by adjusting the impurity concentration of the P-type medium concentration region 113a. is limited to cases where it is possible to adjust to the desired value all at once.

Next, a case will be described in which negative static electricity is discharged to the _VDD terminal.

As shown in FIG. 2E, negative charges flow in the forward direction in the parasitic diode between the N-type high concentration drain region 114a and the P-type well region 112, and then flow from the P-type well region 112 to the P-type high concentration region. It flows to the V _SS terminal via a certain well electrode 114c. Since there are no places in the above path where a high electric field is applied, destruction does not occur.
Therefore, the ESD protection circuit 100 can protect the internal circuit C by flowing negative charges to the V _SS terminal due to the structure of the NMOS transistor 110.

In the method for forming the NMOS transistor 110, for example, first a P-type well region 112 is formed in a semiconductor substrate 111, and a gate insulating film 115 and a gate electrode 116 are formed thereon. Then, a P-type impurity is implanted into the entire surface of the semiconductor substrate 111 so as to penetrate through the gate insulating film 115 and the gate electrode 116 to form a P-type medium concentration region 113a, and then an N-type impurity is implanted at a high concentration. This can be achieved by forming an N-type heavily doped drain region 114a and an N-type heavily doped source region 114b.
Further, the P-type medium concentration region 113a may be formed before forming the gate insulating film 115 and the gate electrode 116.

As described above, the ESD protection circuit 100 is connected in parallel with the internal circuit C that operates at a predetermined operating voltage between the V _DD terminal and the V _SS terminal, and includes the NMOS transistor 110 . In the NMOS transistor 110, an N-type heavily doped drain region 114a and a gate electrode 116 are connected to a _VDD terminal, and an N-type heavily doped source region 114b is connected to a _VSS terminal. As shown in FIG. 2F, this NMOS transistor 110 has a threshold voltage, a Zener breakdown voltage of a parasitic diode, and a trigger voltage of a parasitic bipolar transistor that are higher than the operating voltage of the internal circuit C, and the internal circuit C is destroyed. lower than the voltage.
Thereby, the ESD protection circuit 100 can reduce the layout area, reduce leakage current, and prevent malfunctions that occur in capacitively coupled MOS electrostatic circuits.

Next, other examples of structures of NMOS transistors other than the NMOS transistor 110 shown in FIG. 2A will be described with reference to FIGS. 3A to 3H.
Note that FIGS. 3A to 3H are schematic cross-sectional views showing the vicinity of the N-type heavily doped drain region 114a, the N-type heavily doped source region 114b, and the gate electrode 116.
Moreover, in the NMOS transistor of the ESD protection circuit shown in FIG. 1, FIG. 2A, and FIG. 2B, any of the NMOS transistors shown in FIG. 2A and FIG. 3A to FIG. 3H may be used.

3A shows a structure similar to that of the NMOS transistor 110 shown in FIG. 2A, except that a P-type medium concentration channel region 117 is further formed in the NMOS transistor 110 shown in FIG. 2A.
By forming this P-type medium concentration channel region 117, the impurity concentration of the P-type medium concentration channel region 117 can be adjusted separately from the P-type medium concentration region 113a. For example, in order to suppress leakage current when the operating voltage of internal circuit C is applied to the V _DD terminal, the impurity concentration of the P-type medium concentration region 113a is adjusted to the low concentration side, and the avalanche breakdown voltage of the parasitic diode is increased. shall be. As a result of this influence, the threshold voltage decreases and punch-through phenomenon becomes more likely to occur, and the leakage current of the NMOS transistor 110 may not be able to be suppressed after all. Even in such a case, the existence of the P-type medium concentration channel region 117 makes it possible to independently adjust the impurity concentration in this region, so that the threshold can be adjusted without changing the avalanche breakdown voltage of the parasitic diode of the NMOS transistor 110. It is possible to increase the value and suppress leaks.

FIG. 3B shows the NMOS transistor 110 shown in FIG. 3A except that a P-type medium concentration region 113b is formed directly under the N-type high concentration drain region 114a instead of the P-type medium concentration region 113a. The structure is similar to that of the NMOS transistor 110.
By adopting the structure shown in FIG. 3B, not only can an effect equivalent to that of FIG. 3A be obtained, but also the base region concentration of the parasitic bipolar transistor directly under the P-type medium concentration channel region 117 is thinner than that in FIG. 3A, so that the parasitic bipolar transistor The trigger voltage is lowered, making it easier to protect the internal circuit C than in FIG. 3A.

3C shows a structure similar to that of the NMOS transistor 110 shown in FIG. 3B except that an N-type low concentration region 118a is formed in the NMOS transistor 110 shown in FIG. 3B.
The N-type low concentration region 118a has a so-called DDD (Double Diffused Drain) structure. This DDD structure is generally a structure for improving the drain breakdown voltage of a MOS transistor, but this structure can also be applied to the present invention. By forming this N-type low concentration region 118a, the N-type high concentration drain region 114a is substantially expanded and heat is easily dispersed, so that the electrostatic breakdown voltage can be improved.

3D to 3G are similar to the NMOS transistors shown in FIGS. 2A and 3A to 3C, respectively, except that sidewall spacers 119 are provided on the side walls of the gate insulating film 115 and the gate electrode 116. The structure is similar to the NMOS transistor shown in FIG. 3C. 3H shows a structure similar to that of the NMOS transistor shown in FIG. 3G, except that the N-type low concentration region 118a is replaced with a shallowly formed N-type low concentration region 118b.
This sidewall spacer 119 is a technique used in a general semiconductor manufacturing process, and is formed by removing the insulating film formed over the entire surface by etching back after forming the gate insulating film 115 and the gate electrode 116. By using FIGS. 3D to 3H, the present invention can be applied to manufacturing processes using sidewall spacers without additional steps.

Here, in FIGS. 3G to 3H, an N-type region exists directly under the sidewall spacer 119. These N-type low concentration regions 118a and 118b have a so-called DDD (Double Diffused Drain) structure and an LDD (Lightly Doped Drain) structure.
The DDD structure and LDD structure are generally structures for improving the drain breakdown voltage of a transistor, and these structures can also be applied to the present invention. By forming this N-type low concentration region 118b, the N-type high concentration drain region 114a substantially expands, making it easier to disperse heat, thereby improving the electrostatic breakdown voltage.

As explained above, the ESD protection circuit in one embodiment of the present invention is connected between the first terminal and the second terminal in parallel with the protected circuit that operates at a predetermined operating voltage, It has an NMOS transistor. This NMOS transistor has a drain connected to a first terminal, a gate in a floating state, and a source connected to a second terminal, and the threshold voltage and parasitic bipolar trigger voltage are lower than the operating voltage. High and lower than the breakdown voltage of the protected circuit.
Thereby, this ESD protection circuit can reduce the layout area, reduce leakage current, and prevent malfunctions that occur in capacitively coupled MOS type ESD protection circuits.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment, and includes designs within a range that does not depart from the gist of the present invention.
Specifically, in this embodiment, the first terminal is a V _DD terminal, but the first terminal is not limited to this, and may be, for example, an input terminal, an output terminal, or the like.
Further, even if the LDD structure is adopted for the NMOS transistor, the sidewall spacer may not be formed.

10 Semiconductor device 100 ESD protection circuit 110 NMOS transistor 110D Drain 110S Source 110G Gate 111 Semiconductor substrate 112 P-type well region 113a, 113b P-type medium concentration region 114a N-type high concentration drain region 114b N-type high concentration source region 115 Gate insulating film 116 Gate electrode 117 P-type medium concentration channel region (P-type medium concentration region)
118a, 118b N-type low concentration region 119 Sidewall spacer C Internal circuit (protected circuit)

Claims (9)

An ESD protection circuit connected in parallel with a protected circuit operating at a predetermined operating voltage between a first terminal and a second terminal,
an NMOS transistor having a drain connected to the first terminal, a gate in a floating state, and a source connected to the second terminal;
The ESD protection circuit is characterized in that the threshold voltage and the trigger voltage of the parasitic bipolar transistor of the NMOS transistor are higher than the operating voltage and lower than the breakdown voltage of the protected circuit. The NMOS transistor is
a semiconductor substrate;
a P-type well region formed on the front side of the semiconductor substrate;
an N-type heavily doped drain region and an N-type heavily doped source region that are spaced apart above the P-type well region and have an impurity concentration higher than the impurity concentration of the P-type well region;
a P-type medium concentration region provided at least in a region in contact with the N-type high concentration drain region and having a higher concentration of P-type impurities than the impurity concentration of the P-type well region;
a gate insulating film provided on the semiconductor surface between the N-type high concentration drain region and the N-type high concentration source region;
a gate electrode provided on the gate insulating film;
The ESD protection circuit according to claim 1, comprising: The ESD protection circuit according to claim 2, wherein the P-type medium concentration region also contacts the P-type well region. 4. The ESD protection circuit according to claim 2, wherein the P-type medium concentration region is further provided in a channel region between the N-type high concentration drain region and the N-type high concentration source region. 5. The ESD protection circuit according to claim 2, wherein a P-type medium concentration channel region is provided on the surface of the semiconductor substrate between the N-type high concentration drain region and the N-type high concentration source region. The ESD protection circuit according to claim 2, wherein the NMOS transistor further includes a DDD structure. The ESD protection circuit according to claim 4, wherein the NMOS transistor further includes an LDD structure. 8. The ESD protection circuit according to claim 2, wherein the NMOS transistor further includes sidewall spacers on sidewalls of the gate insulating film and the gate electrode. 9. A semiconductor device, wherein the ESD protection circuit according to claim 1 and a protected circuit protected from electrostatic discharge by the ESD protection circuit are connected in parallel.

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