JP2023141299A - memory system - Google Patents

Abstract

To provide a memory system capable of detecting an input signal from a host device and switching to the appropriate voltage.SOLUTION: According to one embodiment, a memory system comprises a connector, a non-volatile memory, and a controller. The connector includes a first terminal and a second terminal each of which is capable of being connected to a host device. The controller is connected between the connector and the non-volatile memory. The controller includes a control circuit, a first signal line, a second signal line, and a first resistance element. The control circuit has a first node and a second node. The first signal line is connected between the first terminal and the first node. The first signal line is capable of being pulled up to a first power level or a second power level. The second signal line is connected to the second terminal. The first resistance element has one end connected to the first signal line and the other end connected to the second signal line.SELECTED DRAWING: Figure 2

Description

This embodiment relates to a memory system.

Memory systems that can be connected to a host device are known. A memory system includes a memory in which data is recorded, a controller connected to the memory to control the memory, and a connector connected to the controller and connectable to an external host device. The memory system is, for example, an SSD, and the memory is, for example, a nonvolatile memory. In order to support low voltage operation, memory systems are required to be able to detect an input signal from a host device and switch to an appropriate voltage.

US Patent No. 11171635 US Patent No. 10901851 US Patent Application Publication No. 2021/0327871

One embodiment aims to provide a memory system that can detect an input signal from a host device and switch to an appropriate voltage.

According to one embodiment, a memory system is provided that includes a connector, non-volatile memory, and a controller. The connector has a first terminal and a second terminal, each of which is connectable to a host device. A controller is connected between the connector and the nonvolatile memory. A peripheral circuit is connected between the connector and the controller. The controller includes a control circuit, a first signal line, a second signal line, and a first resistance element. The control circuit has a first node and a second node. A first signal line is connected between the first terminal and the first node. The first signal line is pullable to a first power level or a second power level. A second signal line is connected to the second terminal. One end of the first resistance element is connected to the first signal line, and the other end is connected to the second signal line.

1 is a block diagram showing the configuration of an information processing system including a memory system according to an embodiment and a host device connected to the memory system. FIG. 1 is a circuit block diagram for explaining the configuration of a memory system according to an embodiment. FIG. 2 is a circuit diagram showing the configuration of an input circuit and an output circuit of a controller of a memory system according to an embodiment. FIG. 3 is a diagram illustrating a signal voltage range of an input/output circuit of a memory system according to an embodiment. 5 is a flowchart for explaining the operation of the memory system according to the embodiment. FIG. 3 is a diagram showing the operation of the memory system according to the embodiment. FIG. 3 is a diagram showing the operation of the memory system according to the embodiment.

A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to this embodiment.

(Embodiment)
FIG. 1 is a block diagram showing the configuration of an information processing system 200 including a memory system 1 according to an embodiment and a host device 101 connectable to the memory system 1. An information processing system 200 including the memory system 1 according to the embodiment may be configured as shown in FIG.

The information processing system 200 includes a host device 101 and a memory system 1. In the information processing system 200, the memory system 1 may be communicably connected to the host device 101.

The host device 101 may be, for example, an information processing device such as a server or a personal computer, or a mobile terminal such as a tablet or a smartphone. Further, it may be a game device, an imaging device, or an in-vehicle terminal such as a car navigation system.

The memory system 1 is, for example, a memory device such as an SSD (Solid State Drive). In this embodiment, the memory system 1 is assumed to be, for example, a relatively small module, and an example of its external dimensions (size) is 22 mm x 80 mm. However, the size of the memory system 1 is not limited to this.

The host device 101 has a connector section 102, and the memory system 1 has a connector section 10. The connector part 10 is arranged at the end of the substrate 8 and can be configured as an edge connector 3. The connector section 102 is disposed on or at an end of a motherboard (not shown) in the host device 101 and can be configured as a socket 103 that corresponds to the edge connector 3 .

The connector section 10 on the memory system 1 side and the connector section 102 on the host device 101 side have shapes that comply with form factor standards (for example, M.2 form factor). A notch 3a is formed in the edge connector 3 of the connector portion 10 at a position offset from the center position along the width direction of the board 8. The position where the notch 3a is formed in the edge connector 3 is, for example, M. It may be the position of the "M key" in the 2 form factor, or it may be the position of the "M key" in the M.2 form factor. It may be the position of the "B&M key" in the 2 form factor. The socket 103 of the connector portion 102 is provided with a protrusion 103a at a position corresponding to the notch 3a of the edge connector 3.

The notch 3a and the protrusion 103a are configured to fit into each other when the edge connector 3 is connected to the socket 103.

As a result, a desired form factor (for example, M.2 form factor) is selected from among the plurality of form factors for the connector unit 102 of the host device 101, and a plurality of types conforming to the standards of the desired form factor are selected. The connector section 10 of the memory system 1 of the desired type (for example, type M corresponding to "M key", type B+M corresponding to "B&M key") is selected and connected from among the connectors in memory system 1. . Furthermore, the positions where the notch 3a and the protrusion 103a are provided are designed to prevent the memory system 1 from being attached to the host device 101 upside down.

A plurality of terminals corresponding to each other are arranged on the edge connector 3 and the socket 103. When the edge connector 3 is connected to the socket 103, each terminal of the edge connector 3 contacts the terminal of the corresponding socket 103 and is electrically connected. Thereby, the memory system 1 can be communicably connected to the host device 101.

Although FIG. 1 shows an example of a configuration in which the edge connector 3 is mounted as a physical connector, the edge connector 3 is formed by plating the edge of the board 8 in a pattern arranged in accordance with the standard. It may be implemented as a group of terminals.

The host device 101 further includes a communication controller 110, a DRAM 106, a bus 109, and a CPU 107. Communication controller 110, DRAM 106, and CPU 107 are connected to each other via bus 109. The CPU 107 centrally controls each part of the host device 101 . The DRAM 106 functions as a buffer when transmitting and receiving signals (for example, commands, data, etc.) to and from the memory system 1, and functions as a work area for the CPU 107.

The memory system 1 further includes a peripheral circuit 20, a controller 30, a DRAM 6, and a nonvolatile memory 40. The peripheral circuit 20 is electrically connected between the connector section 10 and the controller 30. The peripheral circuit 20 may be implemented as a circuit including, for example, a resistor, a capacitor, an FET, etc., with wiring formed by a copper foil pattern formed on a substrate. The controller 30 comprehensively controls each part of the memory system 1. Controller 30 may be implemented as a system on a chip (SoC). The DRAM 6 functions as a buffer when transmitting and receiving signals (for example, commands, data, etc.) to and from the host device 101 or the NAND memories 5-1 to 5-n, and functions as a work area for the controller 30. . The nonvolatile memory 40 includes, for example, a plurality of NAND flash memories (hereinafter referred to as NAND memories) 5-1 to 5-n (n is an integer of 2 or more). Each NAND memory 5-1 to 5-n stores data in a non-volatile manner. The NAND memories 5-1 to 5-n each have a memory cell array in which a plurality of memory cells are arranged in a matrix, and each memory cell is capable of multilevel storage using, for example, an upper page and a lower page. There may be. The NAND memories 5-1 to 5-n are composed of a plurality of memory chips, and in the NAND memories 5-1 to 5-n, data is erased in block units, and data is written and data is erased on a page-by-page basis. is read out. A block is made up of multiple pages.

When the connector unit 10 of the memory system 1 is connected to the connector unit 102 of the host device 101, the communication controller 110 becomes able to communicate with the controller 30 via the connector unit 102, the connector unit 10, and the peripheral circuit 20 under the control of the CPU 107. Become. The communication controller 110 can transmit commands, data, etc. received from the CPU 107 via the bus 109 to the controller 30 via the connector section 102, the connector section 10, and the peripheral circuit 20. The controller 30 writes data to and reads data from the NAND memories 5-1 to 5-n according to commands while using the DRAM 6 as a buffer memory, and then writes the response/data. etc. are sent to the communication controller 110. The communication controller 110 can receive responses, data, etc. from the controller 30 via the peripheral circuit 20, the connector unit 10, and the connector unit 102, and can transfer the received responses, data, etc. to the CPU 107 via the bus 109.

FIG. 2 is a circuit block diagram showing the configuration of the memory system 1 according to this embodiment. The memory system 1 is configured to be able to handle a plurality of different power levels of signals received from the host device 101.

The plurality of power levels includes, for example, two power levels VDD1 and VDD2. For example, power level VDD1 is 1.8V, and power level VDD2 is 3.3V. Here, the signal corresponding to the low power supply level VDD1 will be referred to as a low voltage signal, and the signal corresponding to the high power supply level VDD2 will be referred to as a high voltage signal.

The connector section 10 shown in FIG. 2 has a plurality of terminals 11 to 15. Each of the terminals 11 to 15 can be connected to a plurality of terminals (not shown) in the socket 103 of the host device 101. Each of the terminals 11 to 15 can be implemented, for example, as a terminal of the edge connector 3 (see FIG. 1).

The terminal 11 is a terminal for receiving a first signal from the host device 101. The first signal is, for example, a signal for notifying the occurrence of the first event. The first event includes, for example, a power outage. The first signal is a low active signal, maintained at H level when not reporting the occurrence of the first event, and maintained at L level when notifying the occurrence of the first event. The first signal is determined by the standard to be pulled up on the memory system 1 side at a power level according to the voltage level of the control signal.

The terminal 12 is a terminal for receiving a second signal from the host device 101. The second signal is, for example, a signal indicating whether or not the signal transmitted and received with the host device 101 is a low voltage signal. The second signal is a high active signal and is maintained at H level when the first to sixth signals transmitted and received with the host device 101 are low voltage signals, and the second signal is a high active signal that is maintained at H level when the first to sixth signals transmitted and received with the host device 101 are low voltage signals. Since the second signal is not output from the host device 101 to the terminal 12 when the signals of 6 to 6 are not low voltage signals (that is, high voltage signals), the second signals are maintained at L level.

The terminal 13 is a terminal for transmitting a third signal to the host device 101. The third signal is, for example, a signal for notifying completion of the operation corresponding to the first event. The operation corresponding to the first event includes, for example, a data saving operation in response to power cutoff. The third signal is a low active signal, which is maintained at the H level when not notifying the completion of the operation corresponding to the first event, and is kept at L level when notifying the start of the operation corresponding to the first event. level and is maintained at H level again when signaling completion of the first event.

The terminal 14 is a terminal for receiving the fourth signal from the host device 101. The fourth signal is, for example, a signal for requesting execution of the second event. The second event includes, for example, an initialization operation. The fourth signal is a low active signal, maintained at L level when requesting execution of the second event, and maintained at H level when canceling execution of the second event.

The terminal 15 is a terminal for transmitting a fifth signal to the host device 101 and receiving a sixth signal. The fifth signal is, for example, a signal for requesting execution of the third event. The third event includes, for example, the provision of a high speed clock signal. The fifth signal is a low active signal, and is maintained at L level when requesting execution of the third event, and maintained at H level when not requesting execution of the third event. The sixth signal is, for example, a signal related to the third event. The signal related to the third event includes, for example, the termination of the state in which the high speed clock signal is not supplied due to the termination of the third event. The sixth signal is a low active signal, and by setting the fifth signal, which maintains the H level while the third event is stopped, to the L level, the memory system 1 uses the high-speed clock signal as a reference. Cancel the state where communication has been stopped.

Although the peripheral circuit 20 and the controller 30 can basically operate using the power supply level VDD2, they can also operate using the power supply level VDD1. The peripheral circuit 20 includes signal lines L11-L15, level shifters 21, 23-25, and resistance elements R1, R11-R15. Level shifters 21, 23-25 include transistors NM1, NM3-NM5.

The controller 30 is implemented by, for example, an SoC, and has electrodes N31 to N35 as indicated by circles in FIG. In this embodiment, the electrodes N31 to N35 will be generically referred to as nodes N31 to N35. The term "node" is not limited to electrodes, but may be a connection point on a line, any point on a line, the line itself, or any other form of electrical connection element. good.

For example, the output of the peripheral circuit 20 and the input of the controller 30 may be directly connected, and the controller 30 may be configured to input the output from the peripheral circuit 20 without going through the electrodes. In this case, nodes N31 to N35 correspond to the output of the peripheral circuit 20 or the input of the controller 30. When the controller 30 is configured as an SoC and the peripheral circuit 20 is configured as wiring on a substrate, the nodes N31 to N35 may be electrode pads of the SoC. When the configuration including the peripheral circuit 20 and the controller 30 is configured as an SoC, the peripheral circuit 20 and the controller 30 may each be circuits mounted on the SoC, and the nodes N31 to N35 are lines connecting the circuits. There may be. Alternatively, if the configuration including the peripheral circuit 20 and the controller 30 is configured other than an SoC, for example, if the configuration including the peripheral circuit 20 and the controller 30 is configured as a package, the peripheral circuit 20 and the controller 30 are each included in the package. The nodes N31 to N35 may be mounted chips, and the nodes N31 to N35 may be bonding wires, ball electrodes, through vias (TSV), etc. that connect the chips. In the following, a case where nodes N31 to N35 are electrodes will be exemplified.

Each terminal included in the connector 10 is normally connected to the controller 30 via the peripheral circuit 20 or directly via wiring. Each of the terminals 11, 12, 13, 14, and 15 has nodes N31, N32, N33, N34, and N35, respectively, at locations connected to the controller 30 via the peripheral circuit 20, as shown in FIG. Signal line L11 is connected between terminal 11 and node N31. A resistance element R11 is arranged at a position on the terminal 11 side of the signal line L11. Transistor NM1 is arranged at a position between resistance element R11 and node N31 on signal line L11. Signal line L11 can be pulled up to power level VDD1 or power level VDD2.

The transistor NM1 is, for example, an NMOS transistor, and has a source connected to the resistance elements R1 and R11 via a signal line L11, and a drain connected to the node N31. Transistor NM1 has a parasitic diode D1 and a gate protection diode GD1. The parasitic diode D1 has an anode connected to the source of the transistor NM1, and a cathode connected to the drain of the transistor NM1. The gate protection diode GD1 has one end connected to the gate of the transistor NM1, and the other end connected to the source of the transistor NM1.

Transistor NM1 is capable of level conversion. The transistor NM1 is turned on when the L level low voltage signal is supplied to the signal line L11, and transfers the L level to the node N31 of the controller 30. The transistor NM1 turns off when the H level of the low voltage signal is supplied to the signal line L11, making the node N31 side high impedance. The potential of node N31 is pulled up by resistance element R31, converted to an H level of a high voltage signal, and transmitted. The transistor NM1 is turned on when the low level of the high voltage signal is supplied to the signal line L11, and transfers the low level to the node N31 of the controller 30. The transistor NM1 is turned off when the H level of the high voltage signal is supplied to the signal line L11, making the node N31 side high impedance. The potential of node N31 is pulled up by resistance element R31 and transmitted as an H level high voltage signal.

Signal line L12 is connected between terminal 12 and node N32. A resistance element R12 is arranged at a position on the terminal 12 side of the signal line L12.

Signal line L13 is connected between terminal 13 and node N33. A resistance element R13 is arranged at a position on the terminal 13 side of the signal line L13. Transistor NM3 is arranged at a position between resistance element R13 and node N33 on signal line L13.

The transistor NM3 is, for example, an NMOS transistor, and has a source connected to the resistance element R13 via the signal line L13, and a drain connected to the node N33. Transistor NM3 has a parasitic diode D3 and a gate protection diode GD3. The parasitic diode D3 has an anode connected to the source of the transistor NM3, and a cathode connected to the drain of the transistor NM3. The gate protection diode GD3 has one end connected to the gate of the transistor NM3, and the other end connected to the source of the transistor NM3.

Transistor NM3 is capable of level conversion. The transistor NM3 is turned on when the low voltage signal at the low level is supplied to the signal line L13, and transfers the low level to the node N33 of the controller 30. The transistor NM3 turns off when the H level of the low voltage signal is supplied to the signal line L13, making the node N33 side high impedance. The potential of node N33 is pulled up by resistance element R33, converted to an H level of a high voltage signal, and transmitted. The transistor NM3 is turned on when the low level high voltage signal is supplied to the signal line L13, and transfers the low level to the node N33 of the controller 30. The transistor NM3 is turned off when the H level of the high voltage signal is supplied to the signal line L13, making the node N33 side high impedance. The potential of node N33 is pulled up by resistance element R33 and transmitted as an H level high voltage signal.

Signal line L14 is connected between terminal 14 and node N34. A resistor element R14 is arranged at a position on the terminal 14 side of the signal line L14. Transistor NM4 is arranged at a position between resistance element R14 and node N34 on signal line L14.

The transistor NM4 is, for example, an NMOS transistor, and has a source connected to the resistance element R14 via the signal line L14, and a drain connected to the node N34. Transistor NM4 has a parasitic diode D4 and a gate protection diode GD4. The parasitic diode D4 has an anode connected to the source of the transistor NM4, and a cathode connected to the drain of the transistor NM4. The gate protection diode GD4 has one end connected to the gate of the transistor NM4, and the other end connected to the source of the transistor NM4.

Transistor NM4 is capable of level conversion. The transistor NM4 is turned on when the low voltage signal at the low level is supplied to the signal line L14, and transfers the low level to the node N34 of the controller 30. The transistor NM4 turns off when the H level of the low voltage signal is supplied to the signal line L14, making the node N34 side high impedance. The potential of node N34 is pulled up by resistance element R34, converted to an H level of a high voltage signal, and transmitted. The transistor NM4 is turned on when the high voltage signal at the L level is supplied to the signal line L14, and transfers the L level to the node N34 of the controller 30. The transistor NM4 is turned off when the H level of the high voltage signal is supplied to the signal line L14, making the node N34 side high impedance. The potential of node N34 is pulled up by resistance element R34 and transmitted as an H level high voltage signal.

Signal line L15 is connected between terminal 15 and node N35. A resistor element R15 is arranged at a position on the terminal 15 side of the signal line L15. Transistor NM5 is arranged at a position between resistance element R15 and node N35 on signal line L15.

The transistor NM5 is, for example, an NMOS transistor, and has a source connected to the resistance element R15 via the signal line L15, and a drain connected to the node N35. Transistor NM5 has a parasitic diode D5 and a gate protection diode GD5. The parasitic diode D5 has an anode connected to the source of the transistor NM5, and a cathode connected to the drain of the transistor NM5. The gate protection diode GD5 has one end connected to the gate of the transistor NM5, and the other end connected to the source of the transistor NM5.

Transistor NM5 is capable of level conversion. Transistor NM5 turns on when the low voltage signal at L level is supplied to signal line L15, and transfers the L level to node N35 of controller 30. Transistor NM5 turns off when the H level of the low voltage signal is supplied to signal line L15, making the node N35 side high impedance. The potential of node N35 is pulled up by resistance element R35, converted to H level of a high voltage signal, and transmitted. Transistor NM5 turns on when the L level of the high voltage signal is supplied to signal line L15, and transfers the L level to node N35 of controller 30. Transistor NM5 turns off when the H level of the high voltage signal is supplied to signal line L15, making the node N35 side high impedance. The potential of node N35 is pulled up by resistance element R35 and transmitted as an H level high voltage signal.

Resistance element R1 is connected between signal line L11 and signal line L12. One end of the resistance element R1 is connected to a node between the resistance element R11 and the transistor NM1 on the signal line L11, and the other end is connected to a node between the resistance element R12 and the node N32 on the signal line L12. Thereby, the signal line L11 can be pulled up from the signal line L12 to the power supply level VDD1 or the power supply level VDD2 via the resistance element R1.

The controller 30 sets the node N32 to high impedance when the terminal 12 is at the H level corresponding to the power supply level VDD1 (for example, 1.8V). When the terminal 12 is at the L level, the controller 30 sets the node N32 to the H level corresponding to the power supply level VDD2 (for example, 3.3V). As a result, the signal line L11 is pulled up to the power supply level VDD1 when the terminal 12 is at the H level. Signal line L11 is pulled up to power supply level VDD2 when terminal 12 is at L level.

The controller 30 further includes resistance elements R31, R2, R33, R34, R35, input circuits 31a, 32a, 34a, 35a, output circuits 32b, 33b, 35b, and a control section 36.

One end of resistance element R31 is connected to power supply level VDD2, and the other end is connected to line L31. Line L31 connects node N31 and the input node of input circuit 31a. Resistance element R31 functions as a pull-up resistor and can pull up line L31.

One end of the resistance element R2 is connected to the ground level, and the other end is connected to the line L32. Line L32 connects node N32, the input node of input circuit 32a, and the output node of output circuit 32b. Resistance element R2 can function as a pull-down resistor and pull down line L32.

For example, if the line L32 is connected to the power supply level VDD2 via a pull-up resistor, it becomes difficult for the controller 30 to receive the H level of the low voltage signal from the host device 101. That is, the H level of the low voltage signal corresponds to the power supply level VDD1, but since the line L32 is pulled up to the higher power supply level VDD2, the H level of the low voltage signal is transmitted from the terminal 12 to the node N32 of the controller 30. Not done.

In contrast, in this embodiment, the line L32 is pulled down by the resistive element R2, so that the controller 30 can easily receive the H level of the low voltage signal from the host device 101. That is, the H level of the low voltage signal corresponds to the power supply level VDD1, but since the line L32 is pulled down to a lower ground level, the H level of the low voltage signal can be transmitted from the terminal 12 to the node N32 of the controller 30. .

One end of resistance element R33 is connected to power supply level VDD2, and the other end is connected to line L33. Line L33 connects node N33 and the output node of output circuit 33b. Resistance element R33 functions as a pull-up resistor and can pull up line L33.

One end of resistance element R34 is connected to power supply level VDD2, and the other end is connected to line L34. Line L34 connects node N34 and the input node of input circuit 34a. Resistance element R34 can function as a pull-up resistor and pull up line L34.

One end of resistance element R35 is connected to power supply level VDD2, and the other end is connected to line L35. Line L35 connects node N35, the output node of output circuit 35b, and the input node of input circuit 35a. Resistance element R35 functions as a pull-up resistor and can pull up line L35.

Input circuit 31a is connected between node N31 and control section 36. The input circuit 31a has an input node connected to a node N31 and a resistance element R31 via a line L31, and an output node connected to the control section 36.

FIG. 3 is a circuit diagram showing the configuration of the input circuit and output circuit of the controller 30 of the memory system 1 according to the embodiment. As shown in FIG. 3(a), the input circuit 31a may be configured as a push-pull type. The input circuit 31a includes a transistor NM11 and a transistor PM11. Transistor NM11 and transistor PM11 are inverter-connected between node N31 and control section 36. The transistor NM11 is, for example, an NMOS transistor, and its source is connected to a reference level (eg, ground level). Transistor PM11 is, for example, a PMOS transistor, and its source is connected to power supply level VDD2. The transistor NM11 and the transistor PM11 have gates connected in common to constitute an input node, and drains connected in common to constitute an output node.

When the input circuit 31a shown in FIG. 2 receives an H level signal at the node N31, the transistor PM11 is turned off, the transistor NM11 is turned on, and the input circuit 31a outputs an L level signal to the control section 36. When the input circuit 31a receives an L level signal at the node N31, the transistor PM11 is turned on, the transistor NM11 is turned off, and the input circuit 31a outputs an H level signal to the control section 36.

The input circuit 32a and the output circuit 32b are each connected between the node N32 and the control unit 36. The input circuit 32a has an input node connected to the node N32 and the resistance element R2 via the line L32, and an output node connected to the control unit 36. The output circuit 32b has an input node connected to the control unit 36, and an output node connected to the node N32 and the resistance element R2 via lines L321 and L32. Line L321 has one end connected to line L32 and the other end connected to the output node of output circuit 32b.

As shown in FIG. 3(b), the input circuit 32a may be of a push-pull type, and the output circuit 32b may be of an open-drain type.

The input circuit 32a may be configured as a push-pull type. Input circuit 32a includes a transistor NM12 and a transistor PM12. Transistor PM12 is, for example, a PMOS transistor, and its source is connected to power supply level VDD1. In other respects, the input circuit 32a is configured similarly to the input circuit 31a shown in FIG. 3(a).

When the input circuit 32a receives an H level signal at the node N32, the transistor PM12 is turned off, the transistor NM12 is turned on, and the input circuit 32a outputs an L level signal to the control section 36. When the input circuit 32a receives an L level signal at the node N32, the transistor PM12 is turned on, the transistor NM12 is turned off, and the input circuit 32a outputs an H level signal to the control section 36.

The output circuit 32b may be configured as an open drain type. Output circuit 32b includes a transistor PM13. The transistor PM13 is, for example, a PMOS transistor, and has a source connected to the power supply level VDD2, a drain connected to the node N32 and the resistance element R2 via the line L32, and a gate connected to the control unit 36.

When the output circuit 32b receives an L level signal from the control unit 36, the transistor PM13 turns on and outputs an H level signal to the node N32. In the output circuit 32b, when receiving an H level signal from the control unit 36, the transistor PM13 is turned off and the node N32 becomes high impedance.

Output circuit 33b shown in FIG. 2 is connected between node N33 and control section 36. The output circuit 33b has an input node connected to the control unit 36, and an output node connected to the node N33 and the resistance element R33 via the line L33.

As shown in FIG. 3(c), the output circuit 33b may be configured as an open-drain type. Output circuit 33b includes a transistor NM21. The transistor NM21 is, for example, an NMOS transistor, and has a source connected to a reference level (for example, ground level), a drain connected to a node N33 and a resistance element R33 via a line L33, and a gate connected to the control unit 36. .

When the output circuit 33b receives an H level signal from the control unit 36, the transistor NM21 turns on and pulls the node N33 to the L level. When the output circuit 33b receives an L-level signal from the control unit 36, the transistor NM21 is turned off and the node N33 becomes high impedance.

Input circuit 34a shown in FIG. 2 is connected between node N34 and control section 36. Input circuit 34a shown in FIG. The input circuit 34a has an input node connected to a node N34 and a resistance element R34 via a line L34, and an output node connected to the control unit 36.

The input circuit 34a may have a push-pull configuration similar to the configuration shown in FIG. 3(a).

The output circuit 35b and input circuit 35a shown in FIG. 2 are connected between the node N35 and the control unit 36, respectively. The output circuit 35b has an input node connected to the control unit 36, and an output node connected to the node N35 and the resistance element R35 via the line L35. The input circuit 35a has an input node connected to a node N35 and a resistance element R35 via lines L351 and L35, and an output node connected to the control section 36. Line L351 has one end connected to line L35 and the other end connected to the input node of input circuit 35a.

As shown in FIG. 3(d), the output circuit 35b may be of an open-drain type, and the input circuit 35a may be of a push-pull type.

The output circuit 35b may be configured of an open drain type similar to the configuration shown in FIG. 3(c).

When the output circuit 35b receives an H level signal from the control unit 36, the transistor NM22 is turned on and pulls the node N35 to the L level. When the output circuit 35b receives an L level signal from the control unit 36, the transistor NM22 is turned off and the node N35 becomes high impedance.

The input circuit 35a may have a push-pull configuration similar to the configuration shown in FIG. 3(a).

When the input circuit 35a receives an H level signal from the node N35, the transistor PM15 is turned off, the transistor NM15 is turned on, and the input circuit 35a outputs an L level signal to the control section 36. When the input circuit 35a receives an L level signal from the node N35, the transistor PM15 is turned on, the transistor NM15 is turned off, and the input circuit 35a outputs an H level signal to the control section 36.

FIG. 4 is a diagram illustrating the signal voltage range of the input/output circuit of the memory system according to the embodiment. As shown in FIG. 4, each of the input circuits 31a, 32a, 34a, and 35a is set so that its circuit threshold can correspond to both a low voltage signal and a high voltage signal.

For example, the low voltage signal has a voltage range corresponding to power supply level VDD1. The low voltage signal has an H level V _LH voltage range V _{LH (min)} to V _{LH (max)} that includes the power supply level VDD1 (for example, 1.8 V), and an L level V _LL voltage range that includes ground. The voltage range is V _{LL (min)} to V _{LL (max)} including level GND. For example, the upper limit of H level V _LH is 1.95V, the lower limit of H level V _LH is 1.7V, the upper limit of L level V _LL is VDD1×0.3=0.54V, and the upper limit of H level V LH is VDD1×0.3=0.54V. The lower limit of _LL may be -0.3V.

The high voltage signal has a voltage range corresponding to power supply level VDD2. The high voltage signal can span a voltage range. In the high voltage signal, the voltage range of the H level V _HH is the voltage range V _{HH (min)} to V _{HH (max)} including the power supply level VDD2 (for example, 3.3 V), and the voltage range of the L level V _HL is the ground The voltage range is V _{HL (min)} to V _{HL (max)} including level GND. For example, the upper limit of H level V _HH is 3.456V, the lower limit of H level V _HH is 2.7V, the upper limit of L level V _HL is VDD2×0.25=0.825V, The lower limit of _HL may be -0.3V.

The input circuit 32a has an operating voltage range that can accommodate both low voltage signals and high voltage signals. The input circuit 32a has an H level V _IH voltage range V _{IH (min)} to V _{IH (max)} . The voltage range V _{IH (min)} to V _{IH (max) of the H level V IH of the input circuit 32a is the voltage range V LH (} min) to V _{LH (} max) of the H level V _LH of the low voltage signal and the high voltage signal. The H level V _HH includes a voltage range V _{HH (min)} to V _{HH (max)} . The upper limit of the H level V _HH of the input circuit 32a may be 3.456V, and the lower limit of the H level _VIH may be VDD2×0.5=1.65V.

The input circuit 32a has an L level V _IL voltage range V _{IL (min)} to V _{IL (max)} . The voltage range V _{IL (min)} to V _{IL (max)} of the L level V _IL of the input circuit 32a is the voltage range V LL _{(min) to V LL (} max) of the L level V _LL of the low voltage signal and the high voltage signal. The voltage range of the L level V _HL of V _{HL (min)} to V _{HL (max)} is included. The upper limit of the L level _VIL of the input circuit 32a may be VDD2×0.25=0.825V, and the lower limit of the L level _VHL may be −0.3V.

Note that the voltage ranges of the other input circuits 31a, 34a, and 35a may be the same as the voltage range of the high voltage signal.

FIG. 5 is a flowchart for explaining the operation of the memory system according to the embodiment. FIG. 6 is a diagram showing the operation of the memory system 1 according to the embodiment. FIG. 6 shows the operation when the signal line L11 in the peripheral circuit 20 is pulled up to the power supply level VDD1. FIG. 7 is a diagram showing the operation of the memory system 1 according to the embodiment. FIG. 7 shows the operation when the signal line L11 in the peripheral circuit 20 is pulled up to the power supply level VDD2. The operation of the memory system 1 will be explained using FIGS. 5 to 7.

In the memory system 1, the controller 30 receives from the host device 101 a signal indicating whether the signal to be transmitted by the host device 101 is a low voltage signal (S1), and checks whether the level of the signal is H level or not. (S2).

For example, as shown in FIGS. 6(a) and 7(a), the control unit 36 in the controller 30 receives a second signal from the host device 101 via the terminal 12, the signal line L12, and the input circuit 32a, and receives the second signal as an input signal. Depending on the output of the circuit 32a, it is determined whether the level of the second signal is H level or not. The second signal is a high active signal and is maintained at H level when the first to sixth signals transmitted and received with the host device 101 are low voltage signals, and the second signal is a high active signal that is maintained at the H level when the first to sixth signals transmitted and received with the host device 101 are low voltage signals. When the signal No. 6 is not a low voltage signal (that is, a high voltage signal), the host device 101 does not output the second signal and is therefore maintained at L level. At this time, the control unit 36 turns off the output circuit 32b, and the output node of the output circuit 32b becomes high impedance. That is, the control unit 36 supplies the H level to the gate of the transistor PM13 in the output circuit 32b shown in FIG. 3(b), and the transistor PM13 is maintained in the off state. This maintains the drain of transistor PM13 at high impedance.

Returning to FIG. 5, if the level of the signal received in S1 is H level (Yes in S2), the controller 30 outputs high impedance (S3). Thereby, the peripheral circuit 20 pulls up the signal line L11 to the power supply level VDD1.

For example, as shown in FIG. 6B, the control unit 36 in the controller 30 maintains the output circuit 32b in the off state in response to the second signal being at the H level, and connects the output node of the output circuit 32b. maintains high impedance. That is, the controller 30 outputs high impedance to the signal line L12. As a result, the resistive element R1 receives at one end the second signal having the H level V _LH (that is, the H level V _LH of the low voltage signal) corresponding to the power supply level VDD1, so that the signal line connected to the other end L11 can be pulled up to substantially the power supply level VDD1. Accordingly, the host device 101 can transmit a low voltage signal to the terminal 11, the peripheral circuit 20 can receive the low voltage signal through the terminal 11, and the control unit 36 in the controller 30 can transmit the low voltage signal to the terminal 11, the signal line A low voltage signal can be received via L11 and input circuit 31a.

Returning to FIG. 5, if the level of the signal received in S1 is L level (No in S2), controller 30 outputs H level _VHH (S4). The H level V _HH is the H level V _HH of a high voltage signal, and has a voltage range according to the power supply level VDD2 (see FIG. 4). Thereby, the peripheral circuit 20 substantially pulls up the signal line L11 to the power supply level VDD2.

For example, as shown in FIG. 7B, the control unit 36 in the controller 30 turns on the output circuit 32b in response to the second signal being at the L level, and sets the output node of the output circuit 32b to the H level. Maintain at _VHH . That is, the controller 30 outputs the H level _VHH of the high voltage signal to the signal line L12. As a result, the resistive element R1 receives a signal having an H level corresponding to the power supply level VDD2 from the output circuit 32b at one end, so that the signal line L11 connected to the other end can be substantially pulled up to the power supply level VDD2. Accordingly, as shown in FIG. 7(c), the host device 101 can transmit a high voltage signal to the terminal 11, the peripheral circuit 20 can receive the high voltage signal via the terminal 11, and the controller 30 The control unit 36 can receive a high voltage signal via the terminal 11, the signal line L11, and the input circuit 31a.

As described above, in the embodiment, in the peripheral circuit 20 of the memory system 1, the signal line L11 and the signal line L12 are connected by the resistance element R1. In this configuration, the controller 30 receives the second signal from the host device 101 via the signal line L12. The second signal becomes an H level when the host device 101 should transmit/receive a low voltage signal, and becomes an L level when the host device 101 should transmit/receive a high voltage signal. The controller 30 outputs high impedance to the signal line L12 if the second signal is at an H level _VLH (corresponding to the power supply level VDD1), and outputs high impedance to the signal line L12 if the second signal is at the L level (corresponding to the power supply level VDD2). ) Outputs the H level V _HH to the signal line L12. Thereby, the signal line L11 can be pulled up to the power level VDD1 or the power level VDD2 depending on the signal to be transmitted by the host device 101.

Note that in the embodiment, a configuration in which the peripheral circuit 20 is arranged outside the controller 30 is illustrated, but the peripheral circuit 20 may be arranged inside the controller 30. In this case, the nodes N31 to N35 may be electrodes, or the nodes N31 to N35 may be other than electrodes (for example, the lines themselves). Further, when the peripheral circuit 20 is arranged inside the controller 30, the controller 30 includes signal lines L11 to L15, level shifters 21, 23 to 25, resistance elements R1, R11 to R15, electrodes N31 to N35, resistance element R31, It has R2, R33, R34, R35, input circuits 31a, 32a, 34a, 35a, output circuits 32b, 33b, 35b, and a control section 36.

For example, if a voltage switching circuit is additionally provided between the signal line L12 and the controller 30 in order to pull up the signal line L11 to the power supply level VDD1 or the power supply level VDD2, the circuit on the connector section 10 side in the peripheral circuit 20 There is a possibility that the scale will increase and the cost of the peripheral circuit 20 will increase.

In contrast, in the embodiment, the signal line L11 can be pulled up to the power supply level VDD1 or the power supply level VDD2 without additionally providing a voltage switching circuit, so it is possible to suppress an increase in the cost of the peripheral circuit 20.

Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

1 memory system, 10 connector, 20 peripheral circuit, 30 controller, 31a, 32a, 34a, 35a input circuit, 32b, 33b, 35b output circuit, 36 control unit, 40 nonvolatile memory, 101 host device L11 to L15 signal line, R1, R2, R11~R15, R31, R33~R35 Resistance element.

Claims (7)

a connector having a first terminal and a second terminal, each of which is connectable to a host device;
non-volatile memory,
a controller connected between the connector and the nonvolatile memory;
Equipped with
The controller includes:
a control circuit having a first node and a second node;
a first signal line connected between the first terminal and the first node and capable of being pulled up to a first power level or a second power level;
a second signal line connected to the second terminal;
a first resistance element having one end connected to the first signal line and the other end connected to the second signal line;
A memory system with The memory system according to claim 1, wherein the second signal line is connected between the second terminal and the second node. The control circuit includes:
3. The memory system according to claim 2, further comprising a second resistive element having one end connected to the second node and the other end connected to a reference level. The control circuit includes:
4. The memory system according to claim 3, further comprising a third resistance element having one end connected to the first node and the other end connected to the second power supply level. The control circuit sets the second node to high impedance when the second terminal is at a first level, and sets the second node to a high impedance when the second terminal is at a second level. 3. The memory system of claim 2, having three levels. The control circuit includes:
a push-pull input circuit connected to the second node;
an open-drain output circuit connected to the second node;
6. The memory system according to claim 5, further comprising: the first level corresponds to the first power level;
the second level is a reference level;
6. The memory system of claim 5, wherein the third level corresponds to the second power level.

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