JP2023118911A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device with which it is possible to bring a contact region and a source electrode in a connection region into direct contact on a front surface side of a semiconductor substrate.SOLUTION: A first trench 7 constituting a trench gate structure and a second trench 21 constituting a trench side wall SBD20 are alternately and repeatedly arranged in an active region 41. A gate runner 34 and a gate pad are provided on a front surface of a semiconductor substrate 10 in a connection region 43. Some of the first trenches 7 extends in a first direction X up to a recess 43a in the connection region 43 and is connected in said part 51 facing the gate runner 34 in a depth direction Z. In the connection region 43, a contact hole 11b, having had a p+ type contact region 6 exposed, is provided on a side opposite the first trench 7 as seen from the runner connection region 51 in the first direction X. A source electrode ohmically contacts the p+ type contact region 6 that is exposed to the contact hole 11b.SELECTED DRAWING: Figure 3

Description

The present invention relates to semiconductor devices.

Conventionally, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: hereinafter referred to as SiC-MOSFET) using silicon carbide (SiC) as a semiconductor material, a p-type base region and an n ^{− -type} drift region When the parasitic pn diode formed by the pn junction of is forward-biased and a bipolar current flows through the parasitic pn diode, stacking faults grow inside the semiconductor substrate (semiconductor chip). As a result, deterioration of forward characteristics is caused.

This forward characteristic deterioration can be suppressed by embedding a Schottky barrier diode (SBD) in the same semiconductor substrate as the SiC-MOSFET. The reason is that when the parasitic pn diode of the SiC-MOSFET is forward biased, the bipolar current flows through the SBD at a forward voltage lower than the forward voltage at which the bipolar current begins to flow through the parasitic pn diode. is. Also, by preventing a bipolar current from flowing through the parasitic pn diode, it is possible to reduce the on-resistance of the SiC-MOSFET.

A structure of a conventional SiC-MOSFET will be described. FIG. 14 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device shown in FIG. 14 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 210 made of silicon carbide. The trench sidewall SBD 220 is built in. The trench gate structure consists of p-type base region 204 , n ⁺ -type source region 205 , p ⁺ -type contact region 206 , first trench 207 , gate insulating film 208 and gate electrode 209 provided in active region 241 .

First trench 207 penetrates n ⁺ -type source region 205 and p-type base region 204 to reach n-type current diffusion region 203 . A gate electrode 209 is provided inside the first trench 207 with a gate insulating film 208 interposed therebetween. A second trench 221 is provided between adjacent first trenches 207 so as to be separated from the first trenches 207 . Second trench 221 penetrates p ⁺ -type contact region 206 and p-type base region 204 to reach n-type current diffusion region 203 . A conductive layer 222 made of titanium (Ti) or tungsten (W) is buried inside the second trench 221 .

An SBD (hereinafter referred to as a trench sidewall SBD) 220 is formed on the sidewall of the second trench 221 by a Schottky junction between the conductive layer 222 and the n-type current diffusion region 203 . A p ⁺ -type region 216 is provided to reach a predetermined depth from the bottom surfaces of the first and second trenches 207 and 221 toward the drain side (n ⁺ -type drain region 201 side). The p ⁺ -type region 216 protrudes from the sidewalls of the first and second trenches 207 and 221 in a direction parallel to the front surface of the semiconductor substrate 210 . Numerals 202, 211 to 215 denote an n ⁻ -type drift region, interlayer insulating film, source electrode, barrier metal, source pad and drain electrode, respectively.

As a conventional MOSFET with an SBD built into the same semiconductor substrate, a device has been proposed in which an n-type region with a lower impurity concentration than the drain region of the MOSFET is provided in the center of the semiconductor substrate as the cathode region of the SBD ( For example, see Patent Document 1 below (paragraphs 0101 to 0103, and FIGS. 42 to 44). As another conventional MOSFET with an SBD built into the same semiconductor substrate, a device in which MOSFET cells and SBD cells are arranged in stripes has been proposed (for example, Patent Document 2 below (paragraphs 0086 to 0096, 24-27)).

JP 2008-042056 A Japanese Patent Application Laid-Open No. 2017-175100

However, in the conventional silicon carbide semiconductor device described above, the gate electrode 209 is formed by etching back the polysilicon deposited so as to fill the inside of the first trench 207 and leaving the polysilicon only inside the first trench 207 . When forming, the following problems arise. 15 and 16 are plan views showing layouts of conventional silicon carbide semiconductor devices viewed from the front surface side of the semiconductor substrate. FIG. 15 shows the layout of active area 241 , edge termination area 242 , bridging area 243 and gate pad area 244 . FIG. 16 shows the layout of formation areas for trench sidewall SBD 220 and PiN diode 230 (shown as "SBD" and "PiN" respectively in FIG. 16).

17 is a plan view showing an enlarged area surrounded by a rectangular frame AA in FIGS. 15 and 16. FIG. A region surrounded by a rectangular frame AA in FIGS. 15 and 16 is the same portion of the semiconductor substrate 210, and indicates the vicinity of the boundary between the concave portion 241a of the active region 241 and the convex portion 243a of the connecting region 243, which will be described later. A pair of paired vertices AA1 and AA2 of this rectangular frame AA are located in the active region 241 and the connecting region 243, respectively. Specifically, FIG. 17 shows the layout of the first and second trenches 207 and 221 near the protrusion 243a of the connecting region 243. As shown in FIG. 18 is a plan view showing an enlarged connection region of FIG. 15. FIG. FIG. 19 is a cross-sectional view showing a cross-sectional structure taken along line BB1-BB3 of FIG.

The conventional silicon carbide semiconductor device shown in FIGS. 15 to 19 is a SiC-SiC semiconductor device in which a gate pad region 244 is provided in a region (hereinafter referred to as a connecting region) 243 between an active region 241 and an edge termination region 242 of a semiconductor substrate 210 . MOSFETs. The active region 241 has a substantially rectangular planar shape, and has a concave portion 241a which is partially recessed inward in a substantially rectangular shape on one side thereof. Unit cells of the SiC-MOSFET and the trench sidewall SBD 220 are arranged in the active region 241 . The cross-sectional structure of the active region 241 (FIG. 17) is similar to that of the conventional SiC-MOSFET shown in FIG. Edge termination region 242 surrounds active region 241 . No device structures are located in the edge termination region 242 (shown as "non" in FIG. 16).

The connecting region 243 is arranged in a substantially annular shape surrounding the active region 241 and has a planar shape having a substantially rectangular projection 243 a that partially fits into the recess 241 a of the active region 241 . The connecting region 243 is composed of a p-type region provided in the surface region of the front surface of the semiconductor substrate 210 . A pn junction between this p-type region and the n ⁻ -type drift region 202 forms a parasitic PiN diode 230 . A gate pad region 244 in which the gate pad 235 (see FIG. 17) is arranged is provided in the convex portion 243a of the connecting region 243. As shown in FIG. In FIG. 15, the connecting region 243 and the gate pad region 244 are indicated by dotted and oblique hatching, respectively.

Further, as shown in FIG. 17, in the active region 241, a first trench 207 forming the trench gate structure of the unit cell of the SiC-MOSFET and a second trench 221 forming the trench side wall SBD 220 are formed on the semiconductor substrate 210. are arranged in stripes extending in a direction X (hereinafter referred to as a first direction) parallel to the front surface of the . The first trenches 207 and the second trenches 221 are alternately and repeatedly arranged in a direction Y (hereinafter referred to as a second direction) parallel to the front surface of the semiconductor substrate 210 and perpendicular to the first direction X. there is The first trench 207a (207) is arranged closest to the protrusion 243a of the connecting region 243 in the second direction Y. As shown in FIG.

The p ⁺ -type region 216 (231) facing in the depth direction Z to the bottom surface of the first trench 207a arranged closest to the protrusion 243a of the connecting region 243 in the second direction Y extends over the entire connecting region 243. (see FIG. 19). In FIG. 19, the portion of this p ⁺ -type region 216 extending to the connecting region 243 is denoted by reference numeral 231 . The p ⁺ -type contact region 206 and the p-type base region 204 of the SiC-MOSFET extend over the bridging region 243 (see FIG. 19). A p + -type region 232 is provided between the p-type base region 204 and the ^{p + -type} region 231 in the connecting region 243 .

The p ⁺ type contact region 206, the p type base region 204, the p ⁺ type region 232 and the p ⁺ type region 231 of these connecting regions 243, the n type current diffusion region 203, the n ⁻ type drift region 202 and A parasitic PiN diode 230 is formed at the pn junction with the n ⁺ -type drain region 201 . PiN diode 230 has substantially the same surface area and substantially the same planar shape as tie region 243 . In the connection region 243, a gate runner 234 made of polysilicon (poly-Si) is provided on the front surface of the semiconductor substrate 210 with a field oxide film 233 interposed therebetween. The gate runner 234 extends annularly around the active region 241 in the same manner as the connecting region 243, and has a planar surface with a substantially rectangular convex portion 234a partially protruding into the convex portion 243a of the connecting region 243. shape.

At the annular portion (not shown) and the convex portion 243a of the connecting region 243, the end portion of the first trench 207 extends to directly under the gate runner 234 (on the side of the n ⁺ -type drain region 201). At the end of the first trench 207, the gate electrode 209 and the gate pad 235 are electrically connected via the gate runner 234. As shown in FIG. Reference numeral 214a is the end of the source pad 214. As shown in FIG. On the other hand, the end of the second trench 221 terminates at a position away from the connecting region 243 (the portion enclosed by the rectangular frame denoted by reference numeral 251 in FIG. 17). In FIG. 17, the first trenches 207 covered with the interlayer insulating film 211 are indicated by broken lines, and the second trenches 221 exposed to the source contact holes 211a of the interlayer insulating film 211 are indicated by solid lines.

In addition, in order to form the source contact hole 211a in the region 252 between the first trench 207a arranged closest to the projection 243a of the connecting region 243 in the second direction Y and the projection 234a of the gate runner 234. cannot secure a margin of Therefore, trench sidewall SBD 220 cannot be formed in this region 252 . Thus, it is difficult to arrange trench sidewall SBD 220 at the boundary between concave portion 241 a of active region 241 and convex portion 243 a of connecting region 243 . In addition, since the distance C101 from the p ⁺ -type contact region 206 of the bridging region 243 to the source electrode 212 is increased, the contact resistance of the p ⁺ -type contact region 206 of the bridging region 243 is increased, causing a decrease in avalanche resistance.

In addition, since the trench sidewall SBD 220 cannot be arranged near the boundary between the concave portion 241a of the active region 241 and the convex portion 243a of the connecting region 243, the trench sidewall SBD 220, the p ⁺ -type contact region 206 of the connecting region 243, distance C102 increases. That is, the distance between trench sidewall SBD 220 and PiN diode 230 increases. This facilitates the flow of bipolar current, and the PiN diode 230 is easily turned on when a large current flows. FIG. 20 is a characteristic diagram showing the relationship between the distance between a PiN diode and a unipolar element arranged on the same semiconductor substrate and the bipolar current. FIG. 21 is a cross-sectional view showing a cross-sectional structure of a sample used for verification of FIG.

The horizontal axis of FIG. 20 is the distance d between the PiN diode 260a and the unipolar element 260b of FIG. The vertical axis in FIG. 20 represents the ratio of the current amount of the bipolar element arranged on the semiconductor substrate 265 to the current amount of the unipolar element 260b (=current amount of the bipolar element/current amount of the unipolar element). FIG. 20 shows the ratio of the current amount of the bipolar element arranged on the semiconductor substrate 265 to the current amount of the unipolar element 260b (hereinafter referred to as the bipolar current amount ratio), which was measured by changing the critical current density Jc of the bipolar element. ). It is assumed that when the bipolar current amount ratio is in the range E of 1×10 ⁻¹ or more, the bipolar element in FIG. 21 suffers forward deterioration due to the operation of the PiN diode 260a.

The sample shown in FIG. 21 incorporates a unipolar element 260b in the same semiconductor substrate 265 as a bipolar element (not shown). A semiconductor substrate 265 is a silicon carbide epitaxial substrate obtained by epitaxially growing an n ⁻ -type layer 262 on an n ⁺ -type starting substrate 261 made of silicon carbide. Two p ^- type regions 263 are selectively separated from each other on the surface layer of the n − -type layer 262 opposite to the n ⁺ -type starting substrate 261 side (surface layer on the front surface of the semiconductor substrate 265). formed. A width wJFET of a portion (hereinafter referred to as a JFET region) 264 sandwiched between two p-type regions 263 of the n ⁻ -type layer ₂₆₂ is set to 1.0 μm. An SBD (not shown) is arranged on this JFET region 264 via an oxide film.

The bipolar current amount ratio was measured by variously changing the critical current density Jc of the bipolar element shown in FIG. In FIG. 21, the direction of the arrow labeled 266 is the direction in which the PiN diode 260a separates from the unipolar element 260b (that is, the direction in which the distance d between the PiN diode 260a and the unipolar element 260b increases). FIG. 20 shows the relationship between the distance d between the PiN diode 260a and the unipolar element 260b and the bipolar current amount ratio. As shown in FIG. 20, it was confirmed that the longer the distance d between the PiN diode 260a and the unipolar element 260b, the easier the flow of the bipolar current. This result becomes more pronounced as the critical current density Jc of the bipolar element increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a contact region of a connecting region and a source electrode can be brought into direct contact on the front surface side of a semiconductor substrate.

In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. That is, in a semiconductor device including a semiconductor substrate made of silicon carbide, a drift region of a first conductivity type provided in the semiconductor substrate and a drift region provided between the front surface of the semiconductor substrate and the drift region. a second conductive type base region provided on the front surface side of the semiconductor substrate; a first conductive type source region provided on the front surface side of the semiconductor substrate; a plurality of trenches extending into a semiconductor substrate; a gate runner provided on a front surface of the semiconductor substrate; and a gate runner provided on the front surface of the semiconductor substrate and electrically connected to the gate runner. and a second pad provided on the front surface of the semiconductor substrate and not electrically connected to the gate runner, wherein the plurality of trenches are adjacent to the source region. a first trench extending in a first direction to a runner connection region where the first conductive portion is provided inside and the first conductive portion is connected to the gate runner; A contact region of the second conductivity type is provided on the front surface side of the semiconductor substrate opposite to the first trench as viewed from above, and a contact hole is provided to expose the contact region. Alternatively, a semiconductor device comprising a semiconductor substrate made of silicon carbide, wherein a first conductivity type drift region provided in the semiconductor substrate, a front surface of the semiconductor substrate, and a front surface of the semiconductor substrate. A base region of a second conductivity type provided between the drift region, a source region of a first conductivity type provided on the front surface side of the semiconductor substrate, and from the front surface of the semiconductor substrate a plurality of trenches extending through the base region to the inside of the semiconductor substrate; a gate runner provided on a front surface of the semiconductor substrate; a first pad provided on the front surface of the semiconductor substrate and electrically connected to the gate runner; and a second pad provided on the front surface of the semiconductor substrate and not electrically connected to the gate runner. and a plurality of said trenches adjacent to said source region and provided therein with a first conductive portion, said first conductive portion extending in a first direction to a runner connection region where said first conductive portion is connected to said gate runner. A first trench and a second conductive portion electrically connected to the second pad are provided therein, and the second conductive portion extends from the opposite side of the first trench toward the runner connection region in the first direction. 2 trenches.

According to the semiconductor device of the present invention, it is possible to bring the contact region of the connecting region into direct contact with the source electrode on the front surface side of the semiconductor substrate.

1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate; FIG. 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate; FIG. It is a top view which expands and shows the area|region enclosed by the rectangular frame A of FIG.1, 2. FIG. FIG. 2 is a plan view showing an enlarged connection region of FIG. 1; FIG. 4 is a cross-sectional view showing a cross-sectional structure taken along line B1-B2 in FIG. 3; FIG. 10 is a plan view showing the layout of the silicon carbide semiconductor device according to the second embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 7 is a cross-sectional view showing a cross-sectional structure taken along line D1-D2 in FIG. 6; FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a third embodiment, viewed from the front surface side of a semiconductor substrate; FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line E1-E2 in FIG. 8; FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a fourth embodiment, viewed from the front surface side of a semiconductor substrate; FIG. 11 is a cross-sectional view showing a cross-sectional structure taken along line F1-F2 of FIG. 10; FIG. 11 is a plan view showing a layout of a silicon carbide semiconductor device according to a fifth embodiment, viewed from the front surface side of a semiconductor substrate; FIG. 13 is a plan view showing an enlarged connection region of FIG. 12; It is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. It is a top view which shows the layout which looked at the conventional silicon carbide semiconductor device from the front surface side of a semiconductor substrate. It is a top view which shows the layout which looked at the conventional silicon carbide semiconductor device from the front surface side of a semiconductor substrate. FIG. 17 is a plan view showing an enlarged area surrounded by a rectangular frame AA in FIGS. 15 and 16; FIG. 16 is a plan view showing an enlarged connection region of FIG. 15; FIG. 18 is a cross-sectional view showing the cross-sectional structure taken along the line BB1-BB3 of FIG. 17; FIG. 4 is a characteristic diagram showing the relationship between the distance between a PiN diode and a unipolar element arranged on the same semiconductor substrate and the bipolar current; FIG. 21 is a cross-sectional view showing a cross-sectional structure of a sample used for verification of FIG. 20;

Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

(Embodiment 1)
A structure of the silicon carbide semiconductor device according to the first embodiment will be described. 1 and 2 are plan views showing layouts of the silicon carbide semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate. FIG. 2 shows the layout of formation regions for trench sidewall SBD 20 and PiN diode 30 (shown as "SBD" and "PiN" respectively in FIG. 2). 2 also shows the layout of the active region 41, the edge termination region 42, the connecting region 43 and the gate pad region 44 shown in the semiconductor substrate (semiconductor chip) 10 of FIG. 1 by dashed lines.

FIG. 3 is a plan view showing an enlarged area surrounded by a rectangular frame A in FIGS. 1 and 2. FIG. A region surrounded by a rectangular frame A in FIGS. 1 and 2 is the same portion of the semiconductor substrate 10, and indicates the vicinity of the boundary between the concave portion 41a of the active region 41 and the convex portion 43a of the connecting region 43, which will be described later. A pair of paired vertices A1 and A2 of the rectangular frame A are located in the active region 41 and the connecting region 43, respectively. FIG. 3 shows the layout of the first and second trenches 7 and 21 near the protrusion 43a of the connecting region 43. As shown in FIG. 4 is a plan view showing an enlarged connection region of FIG. 1. FIG.

Silicon carbide semiconductor device 40 according to the first embodiment shown in FIGS. - It is a MOSFET. As shown in FIGS. 1 and 2, the active region 41 has a substantially rectangular planar shape and has a concave portion 41a formed by recessing a portion of one side of the active region 41 inward. The active region 41 is a region through which the main current flows when the SiC-MOSFET is on. SiC-MOSFET unit cells and trench sidewalls SBD20 are arranged in the active region 41 .

The edge termination region 42 is a region between the active region 41 and the side surface of the semiconductor substrate 10, surrounds the active region 41, relaxes the electric field on the front surface side of the semiconductor substrate 10, ). The withstand voltage is the limit voltage at which the semiconductor device does not malfunction or break down. General breakdown voltage structures such as guard rings, field plates, and resurfs are arranged in the edge termination region 42 . No device structures are located in the edge termination region 42 (shown as "non" in FIG. 2).

The connecting region 43 is in contact with the active region 41 and the edge termination region 42 between the two regions, is arranged in a substantially annular shape surrounding the active region 41 , and has a size partly fitting into the recessed portion 41 a of the active region 41 . It has a planar shape having a convex portion 43a protruding in a substantially rectangular shape. The connecting region 43 is composed of a p-type region provided in the surface region of the front surface of the semiconductor substrate 10 . A pn junction between the p-type region and the n ⁻ -type drift region 2 forms a parasitic PiN diode 30 . The PiN diode 30 is formed over the entire surface of the connecting region 43 .

The p-type region forming the connecting region 43 is composed of the p ⁺ -type contact region 6, the p-type base region 4, and the p ⁺ -type regions 31 and 32, which will be described later. The p ⁺ -type regions 31 and 32 have substantially the same surface area and substantially the same planar shape as the connecting region 43 . In the connecting region 43, a gate runner 34 made of polysilicon (poly-Si) is formed on the front surface of the semiconductor substrate 10 with a gate insulating film 8 and a field oxide film 33 (see FIG. 5) interposed therebetween. is provided.

The gate runner 34 is arranged in a substantially annular shape surrounding the active region 41 and has a planar shape having a substantially rectangular convex portion 34 a that partially fits into the concave portion 41 a of the active region 41 . In the convex portion 34a of the gate runner 34, one side parallel to the first direction X among the three sides of the outer circumference of the convex portion 34a is patterned so as to remove a part of the convex portion 34a and is recessed inward. A concave portion 34b is formed. A second trench 21a (21) of the trench side wall SBD20 is arranged in the concave portion 34b of the convex portion 34a of the gate runner 34 as will be described later (see FIGS. 3 and 4).

Further, a gate pad region 44 is provided on the convex portion 43 a of the connecting region 43 . The gate pad region 44 has, for example, a substantially rectangular planar shape with a surface area smaller than that of the protrusion 43 a of the connecting region 43 . A gate pad (first pad) 35 is arranged in the gate pad region 44 . The gate pad 35 is provided on the gate runner 34 via the interlayer insulating film 11 (see FIG. 5). In FIG. 1, the connecting region 43 and the gate pad region 44 are indicated by dotted and oblique hatching, respectively.

As shown in FIG. 3, the first trench 7 forming the trench gate structure of the SiC-MOSFET unit cell (element unit) and the second trench 21 forming the trench sidewall SBD 20 are formed in the active region 41. They are arranged in stripes extending in a direction (first direction) X parallel to the front surface of the semiconductor substrate 10 . The first trenches (first and third trenches) 7 and the second trenches (second, third and fourth trenches) 21 are arranged parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X ( (second direction) Y) are alternately and repeatedly arranged.

A gate electrode (first and third conductive portions) 9 is provided inside the first trench 7 via a gate insulating film 8 (see FIG. 5). In FIG. 3, the gate insulating film 8 is omitted. The first trench 7 is covered with an interlayer insulating film 11 . A conductive layer (second to fourth conductive portions) 22 is embedded inside the second trench 21 . The second trench 21 is exposed to the first source contact hole 11 a of the interlayer insulating film 11 together with the p ⁺ -type contact region 6 adjacent to the second trench 21 .

In FIG. 3, the interlayer insulating film 11 is indicated by dotted hatching, and the conductive layer 22 is indicated by oblique hatching. In FIG. 3, the first trenches 7 covered with the interlayer insulating film 11 are indicated by broken lines, and the second trenches 21 exposed to the first source contact holes 11a of the interlayer insulating film 11 are indicated by solid lines. A second trench 21a (21) exposed in a second source contact hole 11b of an interlayer insulating film 11, which will be described later, is also indicated by a solid line (the same applies to FIGS. 6, 8, 10, and 12).

The first trench 7 extends in the first direction X to an annular portion (not shown) of the connecting region 43 . Among the plurality of first trenches 7 , the first trench (first trench) 7 of the active region 41 facing the protrusion 43 a of the connecting region 43 in the first direction X is located in the connecting region 43 in the first direction X. (portion indicated by reference numeral 51: runner connection region). The end of the first trench 7 faces the gate runner 34 in the depth direction Z in the connecting region 43 . At the end of first trench 7 , gate electrode 9 and gate pad 35 are electrically connected via gate runner 34 .

The second trench 21 terminates in the first direction X at a position away from the connecting region 43 . Further, when the first and second trenches 7 and 21 are alternately and repeatedly arranged in the second direction Y, the second trenches 21a (21) are arranged closest to the protrusion 43a of the connecting region 43 in the second direction Y. As shown in FIG. This second trench (second trench) 21a is arranged at a position 52 close to the concave portion 34b of the convex portion 34a of the gate runner 34, and the entirety thereof faces the concave portion 34b of the convex portion 34a of the gate runner 34 in the second direction Y. (see Figure 4). Part or all of the second trench 21 a may be arranged in the recess 34 b of the protrusion 34 a of the gate runner 34 .

Next, a cross-sectional structure of silicon carbide semiconductor device 40 according to the first embodiment will be described. FIG. 5 is a cross-sectional view showing a cross-sectional structure taken along line B1-B2 in FIG. The semiconductor substrate 10 includes silicon carbide layers 61 and 61 that form the n ^{− -type} drift region 2 and the p-type base region 4 on the front surface of an n ⁺ -type starting substrate made of silicon carbide that forms the n + -type drain region 1 . It is an epitaxial substrate on which 62 is epitaxially grown in order. The main surface of semiconductor substrate 10 on the p-type silicon carbide layer 62 side is the front surface, and the main surface on the n ⁺ -type starting substrate (n ⁺ -type drain region 1) side is the rear surface.

An n ^- type region (hereinafter referred to as an n-type current diffusion region) 3 is provided in n − -type silicon carbide layer 61 to reach a predetermined depth from the interface with p-type silicon carbide layer 62 . The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces spreading resistance of carriers. The n-type current diffusion region 3 extends from the active region 41 to the connection region 43 with a uniform thickness in the direction parallel to the front surface of the semiconductor substrate 10 . The n-type current spreading region 3 may extend up to the edge termination region 42 .

A portion of n ⁻ -type silicon carbide layer 61 other than n-type current diffusion region 3 is n ⁻ -type drift region 2 . N-type current diffusion region 3 is exposed on sidewalls of first and second trenches 7 and 21 between n ⁻ type drift region 2 and p-type base region 4 (p-type silicon carbide layer 62). An n ⁺ -type source region 5 and a p ⁺ -type contact region 6 are selectively provided inside the p-type silicon carbide layer 62 . A portion of p-type silicon carbide layer 62 other than n ⁺ -type source region 5 and p ⁺ -type contact region 6 is p-type base region 4 .

Further, in the p-type silicon carbide layer 62 , a second layer extending from the front surface of the semiconductor substrate 10 through the n ⁺ -type source region 5 and the p-type base region 4 in the depth direction Z and reaching the n-type current diffusion region 3 is provided. 1 trenches 7 are provided. A gate electrode 9 made of polysilicon is provided inside the first trench 7 with a gate insulating film 8 interposed therebetween. Furthermore, in the p-type silicon carbide layer 62 , a second silicon carbide layer is formed extending from the front surface of the semiconductor substrate 10 through the p ⁺ -type contact region 6 and the p-type base region 4 in the depth direction Z to reach the n-type current diffusion region 3 . 2 trenches 21 are provided.

A conductive layer 22 made of titanium (Ti) or tungsten (W) is buried inside the second trench 21 . SBDs (trench side wall SBDs) 20 are formed on both sidewalls of the second trench 21 by Schottky junctions between the conductive layers 22 and the n-type current diffusion regions 3 . The conductive layer 22 extends from the side wall of the second trench 21 onto the front surface of the semiconductor substrate 10 and partially covers the p ⁺ -type contact region 6 . Also, the conductive layer 22 is connected to the source electrode 12 on the front surface of the semiconductor substrate 10 .

An interlayer insulating film 11 is provided on the front surface of semiconductor substrate 10 so as to cover gate electrode 9 . The n ⁺ type source region 5 , the p ⁺ type contact region 6 and the conductive layer 22 are exposed in the first source contact hole 11 a of the interlayer insulating film 11 . The source electrode 12 is in ohmic contact with the semiconductor portion (the n ⁺ -type source region 5 and the p ⁺ -type contact region 6) inside the first source contact hole 11a. Source electrode 12 is not in contact with interlayer insulating film 11 and gate insulating film 8 due to barrier metal 13 covering the entire surface of interlayer insulating film 11 .

The source electrode 12 is formed by, for example, reaction between nickel atoms in a nickel (Ni) film deposited on the semiconductor substrate 10 inside the first source contact hole 11a and silicon (Si) atoms in the semiconductor substrate 10. It may be a nickel silicide (NiSi) film made of The barrier metal 13 prevents, for example, diffusion of metal atoms from a source pad (first pad) 14 to be described later to the interlayer insulating film 11 side, and prevents mutual reaction between regions facing each other with the barrier metal 13 interposed therebetween. It has the function to The barrier metal 13 may be, for example, a titanium nitride (TiN) film.

Conductive layer 22 extends from inside second trench 21 on the surfaces of source electrode 12 and barrier metal 13 . Source electrode 12 and barrier metal 13 are covered with conductive layer 22 . A source pad 14 is provided on the surface of the conductive layer 22 . The source pad 14 is made of aluminum (Al), for example. Source pad 14 and conductive layer 22 may extend to gate pad region 44 of tether region 43 . Reference numeral 14a in FIG. 3 denotes the end of the source pad 14. As shown in FIG.

Source pad 14 and conductive layer 22 terminate at a location remote from gate pad 35 . A drain electrode 15 is provided on the entire back surface of the semiconductor substrate 10 (the back surface of the n ⁺ -type starting substrate that becomes the n ⁺ -type drain region 1). The drain electrode 15 is in ohmic contact with the back surface of the semiconductor substrate 10 . The drain electrode 15 is, for example, a silicide formed by reacting nickel atoms and titanium atoms in a nickel film and a titanium (Ti) film sequentially deposited on the back surface of the semiconductor substrate 10 with silicon atoms in the semiconductor substrate 10 . It may be a membrane.

In the active region 41, the p ⁺ -type region (bottom region) 16 is selectively formed inside the n-type current diffusion region 3 at positions facing the first and second trenches 7 and 21 in the depth direction Z, respectively. is provided. The first and second trenches 7 and 21 may terminate inside each p ⁺ -type region 16 . The p ⁺ -type region 16 is provided apart from the p-type base region 4 . The p ⁺ -type region 16 has the function of suppressing leakage current when the SiC-MOSFET is turned off and of relaxing the electric field applied to the bottom surfaces of the first and second trenches 7 and 21 .

N-type current diffusion region 3 , p-type base region 4 and p ⁺ -type contact region 6 extend from active region 41 to connecting region 43 . In the connecting region 43 , p ⁺ -type regions 31 and 32 are provided inside the n-type current diffusion region 3 . P ⁺ -type region 32 is in contact with p-type base region 4 . The p ⁺ -type region 31 is in contact with the p ⁺ -type region 32 and is provided at a position deeper than the p ⁺ -type region 32 from the front surface of the semiconductor substrate 10 . The p ⁺ -type regions 31 are formed at the same time as the p ⁺ -type regions 16 of the active region 41, for example.

p ^- type contact region 6, p-type base region 4 and p ⁺ -type regions 32 and 31 ⁱⁿ these connecting regions 43; n ^- type current diffusion region 3; A parasitic PiN diode 30 is formed at the pn junction between the regions 1 and . The PiN diode 30 has the same planar shape as the junction region 43 and has a surface area that is the same as or slightly smaller than that of the junction region 43 . A gate runner 34 is provided on the front surface of the semiconductor substrate 10 in the connecting region 43 (including the gate pad region 44) with the gate insulating film 8 and the field oxide film 33 interposed therebetween.

As described above, the gate runner 34 has the protrusion 34a that protrudes into the protrusion 43a of the connecting region 43, and has the recess 34b that is partially recessed inward from the protrusion 34a. A second source contact hole 11b exposing the p ⁺ -type contact region 6 is provided in the interlayer insulating film 11 in the concave portion 34b of the convex portion 34a of the gate runner 34 . A second trench 21a (21) is provided in the second source contact hole 11b to reach the n-type current diffusion region 3 through the p ⁺ -type contact region 6 and the p-type base region 4 in the depth direction Z. ing.

That is, by providing the second trench 21a in the concave portion 34b of the convex portion 34a of the gate runner 34, the second trench 21a is located in the second direction Y at a position closer to the convex portion 43a of the connecting region 43 than the first trench 7. A second trench 21 a can be provided facing the protrusion 43 a of the connecting region 43 . The conductive layer 22 is also buried in the second trench 21a, and a trench sidewall SBD 20 is formed on the sidewall of the second trench 21a by a Schottky junction between the conductive layer 22 and the n-type current diffusion region 3. As shown in FIG. A source electrode 12 is in ohmic contact with the p ⁺ -type contact region 6 exposed in the second source contact hole 11b.

Since the first trench 7 does not exist between the connecting region 43 and the second trench 21a, the trench sidewall SBD20 can be arranged at a position closer to the PiN diode 30 than in the conventional structure (see FIGS. 14 to 19). Specifically, the length C103 (see FIG. 19) of the p ⁺ -type region 231 of the bridging region 243 of the conventional structure is arranged closest to the convex portion 43a of the bridging region 43 in the second direction Y in the present embodiment. It corresponds to a length C3 from the end of the p ⁺ -type region 16 facing the bottom surface of the first trench 7a (7) in the depth direction Z, farther from the connecting region 43 to the edge termination region .

The p ⁺ -type regions 31 and 32 of the bridging region 43 of the present embodiment are separated from the p ⁺ -type region 16 facing the bottom surface of the second trench 21a in the depth direction Z, and are located in the edge termination region from the second trench 21a. 42 side. From the length C3 from the end of the p ⁺ -type region 16 facing the bottom surface of the first trench 7a in the depth direction Z, farther from the connecting region 43 to the edge termination region 42, the p ⁺ -type region of the connecting region 43 The trench sidewall SBD 20 can be arranged at a position closer to the PiN diode 30 than in the conventional structure by the length C1 obtained by subtracting the length C2 of 31 and 32 .

Further, a contact (electrical contact portion) between the source electrode 12 and the p ⁺ -type contact region 6 can be formed in the second source contact hole 11b provided in the concave portion 34b of the convex portion 34a of the gate runner 34. FIG. That is, the p ⁺ -type contact region 6 of the connecting region 43 and the source electrode 12 can be brought into direct contact with each other. As a result, the contact resistance of the p ⁺ -type contact region 6 can be reduced in the vicinity of the boundary between the concave portion 41a of the active region 41 and the convex portion 43a of the connecting region 43, thereby preventing the deterioration of the avalanche resistance.

Gate runner 34 is covered with interlayer insulating film 11 . The interlayer insulating film 11 in the connecting region 43 is covered with the barrier metal 13 . A gate pad 35 (see FIGS. 3 and 4) is provided on the barrier metal 13 in the gate pad region 44 of the connecting region 43 . Gate pad 35 may have the same laminate structure as source pad 14 . Gate pad 35 faces gate runner 34 in depth direction Z with barrier metal 13 and interlayer insulating film 11 interposed therebetween. Gate pad 35 is electrically connected to gate runner 34 .

As described above, according to the first embodiment, the gate runner is made of polysilicon, is arranged in the connecting region between the active region and the edge termination region, and surrounds the active region. In addition, the gate runner has a protrusion formed by protruding inward in a substantially rectangular shape so as to face the gate pad in the depth direction. The convex portion of the gate runner is provided with a concave portion which is recessed inward by removing a part of the convex portion.

By disposing the second trench forming the trench sidewall SBD in the concave portion of the convex portion of the gate runner, the convex portion of the bridging region is positioned closer to the convex portion of the bridging region than the first trench in the second direction. , the trench sidewalls SBD can be positioned opposite to the . As a result, the trench sidewall SBD can be arranged at a position closer to the PiN diode than in the conventional structure, so that the bipolar current is less likely to flow and the PiN diode is less likely to be turned on when a large current flows. Therefore, parasitic PiN diode action can be suppressed.

Moreover, according to the first embodiment, the p ⁺ -type contact region of the connecting region is exposed to the second source contact hole together with the conductive layer in the second trench arranged in the concave portion of the convex portion of the gate runner. Therefore, the p ⁺ -type contact region of the connecting region and the source electrode can be brought into direct contact with each other. As a result, the contact resistance of the p ⁺ -type contact region can be reduced in the vicinity of the boundary between the concave portion of the active region and the convex portion of the bridging region, so that the deterioration of the avalanche resistance can be prevented.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device according to the second embodiment is described. FIG. 6 is a plan view showing the layout of the silicon carbide semiconductor device according to the second embodiment, viewed from the front surface side of the semiconductor substrate. FIG. 6 shows an enlarged view of the area surrounded by the rectangular frame A in FIGS. The layout of the active region 41, the edge termination region 42, the connection region 43 and the gate pad region 44, and the layout of the formation regions of the trench sidewall SBD 20 and the PiN diode 30 are the same as those of the first embodiment (see FIGS. 1 and 2). . The planar shape of the protrusion 34a of the gate runner 34 is the same as that of the first embodiment (see FIG. 4). FIG. 7 is a cross-sectional view showing a cross-sectional structure taken along line D1-D2 in FIG.

The silicon carbide semiconductor device 50 according to the second embodiment differs from the silicon carbide semiconductor device 40 according to the first embodiment in the width of the second source contact hole 11b' formed in the recess 34b of the projection 34a of the gate runner 34. The difference is that w2 is made wider than the width w1 of the first source contact hole 11a of the active region 41 to widen the surface area of the contact between the p ⁺ -type contact region 6 of the connecting region 43 and the source electrode 12. FIG. By increasing the surface area of the p ⁺ -type contact region 6 of the connecting region 43 and the source electrode 12, the contact resistance of the p ⁺ -type contact region 6 near the boundary between the recess 41a of the active region 41 and the projection 43a of the connecting region 43 is can be further reduced.

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Further, according to the second embodiment, by widening the width of the second source contact hole formed in the concave portion of the convex portion of the gate runner, it is possible to further prevent the deterioration of the avalanche resistance.

(Embodiment 3)
Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. FIG. 8 is a plan view showing the layout of the silicon carbide semiconductor device according to the third embodiment, viewed from the front surface side of the semiconductor substrate. FIG. 8 shows an enlarged area surrounded by a rectangular frame A in FIGS. The layout of the active region 41, the edge termination region 42, the connection region 43 and the gate pad region 44, and the layout of the formation regions of the trench sidewall SBD 20 and the PiN diode 30 are the same as those of the first embodiment (see FIGS. 1 and 2). . The planar shape of the protrusion 34a of the gate runner 34 is the same as that of the first embodiment (see FIG. 4). FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line E1-E2 in FIG.

Silicon carbide semiconductor device 60 according to the third embodiment differs from silicon carbide semiconductor device 40 according to the first embodiment in that a trench is formed in second source contact hole 11b formed in recess 34b of protrusion 34a of gate runner 34. The difference is that a plate-like SBD (hereinafter referred to as a plane SBD) 20 ′ is provided on the front surface of the semiconductor substrate 10 instead of the side wall SBD 20 . The plane SBD 20 ′ is provided along the front surface of the semiconductor substrate 10 at the n-type region 23 exposed to the front surface of the semiconductor substrate 10 at the second source contact hole 11 b and at the second source contact hole 11 b. It is formed by Schottky junction with the conductive layer 22 .

Specifically, the n-type region 23 and the p ⁺ -type contact region 6 are exposed in the second source contact hole 11b formed in the concave portion 34b of the convex portion 34a of the gate runner 34 . N-type region 23 penetrates p-type silicon carbide layer 62 in depth direction Z from the front surface of semiconductor substrate 10 to reach n-type current diffusion region 3 in second source contact hole 11b. Conductive layer 22 extends from active region 41 into second source contact hole 11 b and is provided along the front surface of semiconductor substrate 10 . A source electrode 12 is in ohmic contact with the p ⁺ -type contact region 6 exposed in the second source contact hole 11b, as in the first embodiment.

A p ⁺ -type region 24 is selectively provided inside the n-type current diffusion region 3 directly under the plane SBD 20′ (n ⁺ -type drain region 1 side). The p ⁺ -type region 24 is spaced apart from the n-type region 23 , the p ⁺ -type region 16 of the active region 41 , the p-type base region 4 of the junction region 43 , and the p ⁺ -type regions 31 and 32 of the junction region 43 . there is The p ⁺ -type regions 24 may be formed simultaneously with the p ⁺ -type regions 16 of the active region 41 . The p ⁺ -type regions 24 are separated from each other by the p ⁺ -type regions 16 of the active region 41 and the p ^{+ -type regions 31 and 32 of the connecting region 43 at intervals equal to or narrower than the intervals between the adjacent p +} -type regions 16 of the active region ⁴¹ . and away.

In addition, at least a part of the p ⁺ -type region 24 may be located directly under the plane SBD 20 ′, and may be arranged in the active region 41 or may be arranged in the connecting region 43 . It may be arranged from the region 41 to the connecting region 43 . By providing the p ⁺ -type region 24 inside the n-type current diffusion region 3 immediately below the plane SBD 20 ′ in this way, the electric field concentration of the junction region 43 at the end of the p-type base region 4 can be alleviated. . Thereby, a predetermined breakdown voltage can be maintained in the vicinity of the boundary between the active region 41 and the connecting region 43 .

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained even when the plane SBD is provided instead of the trench sidewall SBD.

(Embodiment 4)
Next, the structure of the silicon carbide semiconductor device according to the fourth embodiment will be described. FIG. 10 is a plan view showing the layout of the silicon carbide semiconductor device according to the fourth embodiment, viewed from the front surface side of the semiconductor substrate. FIG. 10 shows an enlarged view of the area surrounded by the rectangular frame A in FIGS. The layout of the active region 41, the edge termination region 42, the connection region 43 and the gate pad region 44, and the layout of the formation regions of the trench sidewall SBD 20 and the PiN diode 30 are the same as those of the first embodiment (see FIGS. 1 and 2). . The planar shape of the protrusion 34a of the gate runner 34 is the same as that of the first embodiment (see FIG. 4). FIG. 11 is a cross-sectional view showing the cross-sectional structure taken along line F1-F2 in FIG.

The silicon carbide semiconductor device 70 according to the fourth embodiment applies the second embodiment to the silicon carbide semiconductor device 60 according to the third embodiment, and the second source formed in the concave portion 34b of the convex portion 34a of the gate runner 34 is formed. The width w2 of the contact hole 11b' is made wider than the width w1 of the first source contact hole 11a of the active region 41. FIG. That is, a plane SBD20' is provided in the second source contact hole 11b'. In addition, the contact resistance of the p ⁺ -type contact region 6 is further reduced in the vicinity of the boundary between the recess 41 a of the active region 41 and the projection 43 a of the connecting region 43 .

As described above, according to the fourth embodiment, the same effects as those of the second embodiment can be obtained even when the planar SBD is provided instead of the trench sidewall SBD.

(Embodiment 5)
Next, the structure of the silicon carbide semiconductor device according to the fifth embodiment is described. FIG. 12 is a plan view showing the layout of the silicon carbide semiconductor device according to the fifth embodiment, viewed from the front surface side of the semiconductor substrate. FIG. 12 shows an enlarged view of the area surrounded by the rectangular frame A in FIGS. The layout of the active region 41, the edge termination region 42, the connection region 43 and the gate pad region 44, and the layout of the formation regions of the trench sidewall SBD 20 and the PiN diode 30 are the same as those of the first embodiment (see FIGS. 1 and 2). . The cross-sectional structure along the cutting line G1-G2 in FIG. 12 is the same as that of the first embodiment (see FIG. 5). 13 is a plan view showing an enlarged connection region of FIG. 12. FIG.

Silicon carbide semiconductor device 80 according to the fifth embodiment differs from silicon carbide semiconductor device 40 according to the first embodiment in the following two points. The first difference is that the convex portion 34a' of the gate runner 34 is not provided with a concave portion. That is, the convex portion 34a' of the gate runner 34 has a substantially rectangular planar shape as in the conventional structure. The second difference is that the ends of the first trenches 7 adjacent to each other across the corners 34c of the protrusions 34a' of the gate runners 34 are connected in the second direction Y to form a substantially U-shaped flat surface. The point is that a trench having a shape (hereinafter referred to as a connecting trench) 7b is arranged. The corner portion 34c of the protrusion 34a' of the gate runner 34 is one side parallel to the first direction X and one side parallel to the second direction Y among the three sides of the periphery of the protrusion 34a' of the gate runner 34. and are vertices shared by .

The first trenches 7 connected by the connecting trenches 7b in this way surround the corners 34c of the protrusions 34a' of the gate runners 34, and extend only in the corners 34c of the protrusions 34a' of the gate runners 34 in the second direction Y. opposite. The second trench 21b (21) located closest to the protrusion 43a of the connecting region 43 in the second direction Y faces the protrusion 43a of the connecting region 43 in the second direction Y with the connecting trench 7b interposed therebetween. The second trench 21b is formed in the connection region 43 at a portion other than the corner 34c of the projection 34a' of the gate runner 34 without interposing the first trench 7 between the projection 43a of the connection region 43 in the second direction Y. is opposed to the convex portion 43a. A gate electrode 9 is provided inside the connecting trench 7 b with a gate insulating film 8 interposed therebetween, similarly to the first trench 7 .

As described above, according to the fifth embodiment, by connecting the ends of the first trenches 7 adjacent in the second direction near the corners of the protrusion of the gate runner, the protrusion of the gate runner is formed. Effects similar to those of Embodiments 1 to 4 can be obtained without providing a recess in the portion.

As described above, the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the scope of the present invention. For example, in Embodiments 1 to 4 described above, the case where the concave portion is provided on one of the three outer peripheral sides of the convex portion of the gate runner parallel to the first direction is described as an example, but the present invention is not limited to this. , the recesses may be provided on the sides parallel to the first and second trenches, among the three sides of the periphery of the protrusion of the gate runner. For this reason, when the first and second trenches are arranged in stripes extending in the second direction, recesses are provided on two sides parallel to the second direction among the three sides of the periphery of the protrusion of the gate runner. , an SBD may be placed in each of the two recesses.

As described above, the present embodiment is useful for semiconductor devices having a semiconductor substrate made of silicon carbide.

Reference Signs List 1 n ⁺ type drain region 2 n ⁻ type drift region 3 n type current diffusion region 4 p type base region 5 n ⁺ type source region 6 p ⁺ type contact region 7, 7a MSOFET gate trench (first trench)
7b connecting trench 8 gate insulating film 9 gate electrode 10 semiconductor substrate 11 interlayer insulating film 11a, 11b, 11b' source contact hole 12 source electrode 13 barrier metal 14 source pad 15 drain electrode 16, 31, 32 p ⁺ -type region 20 trench side wall SBD
20' planar SBD
21, 21a, 21b trenches on trench side walls SBD (second trenches)
22 conductive layer 23 n-type region 30 PiN diode 33 field oxide film 34 gate runner 34a, 34a' protrusion of gate runner 34b recess of protrusion of gate runner 34c corner of protrusion of gate runner 35 gate pad 40, 50, 60, 70, 80 silicon carbide semiconductor device 41 active region 41a concave portion of active region 42 edge termination region 43 connecting region 43a convex portion of connecting region 44 gate pad region 52 position near convex portion of connecting region 61 n ⁻ -type silicon carbide layer 62 p-type silicon carbide layer X direction parallel to front surface of semiconductor substrate (first direction)
Y A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction)
Z Depth direction w1, w2 Width of source contact hole

Claims (14)

A semiconductor device comprising a semiconductor substrate made of silicon carbide,
a drift region of a first conductivity type provided in the semiconductor substrate;
a base region of a second conductivity type provided between the front surface of the semiconductor substrate and the drift region;
a first conductivity type source region provided on the front surface side of the semiconductor substrate;
a plurality of trenches extending from the front surface of the semiconductor substrate through the base region to the inside of the semiconductor substrate;
a gate runner provided on the front surface of the semiconductor substrate;
a first pad provided on the front surface of the semiconductor substrate and electrically connected to the gate runner;
a second pad provided on the front surface of the semiconductor substrate and not electrically connected to the gate runner;
with
The plurality of trenches are
a first trench adjacent to the source region and provided therein with a first conductive portion extending in a first direction to a runner connection region where the first conductive portion is connected to the gate runner;
A contact region of a second conductivity type is provided on a front surface side of the semiconductor substrate opposite to the first trench when viewed from the runner connection region in the first direction, and the contact region is exposed. A semiconductor device comprising a contact hole. The plurality of trenches are
a second conductive portion provided therein and electrically connected to the second pad and extending in the first direction from a side opposite to the first trench toward the runner connection region;
2. The semiconductor device according to claim 1, wherein said second conductive portion is electrically connected to said second pad through said contact hole. 3. The semiconductor device according to claim 2, further comprising a bottom region of the second conductivity type facing the bottom of said second trench in the depth direction. 4. The semiconductor device according to claim 2, wherein said contact region forms a diode by a pn junction with said drift region at a position deeper than said second trench on the back side of said semiconductor substrate. the contact region has a higher impurity concentration than the base region;
5. The semiconductor device according to claim 1, wherein said source region has a higher impurity concentration than said drift region. on the semiconductor substrate,
an active region provided with the source region;
an edge termination region including one of a guard ring, field plate, and resurf;
a bridging region between the active region and the edge termination region;
6. The semiconductor device according to claim 1, wherein said contact hole exposes said contact region in said connecting region. A semiconductor device comprising a semiconductor substrate made of silicon carbide,
a drift region of a first conductivity type provided in the semiconductor substrate;
a base region of a second conductivity type provided between the front surface of the semiconductor substrate and the drift region;
a first conductivity type source region provided on the front surface side of the semiconductor substrate;
a plurality of trenches extending from the front surface of the semiconductor substrate through the base region to the inside of the semiconductor substrate;
a gate runner provided on the front surface of the semiconductor substrate;
a first pad provided on the front surface of the semiconductor substrate and electrically connected to the gate runner;
a second pad provided on the front surface of the semiconductor substrate and not electrically connected to the gate runner;
with
The plurality of trenches are
a first trench adjacent to the source region, provided with a first conductive portion therein, and extending in a first direction to a runner connection region where the first conductive portion is connected to the gate runner;
a second trench provided therein with a second conductive portion electrically connected to the second pad and extending in the first direction from a side opposite to the first trench toward the runner connection region; A semiconductor device comprising: The plurality of trenches are
8. The semiconductor device according to any one of claims 2, 3, 4, and 7, further comprising a third trench facing the first trench and the second trench in a second direction orthogonal to the first direction in plan view. 10. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 8, wherein the third trench is provided therein with a third conductive portion electrically connected to the second pad. 9. The semiconductor device according to claim 8, wherein the third trench is provided therein with a third conductive portion electrically connected to the first pad. 11. The semiconductor device according to claim 8, wherein the third trench faces the end of the runner connection region in the second direction in plan view. The plurality of trenches are
2. A fourth trench disposed between the two first trenches in a plan view and provided therein with a fourth conductive portion electrically connected to the second pad. 12. The semiconductor device according to any one of 11. the second pad is a source pad;
3. The runner connection region is a region in which the gate runner extends in a second direction orthogonal to the first direction, including a portion where the first conductive portion is connected to the gate runner. 8. The semiconductor device according to any one of 1 to 7. the second pad is a source pad;
12. The runner connection region is a region where the gate runner extends in the second direction and includes a portion where the first conductive portion is connected to the gate runner. 2. The semiconductor device according to item 1.

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