JP2023114226A - Display device - Google Patents

Abstract

To provide a display device capable of achieving downsizing by reducing an area occupied by a contact part.SOLUTION: A display device in an embodiment includes a plurality of signal lines, and a signal line switch circuit including a plurality of transistors arranged in a first direction and connected to the plurality of signal lines. A light-blocking layer of the transistor has a first extension part LSE1 extending in a second direction intersecting with the first direction. A gate electrode includes a second extension part GEE1 extending in the second direction and disposed so as to be displaced in the first direction relative to the first extension part. A part of the second extension part is located so as to overlap with a part of the first extension part. A contact part includes a single contact hole CH6 provided so as to overlap with the first extension part and the second extension part, and a wiring layer SLC1 formed in the contact hole and connected to a part of the first extension part and a part of the second extension part.SELECTED DRAWING: Figure 6

Description

Embodiments of the present invention relate to display devices.

A display device using a light shielding layer as a back gate has been developed.
In such a display device, a plurality of signal line switch circuits are provided side by side on a substrate, and the plurality of wirings of the signal line switch circuits are arranged substantially parallel to each other. A contact portion between the back gate and the gate electrode extending from the transistor is arranged to overlap a plurality of wirings. Since the contact portion is connected through the signal wiring layer, it is usually necessary to use two contact holes.

JP 2016-134388 A Japanese Patent Application Laid-Open No. 2002-221738

An object of the embodiments of the present invention is to reduce the area occupied by the contact portion and to provide a display device that can be miniaturized.

A display device according to an embodiment electrically connects a plurality of signal lines, a gate electrode provided to overlap the light shielding layer with a light shielding layer and an insulating layer interposed therebetween, and the light shielding layer and the gate electrode. a signal line switch circuit having contact portions, including a plurality of transistors arranged side by side in a first direction, and connected to the plurality of signal lines. The light shielding layer has a first extending portion extending in a second direction intersecting the first direction, and the gate electrode extends in the second direction and extends in the first direction with respect to the first extending portion. It has a second extension portion that is displaced in one direction, and a portion of the second extension portion is positioned so as to overlap a portion of the first extension portion. The contact portion includes a single contact hole provided to overlap the first extending portion and the second extending portion, and a portion of the first extending portion and the contact hole formed in the contact hole. and a wiring layer connected to a portion of the second extension.

1 is a circuit diagram of a display device according to a first embodiment; FIG. FIG. 2 is a diagram schematically showing an example of pixels provided in the display device; FIG. 3 is a cross-sectional view of the display device in the pixel portion; 4 is a plan view schematically showing a signal line switch circuit of the display device; FIG. 5 is a cross-sectional view of the transistor portion along line AA in FIG. 4; FIG. FIG. 6 is a plan view showing an enlarged extension of a gate electrode and an extension of a light shielding layer of the transistor; 7 is a cross-sectional view of the extension along line BB of FIG. 6; FIG. 8 is a cross-sectional view of the extension along line DD of FIG. 6; FIG. FIG. 9 is an enlarged plan view showing an extended portion of a gate electrode of a transistor and an extended portion of a light shielding layer in a display device according to a second embodiment; 10 is a cross-sectional view of the extension along line EE of FIG. 9; FIG. FIG. 11 is an enlarged plan view showing an extended portion of a gate electrode of a transistor and an extended portion of a light shielding layer in a display device according to a third embodiment; 12 is a cross-sectional view of the extension along line FF of FIG. 11; FIG. FIG. 13 is an enlarged plan view showing an extended portion of a gate electrode of a transistor and an extended portion of a light shielding layer in a display device according to a fourth embodiment; 14 is a cross-sectional view of the extension along line GG of FIG. 13; FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
It should be noted that the disclosure is merely an example, and appropriate modifications that can be easily conceived by those skilled in the art while keeping the gist of the invention are naturally included in the scope of the present invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example, and the interpretation of the present invention is not intended. It is not limited. In addition, in this specification and each figure, the same reference numerals may be given to the same elements as those described above with respect to the existing figures, and detailed description thereof may be omitted as appropriate.

(First embodiment)
Hereinafter, the display device according to the first embodiment will be described in detail with reference to the drawings.
In this embodiment, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but they may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow in the third direction Z is defined as upward or upward, and the direction opposite to the direction toward the tip of the arrow in the third direction Z is defined as downward.

It is assumed that there is an observation position where the display device is observed on the tip side of the arrow in the third direction Z, and the XY plane defined by the first direction X and the second direction Y is viewed from this observation position. Planar view. Viewing a cross section of the display device on the XZ plane defined by the first direction X and the third direction Z or the YZ plane defined by the second direction Y and the third direction Z is referred to as a cross-sectional view.

FIG. 1 is a plan view schematically showing the display device according to the first embodiment. FIG. A liquid crystal display device is shown as an example of the display device. As illustrated, the display device DSP has a display area DA formed on a substrate (base material), which will be described later, and a non-display area (frame area) located around the display area.
A plurality of pixels PX, a plurality of scanning lines GL, and a plurality of signal lines SL are provided in the display area DA. The multiple scanning lines GL extend in the first direction X and are arranged side by side in the second direction Y at intervals. The plurality of signal lines SL extend in the second direction Y and are arranged side by side in the first direction X at intervals. Note that the scanning lines GL and signal lines SL may also be referred to as gate lines and source lines, respectively.

Each of the plurality of pixels PX includes sub-pixels SXR, SXG, and SXB that display colors of R (red), G (green), and B (blue), respectively. The sub-pixels SXR, SXG, and SXB are simply referred to as sub-pixels SX when they are not distinguished from each other. A plurality of sub-pixels SX are arranged in a matrix in the first direction X and the second direction Y, and are provided near the intersections of the scanning lines GL and the signal lines SL. In other words, each sub-pixel SX is provided in a region surrounded by two adjacent scanning lines GL and two adjacent signal lines SL.

FIG. 2 is a circuit diagram of the sub-pixel SX.
As illustrated, each sub-pixel SX includes a switching element PSW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, a storage capacitor CS, and the like. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line GL and the signal line SL. The scanning line GL is connected to the gate electrode GE of the switching element SW in each of the sub-pixels SX arranged in the first direction X. As shown in FIG. The signal line SL is connected to the source electrode SE of the switching element PSW in each of the sub-pixels SX arranged in the second direction Y. As shown in FIG. The pixel electrode PE is electrically connected to the drain electrode DE of the switching element PSW. Each pixel electrode PE faces the common electrode CE, and the electric field generated between the pixel electrode PE and the common electrode CE drives the liquid crystal layer LC. The storage capacitor CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

The source electrode SE of the switching element PSW of the sub-pixel SX is formed integrally with the signal line SL. Also, each of the plurality of signal lines SL is connected to a signal line driving circuit SLC, which will be described later, to which a video signal supplied to each sub-pixel SX is input. That is, the plurality of signal lines SL connect the plurality of sub-pixels SX and the signal line driving circuit SLC. A gate electrode GE of the switching element PSW is formed integrally with the scanning line GL. Each scanning line GL is connected to a scanning line driving circuit GLC, which will be described later, and which supplies a scanning signal to each sub-pixel SX. The common electrode CE is connected to the common wiring CML.

On the other hand, as shown in FIG. 1, the display device DSP drives a scanning line driving circuit GLC that drives the scanning lines GL, a signal line driving circuit SLC that drives the signal lines SL, a signal line switch circuit ASW, and a common electrode CE. It has a common electrode drive circuit CD and a switch circuit MUX connected to the common line CML. The signal line driving circuit SLC and the scanning line driving circuit GLC are electrically connected to the driving element (control circuit) DD. The drive element DD outputs a signal necessary for image display to the sub-pixel SX via the signal line drive circuit SLC and the scanning line drive circuit GLC.
Although details will be described later, a plurality of lead wirings WL1 and WL2 electrically connected to the signal line SL are provided between the signal line driving circuit SLC and the driving element DD.

A connection relationship between the signal line SL and the signal line switch circuit ASW will be described. In the example shown in FIG. 1, signal lines SLR, SLG, and SLB are provided as the signal lines SL connected to each of the sub-pixels SX. The signal lines SLR, SLG and SLB are connected to the signal line switch circuit ASW. The signal line SLR is a signal line connected to the sub-pixel SXR displaying red (R). The signal line SLG is a signal line connected to the sub-pixel SXG displaying green (G). The signal line SLB is a signal line connected to the sub-pixel SXB displaying blue (B).
The signal line SLR is connected to a sub-pixel column including a plurality of sub-pixels SXR arranged in the second direction Y. As shown in FIG. The signal line SLG is connected to a sub-pixel column including a plurality of sub-pixels SXG arranged in the second direction Y. As shown in FIG. The signal line SLB is connected to a sub-pixel column including a plurality of sub-pixels SXB arranged in the second direction Y. FIG.

The signal line switch circuit ASW is a control circuit that supplies image-related signals to the display area DA as a pixel circuit. The signal line switch circuit ASW has transistors STR, STG, and STB as switching elements, and selection lines SSR, SSG, and SSB. Each of the transistors STR, STG and STB is, for example, a thin film transistor. Note that the transistors STR, STG, and STB are simply referred to as a transistor ST when there is no particular need to distinguish between them. Also, the signal line switch circuit ASW may be simply referred to as a switch circuit.
The transistor STR is connected with the signal line SLR. The transistor STG is connected with the signal line SLG. The transistor STB is connected with the signal line SLB.

The driving element DD shown in FIG. 1 operates as a signal line driving circuit SLC, a scanning line driving circuit GLC, and a scanning line driving circuit GLC based on display control signals such as display data, clock signals, and display timing signals transmitted from the outside of the display device. It controls the signal line switch circuit ASW.
The transistors STR, STG, and STB of the signal line switch circuit ASW are controlled to be turned on and off by switch switching signals output from the drive element DD through the selection lines SSR, SSG, and SSB, respectively.

The drive element DD controls the signal line drive circuit SLC to time-divisionally output the red video signal, the green video signal, and the blue video signal within one horizontal period, and the signal line switch circuit ASW. control the on and off of the transistor STR, transistor STG, and transistor STB. That is, the transistors ST (STR, STG, STB) included in the signal line switch circuit ASW are driven in a time division manner. More specifically, of the transistors STR, STG, and STB, a video signal from the signal line driving circuit SLC is input to the signal line SL connected to the ON-state transistor ST through the lead lines WL1 and WL2. be done. Further, the driving element DD controls the scanning line driving circuit GLC so as to maintain the ON state of the switching element PSW of the sub-pixel SX to which the video signal is written while the video signal of each color is being output.

Note that the signal line switch circuit ASW may be simply called an RGB switch, a time-division switch, an analog switch, or a selector. In this embodiment, one signal line switch circuit is provided for the three signal lines connected to the red, green, and blue subpixels. A configuration in which a signal line switch circuit is provided in the . Alternatively, one signal line switch circuit may be provided for six signal lines connected to two pixels, that is, six sub-pixels. In this case, the signal line driving circuit outputs the video signal six times in one horizontal period. The number of time divisions can be arbitrarily set depending on the state of video signal writing to each sub-pixel and the processing capability of the signal line driving circuit.

During the display period including the horizontal period, a constant DC voltage is supplied from the common electrode drive circuit CD to the switch circuit MUX through the wiring VDCL. The switch circuit MUX supplies the constant DC voltage to all common electrodes CE via the common wiring CML. As a result, an electric field for driving the liquid crystal layer LC is generated between the pixel electrode PE and the common electrode CE as described above.

Next, the cross-sectional structure of the display device DSP in the pixel portion will be described with reference to FIG.
As shown, the display device DSP includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1 with a gap therebetween, and a liquid crystal layer LC sealed between these substrates. . The first substrate SUB1 includes a substrate BA1, an insulating layer UC, scanning lines GL, signal lines SL, switching elements PSW, an insulating layer PLN1, an insulating layer PLN2, a common electrode CE, an insulating layer PAS, a pixel electrode PE1, and an alignment film AL1. I have. The switching element PSW has a semiconductor layer SC, an insulating layer GI, a gate electrode GE integrally formed with the scanning line GL, an insulating layer ILI, a source electrode SL and a drain electrode DE integrally formed with the signal line SL. and are stacked in this order.

The base material BA1 is a light-transmitting substrate such as a glass substrate or a flexible resin substrate. The insulating layer UC is located on the substrate BA1. The light shielding layer LS is formed between the base material BA1 and the insulating layer UC. The light shielding layer LS overlaps the scanning line GL (gate electrode) with the semiconductor layer SC interposed therebetween. The insulating layer GI is located above the insulating layer UC. The insulating layer ILI is located above the insulating layer GI.

The insulating layers UC, GI, ILI, and PAS are inorganic insulating layers made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating layers UC, GI, and ILI may have a single-layer structure using the inorganic insulating material, or may have a multi-layer structure in which a plurality of the inorganic insulating materials are laminated. On the other hand, the insulating layers PLN1 and PLN2 are organic insulating layers formed of an organic insulating material such as acrylic resin, for example. Also, the insulating layer PLN2 may be an inorganic insulating layer.

The semiconductor layer SC is provided on the insulating layer UC. The semiconductor layer SC is made of, for example, polycrystalline silicon. The semiconductor layer SC may be made of amorphous silicon or an oxide semiconductor.

The scanning line GL is provided on the semiconductor layer SC and the insulating layer GI. The scanning lines GL are made of metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), and chromium (Cr), and these metal materials. It is formed of a combined alloy or the like, and may have a single-layer structure or a multi-layer structure. In one example, the scanning line GL is made of molybdenum-tungsten alloy. In this embodiment, the wiring layer in the same layer as the scanning lines GL is called a first wiring layer Wg. Also, the first wiring layer Wg may be referred to as a scanning line layer, a gate layer, or a GL layer. Alternatively, the first wiring layer Wg may be called a first metal layer.

The signal line SL is located on the insulating layer ILI. The signal line SL is connected to the semiconductor layer SC through contact holes provided in the insulating layers GI and ILI. The signal line SL is made of metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), chromium (Cr), or these metal materials. It is formed of a combined alloy or the like, and may have a single-layer structure or a multi-layer structure. In one example, the signal line SL is a laminate in which a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing titanium (Ti) are laminated in this order. In this embodiment, the wiring layer in the same layer as the signal line SL is called a second wiring layer Ws. Also, the second wiring layer Ws may be called a signal line layer, a Sig layer, or an SL layer. Alternatively, the second wiring layer Ws may be called a second metal layer.

The drain electrode DE is located on the insulating layer ILI. The drain electrode DE is connected to the semiconductor layer SC through contact holes provided in the insulating layers GI and ILI. The drain electrode DE is formed of the second wiring layer Ws.
The insulating layer PLN1 covers the signal line SL, the drain electrode DE, and the insulating layer ILI. The extraction electrode TE is provided on the insulating layer PLN1 and connected to the drain electrode DE through a contact hole provided in the insulating layer PLN1.

The extraction electrode TE is made of the metal material described above, an alloy obtained by combining the metal materials described above, or the like, and may have a single-layer structure or a multi-layer structure. In one example, the extraction electrode TE is a laminate in which a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing titanium (Ti) are laminated in this order, or It is a laminate in which a first layer containing molybdenum (Mo), a second layer containing aluminum (Al), and a third layer containing molybdenum (Mo) are laminated in this order. The extraction electrode TE is formed in the same wiring layer as the common wiring CML. In this embodiment, the wiring layer in the same layer as the common wiring CML is called a third wiring layer Wt. Also, the third wiring layer Wt may be called a third metal layer.

An insulating layer PLN2 is provided to cover the insulating layer PLN1 and the extraction electrode TE.
A common electrode CE and a relay electrode RE are provided on the insulating layer PLN2, the relay electrode RE is positioned in the opening of the common electrode CE, and the common electrode CE and the relay electrode RE are separated from each other.

The relay electrode RE is located on the insulating layer PLN2. The relay electrode RE is in contact with the lead-out electrode TE through a contact hole formed in the insulating layer PLN1 at a position overlapping with the lead-out electrode TE. The relay electrode RE is a transparent electrode made of the same transparent conductive material as the common electrode CE, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The insulating layer PAS covers the common electrode CE and the relay electrode RE.
The pixel electrode PE is located on the insulating layer PAS. Also, the pixel electrode PE is covered with an alignment film AL1. That is, the pixel electrode PE is provided between the insulating layer PAS and the alignment film AL1. The pixel electrode PE, like the common electrode CE, is a transparent electrode made of the transparent conductive material described above.
The pixel electrode PE is connected to the relay electrode RE through a contact hole formed in the insulating layer PAS, and overlaps the common electrode CE with the insulating layer PAS interposed therebetween.
The alignment film AL1 also covers the insulating layer PAS.

The second substrate SUB2 includes a base material BA2, a light shielding layer BM, color filters CF, an overcoat layer OC, and an alignment film AL2.
The substrate BA2 is, like the substrate BA1, a substrate having optical transparency such as a glass substrate or a resin substrate. The light shielding layer BM and the color filters CF are located on the side of the base material BA2 facing the first substrate SUB1.
The color filters CF include red color filters CFR, green color filters CFG, and blue color filters CFB.
An overcoat layer OC covers the color filters CF. The overcoat layer OC is made of transparent resin.
The alignment film AL2 covers the overcoat layer OC. The alignment film AL1 and the alignment film AL2 are made of, for example, a material exhibiting horizontal alignment.

The above-described first substrate SUB1 and second substrate SUB2 are arranged such that the alignment film AL1 and the alignment film AL2 face each other. The first substrate SUB1 and the second substrate SUB2 are bonded together with a seal while forming a predetermined cell gap. The liquid crystal layer LC is held between the alignment films AL1 and AL2. The liquid crystal layer LC is composed of a positive (positive dielectric anisotropy) liquid crystal material or a negative (negative dielectric anisotropy) liquid crystal material.

Polarizing plate PL1 is adhered to base material BA1. The polarizing plate PL2 is adhered to the base material BA2. In addition to the polarizing plates PL1 and PL2, a retardation plate, a scattering layer, an antireflection layer, and the like may be provided.
The display device DSP includes an illumination device (not shown) arranged below the first substrate SUB1.

Next, the configuration of the signal line switch circuit ASW will be described in detail. 4 is a more detailed plan view of the signal line switch circuit ASW, and FIG. 5 is a cross-sectional view of the transistor portion along line AA in FIG. FIG. 4 shows an example of the first stage of the two stages of transistors of the signal line switch circuit ASW.
As shown in FIG. 4, the signal line switch circuit ASW has selection lines SSR1, SSG1, SSB1, SSR2, SSG2, and SSB2 as selection lines (first wirings) SSR, SSG, and SSB. Note that the select lines SSR1, SSG1, SSB1, SSR2, SSG2, and SSB2 may be simply referred to as select lines SS when there is no particular need to distinguish them. The six selection lines SS each extend along the first direction X and are arranged side by side in the second direction Y at intervals. In one example, the selection lines SSR1, SSG1, SSB1, SSR2, SSG2, and SSB2 are arranged in the second direction Y in that order. These select lines SS are connected to the drive elements DD. In FIG. 4, the selection lines are hatched.
The signal line switch circuit ASW has connection wirings CNW1 and CNW2. The connection wirings CNW1 and CNW2 each extend in the first direction X and are spaced apart in the second direction Y with respect to the selection line SSB2.

The signal line switch circuit ASW shown in FIG. 4 has transistors STR11, STG11, STB11, STR12, STG12, STB12, STR21, STG21, STB21, STR22, STG22, and STB22 as the transistors STR, STG, and STB. . When there is no need to distinguish between the above transistors, they are referred to as transistors ST. The plurality of transistors ST are arranged in the first direction X at intervals in the first direction X, and are located at intervals in the second direction Y with respect to the connection wirings CNW1, SNW2, and the selection line SSB2. .

In this embodiment, two transistors are integrally formed using a common semiconductor layer and a common drain electrode.
In one example, transistors STR11 and STB11, transistors STG21 and STR21, transistors STB21 and STG11, transistors STG12 and STB22, transistors STR22 and STG22, and transistors STR12 and STB12 are integrally formed.
For example, the transistors STR11 and STB11 are arranged between a rectangular semiconductor layer SC, a pair of source electrodes SE1 and SE2 provided to overlap the semiconductor layer SC with an insulating layer interposed therebetween, and a pair of source electrodes SE1 and SE2. and a pair of gate electrodes (a first gate electrode, a second and gate electrodes GE1 and GE2. The transistors STR11 and STB11 form a so-called dual-gate transistor. The source electrodes SE1 and SE2, the drain electrode DE, and the pair of gate electrodes GE1 and GE2 each extend in the second direction Y and are arranged in the first direction X at intervals.
Each of the source electrodes SE1 and SE2 is connected to the semiconductor layer SC via a plurality of contact holes CH1 arranged in the second direction Y at intervals. The drain electrode DE is connected to the semiconductor layer SC via a plurality of contact holes CH2 arranged in the second direction Y at intervals.

The transistors STR11 and STB11 further have two light shielding layers (first light shielding layer and second light shielding layer) LS1 and LS2 which are conductive and function as back gates. The light shielding layers LS1 and LS2 are provided so as to overlap with the gate electrodes GE1 and GE2 via the semiconductor layer SC and the insulating layer, respectively. The light shielding layers LS1 and LS2 each have a width substantially equal to that of the gate electrode GE, and extend in the second direction Y from one end to the other end of the gate electrode GE. In addition, in FIG. 4, the light shielding layers LS1 and LS2 are hatched.

The source electrode SE1 is formed integrally with the signal line SLR11. The signal line SLR11 extends in the second direction Y from the source electrode SE1 in the direction opposite to the selection line SSB, and is connected to the source electrode of the not-shown second-stage transistor. The source electrode SE2 is formed integrally with the signal line SLB11. The signal line SLB11 extends in the second direction Y from the source electrode SE2 in the direction opposite to the select line SSB, and is connected to the source electrode of the not-shown second-stage transistor. In FIG. 4, the signal lines are hatched.
One end of the drain electrode DE on the select line SSB side is connected to the connection wiring CNW1. The other end of the drain electrode DE opposite to the selection line SSB extends in the second direction Y in the direction opposite to the selection line SSB and is connected to the drain electrode of the not-shown second-stage transistor.

One end of the gate electrode GE1 on the select line SSB side is connected to a gate line (second wiring) GEL1 formed integrally with the gate electrode. The gate line GEL1 extends in the second direction Y in the direction of the selection line SSB from the transistor STR11, and is connected to the selection line SSR1 through the contact hole CH3. One end of the gate electrode GE2 on the select line SSB side is connected to a gate line (second wiring) GEL2 formed integrally with the gate electrode. The gate line GEL2 extends in the second direction Y in the direction of the selection line SSB from the transistor STB11, and is connected to the selection line SSB1 through the contact hole CH3.

The gate electrode GE1 integrally has an extending portion (second extending portion) GEE1 extending from the other end opposite to the selection line SSB in the second direction Y in the direction opposite to the selection line SSB by a predetermined length. ing. Similarly, the light-shielding layer LS1 integrally includes an extension (first extension) LSE1 extending a predetermined length in the second direction Y in the direction opposite to the selection line SSB from the end opposite to the selection line SSB. have. The extension part LSE1 overlaps the extension part GEE1 of the gate electrode GE1 via the insulating layer. The extension LSE1 extends slightly longer than the extension GEE1. As will be described later, the extension LSE1 of the light shielding layer LS1 is electrically connected to the extension GEE1 of the gate electrode GE1 via the connection wiring SLC1. Thus, the light shielding layer LS1 is electrically connected to the gate electrode GE1 to form a back gate.

The gate electrode GE2 integrally has an extension part GEE2 extending by a predetermined length in the second direction Y in the direction opposite to the selection line SSB from the other end opposite to the selection line SSB. Similarly, the light shielding layer LS2 integrally has an extending portion LSE2 extending a predetermined length in the second direction Y in the direction opposite to the selection line SSB from the end opposite to the selection line SSB. The extension part LSE2 overlaps the extension part GEE2 of the gate electrode GE2 via the insulating layer. The extension LSE2 extends slightly longer than the extension GEE2. As will be described later, the extension LSE2 of the light shielding layer LS2 is electrically connected to the extension GEE2 of the gate electrode GE2 via the connection wiring SLC2. Thus, the light shielding layer LS2 is electrically connected to the gate electrode GE2 to form a back gate.

FIG. 5 is a cross-sectional view of the transistor portion along line AA of FIG.
As shown, the transistors STR11 and STB11 have substantially the same cross-sectional structure as the switching element PSW of the sub-pixel SX shown in FIG. Light-shielding layers LS1 and LS2 are formed on the surface of the base material BA1, and an insulating layer UC is formed over the surface and the light-shielding layers LS1 and LS2. A semiconductor layer SC and a gate insulating layer GI are laminated over the insulating layer UC. Gate electrodes GE1 and GE2 are provided over the gate insulating layer GI. The gate electrodes GE1 and GE2 overlap the light shielding layers LS1 and LS2 with the insulating layers UC and GI and the semiconductor layer SC interposed therebetween.

The light shielding layers LS1 and LS2 have the same shape and width as the gate electrodes GE1 and GE2. The widths in the first direction X of the light shielding layers LS1 and LS2 substantially match the widths in the first direction X of the gate electrodes GE1 and GE2. The side edges of the light shielding layers LS1 and LS2 are aligned with the side edges of the gate electrodes GE1 and GE2, and both are positioned so as to overlap each other in the third direction Z. As shown in FIG.
An insulating layer ILI is formed overlying the gate insulating layer GI and the gate electrodes GE1 and DE2. Source electrodes SE1 and SE2 and a drain electrode DE are provided overlying the insulating layer ILI. The source electrode SE1 is connected to the semiconductor layer SC through a contact hole CH1. Similarly, the source electrode SE2 is connected to the semiconductor layer SC through the contact hole CH1. The drain electrode DE is located between the source electrodes SE1 and SE2 and connected to the semiconductor layer SC via the contact hole CH2.
The insulating layer ILI, the source electrodes SE1, SE2 and the drain electrode DE are covered with the insulating layer PLN1.

Source electrodes (sometimes referred to as signal lines) SE1 and SE2, gate electrodes (sometimes referred to as gate lines or scanning lines) GE1 and GE2 are aluminum (Al), titanium (Ti), silver (Ag), molybdenum. (Mo), tungsten (W), copper (Cu), chromium (Cr), and other metal materials, or alloys that combine these metal materials, and may have a single-layer structure or a multi-layer structure. There may be.
The light shielding layers LS1 and LS2 may be made of a metal material having a light shielding property. More specifically, they are preferably formed of the same material as the gate lines (scanning lines).

6 is an enlarged plan view showing the extension GEE1 of the gate electrode GE1 and the extension LSE1 of the light shielding layer LS1, FIG. 7 is a cross-sectional view of the extension along the line BB in FIG. 8 is a cross-sectional view of the extension along line DD of FIG. 6. FIG.
As shown in FIG. 6, the light shielding layer LS1 and its extending portion LSE1 are formed on the base material BA1 and extend in the second direction Y by a predetermined length. The extending end of the extending portion LSE1 is shifted in the first direction X by a predetermined width, for example, the width in the first direction X of the light shielding layer LS1, with respect to the central axis of the light shielding layer LS1. An insulating layer US and a gate insulating layer GI are stacked in this order over the light shielding layer LS1 and the extending portion LSE1.
The gate electrode GE1 and its extension GEE1 are provided to overlap the gate insulating layer GI and extend in the second direction Y by a predetermined length. The extending end of the extending portion GEE1 extends in the first direction X by a predetermined width, for example, about half the width of the gate electrode GE1 in the first direction X, with respect to the central axis of the gate electrode GE1. It is shifted to the side of part LSE1.
As a result, approximately half the widthwise region of the extending portion GEE1 overlaps in the third direction Z with approximately half the widthwise region of the extending portion LSE1. Further, the extending portion LSE1 extends in the second direction Y slightly longer than the extending portion GEE1. The central axis of the extending portion GEE1 and the central axis of the extending portion LSE1 are spaced apart in the first direction X by a distance L1.

As shown in FIGS. 7 and 8, the insulating layer ILI is stacked over the gate electrode GE1, the extension GEE1, and the gate insulating layer GI. A contact hole CH6 is formed through the insulating layer IL1, the gate insulating layer GI, and the insulating layer UC. As shown in FIG. 6, in one example, the contact hole CH6 is formed in a substantially rectangular shape and provided so as to overlap the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1. The width in the first direction X and the width in the second direction Y of the contact hole CH6 are formed larger than the width in the first direction X of the region where the extending portions LSE1 and GEE1 overlap. The contact hole CH6 is provided at a position where the central axis C extending in the second direction Y overlaps the center in the first direction X of the region where the extensions LSE1 and GEE1 overlap. Further, the contact hole CH6 is formed and arranged such that the end in the second direction Y is located outside in the second direction Y the extending end of the extending portion LSE1 and the extending end of the extending portion GFF1. ing. A part of the extending end of the extending part LS1 and a part of the extending end of the extending part GEE1 are exposed in the contact hole CH6.

As shown in FIGS. 6, 7, and 8, a connection wiring SLC1 is formed over the entire contact hole CH6. The connection wiring SLC1 functioning as a wiring layer is formed of, for example, the same metal layer as the signal line SL. The connection wiring SLC1 formed in the contact hole CH6 overlaps and directly contacts the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1, and is electrically connected to these extending ends. there is Thus, the extending end of the extending portion LSE1 is electrically connected to the extending end of the extending portion GEE1 via the connection wiring SLC1. That is, the light shielding layer LS is electrically connected to the gate electrode GE1 via the single contact hole CH6 and the connection wiring SLC1. The insulating layer ILI and the connection wiring SLC1 are covered with an insulating layer PLN1. In the embodiment, it is assumed that the contact hole CH6 and the connection wiring SLC1 constitute a contact portion.
The other extending portions LSE2 and GEE2 of the transistors STR11 and STB11 are also configured in the same manner as the extending portions LSE1 and GEE1 described above, and are electrically connected to each other by connection wirings formed in a single contact hole. It is

As described above, the extending portion GEE of the gate electrode GE of the transistor ST and the extending portion LSE of the light shielding layer LS are extended in the direction opposite to the plurality of selection lines SSB, and the extending ends are electrically connected to each other by the connection wiring. By forming the contact portions (connection wirings SLC) in such a manner that the extension portions GEE, LSE and the contact portions can be arranged in a vacant region where a plurality of selection lines SSB do not exist. As a result, the contact portion connecting the gate electrode and the light shielding layer does not overlap with a plurality of selection lines or other wirings, and disconnection of the wiring caused by the contact portion can be prevented. At the same time, by arranging the extension portions GEE, LSE and the contact portion in a region where a plurality of selection lines SSB and lead lines are not provided, it is possible to contribute to an unintended reduction in capacitance.
Further, as described above, the extending portion GEE1 is shifted in the first direction X with respect to the extending portion LSE1, and is partially overlapped with the extending portion GEE1, thereby forming a single contact hole CH6. Connection line SLC1 can contact both extended end portion SL1 and extended end portion GG1 over a relatively large area. This makes it possible to reliably electrically connect the light shielding layer LS and the gate electrode GE. By enabling connection through a single contact hole CH6, the area occupied by the contact portion can be reduced compared to the case of connection through a plurality of contact holes, and as a result, the size of the switch circuit can be reduced. can contribute to Furthermore, in this embodiment, since there is no shift (offset) of the extension end in the second direction Y, the extension length of the extension in the second direction Y can be shortened to achieve further miniaturization. can be done.
By forming the gate electrode GE, the light shielding layer LS overlapping with the extension GEE, and the extension LSE in the same shape, the capacitance generated in the gate electrode GE and the capacitance generated in the light shielding layer LS can be the same. can. This makes it possible to improve the characteristics of the transistor.

As shown in FIG. 4, other transistors STG21, STR21, transistors STB21, STG11, transistors STG12, STB22, transistors STR22, STG22, transistors STR12, STB12 are configured similarly to the transistors STR11, STB11 described above. . Components identical to those of the transistors STR11 and STB11 are denoted by the same reference numerals. These transistors ST are arranged side by side at predetermined intervals in the first direction.

The signal lines SLG21 and SLR21 extending from the source electrodes SE1 and SE2 of the transistors STG21 and STR21 extend in the second direction Y and are connected to the source electrodes of the corresponding transistors in the second stage. The drain electrodes DE of the transistors STG21 and STR21 are connected to the connection wiring CNW1. The gate electrode GE1 of the transistor STG21 is connected to the select line SSG2 through the gate line GEL1. A gate electrode GE2 of the transistor STR21 is connected to the selection line SSR2 through the gate line GEL2.

The signal lines SLB21 and SLG11 extending from the source electrodes SE1 and SE2 of the transistors STB21 and STG11 extend in the second direction Y and are connected to the source electrodes of the corresponding transistors in the second stage. The drain electrodes DE of the transistors STB21 and STG11 are connected to the connection wiring CNW1. The gate electrode GE1 of the transistor STB21 is connected to the select line SSB2 through the gate line GEL1. The gate electrode GE2 of the transistor STG11 is connected to the select line SSG1 through the gate line GEL3.
The connection wiring CNW1 is connected to the lead wiring WL1 via the contact hole CH4, and is connected to the signal line drive circuit SLC via the lead wiring WL1.

The signal lines SLG12 and SLB22 extending from the source electrodes SE1 and SE2 of the transistors STG12 and STB22 extend in the second direction Y and are connected to the source electrodes of the corresponding transistors in the second stage. The drain electrodes DE of the transistors STG12 and STB22 are connected to the connection wiring CNW2. A gate electrode GE1 of the transistor STG12 is connected to the select line SSG1 through a common gate line GEL3. A gate electrode GE2 of the transistor STB22 is connected to the selection line SSB2 through the gate line GEL2.

The signal lines SLR22 and SLG22 extending from the source electrodes SE1 and SE2 of the transistors STR22 and STG22 extend in the second direction Y and are connected to the source electrodes of the corresponding transistors in the second stage. The drain electrodes DE of the transistors STR22 and STG22 are connected to the connection wiring CNW2. A gate electrode GE1 of the transistor STR22 is connected to the selection line SSR2 through the gate line GEL1. A gate electrode GE2 of the transistor STB22 is connected to the selection line SSG2 through the gate line GEL2.

The signal lines SLR12 and SLB12 extending from the source electrodes SE1 and SE2 of the transistors STR12 and STB12 extend in the second direction Y and are connected to the source electrodes of the corresponding transistors in the second stage. The drain electrodes DE of the transistors STR12 and STB12 are connected to the connection wiring CNW2. A gate electrode GE1 of the transistor STR12 is connected to the selection line SSR1 through the gate line GEL1. A gate electrode GE2 of the transistor STB12 is connected to the selection line SSB1 through the gate line GEL2.
The connection wiring CNW2 is connected to the lead wiring WL2 via the contact hole CH4, and is connected to the signal line drive circuit SLC via the lead wiring WL2.

In any of the other transistors STG21, STR21, transistors STB21, STG11, transistors STG12, STB22, transistors STR22, STG22, transistors STR12, STB12, the extensions GEE1, GEE2 of the gate electrode GE and the extension LSE1 of the light shielding layer LS , LSE2 extend in the second direction Y in the direction opposite to the selection line SSB, and the extending ends are electrically connected to each other by a connection wiring formed in a single contact hole.

As described above, according to the first embodiment, the extending portion of the light shielding layer and the extending portion of the gate electrode are electrically connected by the connection wiring provided in the single contact hole without changing the size of the contact hole. The direct connection reduces the number of contact holes and contact portions, reduces the area occupied by the contact portions, and provides a miniaturized display device.

Next, a signal line switch circuit of a display device according to another embodiment will be described. In other embodiments described below, the same reference numerals as in the first embodiment are given to the same components as in the first embodiment described above, and detailed description thereof may be omitted or simplified. .
(Second embodiment)
9 is a plan view showing the contact portion of the signal line switch circuit in the display device according to the second embodiment, and FIG. 10 is a sectional view of the contact portion taken along line EE in FIG.
As shown in the figure, according to the second embodiment, in the transistor ST of the signal line switch circuit ASW, the extension GEE1 of the gate electrode GE1 is the extension LSE1 of the light shielding layer LS1. It is shifted in the first direction X by about half the width in the first direction X and on the side of the drain electrode DE. As a result, approximately half the widthwise region of the extending portion GEE1 overlaps in the third direction Z with approximately half the widthwise region of the extending portion LSE1.
In the present embodiment, the extending portion LSE1 and the extending portion GEE1 have substantially the same extending length in the second direction Y, and the extending portion LSE1 and the extending portion GEE1 are shifted in the second direction Y. not.

A contact hole CH6 is formed through the insulating layer IL1, the gate insulating layer GI, and the insulating layer UC. In one example, the contact hole CH6 is formed in a substantially rectangular shape and provided so as to overlap the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1. The width in the first direction X and the width in the second direction Y of the contact hole CH6 are substantially equal to or slightly smaller than the width in the first direction X of the extending portion LSE1. The contact hole CH6 is provided at a position where the central axis C extending in the second direction Y overlaps the central axis of the extending portion LSE1 of the light shielding layer LS1. Further, the contact hole CH6 is located closer to the base end than the extending ends of the extending portions LSE1 and GEE1, and the entire contact hole CH6 overlaps the extending ends of the extending portions LSE1 and GEE1. A part of the extending end of the extending part LSE1 and a part of the extending end of the extending part GEE1 are exposed in the contact hole CH6.

As shown in FIGS. 9 and 10, a connection wiring SLC1 is formed over the entire contact hole CH6. The connection wiring SLC1 is formed of, for example, the same metal layer as the signal line SL. The connection wiring SLC1 formed in the contact hole CH6 overlaps and directly contacts the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1, and is electrically connected to these extending ends. there is Thus, the extending end of the extending portion LSE1 is electrically connected to the extending end of the extending portion GEE1 via the connection wiring SLC1. That is, the light shielding layer LS is electrically connected to the gate electrode GE1 via the single contact hole CH6 and the connection wiring SLC1. The insulating layer ILI and the connection wiring SLC1 are covered with an insulating layer PLN1.
The other extending portions LSE2 and GEE2 of the transistors STR11 and STB11 are also configured in the same manner as the extending portions LSE1 and GEE1 described above, and are electrically connected to each other by connection wirings formed in a single contact hole. It is
In the second embodiment, other configurations of the signal line switch circuit ASW are common to the signal line switch circuit ASW in the first embodiment described above.

As described above, the extension part GEE1 is shifted in the first direction X with respect to the extension part LSE1, and is partially overlapped with the connection wiring formed in the single contact hole CH6. SLC1 can be brought into contact with the extending end portions of the extending portion LSE1 and the extending portion GEE1 over a relatively large area. This makes it possible to reliably electrically connect the light shielding layer LS and the gate electrode GE. By enabling connection through a single contact hole, the area occupied by the contact portion can be reduced compared to the case of connection through a plurality of contact holes, resulting in miniaturization of the switch circuit. can contribute to
Furthermore, in the second embodiment, since the extending ends of the extending portions LSE1 and GEE1 are not shifted in the second direction Y, the length of extension in the second direction Y is shortened to further reduce the size. It is possible to plan

Note that, in the second embodiment, the extension GEE1 of the gate electrode GE1 is shifted in the opposite direction to the extension LSE1 of the light shielding layer LS1, that is, in the first direction X and the signal line SLR11. may be shifted to the side of Even in such a configuration, it is possible to obtain the same effects as those of the above-described second embodiment.

(Third embodiment)
11 is a plan view showing the contact portion of the signal line switch circuit in the display device according to the third embodiment, and FIG. 12 is a cross-sectional view of the contact portion taken along line FF in FIG.
As shown in the figure, according to the third embodiment, in the transistor ST of the signal line switch circuit ASW, the extension GEE1 of the gate electrode GE1 is located at the extension LSE1 of the light shielding layer LS1. It is shifted in the first direction X by about half the width in the one direction X, in one example, on the side of the drain electrode DE. As a result, approximately half the widthwise region of the extending portion GEE1 overlaps in the third direction Z with approximately half the widthwise region of the extending portion LSE1.
In the present embodiment, the extending portion LSE1 and the extending portion GEE1 have substantially the same extending length in the second direction Y, and the extending ends of the extending portions LSE1 and GEE1 are substantially aligned with each other. .

A contact hole CH6 is formed through the insulating layer IL1, the gate insulating layer GI, and the insulating layer UC. In one example, the contact hole CH6 is formed in a substantially rectangular shape and provided so as to overlap the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1. The width in the first direction X and the width in the second direction Y of the contact hole CH6 are substantially equal to or slightly smaller than the width in the first direction X of the extending portion LSE1. The contact hole CH6 is provided at a position where the central axis C extending in the second direction Y overlaps the central axis of the extending portion LSE1 of the light shielding layer LS1.
Further, the contact hole CH6 is positioned to be shifted in the extending direction of the second direction Y from the extending ends of the extending portions LSE1 and GEE1. In one example, the contact hole CH6 is shifted in the extension direction of the second direction Y by about half of the width in the second direction Y. As shown in FIG. Thus, the contact hole CH6 has a region of about half the width in the second direction Y overlapping the extending end portions of the extending portions LSE1 and GEE1. A part of the extending end of the extending part LSE1 and a part of the extending end of the extending part GEE1 are exposed in the contact hole CH6.

As shown in FIGS. 11 and 12, a connection wiring SLC1 is formed over the entire contact hole CH6. The connection wiring SLC1 is formed of, for example, the same metal layer as the signal line SL. The connection wiring SLC1 formed in the contact hole CH6 overlaps and directly contacts the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1, and is electrically connected to these extending ends. there is Thus, the extending end of the extending portion LSE1 is electrically connected to the extending end of the extending portion GEE1 via the connection wiring SLC1. That is, the light shielding layer LS is electrically connected to the gate electrode GE1 via the single contact hole CH6 and the connection wiring SLC1. The insulating layer ILI and the connection wiring SLC1 are covered with an insulating layer PLN1.
The other extending portions LSE2 and GEE2 of the transistors STR11 and STB11 are also configured in the same manner as the extending portions LSE1 and GEE1 described above, and are electrically connected to each other by connection wirings formed in a single contact hole. It is
In the second embodiment, other configurations of the signal line switch circuit ASW are common to the signal line switch circuit ASW in the first embodiment described above.

As described above, the extension part GEE1 is shifted in the first direction X with respect to the extension part LSE1, and is partially overlapped with the connection wiring formed in the single contact hole CH6. SLC1 can be in contact with extended end LSE1 and extended end GEE1. This makes it possible to reliably electrically connect the light shielding layer LS and the gate electrode GE. By enabling connection through a single contact hole, the area occupied by the contact portion can be reduced compared to the case of connection through a plurality of contact holes, resulting in miniaturization of the switch circuit. can contribute to
In the second embodiment and the third embodiment, when the formation position of the contact hole CH6 is the same, according to the third embodiment, the second direction Y of the extensions LSE1 and GEE1 is different from the second embodiment. can be shortened by about half the width of the contact hole CH6, so that the size of the transistor ST can be further reduced.

In the third embodiment, the extending portion GEE1 of the gate electrode GE1 is shifted in the opposite direction to the extending portion LSE1 of the light shielding layer LS1, that is, in the first direction X and the signal line SLR11. may be shifted to the side of Even in such a configuration, it is possible to obtain the same effects as those of the above-described second embodiment.

(Fourth embodiment)
13 is a plan view showing the contact portion of the signal line switch circuit in the display device according to the fourth embodiment, and FIG. 14 is a sectional view of the contact portion taken along line GG in FIG.
As illustrated, according to the fourth embodiment, in the transistor ST of the signal line switch circuit ASW, the extension GEE1 of the gate electrode GE1 and the extension LSE1 of the light shielding layer LS1 are shifted relative to each other in the first direction X. It is provided so as to overlap in the Z direction over the entire width. The extending portion LSE1 of the light shielding layer LS1 is formed so that the extending length in the second direction Y is longer than the extending length of the extending portion GEE1 of the gate electrode GE. It extends in the second direction Y beyond the extending end of the extending portion GEE1. In one example, the extension SLE1 is formed longer than the extension GEE1 by approximately half the width of the extension SLE1 in the first direction X.

In one example, the contact hole CH6 is formed in a substantially rectangular shape and provided so as to overlap the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1. The width in the first direction X and the width in the second direction Y of the contact hole CH6 are substantially equal to or slightly smaller than the width in the first direction X of the extending portion LSE1. The contact hole CH6 is provided at a position where the central axis C extending in the second direction Y overlaps the central axis of the extending portion LSE1 of the light shielding layer LS1.
Almost half of the contact hole CH6 in the second direction Y overlaps the extending end of the extending portion LSE1, and the other half of the contact hole CH6 overlaps the extending end of the extending portion GEE1. That is, the extending end portion of the extending portion LSE1 and the extending end portion of the extending portion GEE1 are exposed in the contact hole CH6.

As shown in FIGS. 13 and 14, a connection wiring SLC1 is formed over the entire contact hole CH6. The connection wiring SLC1 is formed of, for example, the same metal layer as the signal line SL. The connection wiring SLC1 formed in the contact hole CH6 overlaps and directly contacts the extending end of the extending portion LSE1 and the extending end of the extending portion GEE1, and is electrically connected to these extending ends. there is Thus, the extending end of the extending portion LSE1 is electrically connected to the extending end of the extending portion GEE1 via the connection wiring SLC1. That is, the light shielding layer LS is electrically connected to the gate electrode GE1 via the single contact hole CH6 and the connection wiring SLC1. The insulating layer ILI and the connection wiring SLC1 are covered with an insulating layer PLN1.
The other extending portions LSE2 and GEE2 of the transistors STR11 and STB11 are also configured in the same manner as the extending portions LSE1 and GEE1 described above, and are electrically connected to each other by connection wirings formed in a single contact hole. It is
In the fourth embodiment, other configurations of the signal line switch circuit ASW are common to those of the signal line switch circuit ASW in the first embodiment described above.

According to the fourth embodiment described above, the extending end of the extending portion LSE1 is shifted in the second direction Y with respect to the extending portion GEE1, thereby forming the single contact hole CH6. The connection wiring SLC1 can be brought into contact with the extension LSE1 and the extension GEE1. This makes it possible to reliably electrically connect the light shielding layer LS and the gate electrode GE. By enabling connection through a single contact hole, the area occupied by the contact portion can be reduced compared to the case of connection through a plurality of contact holes, resulting in miniaturization of the switch circuit. can contribute to

It should be noted that although several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. The novel embodiments can be embodied in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. Embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.
Based on the configurations described above as the embodiments of the present invention, all configurations that can be implemented by those skilled in the art by appropriately designing and modifying them also belong to the scope of the present invention as long as they include the gist of the present invention.
For example, each transistor in the signal line switch circuit is not limited to a dual-gate transistor, and may be a single transistor, a transmission gate, or the like. The number of transistors and the number of wirings can be varied according to the design.
In the embodiments, a liquid crystal display device has been described as an example of the display device DSP, but the present embodiment is not limited to this, and can be applied to an electrophoretic display device, an organic EL (Electro-Luminescence) display device, and a plasma display. It can also be applied to display devices, Micro-Electro Mechanical System (MEMS) display devices, and the like.

ASW... signal line switch circuit, CNW... connection wiring, CNW1... connection wiring,
CNW2...connection wiring, STR, SRG, STG...transistor,
GE, GE1, GE2... gate electrode, GEE... extension, SE1, SE2... source electrode,
LS, LS1, LS2...Light shielding layer, LSE...Extension part, SL...Signal line, SLC...Connection wiring
SSR, SSB, SSG... selection lines, GEL1, GEL2, GEL3... gate lines,
WL1, WL2... leader line, CH... contact hole

Claims (6)

a plurality of signal lines;
Each has a gate electrode superimposed on the light shielding layer with a light shielding layer and an insulating layer interposed therebetween, and a contact portion electrically connecting the light shielding layer and the gate electrode, and arranged side by side in a first direction. a signal line switch circuit comprising a plurality of transistors connected to the plurality of signal lines,
The light shielding layer has a first extending portion extending in a second direction intersecting the first direction, and the gate electrode extends in the second direction and extends in the first direction with respect to the first extending portion. having a second extending portion that is displaced in one direction, a portion of the second extending portion overlapping a portion of the first extending portion;
The contact portion includes a single contact hole provided to overlap the first extending portion and the second extending portion, and a portion of the first extending portion and the contact hole formed in the contact hole. a wiring layer connected to a portion of the second extension;
display device. the contact hole has a central axis extending in the second direction;
The first extending portion is arranged shifted in the first direction with respect to the central axis of the contact hole, and the second extending portion is disposed with respect to the central axis of the contact hole in the first direction. 2 . The display device according to claim 1 , wherein the first extension portion and the first extension portion are shifted in a direction opposite to each other. The first extending portion has an extending end extending in the second direction beyond the extending end of the second extending portion, and the contact portion extends from the first extending portion. 3. The display device according to claim 2, wherein the extended end portion and the extended end portion of the second extended portion overlap each other. the contact hole has a central axis extending in the second direction;
The first extension has a center axis extending in the second direction that overlaps the center axis of the contact hole, and the second extension is shifted in the first direction with respect to the center axis of the contact hole. 2. A display device according to claim 1, wherein the display device is arranged at The contact hole is located closer to the base end of the first extension than the extension end of the first extension and the extension end of the second extension, and the contact hole extends over the entire area of the contact hole. 5. The display device according to claim 4, which overlaps the first extension and the second extension. A part of the contact hole overlaps the first extension and the second extension, and the other area is an extension end of the first extension and an extension of the second extension. 5. The display device according to claim 4, which is positioned outside in the second direction from the protruding end.

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