JP2023106490A - Storage device having programmed cell storage density modes that are function of storage device capacity utilization - Google Patents

Abstract

To provide an apparatus, computing system, program and computer-readable storage medium for speeding up the performance of storage devices composed of memory chips having high-density but slow cells.SOLUTION: A solid state drive (SSD) as a storage device has a controller and a plurality of FLASH memory chips, the plurality of FLASH memory chips comprising three-dimensional stacks of multi-bit storage cells, the multi-bit storage cells having a plurality of storage density modes. The controller programs the multi-bit storage cells in a low-density storage mode up to a storage capacity threshold of the storage device of at least 25%, and programs the multi-bit storage cells in a high-density storage mode once the storage capacity threshold is reached.SELECTED DRAWING: Figure 4

Description

The present invention relates generally to storage devices having programmed cell storage density modes that are a function of capacity utilization of the storage device.

As computing systems become more powerful, their storage must continue to grow. In response to this trend, manufacturers of mass storage semiconductor chips are developing techniques for storing more than one bit per storage cell. Unfortunately, such cells may exhibit slower programming times compared to their binary storage cell predecessors. Therefore, manufacturers of mass storage devices are developing new techniques to speed up the performance of storage devices constructed from memory chips with denser but slower cells.

A better understanding of the invention can be obtained from the following detailed description in conjunction with the following drawings.

Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. Figure 2 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization.

Figure 2 shows charge transfer from MLC mode to QLC mode.

FIG. 1 shows an SSD capable of implementing the write pattern of FIGS. 1a-1g. FIG.

Figure 4 shows a method performed by the SSD of Figure 3;

A computing system is shown.

The structure of a flash memory device can be understood as a three-dimensional arrangement of storage cells extending vertically over a semiconductor substrate and consisting of an array of columns, each column containing a number of individual storage cells stacked on top of each other. A storage block corresponds to a number of such columns. To access a particular number of storage cells within a block of storage cells, word line wire structures ("word lines") are coupled to the same vertically located storage cells within different columns of the block of storage cells.

For example, if each column of storage blocks consists of a vertical stack of eight storage cells, then eight different word lines would access each cell in the column of storage blocks at eight different storage levels. (e.g., the first word line may be coupled to the lowest cell in each of its columns, the second word line may be coupled to the second lowest cell in each of its columns, etc.) . In the case of flash memory, where each storage cell can store more than one bit, multiple pages of information can be accessed through a single word line. Here, mass storage devices are traditionally accessed (read/write) in blocks of data, each consisting of multiple pages. Flash memory devices that can store more than one bit per storage cell typically can access different pages by activating a single word line within the storage block in which the pages are stored.

A storage block is generally the smallest unit in which storage cells can be erased (cells in the same block are erased together), and a page is generally the smallest unit in which cells can be written or "programmed." So, for example, if the host commands the SSD to write a number of pages, multiple of those pages can be programmed within the same storage block by activating a single word line. The number of wordlines activated to fully execute a write command depends on how many pages are associated with the write and how many pages are accessible per wordline. A single flash memory chip is also typically composed of multiple sides. Each plane contains a unique set of storage blocks within the chip.

As mentioned above, different flash memory technologies are generally characterized by how many bits can be stored per storage cell. Specifically, single-level cells (SLC) store one bit per cell, multi-level cells (MLC) store two bits per cell, and ternary-level cells (TLC) store one bit per cell. Stores 3 bits per cell, and Quad Level Cells (QLC) store 4 bits per cell. While only SLC cells can store two logic states (“1” or “0”) per cell, MLC cell types, TLC cell types and Each of the QLC cell types greatly expands the storage capacity of flash devices. This is because more than two digital states can be stored in a single cell (e.g. four digital states can be stored in one MLC cell and eight digital states can be stored in one TLC cell). 16 logic states can be stored in one QLC cell).

However, there is a trade-off in terms of storage density per cell and access time per cell. That is, in general, the more bits a storage cell stores, the longer the amount of time required to write information to the cell. Here, storage cells that store more bits can be understood to have tighter charge storage tolerances than storage cells that store fewer bits. That is, cells that store more bits have a smaller amount of charge that indicates the difference between the different logic states that the cell can store, while cells that store fewer bits store more bits than the cells store. It has a larger amount of charge that indicates the difference between logic states obtained.

Flash cells are programmed or erased by pumping them with charge. Cells that store fewer bits per invocation have a larger difference between their stored charge states than cells that store more bits per cell, resulting in more "coarse-grained" pumping. Use processing. This pumping process applies a greater charge boost in fewer pumping cycles than cells using a more "fine-grained" pumping process that stores more bits per cell. This pumping process applies less charge increments (at least the maximum amount of pumping charge) in more pumping cycles. With fewer pumping cycles associated with cells storing fewer bits, such cells will exhibit lower program access times on average compared to cells storing more bits.

Therefore, next-generation flash fabrication technologies will provide improved performance in terms of storage capacity per cell, but at the same time performance will decrease in terms of average program time per cell.

To address this trade-off, flash-based storage devices such as solid-state drives (SSDs) have storage buffers composed of cells that store fewer bits per cell than their underlying manufacturing technology can store. is implemented. For example, SSDs constructed from QLC flash memory chips use a percentage of QLC cells to operate in SLC or MLC mode. Cells operating in low density mode are used by SSDs as cache-like buffers into which newly input data is written. By writing new input data to a buffer composed of lower density but faster cells, the raw program access time of the SSD is observed to be faster.

However, there are problems with implementing such buffers. The first problem is that the contents of the buffer must be constantly "cleared" by writing back the contents to the high density cells as a background process. Here, in general, SSD buffers occupy only more than 1 or 2 percent of the total storage capacity of the SSD. If the contents of the buffer are not written back to the high density cells regularly, the buffer will fill up and become unavailable for subsequent writes to the SSD. Unfortunately, the background process itself can block the buffer for new write commands (if the buffer is cleared when the new write command arrives, the write command will either clear the buffer or the background process can be interrupted). In addition, background processing increases the overall complexity of SSD operation, resulting in increased power consumption, cost and/or failure mechanisms, for example.

Figures 1a through 1f show operation in low density mode of the improved SSD design using a much larger percentage of the high density storage cells of the device. In addition, these cells operate more than the device's standard storage cells and less than the device's buffers described above. As a result, the problems just described with respect to continuously running highly managed background processes should be reduced.

As shown in FIG. 1a, an SSD can be viewed as being composed of multiple flash memory chips, each composed of N storage blocks. For simplicity, the exemplary architecture of FIG. 1a assumes that there are only two flash memory chips (die_0 and die_1) in the SSD. However, one skilled in the art could readily apply the teachings of the exemplary devices described herein to other devices containing more than two flash memory chips. Both of these memory devices consist of four planes (plane_0 to plane_3). Each plane contains N storage blocks (so there are 4×N storage blocks per memory device). Each storage block contains M word lines and each word line, when operated in its highest density QLC mode, has four different pages (bottom (L), top (U), spare (X) and top (T)). )) to support access. FIG. 1a, for example, shows the initial state when the device is being used for the first time and no random customer data has yet been stored.

FIG. 1b shows the state of the SSD after the first page number 101 has been programmed into the device. Here, an SSD includes a controller that manages a mapping table (also called an address translation table) that maps logical addresses to physical addresses. When the host sends a block of data to be written to the SSD, it also appends the block address to this data. This block address is called a logical block address (LBU). The SSD then writes this block of data to the SSD and associates in a mapping table the LBU of this data with the physical location within the SSD where the pages of data for this block are stored. These specific physical locations are designated by physical block addresses (PBA) that uniquely identify one or more die, side, block, wordline and page resources within the SSD in which the page is stored.

As can be seen from FIG. 1b, the exemplary SSD sequentially programs input pages to the same storage block and wordline (WL) locations across different sides and different memory chips, which causes the amount of memory consumed to be , extending laterally from left to right over the same block and wordline locations in . Different SSD implementations may use different write patterns. For example, in another approach, the SSD may write input pages sequentially across the same die and plane resources across different blocks and word lines (in which case the consumed storage capacity is increased along the same plane within the same die). It will be appreciated that it extends vertically from the bottom to the bottom).

As can be seen from Fig. 1b, programming these first few pages leads to cells operating at less memory capacity per cell (MLC) than what the underlying manufacturing technology supports as the highest density (QLC). including the writing of Writing pages to cells operating in low-density MLC mode improves the program access time performance of SSDs compared to approaches in which pages are written only to cells operating in highest-density QLC mode. That is, as noted above, low storage capacity cells have less write access time than high density cells.

In addition, due to the lower storage density, only half the page capacity is consumed per wordline. That is, for example, with cells operating in MLC mode where only two bits are stored per cell, only two pages can be stored per word line. As will be explained in further detail below, the unused half of a page's storage capacity can be consumed when a threshold amount of the total capacity of the SSD's storage cells is consumed, resulting in these cells may be a justification for switching from low-density MLC mode to high-density QLC mode.

The pattern of writes to only half of the potential page stores on one word line is that only two pages (L and U) at block address 0 (BA=0) and word line address 0 (WL=0) are multiple. It can be seen directly from FIG. 1b in that it is written across the face and die. Now, in order to write 4 pages of information (even if 4 pages of information are two blocks are required, even though they can be stored in a single word line of blocks of . That is, each block can only store two pages per word line since the cells are operating in low density mode (two bits per cell mode). Therefore, the second block and wordline combination is required to store the third and fourth pages. In contrast, if the cell were operating in high density mode (4 bits per cell mode), four pages per block and word line combination could be programmed.

Again, in an alternative implementation using a write pattern in which data is written sequentially across different blocks and word lines of the same side and die, pages L and U are on side 0 of die 1 with BA=0 and WL=0. After being written, the SSD may write pages L and U to BA=0 and WL=1 on side 0 of die 1, for example. In this particular embodiment, again, only half of the potential storage capacity along a particular wordline is programmed. Thus, there are a myriad of different sequences of storage block and word line combinations that can be used to define a particular programming pattern as a new page being written to the SSD. For ease of discussion, the remainder of this description will primarily refer only to the embodiment in which the page write pattern is shown in FIGS. 1b-1f.

FIG. 1c shows the further state of the SSD after an additional new page has been programmed into the SSD in low density mode. Here, as can be seen from FIG. 1c, all of the L and U page locations at BA=0 and WL=0 yield lower storage densities per cell across all sides of both dies in the SSD. is written in Therefore, since all cells at locations BA=0 and WL=0 across the SSD have been written in low density mode, such cells have the maximum capacity of their current mode (2 pages per wordline). but not their maximum potential capacity (4 pages per word line). That is, as can be seen from FIG. 1c, page locations X and T have nothing written across these same storage blocks, sides and dies, which limits the potential maximum storage capacity of these blocks. resulting in a 50% drop in utilization. However, programming of these pages can be done in less time due to the storage cells operating in a lower density storage mode.

FIG. 1d shows another further state of the SSD after an additional number of pages, whose combined amount of data corresponds to a capacity of 50% of the SSD's maximum capacity, have been programmed into the SSD according to the aforementioned write pattern. . Here again, the written cells are operating in a low density mode where the SSD write access time is improved to 50% utilization of the SSD's storage capacity. Reflecting on the discussion at the beginning of this description that traditional SSD buffers typically only use 1% or 2% of an SSD's storage cells, the improved approach described herein should show SSD performance "as if" it consisted of buffers that consumed 50% of the SSD's storage cells.

Importantly, with such a large effective buffer, due to the small size of the buffer, constantly reading information from the buffer to generate available space is costly and expensive. There is little/no need to implement background processes that require administration. Rather, the effective buffer of the improved approach has an initial capacity that is 50% of the SSD's storage capacity. With such a large valid buffer, at least initially, data need not be read continuously from the valid buffer; rather, programmed data is simply stored in place according to the standard cell storage usage model. can stay in

Figures 1e to 1f show the write pattern continuing from the state of Figure 1d onwards after the SSD has programmed more pages to the SSD. Now, after the situation in Fig. 1d, where 50% of the SSD's storage capacity has been consumed but 100% of the storage cells are being used at 50% of their maximum storage capacity, the cells can store more pages of storage. must be switched from MLC modes to their full QLC mode to accommodate .

Therefore, as seen in FIG. 1e, the writing pattern repeats for the second pass, but in the QLC density mode rather than the MLC density mode. Therefore, two additional pages of storage capacity are available along all BA=0 and WL=0 locations across different sides and dies of the SSD. Specifically, FIG. 1e shows the previously unused capacity of these locations being consumed by data in page locations X and T of locations with BA=0 and WL=0 across different sides and dies of the SSD. show. Writing a page in maximum cell density mode can slow down SSD performance compared to the initial 50% cell utilization due to the longer write times associated with QLC mode. In another approach above, SSDs show a speedup to the first 50% of the capacity utilization of SSDs like MLC. After the first 50% of the SSD's storage capacity has been utilized (FIGS. 1d to 1e), the SSD's performance experiences some degradation due to the introduction of the slow QLC programming process.

According to one approach, to program cells that store MLC data together with QLC data, the charge distribution in the original MLC mode is converted to QLC mode according to the charge distribution transfer diagram provided in FIG. Here, as can be seen, the 2 bits stored per cell are converted to the 2 least significant bits in 4-bit QLC mode. Comparing FIG. 2 with FIGS. 1a to 1f, the L and U pages occupy the least significant bits of the four bits stored in the new QLC mode, whereas of the newly written pages X and T pages occupy the two most significant bits of the four bits stored in QLC mode. In one embodiment, the four stored bits per cell are organized in terms of pages where they are represented as T, X, U, L from most significant bit to least significant bit.

In various embodiments, to properly perform charge redistribution from MLC to QLC when the second pass of the write pattern is written at QLC density, initially during the first pass is in MLC mode. A pair of bits that were stored in a cell are read from that cell and then combined with the new data to be written to that cell. The combined 4 bits (the original 2 bits and the new 2 bits) are then programmed into the cell.

Figures 1f and 1g show the following conditions which are equivalent to Figures 1c and 1d respectively with respect to the number of additional stored pages. As can be seen from FIGS. 1f and 1g, the cells in the SSD are continuously overwritten during the second pass in maximum storage density mode per cell, which increases the storage capacity of each cell by two additional are extended by an additional 2 bits from each of pages X and T of . Therefore, at the time of the state of the SSD in FIG. 1g, the full storage capacity of the SSD has been reached.

In various embodiments, the information maintained by the SSD's wear leveling function can be used to minimize the perceived performance hit to the SSD as a result of switching to denser and slower cells. Here, as is known in the art, storage cells that are written more frequently wear out faster than cells that are written less frequently.

Thus, the SSD's controller performs wear leveling to remap frequently accessed "hot" blocks of information to infrequently accessed "colder" blocks. Here, the controller monitors the access rate (and/or total number of accesses) of the physical addresses of the SSD and maintains an internal map mapping these physical addresses to the original LBUs provided by the host. Based on the monitored rates and/or counts, the controller can determine when certain blocks are considered "hot" and require swapping of their associated data, and when certain blocks are "cold." ” to determine if a hot block of data can be received. In the traditional wear leveling approach, information in colder blocks may also be swapped to hot blocks.

The hot and cold block data maintained by the wear leveling feature is also used to reduce the impact of degraded programming performance once utilization of the high density cell storage mode begins. It can be used to maintain pages and to maintain cold pages in storage cells operating in QLC mode. Here, for example, FIG. 1e shows an SSD. A significant percentage of SSD storage cells operate in MLC mode and a significant percentage of SSD storage cells operate in QLC mode. Therefore, there may be a sufficient number of hot blocks in slow QLC cells and a sufficient number of cold blocks in fast MLC cells. Wear leveling data maintained by the controller can be used to intelligently swap the positions of these pages such that hot blocks are moved to fast MLC cells and cold blocks are moved to slow QLC cells.

Note that when capacity utilization drops below 50%, the SSD may return to operating entirely in MLC mode.

FIG. 3 illustrates an embodiment of SSD 301 that may operate consistent with the teachings provided above. As can be seen in FIG. 3, SSDs contain many storage cells 302 that can store more than one bit. Additionally, most or all of the storage cells in SSDs can operate in both MLC and QLC modes. Which one of these modes a particular one of these cells will operate in depends on the storage capacity utilization of the SSD (e.g., at 50% or less of full capacity utilization, all cells operate in MLC mode, and between 50% and 100% capacity utilization, some cells operate in MLC mode, while other cells operate in QLC mode, and at 100% capacity utilization, all cells operate in QLC mode).

The SSD includes controller 306 . Controller 306 is responsible for determining which cells operate in MLC mode and which cells operate in QLC mode. According to one embodiment described in detail above, a first programming pass is applied to all cells operating in MLC mode and then a second pass is applied to all cells operating in QLC mode. be. Capacity utilization information and/or information identifying which cells are operating in which mode 311 is maintained, for example, in memory and/or register areas 310 combined and/or integrated within controller 306 . In one embodiment, such information is provided for each physical address or some granularity (e.g. block ID) where a set of cells are treated identically as a common group with respect to their MLC mode/QLC mode of operation. Represented by QLC bits or similar digital record.

Thus, if such granularity is at the block level, each block is identified in information 311, further specifying for the MLC when each of these blocks is first programmed. Above 50% capacity utilization, when the SSD starts converting from MLC cells to QLC cells, the information 311 is changed to indicate the QLC mode with each MLC block newly overwritten with the QLC mode. . By the time 100% capacity utilization is reached, the information 311 of all blocks should indicate QLC mode. Information 311 may also specify which blocks are actually written. This allows the controller 306 to determine the percentage of capacity utilization. Moreover, as described above, information 311 may be used to enhance wear leveling algorithms executed by controller 306 . Specifically, the wear leveling algorithm executed by controller 306 may swap hot blocks from QLC blocks to MLC blocks, and cold blocks from MLC blocks to QLC blocks.

Controller 306 is also coupled to charge pumping circuitry 307 . Charge-pumping circuit 307 is designed to generate different charge-pumping signal sequences for QLC and MLC modes. Here, the controller 306 applies which signal (MLC or QLC) to any particular programming sequence according to the controller's determination based on the capacity utilization of the SSD as to which operating mode is appropriate for the cell being written. Tells the charge pumping circuit 307 whether to apply.

Controllers may include dedicated hardwired logic circuits (e.g., hardwired application-specific integrated circuit (ASIC) state machines and support circuits), programmable logic circuits (e.g., field programmable gate arrays (FPGAs)), programmable logic devices (PLDs), It may be implemented as logic circuitry (eg, an embedded processor, embedded controller, etc.) designed to execute program code, or any combination thereof. In embodiments in which at least some portion of controller 306 is designed to execute program code, the program code is stored in local memory (eg, the same memory in which information 311 is maintained) and executed by the controller therefrom. be done. I/O interface 312 is coupled to controller 306 and may be any industry standard peripheral or storage interface (e.g., Peripheral Component Interconnect (PCIe), Advanced Technology Attachment/Integrated Drive Electronics (ATA/IDE), Universal Serial Bus (USB)). , IEEE 1394 (“Firewire”), etc.).

This is related to recognizing that other embodiments may utilize the teachings provided herein, even if they deviate somewhat from the specific embodiments described above. In particular, other embodiments may change the percentage of SSD capacity utilization at which new programming changes from MLC mode to QLC mode due to SSD operation. For example, in one embodiment, cell writing begins in QLC mode when capacity reaches 25% instead of 50% (or any capacity between 25% and 50%). In this case, for example, programming in QLC mode is started before reaching the state of FIG. 1d. Various embodiments may also allow the user/host to configure at what capacity utilization the switch to QLC mode will begin. For example, SSDs may support configurable options of 25%, 30%, 33%, 40% and 50%, or any capacity utilization between 25% and 50%. Possibly less than 25% capacity utilization can also be used to trigger switching to QLC mode.

It is also recognized that the MLC low density mode and QLC high density mode are exemplary only, and that other embodiments may have different low density modes and/or different high density modes. related. For example, in one embodiment, the low density is TLC and the high density is QLC. Note that in this embodiment, switching to high density mode may occur when capacity utilization reaches, for example, 75% (when all cells are programmed at 3 bits per cell) or less. sea bream. In another embodiment, the low density is SLC and the high density is QLC. Note that in this embodiment, switching to high density mode can occur when capacity utilization reaches 25% (when all cells are programmed with 1 bit per cell). Previous TLC/QLC SSDs had more but slower effective buffers than SLC/QLC SSDs which had less but faster effective buffers. Therefore, the exact rate at which switching to high density mode occurs may also be a function of the particular low and high density modes utilized.

The teachings herein may also be applied to systems other than the specific SSD described above in connection with FIG. For example, the functions of controller 306 described above may be partially or wholly integrated into the host system.

FIG. 4 illustrates the method described above. The method includes programming (401) multi-bit storage cells of a plurality of flash memory chips to a low density storage mode. The method also includes programming (402) multi-bit storage cells of the plurality of flash memory chips to a high density storage mode after at least 25% of the storage capacity of the plurality of flash memory chips has been programmed.

FIG. 5 provides an exemplary diagram of a computing system 500 (eg, smart phone, tablet computer, laptop computer, desktop computer, server computer, etc.). As seen in FIG. 5, a basic computing system 500 includes a central processing unit 501 (which may, for example, include multiple general-purpose processing cores 515_1 through 515_X) and a main memory controller 517 located on a multi-core processor or application processor. , system memory 502, display 503 (e.g., touch screen, flat panel), local wired point-to-point link (e.g., USB interface 504), and various network I/O functions 505 (Ethernet interface). and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface 506, a wireless point-to-point link (e.g., Bluetooth®) interface 507, a global positioning system interface 508, It may include various sensors 509_1 through 509_Y, one or more cameras 510, a battery 511, a power management control unit 512, a speaker and microphone 513, and an audio coder/decoder 514.

Application processor or multi-core processor 550 includes one or more general-purpose processing cores 515, one or more graphics processing units 516, memory management functions 517 (e.g., memory controllers), and I/O control functions 518 within its CPU 501. and General-purpose processing core 515 typically executes the operations of the computing system's operating system and application software. Graphics processing unit 516 typically performs graphics intensive functions that generate graphical information to be displayed on display 503, for example. Memory control function 517 interfaces with system memory 502 to write data to and read data from system memory 502 . Power management control unit 512 generally controls power consumption of system 500 .

Each of the touch screen display 503, communication interfaces 504-707, GPS interface 508, sensor 509, camera 510 and speaker/microphone codecs 513, 514 may optionally be integrated peripheral devices (eg, one or more cameras 510). It can be seen as various forms of I/O (input and/or output) to the overall computing system, including Depending on the implementation, various of these I/O components may be integrated on the application processor/multicore processor 550 or located off-die or out of the application processor/multicore processor 550 package. obtain.

The computing system also includes non-volatile storage 520, which can be a mass storage component of the system. Here, for example, mass storage consists of flash memory chips whose multi-bit storage cells are programmed with different storage densities depending on the capacity utilization of the SSD, as explained in detail above. It can consist of multiple SSDs.

Embodiments of the invention may include various processes described above. These processes may be embodied in machine-executable instructions. The instructions may be used to cause a general purpose or special purpose processor to perform specific processing. Alternatively, these processes may be performed by specific/custom hardware components including hardwired or programmable logic circuits (e.g., FPGAs, PLDs) to perform the processes, or by programmed computer components and It can be implemented by any combination of custom hardware components.

Elements of the present invention may also be provided as a machine-readable medium for storing machine-executable instructions. Machine-readable media include, but are not limited to, floppy diskettes, optical disks, CD-ROMs, magneto-optical disks, flash memory, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, transmission media, or electronic instructions. Other types of media/machine-readable media suitable for storage may be included. For example, the present invention enables a computer requesting data from a remote computer (e.g., a server) using data signals embodied in carrier waves or other propagation media over a communications link (e.g., a modem or network connection). It can be downloaded as a computer program that can be transferred to (eg, a client).

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes can be made without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[Item 1]
with a storage device,
The storage device has a controller and a plurality of flash memory chips,
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
The multi-bit storage cell has multiple storage density modes,
the controller programs the cells to a low density storage mode up to a storage capacity threshold of the storage device of at least 25%, and once the capacity threshold is reached, programs the cells to a high density mode;
Device.
[Item 2]
the low density storage mode is a multi-level cell (MLC),
A device according to item 1.
[Item 3]
the high density storage mode is quad level cell (QLC),
A device according to item 2.
[Item 4]
the storage capacity threshold is 50%;
A device according to item 3.
[Item 5]
The storage capacity threshold is in the range of 25% or more and 75% or less,
A device according to item 1.
[Item 6]
the high density storage mode is QLC;
A device according to item 1.
[Item 7]
the storage device is a solid state drive,
A device according to item 1.
[Item 8]
with a controller that determines the programming level of multiple flash memory chips,
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
The multi-bit storage cell has multiple storage density modes,
the controller programs the cells to a low density storage mode up to a storage capacity threshold of the flash memory chip of at least 25%, and once the capacity threshold is reached, programs the cells to a high density storage mode;
Device.
[Item 9]
the low density storage mode is a multi-level cell (MLC),
9. Apparatus according to item 8.
[Item 10]
the high density storage mode is quad level cell (QLC),
10. Apparatus according to item 9.
[Item 11]
the storage capacity threshold is 50%;
11. Apparatus according to item 10.
[Item 12]
The storage capacity threshold is in the range of 25% or more and 75% or less,
9. Apparatus according to item 8.
[Item 13]
the high density storage mode is QLC;
9. Apparatus according to item 8.
[Item 14]
the storage device is a solid state drive,
9. Apparatus according to item 8.
[Item 15]
a plurality of processing cores;
main memory and
a memory controller coupled between the plurality of processing cores and the main memory;
a peripheral hub controller;
a solid state drive coupled to the peripheral hub controller;
The solid state drive has a controller and a plurality of flash memory chips,
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
The multi-bit storage cell has multiple storage density modes,
the controller programs the cells to a low density storage mode up to a storage capacity threshold of the storage device of at least 25%, and once the capacity threshold is reached, programs the cells to a high density storage mode;
computing system.
[Item 16]
the low density storage mode is a multi-level cell (MLC),
16. A computing system according to item 15.
[Item 17]
the high density storage mode is quad level cell (QLC),
17. A computing system according to item 16.
[Item 18]
the storage capacity threshold is 50%;
18. A computing system according to item 17.
[Item 19]
The storage capacity threshold is in the range of 25% or more and 75% or less,
16. A computing system according to item 15.
[Item 20]
When processed by the controller of a storage device with multiple flash memory chips,
programming multi-bit storage cells of said plurality of flash memory chips to a low density storage mode;
programming the multi-bit storage cells of the plurality of flash memory chips to a high density storage mode after at least 25% of the storage capacity of the plurality of flash memory chips has been programmed. An article of manufacture that contains stored program code for execution.

Claims (21)

with a storage device,
The storage device has a controller and a plurality of flash memory chips,
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
the multi-bit storage cell has a plurality of storage density modes;
The controller at least:
writing first data to a first multi-bit storage cell in a low density storage mode from the plurality of storage density modes;
determining that the storage capacity of the storage device has reached a storage capacity threshold in response to writing the first data;
determining that second data stored in the low-density storage mode is being accessed with low frequency; in response to determining that the storage capacity of the storage device has reached the storage capacity threshold; and the first multi-bit storage in a high density storage mode from the plurality of storage density modes in response to determining that the second data stored in the low density storage mode is accessed infrequently; configured to write a combination of bits including the first data and the second data into a cell;
Writing the bit combination to the first multi-bit storage cell in the high density storage mode comprises:
reading the second data stored in the low density storage mode from a second multi-bit storage cell;
generating the bit combination including the first data and the second data;
writing the combination of bits in the high density storage mode to the first multi-bit storage cell;
Device. the low density storage mode is a multi-level cell (MLC) mode;
A device according to claim 1 . the high density storage mode is a quad level cell (QLC) mode;
3. Apparatus according to claim 2. the storage capacity threshold is at least 25%;
4. Apparatus according to claim 3. The storage capacity threshold is in the range of 25% or more and 75% or less,
4. Apparatus according to any one of claims 1-3. the high density storage mode is a QLC mode;
A device according to claim 1 . the storage device is a solid state drive;
7. Apparatus according to any one of claims 1-6. a device,
a controller configured to at least determine a write level of a plurality of flash memory chips;
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
the multi-bit storage cell has a plurality of storage density modes;
The controller at least:
writing first data to a first multi-bit storage cell in a low density storage mode from the plurality of storage density modes;
determining that the storage capacity of the device has reached a storage capacity threshold in response to writing the first data;
determining that second data stored in the low density storage mode is being accessed infrequently;
in response to determining that the storage capacity of the device has reached the storage capacity threshold and in response to determining that the second data stored in the low density storage mode is accessed infrequently. write a combination of bits including the first data and the second data to the first multi-bit storage cell in a high density storage mode from the plurality of storage density modes;
Writing the bit combination to the first multi-bit storage cell in the high density storage mode comprises:
reading the second data stored in the low density storage mode from a second multi-bit storage cell;
generating the bit combination including the first data and the second data;
writing the combination of bits in the high density storage mode to the first multi-bit storage cell;
Device. the low density storage mode is a multi-level cell (MLC) mode;
9. Apparatus according to claim 8. the high density storage mode is a quad level cell (QLC) mode;
10. Apparatus according to claim 9. the storage capacity threshold is at least 25%;
11. Apparatus according to claim 10. The storage capacity threshold is in the range of 25% or more and 75% or less,
11. Apparatus according to any one of claims 8-10. the high density storage mode is a QLC mode;
9. Apparatus according to claim 8. the device is a solid state drive;
14. Apparatus according to any one of claims 8-13. a plurality of processing cores;
main memory and
a memory controller coupled between the plurality of processing cores and the main memory;
a peripheral hub controller;
a solid state drive coupled to the peripheral hub controller;
The solid state drive has a controller and a plurality of flash memory chips,
the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells;
the multi-bit storage cell has a plurality of storage density modes;
The controller at least:
writing first data to a first multi-bit storage cell in a low density storage mode from the plurality of storage density modes;
determining that a storage capacity of the solid state drive has reached a storage capacity threshold in response to writing the first data;
determining that second data stored in the low density storage mode is being accessed infrequently;
responsive to determining that the storage capacity of the solid state drive has reached the storage capacity threshold and determining that the second data stored in the low density storage mode is accessed infrequently. writing a bit combination including the first data and the second data to the first multi-bit storage cell in a high density storage mode from the plurality of storage density modes according to;
Writing the bit combination to the first multi-bit storage cell in the high density storage mode comprises:
reading the second data stored in the low density storage mode from a second multi-bit storage cell;
generating the bit combination including the first data and the second data;
writing the combination of bits in the high density storage mode to the first multi-bit storage cell;
computing system. the low density storage mode is a multi-level cell (MLC) mode;
16. A computing system according to claim 15. the high density storage mode is a quad level cell (QLC) mode;
17. A computing system according to claim 16. the storage capacity threshold is at least 25%;
18. A computing system according to claim 17. The storage capacity threshold is in the range of 25% or more and 75% or less,
A computing system according to any one of claims 15-17. When processed by the controller of a storage device with multiple flash memory chips,
writing first data to a first multi-bit storage cell in a low density storage mode from a plurality of storage density modes;
determining that a storage capacity of the storage device has reached a storage capacity threshold in response to writing the first data;
determining that second data stored in the low density storage mode is being accessed infrequently;
in response to determining that the storage capacity of the storage device has reached the storage capacity threshold and in determining that the second data stored in the low density storage mode is accessed infrequently. accordingly, writing a combination of bits including the first data and the second data to the first multi-bit storage cell in a high density storage mode from the plurality of storage density modes. causing the storage device to execute
Writing the bit combination to the first multi-bit storage cell in the high density storage mode comprises:
reading the second data stored in the low density storage mode from a second multi-bit storage cell;
generating the bit combination including at least one bit from the first data and the second data;
writing the combination of bits in the high density storage mode to the first multi-bit storage cell;
program. A computer-readable storage medium storing the program according to claim 20.

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