JP2023085175A - メモリ一致低密度パリティ検査符号化方式 - Google Patents
メモリ一致低密度パリティ検査符号化方式 Download PDFInfo
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Abstract
【解決手段】データ記憶デバイスにおけるメモリセル電圧分布に基づくLDPC符号化を実行するシステム100であって、コントローラは、不揮発性メモリとインタフェースするメモリインタフェースと、コントローラ回路と、を含む。コントローラは、不揮発性メモリに記憶される複数のデータページを受信し、複数のデータページを複数の変換されたデータページに変換し、複数の変換されたデータページに基づいて複数のパリティビットを決定し、複数のデータページ及び複数のパリティビットを不揮発性メモリに記憶する。
【選択図】図1
Description
BERLower+BERMiddle+BERUpper+BERTop=BERt1+BERt2+...+BERt15
平均して、各変換されたページ320によって観察されたBERは、元のページのn/t=4/15である。従って、変換されたページ320を保護するために必要な全体的なECC冗長性は、n=4個の元のデータページを保護するために必要なECC冗長性と同じである。
Claims (20)
- メモリコントローラであって、
不揮発性メモリとインタフェースするように構成されたメモリインタフェースと、
コントローラであって、
前記不揮発性メモリに記憶される複数のデータページを受信し、
前記複数のデータページを複数の変換されたデータページに変換し、
前記複数の変換されたデータページに基づいて、複数のパリティビットを決定し、
前記複数のデータページ及び前記複数のパリティビットを前記不揮発性メモリに記憶する
ように構成された、コントローラと、を備える、メモリコントローラ。 - 前記複数の変換されたデータページの各々は、前記不揮発性メモリの関連付けられた読み出し閾値のエラーによって影響を受ける、請求項1に記載のメモリコントローラ。
- 前記複数のデータページのビットエラー率は、前記複数の変換されたデータページのビットエラー率に等しい、請求項1に記載のメモリコントローラ。
- 前記不揮発性メモリは複数のメモリセル状態を含み、前記複数の変換されたデータページの数は、前記複数のメモリセル状態の読み出し閾値の数に基づく、請求項1に記載のメモリコントローラ。
- 前記コントローラは、
前記記憶された複数のデータページ及び前記記憶された複数のパリティビットを前記不揮発性メモリから取り出すように更に構成されており、前記記憶された複数のデータページは、複数のデータハードビット及び複数のデータソフトビットを含み、前記記憶された複数のパリティビットは、複数のパリティハードビット及び複数のパリティソフトビットを含むように更に構成されている、請求項1に記載のメモリコントローラ。 - 前記コントローラは、
前記記憶された複数のデータページを第2の複数の変換されたデータページに変換し、
前記第2の複数の変換されたデータページ及び前記複数のパリティビットについての対数尤度比推定値を決定する、ように更に構成されている、請求項5に記載のメモリコントローラ。 - 前記コントローラは、
前記第2の複数の変換されたデータページの前記対数尤度比推定値と、前記複数のパリティビットの前記対数尤度比推定値とに基づいて、訂正された複数のデータページを生成する、ように更に構成されている、請求項6に記載のメモリコントローラ。 - 前記コントローラは、
前記記憶された複数のデータページを第2の複数の変換されたデータページに変換し、
前記第2の複数の変換されたデータページ及び前記複数のパリティビットが、一組のパリティ検査制約を満たすかどうかを判定し、
前記第2の複数の変換されたデータページ及び前記複数のパリティビットが前記一組のパリティ検査制約を満たしていないことに応答して、前記第2の複数の変換されたデータページのうちの少なくとも1つの変換されたデータページの値を調整する、ように更に構成されている、請求項5に記載のメモリコントローラ。 - 前記コントローラは、
前記第2の複数の変換されたデータページ及び前記複数のパリティビットが、前記一組のパリティ検査制約を満たすかどうかを判定し、
前記第2の複数の変換されたデータページのうちの少なくとも1つの変換されたデータページの前記値を、前記第2の複数の変換されたデータページ及び前記複数のパリティビットが前記一組のパリティ検査制約を満たすまで調整する、ように更に構成されている、請求項8に記載のメモリコントローラ。 - 前記複数の変換されたデータページにわたって前記不揮発性メモリによって引き起こされるビットエラー分布は、前記複数のデータページにわたるエラー分布とは異なる、請求項1に記載のメモリコントローラ。
- 前記コントローラは、
前記複数の変換されたデータページの推定ビットエラー率に基づいて、前記不揮発性メモリのメモリエラーモデルを決定し、
前記メモリエラーモデルに基づいて、前記不揮発性メモリの健全性を判定する、ように更に構成されている、請求項1に記載のメモリコントローラ。 - 前記コントローラは、
前記複数の変換されたデータページの推定ビットエラー率に基づいて、前記不揮発性メモリの読み出し閾値を調整する、ように更に構成されている、請求項1に記載のメモリコントローラ。 - 方法であって、
不揮発性メモリに記憶される複数のデータページを受信することと、
前記複数のデータページを複数の変換されたデータページに変換することと、
前記複数の変換されたデータページに基づいて、複数のパリティビットを決定することと、
前記複数のデータページ及び前記複数のパリティビットを前記不揮発性メモリに記憶することと
を含む、方法。 - 前記複数の変換されたデータページは、前記複数のデータページよりも多数のページを含む、請求項13に記載の方法。
- 前記複数のデータページのビットエラー率は、前記複数の変換されたデータページのビットエラー率に等しい、請求項13に記載の方法。
- 前記不揮発性メモリは複数のメモリセル状態を含み、前記複数の変換されたデータページの数は、前記複数のメモリセル状態の数に基づく、請求項13に記載の方法。
- 前記記憶された複数のデータページ及び前記記憶された複数のパリティビットを前記不揮発性メモリから取り出すことを更に含み、前記記憶された複数のデータページは、複数のデータハードビット及び複数のデータソフトビットを含み、前記記憶された複数のパリティビットは、複数のパリティハードビット及び複数のパリティソフトビットを含む、請求項13に記載の方法。
- 前記記憶された複数のデータページを第2の複数の変換されたデータページに変換することと、
前記第2の複数の変換されたデータページ及び前記複数のパリティビットについての対数尤度比推定値を決定することと
を更に含む、請求項17に記載の方法。 - 前記第2の複数の変換されたデータページの前記対数尤度比推定値と、前記複数のパリティビットの前記対数尤度比推定値とに基づいて、訂正された複数のデータページを生成すること
を更に含む、請求項18に記載の方法。 - 装置であって、
不揮発性メモリとインタフェースするための手段と、
前記不揮発性メモリに記憶される複数のデータページを受信するための手段と、
前記複数のデータページを複数の変換されたデータページに変換するための手段と、
前記複数の変換されたデータページに基づいて、複数のパリティビットを決定するための手段と、
前記複数のデータページ及び前記複数のパリティビットを前記不揮発性メモリに記憶するための手段と
を備える、装置。
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