JP2023082386A - Design condition calculation system and semiconductor device manufacturing method - Google Patents

Abstract

To provide an appropriate design value for a power device quickly and at low costs.SOLUTION: A design condition calculation system comprises an optimization calculation unit for calculating a first parameter and a second parameter so as to satisfy a predetermined condition using models constructed by a model construction unit. Of the models constructed by the model construction unit, a first conversion model provided at a front stage converts at least either of the first and second parameters to a physical property value to be input to a characteristic regression model, the characteristic regression model is provided at the middle stage and converts an unobservable physical property value to an unobservable theoretical characteristic value, and a second conversion model provided at a rear stage converts the theoretical characteristic value to an actual characteristic value. The optimization calculation unit uses the constructed models and takes fixed values set at parts of the first and second parameters as a constraint condition to calculate the first and second parameters which are not the constraint condition so as to satisfy a condition based on one or a combination of a value and a range of a third parameter.SELECTED DRAWING: Figure 1B-1

Description

The present invention relates to a design condition calculation system that supports the design of semiconductor devices, and more particularly to technology that supports the design of manufacturing parameters for power semiconductor devices.

Power semiconductor devices are required to have high withstand voltage, low on-resistance, and low switching loss, but silicon (Si) power devices, which are currently mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength about one order of magnitude higher than that of Si. Element resistance can be reduced by three orders of magnitude or more. Also, since the bandgap is about three times larger than that of Si, high temperature operation is also possible. Thus, the SiC semiconductor element is expected to have performance exceeding that of the Si semiconductor device, and the development of the SiC power semiconductor device is proceeding.

As background arts in this technical field, there are the following prior arts. In Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2020-184123), a circuit design apparatus includes an operation unit for inputting the circuit configuration of a circuit under design, the names of circuit characteristic items of the circuit under design, and the names of elements constituting the circuit under design. and a storage unit, a simulation unit that generates the element value of each circuit element and the characteristic value of each circuit characteristic item corresponding thereto by simulating the circuit under design while changing the element value of each circuit element, and in the learning mode Deep learning is performed using the element values of the circuit elements and the characteristic values of the corresponding circuit characteristic items, and at least one of the element values corresponding to the characteristic values and the characteristic values corresponding to the element values is generated by regression analysis in the design mode. A circuit design device is described that includes a design processing unit that performs

In Patent Document 2 (Japanese Patent Application Laid-Open No. 2012-150574), in order to perform simulation cooperation, device characteristics required for at least a semiconductor device equivalent circuit model used in circuit simulation are obtained from the output of semiconductor device simulation. A process of setting a semiconductor device equivalent circuit model to obtain a semiconductor A simulation collaboration method is described that includes an information feedback step with a knowledge database for feedback to device simulation.

JP 2020-184123 A JP 2012-150574 A

In order to control high power, power semiconductor devices must satisfy many performances such as on-resistance, short-circuit time, threshold voltage, breakdown voltage, switching loss, and insulating film reliability. Many of these parameters are in a trade-off relationship, and it is necessary to seek a design suitable for the application used in the trade-off. Furthermore, in recent years, device structures, processes, and circuit structures have become more complex, and many parameters are involved in design. Therefore, the characteristics of the semiconductor device and the application on which the semiconductor device is mounted, such as on-resistance, short-circuit time, threshold voltage, withstand voltage, switching loss, and insulating film reliability, are considered to be the characteristics of the device design, materials, and manufacturing conditions, and furthermore, the system. Therefore, a design that optimizes the design, materials, and fabrication conditions of the circuit on which the device is mounted is required. To establish such an optimization system, it is necessary to create highly accurate regression models of devices and circuits by simulation.

On the other hand, the characteristics of the power semiconductor device targeted by the present invention cannot be predicted with high accuracy only by existing simulations. This is because a large amount of data has been accumulated for Si, so it is possible to predict the physical property values by manual calculation, but SiC has a short history and it is difficult to predict the physical property values such as the scattering cross section and mobility. In addition, since the simulation used in the regression model calculates the relationship of unobservable parameters, it is necessary to construct a model that can be calculated with observable data.

An object of the present invention is to quickly and at a low cost provide suitable design values for power devices that satisfy a large number of characteristics in accordance with application requirements, even for SiC semiconductor devices.

A representative example of the invention disclosed in the present application is as follows. That is, the design condition calculation system comprises an arithmetic device that executes a predetermined process, an input unit for inputting data, and a storage device that can be accessed by the arithmetic device. A first parameter representing at least one of material, manufacturing process, and design; a second parameter representing at least one of material, manufacturing process, and design of a circuit on which the semiconductor device is mounted; Upon receiving an input with a third parameter representing at least one characteristic of the circuit on which the semiconductor device is mounted, the design condition calculation system causes the arithmetic device to use the model constructed by the model construction unit to set a predetermined condition The model constructed by the model construction unit includes a first transformation model provided in the front stage and a model constructed in the rear stage. A second conversion model provided, and a characteristic regression model provided between the first conversion model and the second conversion model, wherein the first parameter and the second parameter are input, and the Each parameter is related by outputting a third parameter, and the first conversion model converts at least one of the first parameter and the second parameter into the physical properties input to the characteristic regression model. the property regression model converts the unobservable physical property values into unobservable theoretical property values; the second conversion model converts the theoretical property values into actual property values; A computing unit uses the constructed model to set one of the value and the range of the third parameter with a fixed value set to a part of the first parameter and the second parameter as a constraint condition. The first parameter and the second parameter that are not the constraint condition are calculated so as to satisfy one or a combination of conditions, and the calculated first parameter and second parameter are output. .

ADVANTAGE OF THE INVENTION According to one aspect of the present invention, it is possible to quickly and at low cost provide appropriate design values for a power device that satisfies a large number of characteristics according to application requirements. Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

It is a figure which shows the structure of the design condition calculation system of embodiment of this invention. 4 is a flowchart of processing for calculating design conditions by the design condition calculation system according to the embodiment of the present invention; 4 is a flowchart of processing for calculating design conditions by the design condition calculation system according to the embodiment of the present invention; 4 is a flowchart of processing for calculating design conditions by the design condition calculation system according to the embodiment of the present invention; 4 is a flowchart of processing for calculating design conditions by the design condition calculation system according to the embodiment of the present invention; It is a figure which shows the example of the input screen of embodiment of this invention. It is a figure which shows the structure of the model construction unit of embodiment of this invention. Fig. 3 illustrates a calculation method performed in an optimization calculation unit of an embodiment of the invention; 4 is a flow chart of a manufacturing process of a trench MIS FET; FIG. 10 is a diagram showing an example of an input screen according to the first embodiment; FIG. FIG. 10 is a diagram showing an example of an input screen according to the first embodiment; FIG. FIG. 10 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model building unit of the second embodiment; FIG. 11 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model building unit of Example 3; FIG. 11 is a diagram showing an example of a corrector 1 that constitutes the front stage of the model building unit of Example 3; FIG. 12 is a diagram showing an example of a model building unit of Example 4; FIG. 12 is a diagram showing cooperation between the design condition calculation system and the semiconductor manufacturing apparatus of Example 5; 14 is a flow chart of processing for calculating design conditions by the design condition calculation system of Embodiment 6. FIG. 14 is a flow chart of processing for calculating design conditions by the design condition calculation system of Embodiment 6. FIG.

A design condition calculation system 100 for a power semiconductor device according to an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1A is a diagram showing the configuration of a design condition calculation system 100. As shown in FIG.

The design condition calculation system 100 of the present embodiment has a characteristic regression model constructed by simulation in the middle layer, a physical property value calculation model (corrector 1) in the front stage, and a physical quantity calculation model (corrector 2) in the rear stage. A highly accurate regression model is constructed by the provided model construction unit 102 .

The design condition calculation system 100 is composed of a computer having a calculation unit 101 , a data storage unit 104 , a communication section 105 , an operation section 106 , an output section 107 and an input/output unit 108 . The calculation unit 101, the data storage unit 104, the communication unit 105, and the input/output unit 108 are connected via a bus.

The calculation unit 101 is an arithmetic unit (CPU) that executes programs stored in a memory (not shown). The calculation unit 101 executes various programs to implement the functions of the functional units (for example, the model construction unit 102, the optimization calculation unit 103, etc.) of the design condition calculation system 100. FIG. Note that part of the processing performed by the calculation unit 101 by executing the program may be performed by a hardware calculation device such as an ASIC or FPGA.

The memory includes ROM, which is a non-volatile storage element, and RAM, which is a volatile storage element. The ROM stores immutable programs (eg, BIOS) and the like. The RAM is a high-speed and volatile storage device such as a DRAM (Dynamic Random Access Memory), and temporarily stores programs executed by the calculation unit 101 and data used during execution of the programs.

The data storage unit 104 is, for example, a large-capacity, non-volatile storage device configured by a magnetic storage device (HDD), flash memory (SSD), or the like. The data storage unit 104 also stores data used by the calculation unit 101 when executing programs and programs executed by the calculation unit 101 . That is, the program is read out from the data storage unit 104, loaded into the memory, and executed by the calculation unit 101 to realize each function of the design condition calculation system 100. FIG.

A communication unit 105 is a network interface device that controls communication with other devices according to a predetermined protocol.

An operation unit 106 is configured by an input device such as a keyboard, a mouse, and a touch panel, and provides an input interface for receiving operator's operations. The output unit 107 is configured by an output device such as a display device and a printer, and provides an output interface for outputting program execution results in a format that can be visually recognized by the operator. The input/output unit 108 is an interface that transfers data input to the operation unit 106 to the bus. A user terminal connected to the design condition calculation system 100 via a network may provide the operation section and the output section. In this case, the design condition calculation system 100 may have a web server function, and the user terminal may access the design condition calculation system 100 using a predetermined protocol (eg, http).

The program executed by the calculation unit 101 is provided to the design condition calculation system 100 via removable media (CD-ROM, flash memory, etc.) or network, and stored in the non-volatile data storage unit 104, which is a non-temporary storage medium. be done. Therefore, the design condition calculation system 100 preferably has an interface for reading data from removable media.

The design condition calculation system 100 is a computer system configured on one physical computer or on a plurality of logically or physically configured computers, and is built on a plurality of physical computer resources. It may run on a virtual machine. For example, the model construction unit 102 and the optimization calculation unit 103 may operate on separate physical or logical computers, or may be combined to operate on one physical or logical computer. .

1B-1, 1B-2, 1C-1, and 1C-2 are flowcharts of the process of calculating design conditions by the design condition calculation system 100. FIG. 1B-1 and 1C-1 show the processing when the model construction unit 102 is inside the design condition calculation system 100, and FIGS. Indicates the processing when outside the .

First, in step 1, when explanatory variables and objective variables are input to the operation unit 106, the operation content is displayed on the output unit 107 in step 2. FIG. Input explanatory variables include device materials, device fabrication conditions, device structures, circuit materials, circuit fabrication conditions, and circuit structure values or ranges of values. The target variable is a value or range of values of device characteristics, circuit characteristics, or the like. Then, in step 3, the data storage unit 104 stores the input data.

Next, in step 4, the model construction unit 102 creates a regression model for the power semiconductor device and the power semiconductor device mounting circuit using explanatory variables and objective variables based on the data stored in the data storage unit 104 . In the example shown in FIGS. 1B-1 and 1C-1, the model construction unit 102 is provided within the design condition calculation system 100. FIG. The model building unit 102 creates a regression model each time an input is made to the operation unit 106 according to the content of the input, and stores the created regression model in the data storage unit 104 . The created regression model may be directly input to the calculation unit 101 without being stored in the data storage unit 104 .

Next, in step 5, the calculation unit 101 uses the regression model to set the values of the explanatory variables stored in the data storage unit 104 as constraints and the values of the objective variables as targets. The relationship between the explanatory variables whose values are not specified and the objective variables is calculated multiple times, and the optimum values of the explanatory variables whose values are not specified so as to satisfy the conditions of the objective variables are obtained. Then, in step 6, the calculation unit 101 stores the optimal values of the explanatory variables and the values of the target variables at that time in the data storage unit 104. FIG. The processing of steps 5 and 6 is repeatedly executed until a predetermined end condition is satisfied. The termination condition may be that the objective variable reaches the target value, but the termination condition may be that the number of calculations or the calculation time reaches the upper limit. Then, in step 7, the output unit 107 outputs the optimum values of the explanatory variables stored in the data storage unit 104 and the values of the objective variables at that time.

1B-2 and 1C-2, one or more regression models created in advance by the model building unit 102 provided outside the design condition calculation system 100 are stored outside the design condition calculation system 100. , is registered in a database such as the cloud. Since the regression model differs depending on the device type, it is preferable to create a plurality of regression models in advance and store them outside the design condition calculation system 100 . At step 5 , the calculation unit 101 acquires the regression model from the database via the communication section 105 and stores it in the data storage unit 104 . The calculation unit 101 uses the regression model stored in the data storage unit 104 to find the optimum value of the explanatory variable that satisfies the condition of the objective variable. The calculation unit 101 may directly retrieve the regression model from the database without storing it in the data storage unit 104 . The design condition calculation system 100 can communicate with the outside via a network.

As described above, the regression model and the optimum calculation result may be saved in the data storage unit 104 each time the calculation is performed. It doesn't have to be. On the other hand, if the regression model is acquired from the database each time through the communication unit 105, the amount of communication increases and the speed decreases.

FIG. 2 is a diagram showing an example of an input screen displayed on the output unit for inputting explanatory variables and objective variables to the operation unit 106 in steps 1 and 2. FIG.

On the input screen shown in FIG. 2, you can select the type of explanatory variable to be specified in the pull-down input field 8 in the input section. You can specify sub-conditions. The number of pull-down input fields for specifying the types of explanatory variables may be three or more. The pull-down input fields 8 and 9 are used to enter the device material, device fabrication conditions, device structure, circuit material, circuit fabrication conditions, circuit structure, etc. of the semiconductor device, and the device material, device fabrication conditions, device structure, etc. of the circuit on which the semiconductor device is to be mounted. It is preferable that the circuit material, circuit fabrication conditions, and circuit structure can be selected. For example, when device fabrication conditions are selected as an explanatory variable, a process to be specified in the device fabrication process can be selected, and when a device structure is selected as an explanatory variable, the type of structure can be specified. In this way, when a condition is specified in the pull-down input field 8 or the pull-down input fields 8 and 9, a pre-registered variable is displayed on the input screen, and the fixed value or range of the variable is specified by operating the fixed check box. can. A variable with a fixed value or a range of values (maximized, minimized, or both) becomes a constraint during optimization. On the other hand, it is not always necessary to enter a value for a variable, and if no value is entered, an optimum value suitable for the objective variable is obtained in the optimization calculation.

Also, the type of target variable specified in the pull-down input field 11 in the output section can be selected, and the target value or target value range (both or one of maximization and minimization) can be input on the input screen. It is preferable that the pull-down input field 11 can be selected from device characteristics, circuit characteristics, and the like. If you do not enter the target value or range or conditions such as maximum/minimum or a combination thereof, the variable will be calculated with an arbitrary value in the optimization calculation, and the target value or range or conditions such as maximum/minimum or a combination thereof will be calculated. If filled in, it is a condition for deriving objective variables that do not have a fixed value specified in the input section.

When a parameter is input, the optimization calculation unit 103 uses the input parameter value or range as a constraint condition, and the parameter value and range input in the output section as objective variables. Among them, parameters whose values are not specified are obtained by optimization calculation. For example, when values are specified as shown in FIG. 2, the optimization calculation unit 103 maintains the drift layer concentration in the input section at 1×10 ¹⁶ , the breakdown voltage in the output section at 1200 V or more, and the threshold voltage at Optimal values of the JFET length and channel length that minimize the on-resistance are determined by setting the gate withstand voltage to 3 V to 8 V and 25 V or more.

Information about the conditions specified in the pull-down input field 8 or the pull-down input fields 8 and 9 may be displayed in the left area of the input screen. For example, in the illustrated input screen, the device structure TED-MOS is selected, so the structure of a TED-MOS FET is displayed.

FIG. 3 is a diagram showing the configuration of the model building unit 102. As shown in FIG.

The model construction unit 102 constructs a regression model using explanatory variables and objective variables input to the operation unit 106 . The model construction unit 102 is composed of multiple layers, and is roughly divided into a front stage, an intermediate layer, and a rear stage. Although FIG. 3 illustrates the model construction unit 102 composed of three layers, the front layer, middle layer, and rear layer, the model construction unit 102 may be composed of four layers or more. The model construction unit 102 takes parameters (semiconductor device parameters, semiconductor device-mounted circuit parameters) entered in the input section as inputs and selectable parameters in the output section to relate each parameter.

The former stage is a physical property value calculation model (corrector 1), which converts the parameters input to the input section into physical property values used in the simulation. For example, the physical property values used in the simulation are unobservable physical property values such as the amount of traps and mobility at the oxide film interface with respect to the film quality, film thickness, etc. of the oxide film, which are the conditions for forming the oxide film, and the amount of annealing. be. In addition to the above, the unobservable physical property values converted by the physical property value calculation model are the mobility of holes and electrons, the scattering cross section, the trap density in the oxide film, the interface level, the Auger/SRH recombination rate, the lifetime , saturated drift velocity, thermal conductivity, defect density, impurity concentration considering activation rate, design value considering mask misalignment, shape that changes depending on fabrication conditions (shape of trench angle, oxide film thickness, etc.), material (source material of the contact part), etc. In particular, in SiC, it is impossible to predict the mobility, interface traps, and activation rate by theoretical formulas, so the physical property value calculation model by the corrector 1 in the former stage is very effective. Further, the input values to be corrected are not necessarily unobservable physical property values, but may be observable physical property values. For example, when a design value is input, the aperture width actually created using a mask in the photolithography process may be used as the variable after correction.

In addition, in a power semiconductor device using a compound other than Si, traps are formed at the interface with the oxide film, causing variations in threshold voltage and a decrease in switching speed. Since the power semiconductor device controls high voltage, the fluctuation of the threshold voltage lowers the switching speed and poses a problem from the viewpoint of safety and loss. In addition, since the resistance must be reduced to reduce loss, mobility is important, but the mobility in the device is lower than the bulk mobility, making it difficult to predict the mobility based on theoretical characteristics. In addition, a power semiconductor device tends to have a high electric field within the device, and the presence of traps in the oxide film significantly reduces the reliability of the oxide film. Furthermore, there is no established model for the diffusion mechanism when impurities are implanted into devices. The difference in impurity concentration is conspicuous.

The variables corrected in the physical property value calculation model in the previous stage are related to the theoretical properties in the intermediate layer. For example, the intermediate layer creates data by performing many physics simulations and efficiently builds a characteristic regression model by spiral learning using the created data. By modeling the intermediate layer rather than simply simulating it, back propagation from the input in the former stage to the output in the latter stage becomes possible, and learning of the physical property value calculation model becomes possible.

The theoretical properties obtained in the intermediate layer are converted into physical quantities measurable by the physical quantity calculation model (corrector 2) in the latter stage. For example, the corrector 2 performs the following conversions to calculate observable physical quantities.
・Convert the internal temperature of the semiconductor into short-circuit resistance ・Add the offset resistance in the measurement to the on-resistance ・Correct the effect of the contact resistance caused by the measurement to the theoretically derived on-resistance of the semiconductor device ・Especially MIS FET with trench In the case of (Metal-Insulator-Semiconductor FET), the reliability of the gate insulating film is calculated from the electric field intensity applied to the corner of the trench. ・Switching loss and switching time are calculated from the external resistance in the circuit on which the semiconductor device is mounted and the capacitance inside the semiconductor device.・Calculate the short-circuit time from the saturation current characteristics at the time of short-circuit

In particular, the measurable physical quantities preferably include on-resistance, threshold, breakdown voltage, and insulating film reliability as outputs of power semiconductor device characteristics, and include short-circuit resistance and switching loss as characteristics of semiconductor device-mounted circuits. These measurable physical quantities may be derived from the characteristic regression model in the middle, but by deriving them by the corrector 2, a faster regression model can be constructed.

Thus, the corrector 2 can convert a certain physical quantity into an actual physical quantity that is the same physical quantity, and can also derive a different physical quantity from a certain physical quantity. In particular, in a MIS FET structure having an oxide film, the dielectric breakdown strength of SiC is about one order higher than that of Si, so the electric field strength in the oxide film is high, and the reliability of the oxide film is important. On the other hand, there are various indices of the reliability of the oxide film, and they also affect the yield. In addition, negative bias temperature instability (PBTI) and positive bias-temperature. Since there is no accurate theoretical model, derivation by the corrector 2 is required.

The former stage (corrector 1 based on the physical property value calculation model), the middle layer (the characteristic regression model), and the latter stage (the corrector 2 based on the physical quantity calculation model) may all be learning models constructed by learning.

The simulation used in the regression model of the middle layer of the model building unit 102 is related using unobservable parameters, but observable data can be input and output by the corrector 1 at the front stage and the corrector 2 at the rear stage. model can be constructed with high accuracy.

Although FIG. 3 is described as a diagram showing the configuration of the model construction unit 102, the model construction unit 102 and the model constructed by the model construction unit 102 realize the same input/output. When the model constructed by 102 is configured by a neural network, it can also be said to be a diagram showing the configuration of this neural network. In this regard, FIGS. 7 to 10, which will be described later, can also be said to represent the configuration of the model.

FIG. 4 is a diagram showing the calculation method performed by the optimization calculation unit 103. As shown in FIG.

The optimization calculation unit 103 uses the regression model constructed by the model construction unit 102 to set the parameter input in the output section of the input screen as the objective variable, and inputs the parameter to the input section that satisfies the conditions of the objective variable. Performs optimization calculations to find the optimum values of parameters for which values are not specified among the specified parameters. In the optimization calculation, the relationship between the explanatory variable and the objective variable is calculated multiple times from the regression model so that the parameters input in the multiple input sections meet the conditions of the multiple parameters specified in the output section, and the objective variable Find the explanatory variable for which is the optimal value. Through such repeated calculations, it is possible to derive complex conditions for the design, materials, and manufacturing conditions of a semiconductor device and a circuit mounted with a semiconductor device that cannot be conceived by humans.

There are various optimization calculation methods that can be adopted by the optimization calculation unit 103, and there is no need to limit the optimization method in particular in the present invention. Therefore, an example employing Newton's method, which is a general optimization calculation method and will be described later with reference to FIGS. 12A and 12B, will be described.

For example, in FIGS. 12A and 12B, in step 2, an arbitrary objective variable is designated as the minimum value on the input screen (FIG. 2), and the minimum value is calculated by Newton's method. The objective variable and the explanatory variable are related by the regression model created by the model building unit 102. In FIGS. 12A and 12B, the explanatory variable corresponding to the inputs α1, α2, . variable vector), the objective variable corresponding to the output β in FIG. In other words, the regression model can be used to calculate the objective variable y for any explanatory variable x. can derive an explanatory variable x to which is a better fit. When determining the explanatory variable x that minimizes the objective variable y by Newton's method, the tangent line of the function at a certain search point xk is determined for the regression model y = g (x), and the direction in which y decreases is determined from the slope of the tangent line. As the search direction, the value of y at the point xk+1 where the tangent line intersects the x-axis is derived from the regression model y=g(x), and the tangent line of the function at xk+1 is determined to determine the search direction, and the y condition is met. Repeat this until In the example shown in FIG. 4, the point at which the slope of the tangent line changes from positive to negative is the point at which the value of the objective variable y is minimized. Materials, fabrication conditions, and design of circuits mounted on semiconductor devices.

Next, referring to FIG. 5, the manufacturing process of the trench MIS FET will be described.

First, in step A, a SiC bulk substrate (eg, 4H-SiC, 1e18, Si face, 4° off) is prepared. The SiC bulk substrate may be a substrate manufactured using a sublimation method, a substrate using a solution method, a substrate using a gas growth method, or a substrate on which an epitaxial growth layer has already been laminated. Chemical mechanical polishing (CMP) may be performed prior to growth of the epitaxial layers. The substrate concentration may be between 1e18 and 1e21. The crystal type may be 4H—SiC, 6H, or 3C. The plane may be the Si plane, the C plane, or any other plane orientation. Preferably, a substrate having an off angle is used, but a just substrate may be used. For the type, density, surface, off-angle, etc. of the substrate prepared in step A, conditions optimized for semiconductor materials by the design condition calculation system 100 of the present embodiment may be applied.

Next, in step B, an epitaxial growth layer is formed. For example, using H2 as a carrier gas, SiH4 and C3H8 are heated at a temperature of 1500° C. or higher for epitaxial growth to form an epitaxial layer. Although the concentration and film thickness of the epitaxial layer to be formed differ depending on the device to be manufactured, it is preferable that the concentration is about 1e14 to 1e18 and the film thickness is several μm to several tens of μm. Also, a high-concentration buffer layer may be formed before forming the epitaxial layer. The concentration of the buffer layer is preferably about 1e18. Note that the epitaxial layer is also called a drift layer. The growth conditions (temperature, carrier gas, purge gas, other apparatus conditions), concentration, film thickness, etc. of the epitaxial layer and buffer layer are determined by applying the conditions optimized for the semiconductor material by the design condition calculation system 100 of the present embodiment. good too.

Next, in step C, an ion implantation region is formed. Step C is a necessary step in the SiC power semiconductor device described later in Example 5. For example, P-type implanted ions may be aluminum and boron, and N-type implanted ions may be nitrogen and phosphorous. The drift layer includes a P-type body region (p), a potential fixing region (p++) and a guard region (p), an N-type source region (n++), a current diffusion region (n+) and a JFET region (n- to n+ ) are respectively formed by ion implantation. The body region may be formed by P-type epitaxial growth. Note that the polarity may be reversed to P-type or N-type. "-" and "+" are symbols representing the relative impurity concentration of n-type or p-type conductivity, for example, "n--", "n-", "n", "n+", "n++ , the concentration of the n-type impurity increases in the order of .

The source region and potential fixing region are formed in contact with the wafer surface. The body region is in contact with the source region and formed deeper than the source region. Furthermore, the body region is electrically connected to the potential fixing region. The current spreading region is in contact with the body region and is formed at a location deeper than the body region. The guard region is in contact with the current diffusion region and formed at a location deeper than the current diffusion region. Furthermore, the guard region is electrically connected to the potential fixing region. The JFET region is a region sandwiched between guard regions that connects the current diffusion region and the drift region, and ion implantation may be performed to reduce the resistance. In the example shown in FIG. 5, since the minimum configuration for MOS operation is used, a structure that adds functions such as a termination region, for example, may be fabricated.

Mask conditions (type, thickness, fabrication conditions, mask removal conditions, etc.) and implantation conditions (ion species, implantation energy, number of implantation steps, implantation angle, etc.) used for ion implantation are optimized with respect to fabrication conditions in the system of the present invention. Conditions optimized for design and structure by the design condition calculation system 100 of the present embodiment may be applied to the implantation depth, implantation region, impurity concentration, and the like.

Next, in step D, a carbon film as a cap material for impurity activation annealing is deposited around the silicon carbide substrate and the silicon carbide epitaxial layer, and impurity activation annealing is performed at a temperature of 1600 to 1800° C., for example. I do. After that, the carbon layer of the cap material is removed by oxygen plasma ashing. After that, a thermal oxide film may be formed, and the thermal oxide film may be removed using a dilute hydrofluoric acid solution to clean the surface. The type of capping material, annealing temperature, annealing time, conditions for removing the capping material, type, shape, thickness of the thermal oxide film, other formation conditions, removal conditions, etc. are determined by the design condition calculation system 100 of the present embodiment. You may apply the conditions optimized regarding the preparation conditions in .

Next, in step E, trenches are formed. For example, a trench is etched through the source region, the body region, and the current spreading region and bottoms within the guard region.
Thereafter, a thermal oxide film may be formed, and the thermal oxide film may be removed using a dilute hydrofluoric acid solution to clean the etched surface. Mask conditions used for etching (type, thickness, fabrication conditions, mask removal conditions), etching conditions (etching time, etching gas type, applied voltage, etc.), and post-etching treatment (type, shape, thickness of thermal oxide film , other formation conditions, removal conditions, etc.) may apply conditions optimized for fabrication conditions in the design condition calculation system 100 of the present embodiment. For the depth, width, shape, etc. of the trench, conditions optimized for design and structure by the design condition calculation system 100 of this embodiment may be applied.

Next, in step F, a gate insulating film is formed on the semiconductor. For example, the gate insulating film is formed from a SiO2 film by thermal CVD. The thickness of the gate insulating film is, for example, about 0.005 to 0.15 μm. After depositing a gate electrode made of an n-type polycrystalline silicon film with a thickness of about 100 to 300 nm, an interlayer film may be formed to cover the gate electrode. The type of gate insulating film, gate electrode, and interlayer film, manufacturing conditions (manufacturing method, etc.), annealing temperature, annealing time, conditions for cap material removal method, type of thermal oxide film, other formation conditions, removal conditions, etc. Conditions optimized for fabrication conditions by the design condition calculation system 100 of the embodiment may be applied, and the shape, thickness, etc. of the gate insulating film and the thermal oxide film are designed by the design condition calculation system 100 of the present embodiment. and optimized conditions with respect to the structure may be applied.

Next, in step G, various electrodes are formed. For example, in order to make contact with the source region and the potential fixing region, the interlayer film is etched using a resist as a mask, a contact hole is formed, a metal for silicide is deposited, and then annealing is performed at 700° C. to 1000° C. Silicidate to form a source-base common contact. After that, the interlayer film is etched to form a gate contact hole for making contact with the gate electrode.

Furthermore, a source electrode is formed. At the same time, the drain region on the back surface is silicided to form a drain contact and a drain contact electrode. A metal material such as Ni or Al may be used for the silicide metal, the source electrode, and the drain contact electrode. After that, for device protection, the semiconductor device is completed through a step of forming a surface protective film that covers the entire surface made of an insulator and a step of wiring to electrodes.

Interlayer film etching conditions (etching time, etching gas type, applied voltage, etc.), contacts, electrode conditions (metal materials, silicide annealing temperature conditions, etc.), insulating film, wiring fabrication conditions, etc. are calculated using the design condition calculation system of this embodiment. 100 may apply the conditions optimized for the fabrication conditions, and for the electrode and contact regions, ranges, etc., the conditions optimized for design and structure in the design condition calculation system 100 of the present embodiment may be applied. good.

Next, a specific example to which the design condition calculation system 100 of the embodiment described above is applied will be described.

<Example 1>
The design condition calculation system 100 of this embodiment calculates optimum conditions for a trench MIS FET having a structure in which the structure of the channel and the JFET can be independently designed as a power semiconductor device, and an inverter circuit equipped with the trench MIS FET. do.

An example of the input screen of this embodiment will be described with reference to FIGS. 6A and 6B. The semiconductor device optimized in this example is a silicon carbide semiconductor device having a trench MISFET structure. For example, on the input screen, 0 or 1 or more variables that should not be changed in the design, such as trench depth and drift concentration, can be designated as fixed values. On the other hand, variables that are not set as fixed values, such as the design of the JFET regions of the n-type epitaxial layer between the trenches and the channel design corresponding to the width and depth of the trenches, are optimized. In particular, the trench MISFET structure optimized in this example uses the trench as the channel, and the JFET region is formed away from the trench, so that the channel and JFET can be designed independently, which generally poses a problem. A design that avoids the trade-off between on-resistance and short-circuit withstand capability becomes possible. Therefore, in the examples shown in FIGS. 6A and 6B, the values of the objective variables are set so that the on-resistance is minimized and the short-circuit resistance is set to a sufficient time (3 μs) or more for the applied circuit. Conditions such as the types and numbers of variables are not limited to those shown in FIGS. 6A and 6B.

As described above, according to the design condition calculation system 100 of the first embodiment, as shown in the first embodiment, the trench MIS FET structure of the optimized semiconductor device can be optimized and designed, and the short circuit time and the on-resistance can be improved. A design that satisfies both requirements is readily possible.

<Example 2>
The design condition calculation system 100 of the present embodiment calculates optimum conditions for heat and noise, which are unique problems because power semiconductor devices whose materials are not limited to SiC are used for power conversion.

This embodiment optimizes power semiconductor devices made of Si or SiC or other materials. A power semiconductor device is used for power conversion and handles a large amount of power, so heat and noise are important from the viewpoint of safety such as malfunction and operational life. In particular, it is difficult to identify whether the source of noise is a device or a circuit, and identification of the cause depends on engineers' empirical knowledge. Therefore, the present invention is very effective in the design of power semiconductor devices and the design of applications on which power semiconductor devices are mounted.

FIG. 7 is a diagram showing an example of the corrector 1 that constitutes the front stage of the model building unit 102 of this embodiment. The corrector 1 is composed of one or more layers. Although FIG. 7 illustrates a four-layer configuration, other numbers of layers are possible. Among these layers, in this embodiment, one or more layers contain a thermal characteristic regression model created by spiral learning using thermal simulation. For example, if a variable that defines the structure of a module is input to the design and structure of a circuit equipped with a semiconductor device in the input, the variables that define the structure of the module are converted into circuit components such as heat capacity and thermal resistance by layers of the thermal characteristic regression model. converted. In this embodiment, in addition to the parameters shown in FIG. 7, parameters that cause heat and noise and parameters that are affected by heat and noise may be input or output.

<Example 3>
In this embodiment, the corrector 1 is composed of one or more layers, and at least one layer uses a physical formula representing the physical characteristics of a semiconductor to extract a feature amount and an encoder that reduces the dimension. Configured. As a result, correction based on physical formulas becomes possible, and overlearning can be avoided.

FIG. 8 is a diagram showing an example of the corrector 1 that constitutes the front stage of the model building unit 102 of this embodiment. As an example of the input whose dimensionality is reduced by the encoder, application to the design value of the device structure will be explained. In the equation for the drain current of a MOS FET, the channel width W and channel length L may differ from the design values due to mask misalignment in the photolithography process. As for L, the on-resistance of the output and the feature amount W/L are correlated.
I _ds =μ _eff C _ox W/L(V _g −V _th )V _ds

Therefore, by calculating the above equation with an encoder existing in one or more layers of the corrector 1 in the preceding stage, the feature amount W/L is extracted and corrected to obtain a correct output. Such encoders are not limited to physical formulas, and can also be extracted by autoencoders that perform learning by inputting the same values into the input and output, as shown in FIG. Also, like the above, an encoder using a physical formula and an encoder constructed by learning can also be applied to the corrector 2 in the subsequent stage.

<Example 4>
In this embodiment, the actual characteristics of the semiconductor device corrected by the corrector 2 are treated as an intermediate layer.

FIG. 10 is a diagram showing an example of the model building unit 102 of this embodiment.

In Example 4, the intermediate layer is composed of a characteristic regression model, a corrector 2A, and a circuit characteristic model.

The parameters of the semiconductor device and the parameters of the circuit on which the semiconductor device is mounted, which have been input to the input screen, are separately input to the correctors 1A and 1B. The corrector 1A converts parameters representing at least one of the material, manufacturing process, and design of the semiconductor device into unobservable physical property values. As shown in FIG. 3, the characteristic regression model converts unobservable physical property values of the semiconductor device into unobservable theoretical property values, and the corrector 2A converts the unobservable theoretical property values of the semiconductor device. Convert to a measurable physical quantity.

Since the actual characteristics of the semiconductor device corrected by the corrector 2 are treated as an intermediate layer, the device characteristics have no correlation with the material, manufacturing process, design, and structure of the mounted circuit, and are clearly related to the device characteristics. are associated only with variables that are transformed from the input values of . Further, the circuit characteristics are not directly related to the device-related variables, but are related to the characteristics β1, β2, . . . of the mounted semiconductor device. Therefore, the characteristic regression model is mainly created by learning by device simulation, and the circuit characteristic model is mainly created by learning by circuit simulation in which the device characteristic is replaced with an equivalent circuit. , and parameters representing at least one of the designs are converted into theoretical characteristic values of the circuit on which the semiconductor device is mounted. The circuit characteristic model may correlate output values of the characteristic regression model with observables of semiconductor device characteristics. For example, when the on-resistance is considered as an observable quantity of the characteristics of the semiconductor device, the characteristics of the semiconductor device obtained by converting the values input as the design and structural conditions of the circuit on which the semiconductor device is mounted are converted by the corrector 1 into the on-resistance and the , the resistance caused by the module structure and the resistance of the circuit are converted into the characteristics of the circuit on which the semiconductor device is mounted by the corrector 2B, and converted into the measured values of the circuit on which the semiconductor device is mounted by the circuit characteristic model.

The corrector 2B converts the theoretical characteristic values of the circuit on which the semiconductor device is mounted into observable characteristic values of the circuit.

In this way, a model that is easier to learn and avoids over-learning can be created by making inferences by considering only some correlations without considering correlations that are not directly correlated in advance.

<Example 5>
In this embodiment, a method for manufacturing a SiC power semiconductor device and a circuit mounted with the SiC power semiconductor device will be described. As described above for the trench MIS FET manufacturing process with reference to FIG. to manufacture a semiconductor device.

The input values on the input screen can be optimized by inputting process conditions such as the etching time and voltage for forming trenches, the type of oxide film, and the pressure during oxide film formation. Also, if the corrector 1 of the model construction unit 102 created by learning is installed in a semiconductor manufacturing apparatus, for example, the amount of displacement of the mask in the photolithography process and the manufacturing conditions such as the conditions of the oxide film manufacturing process can be used to adjust the mobility and the like. Physical property values can be calculated, and learning results of the corrector 1 can be fed back to a manufacturing apparatus that manufactures semiconductor devices.

As described above, if the design condition calculation system 100 of the present embodiment is used, as shown in FIG. manufacturing becomes possible.

<Example 6>
In Examples 1 to 5 described above, the model building unit 102 builds a regression model in advance based on a pre-learned learning model. On the other hand, in this embodiment, even if the regression model constructed by pre-learning does not have sufficient accuracy, the result of the optimization calculation is fed back, the regression model is reconstructed, and the accuracy of the regression model is improved. , repeat the optimization calculation.

12A and 12B are flow charts of processing for calculating design conditions by the design condition calculation system 100 of this embodiment.

In this embodiment, after the optimization calculation is completed, if the determined target variable does not satisfy a certain standard, the physical simulation around the optimization design is redone, and the intermediate layer characteristic regression model of the model construction unit 102 By feeding back and learning again, a more accurate regression model is constructed and optimization calculations are performed. In the example shown in FIGS. 12A and 12B, optimization is performed so that the difference between the objective variable βi and the target value ans, which is the condition of the objective variable input to the input screen, is smaller than a predetermined threshold ε. That is, in step 8, it is determined whether the difference between the objective variable βi and the target value ans is greater than a predetermined threshold value ε. The optimized input value is fed back to the model construction unit 102, the feedback input value is converted by the corrector 1 at the front stage of the model construction unit 102, and the physical property value near the converted physical property value is converted into the feedback input value. A simulation is performed, and the physical property values and the theoretical property values obtained by the physical simulation are fed back to the property regression model of the model construction unit 102 to construct a new property regression model. After that, the optimization calculation is performed again using the new characteristic regression model. The result of the optimization calculation is determined again in step 8, and if the difference between the objective variable βi and the target value ans is greater than the predetermined threshold value ε, the recalculation process is repeated. If the difference between the calculated objective variable βi and the target value ans is smaller than a predetermined threshold value ε, the iterative process is terminated and the optimal calculation result is displayed.

As in the sequence diagram shown in FIG. 12B, the optimization calculation, the physical simulation, and the model construction may be repeated the same number of times. Multiple extractions may be performed. For example, if the number or time of optimization calculation is specified in advance, and no explanatory variable that can derive the objective variable βi whose difference from the target value ans is smaller than ε within the range of the number of times or time, the model is rebuilt. do it. Also in the case of this embodiment, as in the first embodiment, the number of times data is stored in the data storage unit 104 is not limited to the above. may be performed outside the design condition calculation system 100 (for example, in the cloud).

Due to the feedback of the optimization calculation to the model building described above, in the pre-learned intermediate layer characteristic regression model of the model building unit 102, the number of pre-learned simulation data is small and the precision of the characteristic regression model is low. However, because feedback adds simulation data in a range close to the desired design, the accuracy of the regression model is improved in a range close to the optimization calculation results, and the calculation accuracy of the explanatory variables that derive the desired target variable is also improved. can. In FIG. 12A, the condition for the repeated calculation is that the difference between the objective variable βi and the target value ans is smaller than the predetermined threshold value ε. A value and a range of values can be specified.

As described above, the design condition calculation system 100 of the embodiment of the present invention includes an arithmetic unit (calculation unit 101) that executes predetermined processing, an input unit (input/output unit 108) to which data is input, a storage device (data storage unit 104) accessible by the arithmetic device, wherein the input unit includes a first parameter representing at least one of a material, a manufacturing process, and a design of the semiconductor device; Receiving input of a second parameter representing at least one of the material, manufacturing process, and design of a circuit to be mounted, and a third parameter representing at least one characteristic of the semiconductor device and the circuit on which the semiconductor device is mounted , the design condition calculation system 100 is an optimization calculation unit that calculates the first parameter and the second parameter so that the arithmetic device satisfies a predetermined condition using the model constructed by the model construction unit. 103, and the model constructed by the model construction unit 102 includes a first conversion model (corrector 1, which is a physical property value calculation model) provided in the front stage, and a second conversion model (physical quantity calculation model) provided in the rear stage. and a characteristic regression model provided between the first transformation model and the second transformation model, wherein the first parameter and the second parameter are input, and the second Each parameter is related by outputting 3 parameters, and the first conversion model converts at least one of the first parameter and the second parameter to the physical property value input to the characteristic regression model , wherein the characteristic regression model converts unobservable physical property values into unobservable theoretical property values, and the second conversion model converts the theoretical property values into actual property values and performs optimization calculation Unit 103 uses the constructed model to constrain a fixed value set for part of the first parameter and the second parameter, one of the value and range of the third parameter or The first parameter and the second parameter, which are not the constraint condition, are calculated so as to satisfy the combined condition, and the calculated first parameter and the second parameter are output. It is possible to quickly and inexpensively provide an optimized design that satisfies a large number of characteristics in power devices. In addition, while the simulation used in the characteristic regression model can only calculate the relationship of unobservable parameters, the former corrector 1 and the latter corrector 2 can construct a model of observable data with high accuracy. In addition, by creating a model, it is possible to predict characteristics with high accuracy without performing time-consuming simulations each time.

It should be noted that the present invention is not limited to the embodiments described above, but includes various modifications and equivalent configurations within the scope of the appended claims. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and the present invention is not necessarily limited to those having all the described configurations. Also, part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Moreover, the configuration of another embodiment may be added to the configuration of one embodiment. Further, additions, deletions, and replacements of other configurations may be made for a part of the configuration of each embodiment.

In addition, each configuration, function, processing unit, processing means, etc. described above may be realized by hardware, for example, by designing a part or all of them with an integrated circuit, and the processor realizes each function. It may be realized by software by interpreting and executing a program to execute.

Information such as programs, tables, and files that implement each function can be stored in storage devices such as memories, hard disks, SSDs (Solid State Drives), or recording media such as IC cards, SD cards, and DVDs.

In addition, the control lines and information lines indicate those considered necessary for explanation, and do not necessarily indicate all the control lines and information lines necessary for mounting. In practice, it can be considered that almost all configurations are interconnected.

100 design condition calculation system 101 calculation unit 102 model construction unit 103 optimization calculation unit 104 data storage unit 105 communication section 106 operation section 107 output section 108 input/output unit

Claims (13)

A design condition calculation system,
A computing device that executes a predetermined process, an input unit for inputting data, and a storage device that can be accessed by the computing device,
The input section includes a first parameter representing at least one of material, manufacturing process, and design of a semiconductor device, and a second parameter representing at least one of material, manufacturing process, and design of a circuit on which the semiconductor device is mounted. and a third parameter representing at least one characteristic of the semiconductor device and a circuit on which the semiconductor device is mounted;
The design condition calculation system includes an optimization calculation unit in which the calculation device calculates the first parameter and the second parameter so as to satisfy a predetermined condition using the model constructed by the model construction unit. have
The model constructed by the model construction unit is
A first conversion model provided in the preceding stage, a second conversion model provided in the subsequent stage, and a characteristic regression model provided between the first conversion model and the second conversion model,
relating each parameter by taking the first parameter and the second parameter as inputs and the third parameter as an output;
The first conversion model converts at least one of the first parameter and the second parameter into a physical property value input to the characteristic regression model,
The characteristic regression model converts unobservable physical property values into unobservable theoretical property values,
The second conversion model converts theoretical characteristic values into actual characteristic values,
The optimization computation unit comprises:
Using the constructed model, with a fixed value set for part of the first parameter and the second parameter as a constraint condition, one or a combination of the value and range of the third parameter Calculate the first parameter and the second parameter that are not the constraint so as to satisfy
A design condition calculation system that outputs the calculated first parameter and second parameter. The design condition calculation system according to claim 1,
The optimization calculation unit calculates the first parameter and the second parameter that are not the constraint conditions using a regression model created by the model construction unit provided outside the design condition calculation system. A design condition calculation system characterized by The design condition calculation system according to claim 1,
The design condition calculation system, wherein the first parameter includes at least one of mobility, effective impurity concentration, interface level, and trap density in an oxide film, which are physical property values of the semiconductor device. The design condition calculation system according to claim 1,
The third parameter includes at least one of on-resistance, short-circuit resistance, threshold voltage, frequency band, withstand voltage, switching loss, and insulating film reliability, which are characteristics related to the power semiconductor device or the circuit mounted with the power semiconductor device. A design condition calculation system characterized by The design condition calculation system according to claim 4,
The third parameter includes on-resistance and short-circuit capability,
In a silicon carbide semiconductor device in which the structure of a JFET region and the structure of a channel region can be designed independently, the optimization calculation unit includes the first parameter and the A design condition calculation system, characterized by calculating a second parameter. The design condition calculation system according to claim 1,
The first transformation model includes one or more layers,
The design condition calculation system, wherein one or more of the layers included in the first conversion model are thermal characteristic regression models learned by thermal simulation. The design condition calculation system according to claim 1,
The first transformation model includes one or more layers,
At least one of the layers included in the first transformation model is an encoder that extracts at least a part of the feature amount of the first input parameter and the second input parameter to reduce the dimensionality of the input parameter. A design condition calculation system characterized by: The design condition calculation system according to claim 7,
The design condition calculation system, wherein the encoder extracts a feature quantity using a physical formula representing physical characteristics of a semiconductor. The design condition calculation system according to claim 7,
The design condition calculation system, wherein the encoder is an autoencoder that learns using the same input value and output value. The design condition calculation system according to claim 1,
the preceding stage of the model building unit includes the first transformation model and the third transformation model;
the intermediate layer of the model building unit includes the characteristic regression model, the second transformation model and the circuit characteristic model;
The latter stage of the model building unit includes a fourth transformation model,
the first conversion model converts the first input parameter into an unobservable physical property value of the semiconductor device input to the characteristic regression model;
The regression model converts unobservable physical property values of the semiconductor device into unobservable theoretical property values,
The second conversion model converts unobservable theoretical characteristic values of the semiconductor device into actual characteristic values,
The circuit characteristic model converts the actual characteristic value of the semiconductor device output by the second conversion model and the second parameter into a theoretical characteristic value of the circuit mounted with the semiconductor device,
the third conversion model converts the second input parameter into an unobservable physical property value of the semiconductor device-mounted circuit input to the circuit characteristic model;
The design condition calculation system, wherein the fourth conversion model converts the theoretical characteristic values of the semiconductor device-mounted circuit output by the circuit characteristic model into actual characteristic values. The design condition calculation system according to claim 1,
The first conversion model is mounted on a semiconductor manufacturing device connected to the design condition calculation system,
The design condition calculation system, wherein the semiconductor manufacturing equipment calculates the processing conditions using the first conversion model. The design condition calculation system according to claim 1,
The computing device is
After calculating the first parameter and the second parameter that are not the constraint,
comparing the third parameter with a target value;
A design characterized by feeding back the input value and output value of the optimization calculation unit to learn and reconstruct the regression model when the third parameter does not satisfy a predetermined condition for the target value. Condition calculation system. A manufacturing method for manufacturing a semiconductor device under a condition of a first parameter output by a design condition calculation system, comprising:
The design condition calculation system is composed of a computer having an arithmetic device that executes a predetermined process, an input unit for inputting data, and a storage device that can be accessed by the arithmetic device,
The input section includes a first parameter representing at least one of material, manufacturing process, and design of a semiconductor device, and a second parameter representing at least one of material, manufacturing process, and design of a circuit on which the semiconductor device is mounted. and a third parameter representing at least one characteristic of the semiconductor device and a circuit on which the semiconductor device is mounted;
The design condition calculation system includes an optimization calculation unit in which the calculation device calculates the first parameter and the second parameter so as to satisfy a predetermined condition using the model constructed by the model construction unit. have
The regression model constructed by the model construction unit is
A first conversion model provided in the preceding stage, a second conversion model provided in the subsequent stage, and a characteristic regression model provided between the first conversion model and the second conversion model,
relating each parameter by taking the first parameter and the second parameter as inputs and the third parameter as an output;
The first conversion model converts at least one of the first parameter and the second parameter into a physical property value input to the characteristic regression model,
The regression model converts unobservable physical property values into unobservable theoretical property values,
The second conversion model converts theoretical characteristic values into actual characteristic values,
The optimization computation unit comprises:
Using the constructed model, with a fixed value set for part of the first parameter and the second parameter as a constraint condition, one or a combination of the value and range of the third parameter Calculate the first parameter and the second parameter that are not the constraint so as to satisfy
A method of manufacturing a semiconductor device, wherein the calculated first parameter and second parameter are output.

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