JP2023080296A - Photoelectric conversion device and imaging system - Google Patents

Abstract

To provide a photoelectric conversion device capable of implementing reduction in power consumption and improvement of stability of circuit operation.SOLUTION: A photoelectric conversion device includes: an avalanche amplification type photo diode; a signal generating unit that includes a control unit for controlling application voltage to the photo diode and generates photon detection pulses based on output generated by incidence of photons on the photo diode; and a counter for counting the photon detection pulses output from the signal generating unit. The counter outputs a set value detection signal when a counted value of the photon detection pulses reaches a predetermined set value. The control unit controls the application voltage to the photo diode so as to stop generation of avalanche current at the photo diode, when receiving the set value detection signal.SELECTED DRAWING: Figure 7

Description

The present invention relates to a photoelectric conversion device and an imaging system.

2. Description of the Related Art A photon counting type photoelectric conversion device is known that digitally counts the number of photons incident on a light receiving portion and outputs the counted value as a digital signal from a pixel. Japanese Unexamined Patent Application Publication No. 2002-200002 describes an imaging device in which a plurality of pixels for outputting a count value of photons as a digital signal are arranged.

U.S. Patent Application Publication No. 2011/0266420

In a photon counting type photoelectric conversion device, the number of circuit operations required to detect photons increases as the number of photons incident on the light receiving portion increases. On the other hand, the number of photons that can be counted is limited to the upper count limit of the mounted counter. Therefore, in a pixel that reaches the count upper limit value before the end of a predetermined exposure period, an operation is performed to detect photons that are not counted until the end of the exposure period, and power is wasted. be consumed. Further, when the frequency of the photon detection operation increases, the current flowing through the power supply wiring increases, causing a power supply voltage drop according to the wiring resistance, which may destabilize the circuit operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a photoelectric conversion device and an imaging system that can reduce power consumption and improve the stability of circuit operation.

According to one aspect of the present invention, an avalanche amplification type photodiode and a signal generator connected to one terminal of a cathode terminal and an anode terminal of the photodiode, wherein the one terminal of the photodiode a signal generation unit that has a control unit that controls voltage applied to a terminal and generates a photon detection pulse based on an output generated by incident photons on the photodiode; and the photon detection that is output from the signal generation unit. a counter that counts pulses, the counter and the control unit are connected, and the counter outputs a set value detection signal when the count value of the photon detection pulses reaches a predetermined set value. to the control unit.
According to another aspect of the present invention, an avalanche amplification type photodiode and a control unit for controlling a voltage applied to the photodiode are provided, and the output generated by the incidence of photons on the photodiode is and a counter for counting the photon detection pulses output from the signal generation unit, wherein the control unit is provided between a power supply node and the photodiode and a switch connected in series with the switch and provided between the power supply node and the photodiode, and controlled according to a change in voltage of the terminal of the photodiode due to incidence of photons on the photodiode. and a MOS transistor, wherein the counter and the control unit are connected, and the counter outputs a set value detection signal when the count value of the photon detection pulses reaches a predetermined set value. provided is a photoelectric conversion device that outputs the signal to a control unit, and the control unit turns off the switch to stop supplying the applied voltage from the power supply node to the photodiode when the set value detection signal is received by the control unit. be done.

According to the present invention, reduction in power consumption and improvement in stability of circuit operation in a photoelectric conversion device can be realized.

1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention; FIG. 1 is a diagram illustrating a schematic configuration of a pixel in a photoelectric conversion device according to a first embodiment of the invention; FIG. 3 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to the first embodiment of the invention; FIG. FIG. 5 is a circuit diagram showing a configuration example of a pixel in a photoelectric conversion device according to a second embodiment of the invention; FIG. 10 is a circuit diagram showing a configuration example of a pixel in a photoelectric conversion device according to a third embodiment of the invention; It is a timing chart showing the operation of the photoelectric conversion device according to the third embodiment of the present invention. 9 is a flow chart showing a method for driving a photoelectric conversion device according to a third embodiment of the present invention; It is a figure explaining the schematic structure of the pixel in the photoelectric conversion apparatus by 4th Embodiment of this invention. FIG. 11 is a circuit diagram showing a configuration example of a pixel in a photoelectric conversion device according to a fourth embodiment of the present invention; It is a timing chart showing the operation of the photoelectric conversion device according to the fourth embodiment of the present invention. FIG. 10 is a diagram illustrating a schematic configuration of pixels in a photoelectric conversion device according to a fifth embodiment of the present invention; FIG. 11 is a circuit diagram showing a configuration example of a pixel in a photoelectric conversion device according to a fifth embodiment of the present invention; FIG. 11 is a block diagram showing a schematic configuration of an imaging system according to a sixth embodiment of the present invention; FIG. FIG. 21 is a diagram showing a configuration example of an imaging system and a moving body according to a seventh embodiment of the present invention;

[First embodiment]
A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. FIG. 2 is a block diagram showing a schematic configuration of a pixel of the photoelectric conversion device according to this embodiment. FIG. 3 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment.

As shown in FIG. 1, the photoelectric conversion device 100 according to the present embodiment includes a pixel region 10, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output circuit 60, a control circuit 70, including.

The pixel region 10 is provided with a plurality of pixels P arranged in a matrix over a plurality of rows and columns. FIG. 1 shows 36 pixels P arranged in 6 rows from the 0th row to the 5th row and 6 columns from the 0th column to the 5th column together with symbols indicating row numbers and column numbers. ing. For example, the pixel P arranged in the 1st row and the 4th column is denoted by "P14".

The number of rows and the number of columns of the pixel array forming the pixel region 10 are not particularly limited. Further, the pixels P are not necessarily arranged two-dimensionally in the pixel region 10 . For example, the pixel region 10 may be composed of one pixel P, or the pixels P may be arranged one-dimensionally in the row direction or the column direction in the pixel region 10 .

Each row of the pixel array of the pixel region 10 is provided with a control line PVSEL extending in the first direction (horizontal direction in FIG. 1). The control line PVSEL is connected to the pixels P arranged in the first direction and forms a common signal line for these pixels P. As shown in FIG. The first direction in which the control line PVSEL extends is sometimes referred to as the row direction or the horizontal direction. It should be noted that FIG. 1 shows the control line PVSEL together with the code indicating the row number. For example, the control line in the first row is labeled "PVSEL[1]".

A control line PVSEL of each row is connected to the vertical selection circuit 30 . The vertical selection circuit 30 is a circuit unit that supplies a control signal for driving a signal generation circuit (not shown) in the pixel P to the pixel P via the control line PVSEL.

Each column of the pixel array in the pixel region 10 is provided with an output line POUT extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The output line POUT is connected to the pixels P arranged in the second direction and forms a signal line common to these pixels P. As shown in FIG. The second direction in which the output lines POUT extend is sometimes referred to as the column direction or the vertical direction. Note that FIG. 1 shows the output lines POUT together with the symbols indicating the column numbers. For example, the output line of the fourth column is labeled "POUT4". Each of the output lines POUT has n signal lines for outputting an n-bit digital signal.

The output line POUT is connected to the signal processing circuit 40 . The signal processing circuit 40 is provided corresponding to each column of the pixel array in the pixel region 10 and connected to the output line POUT of the corresponding column. The signal processing circuit 40 has a function of holding a signal output from the pixel P via the output line POUT of the corresponding column. Since the signal output from the pixel P is an n-bit signal input via n signal lines of the output line POUT, each of the signal processing circuits 40 holds at least n signals of each bit. holding portion.

The horizontal selection circuit 50 is a circuit unit that supplies the signal processing circuit 40 with a control signal for reading a signal from the signal processing circuit 40 . The horizontal selection circuit 50 supplies a control signal to the signal processing circuit 40 of each column through the control line PHSEL. The signal processing circuit 40 that has received the control signal from the horizontal selection circuit 50 outputs the signal held in the holding unit to the output circuit 60 via the horizontal output line HSIG. In addition, FIG. 1 shows the control line PHSEL together with the code indicating the column number. For example, the control line in the fourth column is labeled "PHSEL[4]". The horizontal output line HSIG has n signal lines for outputting an n-bit digital signal.

The output circuit 60 is a circuit unit for outputting the signal supplied via the horizontal output line HSIG to the outside of the photoelectric conversion device 100 as the output signal SOUT. The control circuit 70 is a circuit section for supplying control signals for controlling the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60. FIG. At least part of the control signals for controlling the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60 may be supplied from outside the photoelectric conversion device 100. FIG.

Each pixel P has an avalanche amplification type photodiode PD, a signal generation circuit 12, and a counter 28, as shown in FIG. The signal generation circuit 12 has a cathode voltage control circuit 14 and a control circuit 16 . In this specification, the signal generation circuit 12 may be referred to as a signal generation section, and the cathode voltage control circuit 14 may be referred to as a cathode voltage control section.

The anode terminal of the photodiode PD is connected to the power supply node of voltage Va. Voltage Va is typically a negative high voltage. A cathode terminal of the photodiode PD is connected to the cathode voltage control circuit 14 . Cathode voltage control circuit 14 is connected to control circuit 16 . Control circuit 16 is connected to counter 28 .

The photodiode PD receives incident photons and generates an avalanche current when a reverse bias voltage applied between the anode terminal and the cathode terminal is equal to or higher than the breakdown voltage Vbd. Due to the avalanche current flowing through the photodiode PD, the voltage of the cathode terminal of the photodiode PD changes. A change in the voltage of the cathode terminal is transmitted to the control circuit 16 via the cathode voltage control circuit 14, and a photon detection pulse is output from the control circuit 16 to the counter 28. FIG. The signal generation circuit 12 has a function of controlling the voltage applied to the photodiode PD and generating a photon detection pulse based on the output generated by the incidence of photons on the photodiode.

The counter 28 counts photon detection pulses input from the control circuit 16 . When the count value of photon detection pulses reaches an arbitrary set value N, the counter 28 outputs a set value detection signal to the control circuit 16 . The set value N is not particularly limited, but can be set to the count upper limit value of the counter 28, for example. In addition, the counter 28 outputs the held count value as an n-bit digital signal to the output line POUT according to the control signal from the vertical selection circuit 30 .

The control circuit 16 has a function of controlling the cathode voltage control circuit 14 according to the set value detection signal received from the counter 28 . That is, the control circuit 16 controls the cathode voltage control circuit 14 in response to receiving the set value detection signal from the counter 28, and breaks down the reverse bias voltage applied between the anode terminal and the cathode terminal of the photodiode PD. Reduce the voltage to less than the voltage Vbd. That is, the cathode voltage control circuit 14 functions as a control section that controls the voltage applied to the photodiode PD, more specifically, the voltage applied to the cathode terminal of the photodiode PD. As a result, the photodiode PD enters a state in which no avalanche current is generated even when photons are incident.

FIG. 3 shows a schematic diagram of the pixel P including specific configuration examples of the cathode voltage control circuit 14 and the control circuit 16. As shown in FIG. As shown in FIG. 3, the cathode voltage control circuit 14 can be composed of a P-type MOS transistor MP1. Also, the control circuit 16 can be configured by an inverter circuit INV and a buffer circuit 18 .

The input terminal of the inverter circuit INV is connected to the cathode terminal of the photodiode PD. An output terminal of the inverter circuit INV is connected to the counter 28 . An input terminal of the buffer circuit 18 is connected to the counter 28 . The output terminal of the buffer circuit 18 is connected to the gate terminal of the P-type MOS transistor MP1. The source terminal of the P-type MOS transistor MP1 is connected to the power supply node of the voltage Vdd. A drain terminal of the P-type MOS transistor MP1 is connected to a connection node between the cathode terminal of the photodiode PD and the input terminal of the inverter circuit INV.

The inverter circuit INV constitutes a waveform shaping section that converts a voltage change at the cathode terminal of the photodiode PD into a pulse signal and outputs a photon detection pulse Pp. Buffer circuit 18 outputs voltage Vdd when set value detection signal Pctl output from counter 28 is at High level (H level), and outputs voltage Vqnc when set value detection signal Pctl is at Low level (L level). Output. Voltage Vqnc is a voltage applied to buffer circuit 18 as a reference voltage on the L level side, and is lower than voltage Vdd. Voltage Vqnc is appropriately set so that P-type MOS transistor MP1 functions as a desired quenching resistor when applied to the gate of P-type MOS transistor MP1.

Thus, the cathode voltage control circuit 14 is configured to connect the drain terminal of the P-type MOS transistor MP1 to the cathode terminal of the photodiode PD. Since the gate voltage of the P-type MOS transistor MP1 during operation is a fixed voltage, the quench circuit composed of the P-type MOS transistor MP1 is of the passive type (passive type), that is, of the passive recharge/passive quench type.

Here, recharging is an operation of increasing the reverse bias voltage of the photodiode PD to the breakdown voltage Vbd or higher to enable avalanche amplification. Quenching is an operation to reduce the reverse bias voltage of the photodiode PD to less than the breakdown voltage Vbd so that avalanche amplification does not occur.

In the initial state where the count value is reset to 0, set value detection signal Pctl output from counter 28 is at L level. Therefore, the voltage Vqnc is applied to the gate of the P-type MOS transistor MP1 of the cathode voltage control circuit 14, and the P-type MOS transistor MP1 is turned on.

As a result, the cathode terminal of the photodiode PD is charged up to the voltage Vdd through the P-type MOS transistor MP1. The magnitude of the reverse bias voltage applied between both terminals of the photodiode PD at this time is expressed as follows. Here, the voltage Vex (excess bias) indicates a voltage value exceeding the breakdown voltage Vbd among the reverse bias voltage values applied to the photodiode PD.
|Va−Vdd|=Vbd+Vex

When a photon is incident on the photodiode PD in this state, an avalanche current is generated in the photodiode PD, and the voltage of the cathode terminal of the photodiode PD drops to (Vdd-Vex). After that, the cathode terminal of the photodiode PD is charged to the voltage Vdd again through the P-type MOS transistor MP1. By waveform-shaping the voltage change of the cathode terminal by the inverter circuit INV of the control circuit 16, the photon detection pulse Pp is generated.

The counter 28 counts photon detection pulses Pp input from the control circuit 16 . That is, the counter 28 increments the count value by one each time it receives one photon detection pulse Pp. When the count value reaches an arbitrary set value N, the counter 28 changes the set value detection signal Pctl from L level to H level.

When the set value detection signal Pctl becomes H level, the output of the buffer circuit 18 of the control circuit 16 becomes the voltage Vdd, and the P-type MOS transistor MP1 of the cathode voltage control circuit 14 is turned off.

As a result, after the count value reaches the set value N, even if a photon is incident on the photodiode PD and an avalanche current flows, the cathode terminal is not charged thereafter, and the voltage applied between both terminals of the photodiode PD is It becomes less than the breakdown voltage Vbd. At this time, the off resistance of the P-type MOS transistor MP1 is sufficiently large, and the voltage applied between both terminals of the photodiode PD can be kept below the breakdown voltage Vbd at least until the operation of resetting the count value.

If the voltage applied between both terminals of the photodiode PD is less than the breakdown voltage Vbd, no avalanche current is generated even if a photon is incident on the photodiode PD. Circuit operation stops. Therefore, power consumption can be reduced until the count value is reset. In addition, since the current consumption can be reduced, the power supply voltage drop due to the wiring resistance of the power supply wiring for supplying the voltage Vdd and the voltage Va can be reduced, and the stability of the circuit operation can be improved.

As described above, according to the present embodiment, it is possible to reduce the power consumption and improve the stability of the circuit operation in the photoelectric conversion device.

[Second embodiment]
A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to FIG. The same reference numerals are given to the same components as in the photoelectric conversion device according to the first embodiment, and the description is omitted or simplified. FIG. 4 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment.

The photoelectric conversion device according to this embodiment is the same as the photoelectric conversion device according to the first embodiment, except that the configuration of the control circuit 16 is different. That is, the control circuit 16 of the photoelectric conversion device according to the present embodiment can be composed of inverter circuits INV1, INV2, and INV3 and an OR gate circuit G1, as shown in FIG. 4, for example.

An input terminal of the inverter circuit INV1 is connected to a connection node between the cathode terminal of the photodiode PD and the drain terminal of the P-type MOS transistor MP1. The output terminal of the inverter circuit INV1 is connected to the input terminal of the inverter circuit INV2. The output terminal of the inverter circuit INV2 is connected to the input terminal of the inverter circuit INV3. An output terminal of the inverter circuit INV3 is connected to the counter circuit . Two input terminals of the OR gate circuit G1 are connected to a connection node between the inverter circuits INV2 and INV3 and to the counter circuit 28 . The output terminal of the OR gate circuit G1 is connected to the gate of the P-type MOS transistor MP1.

The inverter circuits INV1, INV2, and INV3 constitute a waveform shaping section that converts the voltage change at the cathode terminal of the photodiode PD into a pulse signal and outputs the photon detection pulse Pp. The OR gate circuit G1 outputs the voltage Vqnc when both the set value detection signal Pctl output from the counter 28 and the output signal of the inverter circuit INV2 are at L level, and outputs the voltage Vdd otherwise. Voltage Vqnc is a voltage applied to OR gate circuit G1 as a reference voltage on the L level side, and is a voltage lower than voltage Vdd. Voltage Vqnc is appropriately set so that P-type MOS transistor MP1 functions as a desired quenching resistor when applied to the gate of P-type MOS transistor MP1.

The control circuit 16 of this embodiment is configured so that the gate voltage of the P-type MOS transistor MP1 of the cathode voltage control circuit 14 can be actively controlled according to the change in the voltage of the cathode terminal. That is, the circuit of this embodiment is of the active recharge/passive quench type. In the present embodiment, by lowering the on-resistance of the P-type MOS transistor MP1 of the cathode voltage control circuit 14 than in the first embodiment, it is possible to actively expedite recharging.

Also in this embodiment, when the count value of the counter 28 reaches an arbitrary set value N, the set value detection signal Pctl becomes H level and the cathode terminal of the photodiode PD is no longer charged. As a result, the voltage applied across the photodiode PD becomes less than the breakdown voltage Vbd, and the circuit operation can be kept stopped even when photons are incident.

As described above, according to the present embodiment, it is possible to reduce the power consumption and improve the stability of the circuit operation in the photoelectric conversion device.

[Third embodiment]
A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to FIGS. 5 to 7. FIG. Components similar to those of the photoelectric conversion devices according to the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 5 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment. FIG. 6 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment. FIG. 7 is a flow chart showing a method for driving the photoelectric conversion device according to this embodiment.

The photoelectric conversion device according to this embodiment differs from the photoelectric conversion devices according to the first and second embodiments in the configurations of the cathode voltage control circuit 14 and the control circuit 16 . Other points are the same as the photoelectric conversion devices according to the first and second embodiments.

That is, the cathode voltage control circuit 14 in the photoelectric conversion device according to this embodiment can be composed of a P-type MOS transistor MP1 and an N-type MOS transistor MN1, as shown in FIG. 5, for example. The cathode terminal of the photodiode PD is connected to the drain terminal of the P-type MOS transistor MP1 and the drain terminal of the N-type MOS transistor MN1. The source terminal of the P-type MOS transistor MP1 is connected to the power supply node of the voltage Vdd. A source terminal of the N-type MOS transistor MN1 is connected to a reference voltage node of voltage Vss.

Also, the control circuit 16 in the photoelectric conversion device according to the present embodiment can be composed of timing control circuits 20 and 22, OR gate circuits G1 and G3, and an AND gate circuit G2, as shown in FIG. 5, for example. A connection node of the cathode terminal of the photodiode PD, the drain terminal of the P-type MOS transistor MP1 and the drain terminal of the N-type MOS transistor MN1 is connected to the counter 28 via the timing control circuits 20 and 22 . Two input terminals of the OR gate circuit G1 are connected to the timing control circuit 22 and the counter . The output terminal of the OR gate circuit G1 is connected to the gate of the P-type MOS transistor MP1. Two input terminals of the AND gate circuit G2 are connected to the timing control circuit 20 and the timing control circuit 22, respectively. Two input terminals of the OR gate circuit G3 are connected to the output terminal of the AND gate circuit G2 and the counter . The output terminal of the OR gate circuit G3 is connected to the gate of the N-type MOS transistor MN1.

The timing control circuits 20 and 22 are circuits for controlling the timing of the recharge operation and the quench operation in the cathode voltage control circuit 14 according to changes in the voltage Vc of the cathode terminal of the photodiode PD. For example, the timing control circuits 20 and 22 can be composed of a delay circuit formed by connecting a plurality of stages of inverter circuits in series, or a delay circuit using resistance values and capacitance values of various devices. The timing control circuits 20 and 22 as a whole also function as a waveform shaping section that converts changes in the voltage Vc of the cathode terminal of the photodiode PD into a pulse signal and outputs the photon detection pulse Pp. In this specification, the timing control circuits 20 and 22 may be referred to as timing control units.

The OR gate circuit G1 performs a logical sum operation of the control signal Pr' output from the timing control circuit 22 and the set value detection signal Pctl, and supplies the recharge control signal Pr, which is the operation result, to the gate terminal of the P-type MOS transistor MP1. supply. As a result, the P-type MOS transistor MP1 constitutes a recharge circuit.

The AND gate circuit G2 performs a logical product operation of the control signal Pq' output from the timing control circuit 22 and the control signal Pr' output from the timing control circuit 20. FIG. The OR gate circuit G3 performs a logical sum operation of the set value detection signal Pctl and the output signal of the AND gate circuit G2, and supplies the quench control signal Pq, which is the operation result, to the gate terminal of the N-type MOS transistor MN1. Thus, the N-type MOS transistor MN1 constitutes a quench circuit.

Next, an operation example of the photoelectric conversion device according to this embodiment will be described with reference to FIG. FIG. 6 shows voltage Vc, recharge control signal Pr, quench control signal Pq, photon detection pulse Pp, set value detection signal Pctl, photon incidence timing, count value, count value reset, and count value readout timing. there is The photon incidence timing indicates the timing at which photons enter the photodiode PD. A count value indicates the count value of the counter 28 . A count value reset indicates the timing of resetting the count value of the counter 28 . The count value reading indicates the timing of outputting the count value of the counter 28 to the outside.

Here, it is assumed that the timing control circuit 20 outputs a signal obtained by converting a change in the voltage Vc of the cathode terminal of the photodiode PD into a pulse signal as a control signal Pq' whose logic is inverted after a predetermined delay time. . It is also assumed that the timing control circuit 22 outputs the control signal Pq' after a predetermined delay time as the control signal Pr' whose logic is inverted.

First, at time t1, the count value reset signal becomes H level, and the count value of the counter 28 is reset to zero.

When a photon is incident on the photodiode PD, an avalanche current is generated in the photodiode PD, and the voltage Vc of the cathode terminal of the photodiode PD drops. When the voltage Vc of the cathode terminal begins to drop, the control signal Pq' output from the timing control circuit 20 in response to the change in the voltage Vc becomes H level after a predetermined delay time. At this time, since the control signal Pr' output from the timing control circuit 22 is at H level in the initial state, the control signals Pq' and Pr' of H level are received and the quench control signal Pq also becomes H level, and the N-type MOS. Transistor MN1 is turned on. As a result, the voltage Vc further drops via the N-type MOS transistor MN1, the reverse bias voltage applied between both terminals of the photodiode PD becomes less than the breakdown voltage Vbd, and no avalanche current is generated (quench operation).

Next, when the H level control signal Pq' is received and the control signal Pr' becomes L level after a predetermined delay time, the L level control signal Pr' is received and the quench control signal Pq becomes L level, resulting in an N-type. MOS transistor MN1 is turned off. Further, in response to the control signal Pr' of L level, the recharge control signal Pr becomes L level, and the P-type MOS transistor MP1 is turned on. As a result, recharging of the photodiode PD is started, and the reverse bias voltage applied between both terminals of the photodiode PD returns to the breakdown voltage Vbd or higher again (recharging operation).

The recharge operation and the quench operation described above are repeated each time a photon is incident, and the number of photon detection pulses Pp corresponding to the number of repetitions is output from the control circuit 16 to the counter 28 . A counter 28 counts the photon detection pulses Pp output from the control circuit 16 . This series of operations is repeated until time t2 when the count value of photon detection pulses Pp reaches a predetermined set value N. FIG.

At time t2, when the count value reaches an arbitrary set value N, counter 28 controls set value detection signal Pctl from L level to H level. As a result, both the recharge control signal Pr and the quench control signal Pq become H level, the P-type MOS transistor MP1 is turned off, and the N-type MOS transistor MN1 is turned on. As a result, the cathode terminal of the photodiode PD is connected to the reference voltage node via the N-type MOS transistor MN1, and the voltage Vc of the cathode terminal drops to the voltage Vss. At this time, since the reverse bias voltage applied between both terminals of the photodiode PD is less than the breakdown voltage Vbd, no avalanche current is generated and the cathode voltage is fixed at Vss. As a result, the circuit operations of the cathode voltage control circuit 14 and the control circuit 16 are stopped, and power consumption is minimized.

Next, at time t3, the count value (set value N) held by the counter 28 is read out to the external circuit.

Next, at time t4, the count value reset signal goes high and the count value of counter 28 is reset to zero. Thereby, the counting of the number of incident photons is newly started by the same operation.

Next, at time t5, the count value (N-4) held by counter 28 is read out to the external circuit.

Next, at time t6, the count value reset signal goes high and the count value of counter 28 is reset to zero. Since the count value has not reached the set value N until time t6, the set value detection signal Pctl remains at L level during the period from time t4 to time t6. Thus, unless the count value reaches an arbitrary set value N, the photon detection operation continues until just before the count value is reset.

Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIG.
First, the count value of the counter 28 is reset (step S101).

Next, it is determined whether or not the point in time is during the counting period (step S102). Here, the count period refers to a period from immediately after the timing of resetting the count value to just before the timing of reading the count value. As a result of the determination, if it is determined that it is the count period ("Yes" in step S102), the process proceeds to step S103, and if it is determined that it is not the count period ("No" in step S102) , to step S107.

If it is determined in step S102 that it is the count period, it is determined whether or not the count value of the counter 28 has reached an arbitrary set value N (step S103). As a result of the determination, if the count value has not reached an arbitrary set value N ("No" in step S103), the count value is increased according to photon detection (step S104), and the process returns to step S102. When the count value reaches an arbitrary set value N ("Yes" in step S103), the counter 28 outputs a set value detection signal Pctl to the control circuit 16 (step S105). After stopping the generation of the avalanche current in the photodiode PD (step S106), the process returns to step S102.

If it is determined in step S102 that it is not the count period, the count value is read out from the counter 28 in step S107. After that, the process returns to step S101 and repeats the same procedure.

As described above, according to the present embodiment, it is possible to reduce the power consumption and improve the stability of the circuit operation in the photoelectric conversion device.

[Fourth embodiment]
A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to FIGS. 8 to 10. FIG. Components similar to those of the photoelectric conversion devices according to the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 8 is a diagram illustrating a schematic configuration of a pixel in the photoelectric conversion device according to this embodiment. FIG. 9 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment. FIG. 10 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment.

In the pixel P in the photoelectric conversion device according to this embodiment, as shown in FIG. 8, the signal generation circuit 12 further includes a power supply voltage control circuit 24 in addition to the cathode voltage control circuit 14 and the control circuit 16 . Accordingly, the configurations of the cathode voltage control circuit 14 and the control circuit 16 are different from those of the photoelectric conversion devices according to the first to third embodiments. Other points are the same as the photoelectric conversion devices according to the first to third embodiments. In this specification, the power supply voltage control circuit 24 may be referred to as a power supply voltage control unit.

That is, the cathode voltage control circuit 14 in the photoelectric conversion device according to this embodiment can be composed of a P-type MOS transistor MP1 and N-type MOS transistors MN1, MN2 and MN3, as shown in FIG. 9, for example. The cathode terminal of the photodiode PD is connected to the drain terminal of the P-type MOS transistor MP1, the drain terminal of the N-type MOS transistor MN1, and the drain terminal of the N-type MOS transistor MN3. A source terminal of the N-type MOS transistor MN1 is connected to a drain terminal of the N-type MOS transistor MN2. A source terminal of the N-type MOS transistor MN2 and a source terminal of the N-type MOS transistor MN3 are connected to a reference voltage node of the voltage Vss.

Also, the control circuit 16 in the photoelectric conversion device according to the present embodiment can be composed of timing control circuits 20 and 22 as shown in FIG. 9, for example. A connection node of the cathode terminal of the photodiode PD, the drain terminal of the P-type MOS transistor MP1, and the drain terminals of the N-type MOS transistors MN1 and MN3 is connected to the counter 28 via the timing control circuits 20 and 22 . A gate terminal of the N-type MOS transistor MN1 is connected to the timing control circuit 20 . A gate terminal of the P-type MOS transistor MP1 and a gate terminal of the N-type MOS transistor MN2 are connected to the timing control circuit 22 . A gate terminal of the N-type MOS transistor MN3 is connected to the counter .

Also, the power supply voltage control circuit 24 has a P-type MOS transistor MP2. The drain terminal of the P-type MOS transistor MP2 is connected to the source terminal of the P-type MOS transistor MP1. The source terminal of the P-type MOS transistor MP2 is connected to the power supply node of the voltage Vdd. A gate terminal of the P-type MOS transistor MP2 is connected to the counter 28 .

The timing control circuits 20 and 22 are circuits for controlling the timing of the recharge operation and the quench operation in the cathode voltage control circuit 14 in accordance with changes in the voltage Vc of the cathode terminal of the photodiode PD, as in the third embodiment. be. Similarly, the timing control circuits 20 and 22 have a function as a waveform shaping section that outputs the photon detection pulse Pp.

The P-type MOS transistor MP1 and the N-type MOS transistor MN2 are controlled by a control signal Pr' output from the timing control circuit 22. FIG. N-type MOS transistor MN1 is controlled by a control signal Pq' output from timing control circuit 20. FIG. The P-type MOS transistor MP2 and the N-type MOS transistor MN3 are controlled by the set value detection signal Pctl output from the counter 28. FIG.

When the count value of the counter 28 reaches an arbitrary set value N, the set value detection signal Pctl becomes H level, and the P-type MOS transistor MP2 of the power supply voltage control circuit 24 is turned off. As a result, supply of the power supply voltage to the P-type MOS transistor MP1 by the cathode voltage control circuit 14 is stopped, and recharging of the cathode terminal of the photodiode PD is stopped. Also, when the set value detection signal Pctl becomes H level, the N-type MOS transistor MN3 of the cathode voltage control circuit 14 is turned on, and the voltage Vc of the cathode terminal of the photodiode PD is fixed at the voltage Vss. In this sense, the power supply voltage control circuit 24 functions as a control section that controls the voltage applied to the photodiode PD, more specifically, the power supply voltage supplied to the cathode terminal of the photodiode PD.

Next, an operation example of the photoelectric conversion device according to this embodiment will be described with reference to FIG. FIG. 10 shows the voltage Vc, the photon detection pulse Pp, the set value detection signal Pctl, the photon incidence timing, the count value, the count value reset, and the count value readout timing.

Here, it is assumed that the timing control circuit 20 outputs a signal obtained by converting a change in the voltage Vc of the cathode terminal of the photodiode PD into a pulse signal as a control signal Pq' whose logic is inverted after a predetermined delay time. . It is also assumed that the timing control circuit 22 outputs the control signal Pq' after a predetermined delay time as the control signal Pr' whose logic is inverted.

First, at time t1, the count value reset signal becomes H level, and the count value of the counter 28 is reset to zero.

When a photon is incident on the photodiode PD, an avalanche current is generated in the photodiode PD, and the voltage Vc of the cathode terminal of the photodiode PD drops. When the voltage Vc of the cathode terminal begins to drop, the control signal Pq' output from the timing control circuit 20 in response to the change in the voltage Vc becomes H level after a predetermined delay time. At this time, since the control signal Pr' output from the timing control circuit 22 is at H level in the initial state, the N-type MOS transistors MN1 and MN2 are turned on in response to the H level control signals Pq' and Pr'. As a result, the voltage Vc further drops via the N-type MOS transistors MN1 and MN2, the reverse bias voltage applied between the terminals of the photodiode PD becomes less than the breakdown voltage Vbd, and the avalanche current is no longer generated (quench operation). ).

Next, when control signal Pr' becomes L level after a predetermined delay time after receiving H level control signal Pq', P type MOS transistor MP1 is turned on and N type MOS transistor MN2 is turned off. As a result, recharging of the photodiode PD is started, and the reverse bias voltage applied between both terminals of the photodiode PD returns to the breakdown voltage Vbd or higher again (recharging operation).

The recharge operation and the quench operation described above are repeated each time a photon is incident, and the number of photon detection pulses Pp corresponding to the number of repetitions is output from the control circuit 16 to the counter 28 . A counter 28 counts the photon detection pulses Pp output from the control circuit 16 . This series of operations is repeated until time t2 when the count value of photon detection pulses Pp reaches a predetermined set value N. FIG.

At time t2, when the count value reaches an arbitrary set value N, counter 28 controls set value detection signal Pctl from L level to H level. As a result, the P-type MOS transistor MP2 is turned off and the N-type MOS transistor MN3 is turned on. As a result, the cathode terminal of photodiode PD is connected to the reference voltage node through N-type MOS transistor MN3, and voltage Vc of the cathode terminal drops to voltage Vss. At this time, since the reverse bias voltage applied between both terminals of the photodiode PD is less than the breakdown voltage Vbd, no avalanche current is generated and the cathode voltage is fixed at Vss. As a result, the circuit operations of the cathode voltage control circuit 14 and the control circuit 16 are stopped, and power consumption is minimized.

Next, at time t3, the count value (set value N) held by the counter 28 is read out to the external circuit.

Next, at time t4, the count value reset signal goes high and the count value of counter 28 is reset to zero. Thereby, the counting of the number of incident photons is newly started by the same operation.

Next, at time t5, the count value (N-4) held by counter 28 is read out to the external circuit.

Next, at time t6, the count value reset signal goes high and the count value of counter 28 is reset to zero. Since the count value has not reached the set value N until time t6, the set value detection signal Pctl remains at L level during the period from time t4 to time t6. Thus, unless the count value reaches an arbitrary set value N, the photon detection operation continues until just before the count value is reset.

As described above, according to the present embodiment, it is possible to reduce the power consumption and improve the stability of the circuit operation in the photoelectric conversion device.

[Fifth embodiment]
A photoelectric conversion device according to a fifth embodiment of the present invention will be described with reference to FIGS. 11 and 12. FIG. Components similar to those of the photoelectric conversion devices according to the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified. FIG. 11 is a diagram illustrating a schematic configuration of a pixel in the photoelectric conversion device according to this embodiment. FIG. 12 is a circuit diagram showing a configuration example of a pixel in the photoelectric conversion device according to this embodiment.

In the pixel P in the photoelectric conversion device according to this embodiment, the signal generation circuit 12 further includes an anode voltage control circuit 26 in addition to the cathode voltage control circuit 14 and the control circuit 16, as shown in FIG. Accordingly, the configurations of the cathode voltage control circuit 14 and the control circuit 16 are different from those of the photoelectric conversion devices according to the first to fourth embodiments. Other points are the same as the photoelectric conversion devices according to the first to fourth embodiments. In this specification, the anode voltage control circuit 26 may be referred to as an anode voltage control section.

That is, the cathode voltage control circuit 14 in the photoelectric conversion device according to this embodiment can be configured by a P-type MOS transistor MP1, as shown in FIG. 12, for example. The cathode terminal of the photodiode PD is connected to the drain terminal of the P-type MOS transistor MP1. The source terminal of the P-type MOS transistor MP1 is connected to the power supply node of the voltage Vdd. A voltage Vqnc is supplied to the gate terminal of the P-type MOS transistor MP1.

Further, the control circuit 16 in the photoelectric conversion device according to this embodiment can be configured by an inverter circuit INV, as shown in FIG. 12, for example. A connection node between the cathode terminal of the photodiode PD and the drain terminal of the P-type MOS transistor MP1 is connected to the input terminal of the inverter circuit INV. An output terminal of the inverter circuit INV is connected to the counter 28 .

Also, the anode voltage control circuit 26 has a switch SW. The switch SW has a function of switching the voltage supplied to the anode terminal of the photodiode PD between the voltage Va1 and the voltage Va2 according to the set value detection signal Pctl supplied from the counter . For example, the anode voltage control circuit 26 supplies the voltage Va1 to the anode terminal of the photodiode PD when the set value detection signal Pctl is at L level. On the other hand, when the set value detection signal Pctl is at H level, the switch SW is switched so as to supply the voltage Va2 to the anode terminal of the photodiode PD. That is, the anode voltage control circuit 26 functions as a control section that controls the voltage applied to the photodiode PD, more specifically, the voltage applied to the anode terminal of the photodiode PD. Here, voltages Va1 and Va2 have the following relationship with voltage Vdd and breakdown voltage Vbd.
|Vdd-Va1|>|Vbd|>|Vdd-Va2|

When the count value is less than an arbitrary set value N, the counter 28 outputs a set value detection signal Pctl of L level. The anode voltage control circuit 26 receives the set value detection signal Pctl at L level and controls the switch SW so as to supply the voltage Va1 to the anode terminal of the photodiode PD. At this time, since the voltage (Vdd-Va1) applied between both terminals of the photodiode PD is higher than the breakdown voltage Vbd of the photodiode PD, it becomes a condition for avalanche amplification to occur due to incident photons.

When the count value reaches an arbitrary set value N, the counter 28 outputs a set value detection signal Pctl of H level. The anode voltage control circuit 26 receives the set value detection signal Pctl at H level and controls the switch SW so as to supply the voltage Va2 to the anode terminal of the photodiode PD. At this time, since the voltage (Vdd-Va2) applied between both terminals of the photodiode PD is less than the breakdown voltage Vbd of the photodiode PD, no avalanche amplification occurs due to incident photons.

Therefore, in the photoelectric conversion device according to this embodiment as well, when the count value reaches an arbitrary set value N, the signal generation circuit 12 stops operating until the count value of the counter 28 is reset.

As described above, according to the present embodiment, it is possible to reduce the power consumption and improve the stability of the circuit operation in the photoelectric conversion device.

[Sixth embodiment]
An imaging system according to a sixth embodiment of the present invention will be described using FIG. FIG. 13 is a block diagram showing a schematic configuration of an imaging system according to this embodiment.

The photoelectric conversion device 100 described in the first to fifth embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, facsimiles, mobile phones, vehicle-mounted cameras, and observation satellites. The imaging system also includes a camera module that includes an optical system such as a lens and an imaging device. FIG. 13 illustrates a block diagram of a digital still camera as an example of these.

The imaging system 200 illustrated in FIG. 13 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a lens for protecting the lens 202. of barriers 206 . A lens 202 and a diaphragm 204 are an optical system that condenses light on the imaging device 201 . An imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments, and converts an optical image formed by a lens 202 into image data.

The imaging system 200 also has a signal processing unit 208 that processes an output signal output from the imaging device 201 . A signal processing unit 208 performs AD conversion to convert an analog signal output from the imaging device 201 into a digital signal. In addition, the signal processing unit 208 performs various corrections and compressions as necessary and outputs image data. The AD conversion unit, which is part of the signal processing unit 208, may be formed on the semiconductor substrate on which the imaging device 201 is provided, or may be formed on a semiconductor substrate different from that on which the imaging device 201 is provided. Also, the imaging device 201 and the signal processing unit 208 may be formed on the same semiconductor substrate.

The imaging system 200 further includes a memory section 210 for temporarily storing image data, and an external interface section (external I/F section) 212 for communicating with an external computer or the like. Further, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface section (recording medium control I/F section) 216 for recording or reading the recording medium 214. have Note that the recording medium 214 may be built in the imaging system 200 or may be detachable.

The imaging system 200 further includes an overall control/calculation unit 218 that controls various calculations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208 . Here, the timing signal and the like may be input from the outside, and the imaging system 200 only needs to have at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201 .

The imaging device 201 outputs an imaging signal to the signal processing unit 208 . A signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. A signal processing unit 208 generates an image using the imaging signal.

Thus, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fifth embodiments is applied.

[Seventh embodiment]
An imaging system and a moving body according to the seventh embodiment of the present invention will be described with reference to FIG. FIG. 14 is a diagram showing the configuration of an imaging system and a moving object according to this embodiment.

FIG. 14(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 has an imaging device 310 . The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax (phase difference of the parallax image) from the plurality of image data acquired by the imaging system 300. It has a parallax acquisition unit 314 that performs calculation. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 318 that determines whether there is a possibility of collision based on the calculated distance. and have Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means for acquiring distance information to the target object. That is, the distance information is information related to parallax, defocus amount, distance to the object, and the like. The collision determination unit 318 may use any of these distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware, or may be implemented by a software module. Moreover, it may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or by a combination thereof.

The imaging system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330 that is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination section 318 . The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination section 318 . For example, if the collision determination unit 318 determines that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, or suppressing the engine output. The alarm device 340 warns the user by sounding an alarm such as sound, displaying alarm information on a screen of a car navigation system, or vibrating a seat belt or steering wheel.

In this embodiment, the imaging system 300 images the surroundings of the vehicle, for example, the front or rear. FIG. 14B shows an imaging system for imaging the front of the vehicle (imaging range 350). Vehicle information acquisition device 320 sends an instruction to imaging system 300 or imaging device 310 . With such a configuration, the accuracy of distance measurement can be further improved.

In the above, an example of controlling so as not to collide with another vehicle was explained, but it can also be applied to control to automatically drive following another vehicle or control to automatically drive so as not to stray from the lane. . Furthermore, the imaging system can be applied not only to vehicles such as the own vehicle, but also to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[Modified embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

For example, an example in which a part of the configuration of any one of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

Further, the circuit configurations of the cathode voltage control circuit 14, the control circuit 16, and the like shown in the first to fifth embodiments are merely examples, and may be configured by other circuits capable of realizing similar operations. is also possible.

The imaging systems shown in the sixth and seventh embodiments are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied. It is not limited to the configurations shown in FIGS. 13 and 14. FIG.

It should be noted that the above-described embodiments are merely examples of specific implementations of the present invention, and the technical scope of the present invention should not be construed to be limited by these. That is, the present invention can be embodied in various forms without departing from its technical concept or main features.

P pixel PD photodiode 12 signal generation circuit 14 cathode voltage control circuit 16 control circuits 20, 22 timing control circuit 24 power supply voltage control circuit 26 anode voltage control circuit 100 photoelectric conversion device

Claims (10)

an avalanche amplified photodiode;
a signal generator connected to one terminal of a cathode terminal and an anode terminal of the photodiode, comprising a controller for controlling a voltage applied to the one terminal of the photodiode; a signal generator that generates a photon detection pulse based on the output generated by the incidence of photons on the
a counter that counts the photon detection pulses output from the signal generation unit;
the counter and the control unit are connected,
The photoelectric conversion device, wherein the counter outputs a set value detection signal to the control unit when the count value of the photon detection pulses reaches a predetermined set value. 2. The control unit controls the voltage applied to the photodiode so as to stop generating an avalanche current in the photodiode when the set value detection signal is received. The photoelectric conversion device described. The control unit has a switch provided between a power supply node and the photodiode, and when receiving the set value detection signal, turns off the switch to switch the power supply from the power supply node to the photodiode. 3. The photoelectric conversion device according to claim 1, wherein the supply of the applied voltage is stopped. The control unit is connected in series with the switch and provided between the power supply node and the photodiode, and is controlled according to a change in voltage of a terminal of the photodiode due to incidence of photons on the photodiode. 4. The photoelectric conversion device according to claim 3, further comprising a MOS transistor. 5. The photoelectric conversion device according to claim 3, wherein said switch is a MOS transistor controlled by said set value detection signal. 5. The photoelectric conversion device according to claim 1, wherein the applied voltage is supplied to the cathode terminal side of the photodiode. 7. A pixel region in which a plurality of pixels each including the photodiode, the signal generator, and the counter are arranged over a plurality of rows and a plurality of pixels. The photoelectric conversion device according to any one of . an avalanche amplified photodiode;
a signal generation unit having a control unit for controlling a voltage applied to the photodiode and generating a photon detection pulse based on an output generated by incidence of photons on the photodiode;
a counter that counts the photon detection pulses output from the signal generation unit;
The control unit includes a switch provided between a power supply node and the photodiode, and a switch connected in series to the switch provided between the power supply node and the photodiode. a MOS transistor controlled in response to a change in voltage at the terminals of the photodiode due to incident light;
the counter and the control unit are connected,
the counter outputs a set value detection signal to the control unit when the count value of the photon detection pulses reaches a predetermined set value;
The photoelectric conversion device, wherein the control unit turns off the switch to stop supplying the applied voltage from the power supply node to the photodiode when receiving the set value detection signal. A photoelectric conversion device according to any one of claims 1 to 8;
and a signal processing unit that processes a signal output from the photoelectric conversion device. being mobile,
A photoelectric conversion device according to any one of claims 1 to 8;
distance information acquisition means for acquiring distance information to an object from the parallax image based on the signal from the photoelectric conversion device;
and control means for controlling the moving body based on the distance information.

Images