JP2023078537A - Communication device - Google Patents

Abstract

To generate an appropriate pulse signal for synchronous processing using a counter.SOLUTION: A communication device comprises: a counter that is configured to increment a counter value at timing of an external clock, and to set the counter value to a predetermined minimum value when the counter value is more than or equal to a predetermined maximum value; a correction section that corrects the counter value of the counter; and a signal control section that outputs a pulse signal having a low level and a high level while switching the level when the counter value is more than or equal to a specified value by comparing the counter value of the counter with the predetermined specified value, and adds a predetermined value to the specified value to update. When correction to have a value less than the minimum value of the counter is performed by the correction section, or when the updated specified value is more than or equal to a predetermined maximum specified value which can be taken by the specified value, the signal control section does not output the pulse signal for a certain period based on the counter value.SELECTED DRAWING: Figure 9

Description

The present invention relates to time synchronization technology.

2. Description of the Related Art In recent years, in a system composed of a plurality of devices, a technique for synchronizing and operating the plurality of devices has been used in many fields. As an example, technologies such as stadium vision and volumetric studio can be used to create free-viewpoint video by switching in real time to an image of an arbitrary viewpoint using images captured with time synchronization by multiple cameras.

In order to obtain high-quality free-viewpoint video, it is necessary to precisely synchronize the shooting timing of each camera. Therefore, for example, PTP (Precision Time Protocol) is used as a technique for time synchronization between synchronous communication devices (terminals) that control each camera. Further, for example, a synchronization signal such as a Pulse Per Second (PPS) signal or a GenLock signal is used for synchronization between a synchronous communication device and a camera. In addition, since the internal clock of a synchronous communication device may contain errors such as jitter, a time server that distributes its own time has a high-precision clock such as GPS (Global Positioning System) as a reference for aligning the synchronization signal. can be used.

One method of generating the synchronization signal is to use a counter. Counts the internal clock of the synchronous communication device, compares the counted value (counter value) with the specified value, switches the output between “0” (low level) and “1” (high level), and after switching, the specified value is fixed. Add the value of A periodic signal is generated by repeating this process. The counter value is appropriately added/subtracted (corrected) as necessary, and by aligning the counter values in a plurality of synchronous communication devices, a synchronous signal based on a periodic signal whose phases are aligned among the plurality of devices can be generated. is obtained. A time synchronization protocol such as PTP shares the time for correcting this counter. Since the counter consists of a finite number of bits, the counter value has a maximum value, after which it resets to a minimum value and continues counting.

Japanese Patent Laid-Open No. 2002-200002 describes a method of correcting a counter across resets in a counter that receives correction from the outside and is reset to a minimum value and continues counting when the maximum value is exceeded.

Japanese Patent Application Laid-Open No. 2020-148120

However, the method described in Patent Document 1 has the following problems. For example, when correcting a counter by subtracting its counter value, if the value to be subtracted is greater than the current counter value, the counter value will be greater than the current counter value. In such a case, it becomes impossible to generate an accurate periodic signal, that is, a synchronizing signal. Also, depending on the timing of comparison between the counter value and the specified value, it may not be possible to generate an accurate synchronization signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a technique for generating an appropriate pulse signal for synchronization processing using a counter.

As one means for achieving the above object, the communication device of the present invention has the following configuration. That is, the communication device is a counter configured to increment a counter value at the timing of an external clock, and set the counter value to a predetermined minimum value when the counter value exceeds a predetermined maximum value. a correction unit for correcting the counter value of the counter; and a low level and a high level when the counter value of the counter is equal to or greater than the specified value by comparing the counter value of the counter with the specified value. and a signal control unit for switching and outputting the level of the pulse signal having a pulse signal, and updating by adding a predetermined value to the specified value, and the correction unit performs correction such that the counter falls below the minimum value. or if the updated specified value becomes equal to or greater than a predetermined maximum specified value that the specified value can take, the signal control unit outputs the pulse signal based on the counter value Not for a period of time.

According to the present invention, a counter can be used to generate an appropriate pulse signal for synchronization processing.

FIG. 1 shows a configuration example of a synchronous imaging system. FIG. 2 shows an example of the internal configuration of a synchronous communication device. FIG. 3 shows an internal configuration example of the synchronization signal generator. FIG. 4 shows an internal configuration example of the second counter in the synchronization signal generator. FIG. 5 shows an internal configuration example of a correction counter in the second counter. FIG. 6 shows an internal configuration example of a pulse output section in the second counter. FIG. 7 shows an example of timing waveforms for pulse signal generation. FIG. 8 shows another example of timing waveforms for pulse signal generation. 4 is a flow chart of processing executed by a second counter in the synchronization signal generator of the synchronous communication device according to the first embodiment; 9 is a flow chart of processing executed by a second counter in a synchronization signal generator of the synchronous communication device according to the second embodiment;

Embodiments for carrying out the present invention will be described in detail below with reference to the accompanying drawings. The embodiments described below are examples of means for realizing the present invention, and should be appropriately modified or changed according to the configuration of the apparatus to which the present invention is applied and various conditions. It is not limited to the embodiment. Also, not all combinations of features described in the present embodiment are essential for the solution means of the present invention.

<First embodiment>
FIG. 1 is a configuration example of a synchronized imaging system 100 according to the first embodiment. The synchronous imaging system 100 includes a time server 140, a switching hub 130, synchronous communication devices 110-1 to 110-m (m>1), 111-1 to 111-n (n>1), 112, and an imaging device 120-1. 120-m, 121-1 to 121-n, 122. As shown in FIG. 1, each of the synchronous communication devices 110-1 to 110-m, 111-1 to 111-n, and 112 includes the imaging devices 120-1 to 120-m, 121-1 to 121-n, and 122. connected to each of the In the following description, the synchronous communication devices 110-1 to 110-m may be collectively referred to as the synchronous communication device 110, and the synchronous communication devices 111-1 to 111-n may be collectively referred to as the synchronous communication device 111. Also, the imaging devices 120-1 to 120-m and 121-1 to 121-n may be collectively referred to as the imaging devices 120 and 121 in some cases.

The time server 140 has a time source (clock) having accurate time, and transmits the time information of the time to the synchronous communication devices 110-1, 111-1, 121 through the switching hub 130. Based on the time information, the synchronous communication devices 110-1 to 110-m, 111-1 to 111-n, and 112 synchronize their time via the network and transmit and receive data. The network is GbE (Gigabit Ethernet), 10GbE, or 100GbE conforming to the IEEE standard, which is Ethernet (registered trademark, hereinafter omitted), but may be configured by combining interconnect (Infiniband), industrial Ethernet, and the like. . Moreover, it is not limited to these, and other types of networks may be used.

As described above, the time server 140 is a server that has a time source that has accurate time and distributes time information of that time according to the time synchronization protocol. As the time source of the time server 140, for example, GPS or atomic clock is used. Other types of time sources may also be used, such as OCXOs (Oven Controlled X-tal Oscillators). The time source in the time server 140 preferably has higher accuracy than the clocks inside the synchronous communication devices 110 , 111 , 112 .

In this embodiment, PTP (Precision Time Protocol) is used as a time synchronization protocol for distributing time information. Note that other time synchronization protocols such as IEEE802.1 standard AVB (Audio Video Bridging) and PPS (Pulse Per Second) signals can also be used. Also, a plurality of time servers 140 may be used to ensure redundancy.

Synchronous communication devices 110, 111, 112 may all have the same configuration. Each of the synchronous communication devices 110, 111, and 112 has an internal clock and updates its own time information according to the received time information. In addition, the synchronous communication devices 110, 111, and 112 generate shooting synchronization signals as described later, and transmit shooting control signals including the shooting synchronization signals to the shooting devices 120, 121, and 122, respectively.
While the synchronous communication devices 110, 111, and 112 cannot receive the time information, they can use their clocks to update the time information and generate the synchronization signal.

Here, the imaging control signals transmitted to the imaging devices 120, 121 and 122 by the synchronous communication devices 110, 111 and 112 will be described. The shooting control signal is a signal including setting information for the shooting devices 120, 121, and 122 and a shooting synchronization signal. The imaging synchronization signal includes a GenLock signal, a Timecode signal, etc., which are pulses for transmitting accurate imaging intervals to the imaging devices 120 , 121 , 122 . The imaging devices 120, 121, and 122 perform imaging at the same timing based on the imaging synchronization signal, so that these imaging devices can perform imaging at the same imaging time in a constant cycle.

In the synchronous imaging system shown in FIG. 1, synchronous communication devices 110-1 to 110-m are daisy-chained. Similarly, synchronous communication devices 111-1 to 111-n are daisy-chained. Note that the configuration of the synchronous communication devices 110, 111, and 112 is not limited to the configuration shown in FIG. . Further, in order to ensure redundancy, the connections of the synchronous communication devices 110-1 to 110-m (m>1), 111-1 to 111-n (n>1), and 112 may be duplicated.

The switching hub 130 is a hub that connects the time server 140 and the synchronous communication devices 110, 111, 112 while maintaining the time synchronization protocol. As described above, in this embodiment, PTP is used as a time synchronization protocol, and according to PTP, the time server 140 has a TC (Transparent Clock) function. The TC function is a function for adding, when relaying time information (PTP packets), the time required for packet relay, etc., to the time information.
The switching hub 130 is required when using a plurality of time servers 140 or when star connecting the synchronous communication devices 110-1, 111-1, 112, etc., but the time server 140 has a plurality of ports and is directly connected. Optional if you do.

Each of the photographing devices 120, 121, and 122 receives a photographing control signal from each of the synchronous communication devices 110, 111, and 112, performs synchronous photographing based on the photographing synchronization signal included in the photographing control signal, and produces a photographed image. , to the synchronous communication devices 110, 111, and 112, respectively. The shooting control signal corresponds to the shooting control signal 251 shown in FIG. 2 in the case of the synchronous communication device 110-2. Each of the imaging devices 120, 121, and 122 has an internal clock and updates its own time based on the synchronization signal in the received imaging control signal. The image capturing apparatuses 120, 121, and 122 have synchronization signal reception timings for the image capturing synchronization signals in the received image capturing control signals, and receive the image capturing synchronization signals during the reception period. , 112. Note that the imaging devices 120, 121, and 122 do not have to have the same configuration, and for example, they may be configured by devices of different models. The imaging devices 120, 121, and 122 may also include ranging sensors such as LiDAR (Light Detection and Ranging) and RADAR (RADio Detecting and Ranging).

In this embodiment, unless otherwise specified, the term "image" will be described as including the concepts of moving images and still images. In other words, the synchronized imaging system 100 of this embodiment can process both still images and moving images.

[Configuration of Synchronous Communication Device]
FIG. 2 is a block diagram showing an example internal configuration of the synchronous communication device 110-2 in FIG. Here, the synchronous communication device 110-2 will be described as an example, but the other synchronous communication devices 110, 111, and 112 can also have similar internal configurations.
Synchronous communication device 110-2 is composed of first communication unit 210 and second communication unit 211, synchronization signal generation unit 220, storage unit 230, transmission processing unit 240, imaging control unit 250, image processing unit 260, and control unit 270. be done. Each functional block 210 to 270 transmits and receives various information/data via the system bus. Also, the synchronous communication device 110-2 can have a power supply and a clock (not shown).

The first communication unit 210 and the second communication unit 211 are communication interfaces consisting of a MAC (medium access control) unit and a PHY (physical layer) unit. The second communication unit 211 receives image data from the synchronous communication device 110 - 3 and transmits it to the transmission processing unit 240 . The first communication unit 210 receives image data from the synchronous communication device 110-3 and the imaging device 120-2 from the transmission processing unit 240, and transmits the image data to the synchronous communication device 110-1. In addition, the first communication unit 210 and the second communication unit 211 receive time information indicating the correct time via the synchronization protocol, acquire information on the timing of the reception (update timing information), The synchronization signal generation unit 220 is notified of the time information and the update timing information. The time information corresponds to the time information 331 in FIG. 3, and the update timing information corresponds to the first update timing 332 in FIG.

1 is the synchronous communication device (terminal) farthest from the time server 140 in the daisy chain connection of the synchronous communication devices 110-1 to 110-m, the second communication unit 211 may not be connected to an external device. The same applies to the synchronous communication device 111-n.
Further, even when the synchronous communication devices 110-1, 111-1, and 112 are star-connected to the switching hub 130, the second communication unit 211 does not have to be connected to the external device.

The control unit 270 is composed of one or more CPUs (Central Processing Units) that control the entire synchronous communication device 110-2. For example, the control unit 270 controls a time synchronization sequence defined by a time synchronization protocol such as PTP, and controls image packet transfer including image data received from the synchronous communication device 110-3. Also, the control unit 270 generates a timecode to be included in the imaging control signal 251 based on the time information acquired from the first communication unit 210 and the second communication unit 211 via the bus. The control unit 270 also transmits control information (corresponding to the control information 335 in FIG. 3) to the synchronization signal generation unit 220 .

The storage unit 230 is a main storage device that can be shared and used by each functional block in the synchronous communication device 110-2, and is mainly composed of a semiconductor memory such as a DRAM (Dynamic Random Access Memory). The storage unit 230 stores various information handled by the functional blocks 210 to 270, setting information of the imaging device 120-2, and the like.

The synchronization signal generation unit 220 receives time information and update timing information from the first communication unit 210 and the second communication unit 211, and generates a pulse signal that is a synchronization signal. The pulse signal corresponds to the pulse 334 in FIG. 2 and is transmitted to the imaging control section 250 and transmission processing section 240 . An example of a pulse 334 is a PPS with precise intervals and ratios. The synchronization signal generation unit 220 also has a register for setting and storing thresholds and the like for aligning the phases of the pulses 334 via the bus.
The internal configuration of the synchronization signal generator 220 will be described later with reference to FIG.

The transmission processing unit 240 generates image packets to be output by the synchronous communication device 110-2. The transmission processing unit 240 packetizes the image captured by the image capturing device 120-2 obtained from the image processing unit 260, and transmits the packet to the first communication unit 210 together with the image packet from the synchronous communication device 110-3 received from the second communication unit 211. and send. The transmission processing unit 240 also receives the pulse 334 from the synchronization signal generation unit 220 and supplies the time stamp to the image data received from the image processing unit 260 . In the case of the synchronous communication devices 110-m and 111-n in FIG. 1, which are the synchronous communication devices furthest from the time server 140 in the daisy chain connection, there may be no image packets to be received. The same applies when the synchronous communication devices 110-1, 111-1, and 121 are star-connected without daisy-chained synchronous communication devices.

The imaging control unit 250 receives the pulse 334 from the synchronizing signal generating unit 220, and based on the pulse 334, generates an imaging synchronizing signal (imaging process synchronizing signal) indicating imaging timing. Also, the shooting control unit 250 receives the timecode from the control unit 270 . Then, the imaging control unit 250 includes the generated imaging synchronization signal and the received Timecode in the imaging control signal 251 and transmits the imaging control signal 251 to the imaging device 121 .

The photographing device 120-2 performs photographing in synchronization with the synchronization signal included in the photographing control signal 251 from the photographing control unit 250, and transmits the photographed image and the timecode included in the photographing control signal 251 to the image processing unit 260. Output.
The image processing unit 260 receives a photographed image from the photographing device 120-2, performs image processing on the photographed image (cutting out background and foreground, etc.), and generates image data as processed data. The image processing section 260 outputs the generated image data to the transmission processing section 240 .

[Configuration of Synchronization Signal Generation Unit 220]
FIG. 3 is a block diagram showing an example internal configuration of the synchronization signal generator 220 shown in FIG. The synchronization signal generator 220 is composed of a first counter 320 , a second counter 321 and a bus interface 310 . The synchronization signal generator 220 is configured to receive the clock 330 , the time information 331 and the first update timing 332 , and generate and output the pulse 334 to the transmission processor 240 and imaging controller 250 .

A clock 330 is a clock signal based on an external clock that drives the first counter 320 and the second counter 321 . Clock 330 is also used to operate bus interface 310 .
Time information 331 and first update timing 332 are received from first communication unit 210 and second communication unit 211 . The first update timing 332 is the update timing of the first counter 320 .

The bus interface 310 is an interface that communicates with components outside the sync signal generator 220 via a bus. Bus interface 310 acquires control information 335 including an offset value between first counter 320 and second counter 321 from control unit 270 , and outputs the control information to first counter 320 and second counter 321 . An offset value is a value used to calculate a correction value 443 for a correction counter 420, which will be described later with reference to FIG. The control information 335 also includes a limit value that determines the upper limit of the correction value 443, a default value when the first counter 320 and the second counter 321 are reset, initialization of the first counter 320 and the second counter 321, It can include a start instruction, a stop instruction, a threshold used when updating the second counter 321, and the like.

The first counter 320 is a self-running counter whose value can be rewritten from the outside, and increments its own counter value at the timing of the clock 330 except for the timing of the input update timing 332 . The first counter 320 is rewritten to the value of the time information 332 at the timing of the first update timing 332, thereby synchronizing with the accurate time of the time source. The first counter 320 outputs to the second counter 321 a first counter value 336 which is its own counter value and a second update timing 337 generated based on the counter value.

The second counter 321 is a self-running counter whose value can be rewritten from the outside, and increments its own counter value at the timing of the clock 330 except for the timing of the second update timing 337 to be input. The second counter 321 updates its own counter value using the first counter value 336 and the offset value in the control information 335 at the timing of the second update timing 337, and generates the pulse 334 using the counter value. do. The generated pulse 334 is output to the transmission processing section 240 and the imaging control section 250 .
The internal configuration of the second counter 321 will be described later using FIG.

A pulse 334 is a phase pulse generated based on the counter value of the second counter 321 . Since the first counter 320, which is the synchronization source of the second counter 321, is synchronized by the time information 331 and the first update timing 332, the pulse 334 is sent out at the same time.

[Configuration of second counter 321]
FIG. 4 is a block diagram showing an example internal configuration of the second counter 321 in the synchronization signal generator 220 shown in FIG. The second counter 321 is composed of a correction section 410 , a correction counter 420 and a pulse output section 430 . The second counter 321 is configured to receive a first counter value 336 and a second update timing 337 from the first counter 320, receive control information 335 from the bus interface 310, and generate and output a pulse 334. be.

The correction unit 410 calculates the difference between the first counter value 336 received from the first counter 320 and the second counter value 440 received from the correction counter 420, and adds the offset value in the control information 335 to obtain a correction value 443. is calculated and output to the correction counter 420 . Note that the correction unit 410 may calculate the correction value 443 by a method other than this.

The correction counter 420 is a self-running counter whose value can be rewritten from the outside, and increments its own counter value with the clock 330 at timings other than the second update timing 337 . The correction counter 420 corrects its current counter value based on the correction value 443 received from the correction unit 410 at the timing of the second update timing 337 . Correction section 410 notifies correction section 410 and pulse output section 430 of the corrected counter value as second counter value 440 . The range of possible values of the second counter value 440 is set in advance, that is, predetermined maximum and minimum values are set in advance. Then, when the second counter value 440 is corrected to exceed the range, the correction counter 420 notifies the pulse output section to that effect by means of the control signal 441 .

Here, the relationship between the second counter value 440 and the control signal 441 will be specifically described. As described above, the second counter value 440 has a range of possible values, that is, predetermined maximum and minimum values. When the second counter value 440 exceeds the maximum value due to correction or self-running, the second counter value 440 is reset to the minimum value, and the exceeding amount is added to the minimum value (hereinafter, reset to the minimum value). . On the other hand, when the second counter value 440 falls below the minimum value due to correction, the second counter value 440 is reset to the maximum value, and the amount below the minimum value is subtracted from the maximum value (hereinafter referred to as the maximum value). reset). Each reset, that is, the reset to the minimum value and the reset to the maximum value of the second counter value 420 is notified to the pulse output section 430 through the control signal 441 . Each piece of information is distinct.
The internal configuration of correction counter 420 will be described later with reference to FIG.

Pulse output unit 430 generates and outputs pulse 334 based on second counter value 440 and control signal 441 received from correction counter 420 and control information 335 received from bus interface 310 .
The internal configuration of pulse output section 430 will be described later with reference to FIG.

[Configuration of Correction Counter 420]
FIG. 5 is a block diagram showing an internal configuration example of the correction counter 420 in the second counter 321 shown in FIG. The correction counter 420 is composed of a correction value register 510 , a period information register 520 , a counter control section 530 and a counter 540 . Correction counter 420 receives correction value 443 from correction unit 410 , receives second update timing 337 from first counter 320 , and outputs control signal 441 and second counter value 440 to pulse output unit 430 . Configured.

The correction value register 510 is a register that receives the correction value 443 from the correction unit 410 and provides the correction value 443 to the counter control unit 530 .
The period information register 520 is a register that stores the periodic count-up value of the counter 540 as period information 521 . Note that the period information 521 may be rewritable from the outside, and the period information register 520 may have a function of correcting the counter 540 using the period information 521 .

The counter control unit 530 increments the total value of the correction value 443 and the value (count-up value) of the period information 521 at the timing of the second update timing 337, and the value of the period information 521 at other timings. 531 to the counter 540 . Further, the counter control unit 530 has a function of outputting a control signal 441 to that effect when resetting to the maximum value and resetting to the minimum value.

The counter 540 is a counter that adds an increment value 531 given from the counter control unit 530 to its current counter value. Counter 540 outputs its own counter value as second counter value 440 to counter control section 530 and also to correction section 410 and pulse output section 430 .

[Configuration of pulse output unit 430]
FIG. 6 is a block diagram showing an example internal configuration of the pulse output section 430 in the second counter 321 shown in FIG. The pulse output unit 430 is configured to receive the control signal 441 and the second counter value 440 from the correction counter 420 , receive the control information 335 from the bus interface 310 , and output the pulse 334 . The pulse output unit 430 functions as a signal control unit that controls various received signals and the pulse 334 .

A specified value register 610 is a register that stores a specified value 611 . The prescribed value 611 is a value to be compared with the second counter value, and is periodically updated to a new value by the pulse generator 630 . For the specified value 611, it is assumed that a possible maximum value (hereinafter referred to as maximum specified value) and an initial value are set in advance.
Comparing section 620 compares second counter value 440 with specified value 611 , and outputs comparison result 621 to pulse generating section 630 when second counter value 440 becomes equal to or greater than specified value 611 . The comparison result 621 is "1" when the second counter value 440 is equal to or greater than the specified value 611, and "0" otherwise. Note that this is just an example, and other comparison result values may be used.

The pulse generator 630 switches between “0” (low level) and “1” (high level) of the pulse 334 based on the comparison result 621 (hereinafter referred to as pulse (level) switching). The pulse generation unit 630 switches the pulse 334 when the comparison result 621 indicates “1” when the second counter value 440 is equal to or greater than the specified value 611, and indicates “0” otherwise. I do. As will be described later, the A flag and the /B flag 640 are set for a certain period of time based on the second counter value 440, and the pulse generator 630 does not output (generate) the pulse 334 for that certain period of time. works like

At the same time as switching the pulse 334, the pulse generator 630 adds a predetermined value to the specified value 611 and notifies a new specified value 611 (hereinafter referred to as update of specified value). Note that the value to be added to the specified value 611 need not be a fixed value, and may be set to a variable value.

Flag register 660 stores B flag 640 and A flag 650 .
A B flag 640 is a flag set by the pulse generator 630 . It is set (set to "1") when the specified value 611 calculated by the pulse generator 630 is greater than or equal to the maximum specified value. The B flag is cleared (set to "0") when the flag register 660 receives a control signal 441 indicating a reset to the minimum value.
A flag 650 is a flag that is set according to control signal 441 . A flag 650 is set when control signal 441 is received in flag register 660 indicating a reset to maximum value. Also, A flag 650 is cleared when control signal 441 indicating a reset to minimum value is received in flag register 660 .
While the B flag 640 or the A flag 650 is set, the pulse generator 630 does not update the specified value 611 or switch the pulse 334 (stops). Here, for example, while the B flag 640 or the A flag 650 is set, the comparison unit 620 may be configured to stop the comparison process.

[Timing of pulse signal generation]
FIG. 7 shows an example of timing waveforms for pulse signal generation in this embodiment. Specifically, in FIG. 7, in the second counter 321 described with reference to FIGS. is a diagram showing the process up to the generation of . For the sake of explanation, the first counter value 336, the second counter value 440, and the specified value 611 are two digits, but this is an example and the number of digits is not limited. Also, although the increment value 531 (the value of the period information 521) is 1 in the initial state, it may be another value such as a clock period. The specified value 611 has an initial value of "01" and is updated by 10 from "01", and the second counter value 440 has a minimum value of "00" and a maximum value of "100". Also, the maximum specified value of the specified value 611 (the maximum value that the specified value 611 can take) is assumed to be "101".

Time t1 indicates the operation when the timing of the second update timing 337 is not reached. Since "-15" is specified as the offset value in the control information 335, the correction value 443 is calculated as "-15". Since it is not the timing of the second update timing 337, the increment value 531 is "+1".

Time t2 shows the operation when the second counter 321 is reset to the maximum value. Due to the timing of the second update timing 337, the increment value 531 is corrected (“1”+“−15”) and becomes “−14”. Since the subtracted value (=“14”) is greater than “10” which is the second counter value 440, the counter control section 530 notifies the flag register 660 of the control signal 441 indicating resetting to the maximum value. , and accordingly the A flag 650 is set.
The second counter value 440 is obtained by subtracting "4", which is the difference between the second counter value 440 (="10") and the subtracted value (="14"), from the maximum value (="100"). It becomes "96". The second counter value 440 (=“96”) exceeds “11” which is the value of the specified value 611, and the comparison result 621 becomes “1”. Since the A flag 650 is set, the specified value 611 is not updated by the comparison result 621 and the pulse 334 is not switched.

Time t3 shows the operation when the second counter 321 is reset to the minimum value. The second counter value 440 is incremented by "+1" from "99", reaches the maximum value of "100" or more, and is set to the minimum value of "00". At this time, a control signal 441 indicating resetting to the minimum value notifies the flag register 660, and accordingly the A flag 650 and the B flag 640 are cleared.

Time t4 shows the operation when the first counter value 336 is changed from "19" to "05" and the offset value in the control information 335 becomes "0". At this time, the first counter value 336 and the second counter value 337 match, and the correction value 443 calculated by combining the difference between the counter values and the offset value in the control information 335 becomes "0".

Time t5 shows the operation when the second counter value 440 matches the specified value 611. FIG. Since the second counter value 440 and the specified value 611 match and both the A flag 650 and the B flag 640 are “0”, the comparing section 620 notifies the pulse generating section 630 of the comparison result 621 . The pulse generator 630 switches the pulse 334 from "0" to "1" and updates the specified value 611 from "11" to "21".

Time t6 shows the operation when the second counter value 440 and the specified value 611 match after time t5. Since the second counter value 440 and the specified value 611 match, the comparator 620 notifies the pulse generator 630 of the comparison result 621 of "1". In response to this, the pulse generator 630 switches the pulse 334 from "1" to "0" and updates the specified value 611 from "21" to "31".

FIG. 7 also shows a specified value 701 and a pulse 702 defined to compare the operation according to the present embodiment with the conventional technology.
A specified value 701 indicates the behavior of the specified value 611 when the A flag 650 is not referred to. The comparison result 621 is "1" from time t2 to t3. Therefore, the specified value 611 is updated every clock 330, and becomes the updated value "61" after time t3.
Pulse 702 shows the behavior of pulse 334 when A flag 650 is not referenced. Since the comparison result 621 is "1" from time t2 to time t3, the pulse 702 is switched each time the clock is input during this period, and the desired pulse 334 cannot be obtained.

In this way, by controlling the A flag 650, even if the value to be subtracted to correct the counter is greater than the current counter value, the generation of the pulse 334 is not performed for a certain period of time. pulse 334 can be generated.

FIG. 8 shows another example of timing waveforms for pulse signal generation in this embodiment. Specifically, in FIG. 8, the B flag 640 is used in the second counter 321 described with reference to FIGS. 3 is a diagram showing the process up to the generation of H.334; FIG. Conditions such as the first counter value 336, the second counter value 440, the specified value 611, the increment value 531, and the output are the same as in FIG.

Time t7 shows the operation when there is a difference between the first counter value 336 and the second counter value 440. FIG. There is a difference between the first counter value 336 and the second counter value 440 , and “0” is specified as the offset value in the control information 335 . Therefore, the correction value 443 is calculated here as "+2", which is the difference between the two counters. Since it is not the timing of the second update timing 337, the increment value 531 is "+1". The second counter value 440 is incremented to "81" and becomes equal to or greater than the value "81" of the specified value 611. Therefore, the specified value 611 is updated to "91" and the pulse 334 is switched.

Time t8 shows the operation for correcting the second counter value 440 to match the first counter value 336. FIG. Here, the increment value 531 is determined as “+3” based on the value of the period information 520 and the value of the correction value 443 . This is calculated with respect to the second counter value 440 at the second correction timing 337 , and the second counter value 440 changes from “82” to “85” and matches the first counter value 336 .

Time t9 shows the operation when the second counter value 440 and the specified value 611 match at the timing when the specified value 611 becomes equal to or greater than the maximum specified value when updated. Since the second counter value 440 has exceeded the specified value 611, the pulse 334 is switched and the specified value 611 is updated. If 10 is added to the specified value 611 and updated to "101", it is the maximum specified value. "101" or more. Therefore, the specified value 611 is updated to "01", which is the initial value of the specified value, and the B flag 640 is set to "1".

Time t10 shows the operation when clock 330 next to time t9 comes. Since the second counter value 440 is "92" and exceeds the value "01" of the specified value 611, the comparison result 621 indicates "1". Although the comparison result 621 indicates "1", the B flag 640 is set and the prescribed value 611 is not updated and the pulse 334 is not switched.

Time t11 shows the operation when the second counter value 440 becomes equal to or greater than the maximum value and is corrected. Since "+3" is notified as the correction value 443, the increment value 531 is calculated as "+4". This is added to the second counter value 440 "96" (="100"), the second counter value 440 becomes equal to or greater than the maximum value, and is reset to "00". Since the reset to the minimum value has been performed, the counter control unit 530 notifies the flag register 660 of the control signal 441 indicating the reset to the minimum value, and accordingly the A flag 650 and the B flag 640 are set to cleared. Since the second counter value 440 is "00" and the specified value 611 is "01", the comparison result 621 indicates "1".

Time t12 shows the operation when the second counter value 440 reaches the specified value 611 or more. The second counter value 440 becomes "01" due to self-running and becomes equal to or greater than the specified value 611. Since both the A flag 650 and the B flag 640 are cleared, the pulse 334 is switched and the specified value 611 is updated from "01" to "11".

FIG. 8 also shows a specified value 801 and a pulse 802 defined to compare the operation according to the present embodiment with the conventional technology.
A specified value 801 indicates the behavior of the specified value 611 when the B flag 640 is not referred to. If the B flag 640 is not referred to, the second counter value 440 of "92" becomes equal to or greater than the specified value 801 of "01" at time t10. ” will be updated. Thereafter, the pulse 802 is switched and the specified value 801 is updated every clock until the reset to the minimum value is performed, resulting in the desired pulse 334 not being generated.

In this way, even if the specified value 611 exceeds the maximum value of the second counter value 440 due to the update, the B flag 640 stops the generation of the pulse 334 for a certain period of time. A pulse 334 can be generated.

[Process flow]
FIG. 9 shows a flowchart of processing executed by the second counter 321 (FIGS. 4 to 6) in the synchronization signal generator 220 of the synchronous communication device 110-2 according to this embodiment.
This flow is started while the synchronous communication device 110-2 is activated as one of the terminals constituting the system shown in FIG. Similar processing can be performed for other synchronous communication devices 110 , 111 , and 112 . 7 and 8, the minimum value of the second counter value 440 is "00", the maximum value is "100", and the maximum specified value that the specified value 611 can take is "101".

In S901, the second counter 321 is activated and initialized. For example, the second counter 321 sets initial values to the pulse 334 , the specified value 611 , the A flag 650 , the B flag 640 , and the correction value 443 based on the received control information 335 .
In S902, the second counter 321 determines whether or not an instruction (start instruction) to start generating the pulse 334 has been issued. The start instruction can be determined by the control information 335 received by the second counter 321 . If a start instruction has been issued (Yes in S902), the process proceeds to S903; otherwise (No in S902), the second counter 321 waits for a start instruction.

In S<b>903 , the correction unit 410 calculates a correction value 443 . Specifically, the correction unit 410 obtains the difference between the first counter value 336 and the second counter value 440 and adds the difference to the offset value in the control information 335 to generate the correction value 443 . Note that the correction value 443 may be generated by another method.
In S904, the second counter 321 determines whether it is the timing of the second update timing 337 (whether the second update timing 337 has been received). That is, the second counter 321 determines whether or not it is time to correct the second counter value 440 to the correction value 443 . If it is the timing of the second update timing 337 (Yes in S904), the process proceeds to S905, otherwise (No in S904), the process proceeds to S906.

In S<b>905 , the second counter 321 applies the correction value 443 to the second counter value 440 . Addition is performed when the correction value 443 is positive, and subtraction is performed when the correction value 443 is negative.
In S<b>906 , the second counter 321 adds the value of the period information 520 to the second counter value 440 .

In S907, the second counter 321 determines whether or not the second counter value 440 after the processing (corrected) in S905 or S906 (hereinafter referred to as the calculation result) is less than the minimum value that the second counter value 440 can hold. judge. If the calculation result is less than the minimum value (Yes at S907), the process proceeds to S908; otherwise (No at S907), the process proceeds to S910.

In S908, the counter control unit 530 notifies the flag register 660 of the control signal 441 indicating resetting to the maximum value, and accordingly the A flag 650 is set to "1".
In S909, the second counter 321 adjusts the second counter value 440 to a holdable range. By adding the maximum holdable value of the second counter value 440 to the negative calculation result, the second counter value 440 becomes a positive value obtained by subtracting the value calculated in S905 from the maximum value. .

In S910, the second counter 321 determines whether the calculation result in S905 or S906 is equal to or greater than the maximum value that the second counter value 440 can hold. If the calculation result is greater than or equal to the maximum value (Yes at S910), the process proceeds to S911; otherwise (No at S910), the process proceeds to S914.

In S911, the counter control unit 530 notifies the flag register 660 of the control signal 441 indicating resetting to the minimum value, and accordingly the A flag 650 is set (cleared) to "0". Similarly, in S912, the B flag 640 is set (cleared) to "0".
In S913, the second counter 321 adjusts the second counter value 440 to a holdable range. By subtracting the maximum value from the calculation result in which the second counter value 440 is equal to or greater than the maximum value that can be held, the second counter value 440 becomes a positive value less than the maximum value.

In S914, the second counter 321 determines whether the A flag 650 is set to "1". If the A flag 650 is set to "1" (Yes at S914), the process proceeds to S903, otherwise (No at S914), the process proceeds to S915.
In S915, the second counter 321 determines whether or not the B flag 640 is set to "1". If "1" is set in the B flag 640 (Yes at S915), the process proceeds to S903; otherwise (No at S915), the process proceeds to S916.

In S<b>916 , the second counter 321 determines whether the second counter value 440 is equal to or greater than the specified value 611 . Thus, it is determined whether or not it is time for the pulse generator 630 to switch the pulse 334 . If the second counter value 440 is equal to or greater than the specified value 611 (Yes at S916), the process proceeds to S917, and if it is less than the specified value 611 (No at S916), the process proceeds to S903.
Note that the processing of S916 may be performed before S914 and S916.

In S917, the pulse generator 630 switches (changes) the pulse 334 between “0” (low level) and “1” (high level).
In S918, the pulse generation unit 630 calculates the following specified value 611. The calculation may be performed by adding a predetermined value of current default value 611 .
In S<b>919 , the second counter 321 determines whether or not the specified value 611 calculated in S<b>918 is equal to or greater than the maximum specified value of the specified value 611 . If it is less than the maximum specified value of the specified value 611 (No in S919), the process proceeds to S903, and if it is equal to or greater than the maximum specified value of the specified value 611 (Yes in S919), the process proceeds to S920.

In S920, the pulse generator 630 sets the B flag 640 to "1".
In S<b>921 , the second counter 321 updates the specified value 611 with the initial value of the specified value 611 .
In S922, the second counter 321 determines whether or not an instruction to stop the process of generating the pulse 334 has been issued. If no stop instruction has been issued (No in S922), the process proceeds to S903, and if a stop instruction has been issued (Yes in S922), the process of this flow ends.

As described above, according to the present embodiment, when the updated second counter value 440 is less than the maximum value of the second counter value 440, the A flag 650 is set to "1". Then, the generation of the pulse 334 is stopped for a certain period during which the A flag 650 is set to 1. As a result, even if the value to be subtracted to correct the counter is greater than the current counter value, it is possible to generate an accurate pulse 334 without generating unnecessary pulses.

<Second embodiment>
Next, a second embodiment will be described. Note that the configuration of the synchronous communication system 100 and the configuration of each device of the synchronous communication system 100 are the same as those of the first embodiment, and description thereof will be omitted.
[Process flow]
FIG. 10 shows a flowchart of processing executed by the second counter 321 (FIGS. 4 to 6) in the synchronization signal generator 220 of the synchronous communication device 110-2 according to this embodiment. The basic processing flow is the same as in FIG. 9 described in the first embodiment, and different processing will be described.

In S1001 after the processing of S909, the second counter 321 saves the current specified value 611. FIG.
Also, in processing S002 after S913, the second counter 321 updates the specified value 611 to the value saved in S1001 or S1006.
In S1003 after S1001 or S1002, the second counter 321 determines whether or not the A flag 650 is set to "1". If "1" is set in the A flag 650 (Yes in S1003), the process proceeds to S1004, otherwise (No in S1003), the process proceeds to S1005.

In S1004, the second counter 321 sets the specified value 611 to the maximum specified value. The maximum specified value is set to a value greater than the maximum value of the second counter value 440 . By this processing, the prescribed value 611 always becomes a value larger than the second counter value 440, and the branch to S903 is always specified in S916. In the processing after S904, addition to the second counter value 440 is performed, and when the flag is cleared in S911 and S912, the specified value 611 becomes the value before the flag was set in S1002, and the pulse 334 is generated again. switching processing and updating processing of the specified value 611 are performed.

In S1005, the second counter 321 determines whether or not the B flag 640 is set to "1". If the B flag 640 is set to "1" (Yes at S1005), the process proceeds to S1004; otherwise (No at S1005), the process proceeds to S916.

S1006 after S920 indicates that the initial value of the specified value 611 is saved when the specified value 611 exceeds the maximum specified value and the B flag 640 is set. As a result, the specified value 611 is updated to the initial value when the flag is cleared in S911 and S912.

As described above, according to the present embodiment, it is possible not only to obtain the effects described in the first embodiment, but also to manage the specified value 611 by setting the A flag 650 and the B flag 640 .

As described above, according to the above-described embodiments, when generating a pulse signal, which is a synchronization signal, using a counter configured with a finite number of bits and having a maximum value and a minimum value of the counter value, Even when correction is performed, it is possible to generate an appropriate pulse signal.
Further, a synchronization signal generated for specific processing (imaging processing in the embodiment) using the pulse signal enables continuous synchronization processing of the specific processing.

In the above embodiment, the explanation was given on the premise that the counter is an increment counter. Similar statements are applicable.

100: synchronous imaging system, 111: synchronous communication device, 220: synchronization signal generator, 321: second counter, 430: pulse output unit, 640: pulse generator, 640: B flag, 650: A flag

Claims (10)

A communication device,
a counter configured to increment a counter value at the timing of an external clock and set the counter value to a predetermined minimum value when the counter value exceeds a predetermined maximum value;
a correction unit that corrects the counter value of the counter;
The counter value of the counter is compared with a predetermined specified value, and when the counter value exceeds the specified value, the level of a pulse signal having a low level and a high level is switched and output, and the specified value is output. and a signal control unit that updates by adding a predetermined value to
When the correcting unit performs correction such that the counter falls below the minimum value, or when the updated specified value becomes equal to or greater than a predetermined maximum specified value that the specified value can take, the signal The control unit does not output the pulse signal for a certain period of time based on the counter value;
A communication device characterized by: When the correcting unit corrects the counter so as to fall below the minimum value, the counter adds the maximum value to the counter value after the correction, and the signal control unit adds the counter value to the counter value. 2. The communication apparatus according to claim 1, wherein the pulse signal is not output until the counter value becomes equal to or greater than the maximum value after the maximum value is added. The signal control unit is
setting a first flag to 1 when the correcting unit corrects the counter so as to fall below the minimum value;
setting the first flag to 0 when the counter value becomes equal to or greater than the maximum value after the counter adds the maximum value to the corrected counter value;
2. The communication apparatus according to claim 1, wherein the pulse signal is not output while the first flag is set to 1. When the updated specified value is greater than or equal to the maximum specified value, the signal control unit updates the specified value to a predetermined initial value, and after the specified value is updated to the initial value, the 4. The communication device according to any one of claims 1 to 3, wherein the pulse signal is not output until the counter value reaches or exceeds the maximum value. The signal control unit sets a second flag to 1 when the specified value is updated to the initial value, and after the specified value is updated to the initial value, the counter value is equal to or greater than the maximum value. When it becomes, the second flag is set to 0,
5. The communication apparatus according to claim 4, wherein the pulse signal is not output while the second flag is set to 1. 6. The signal control unit sets the specified value so that the counter value does not exceed the specified value while the pulse signal is not output. The communication device according to . 7. The maximum specified value according to claim 6, wherein the maximum specified value is a value larger than the maximum value of the counter value, and the signal control section sets the specified value to the maximum specified value. Communication device. 7. The communication apparatus according to any one of claims 1 to 6, wherein the value by which the counter value is incremented by the counter is a period value of the external clock. 9. The communication device according to any one of claims 1 to 8, wherein said predetermined value to be added to said specified value is variably set. 10. The apparatus according to any one of claims 1 to 9, further comprising a generation section that generates a processing synchronization signal for predetermined processing based on the pulse signal output from the signal control section. Communication device.

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