JP2023050449A - Circuit board and manufacturing method thereof - Google Patents

Abstract

To provide a highly reliable circuit board.SOLUTION: A circuit board includes a ceramic substrate 2, a circuit pattern 4a bonded to the surface of the ceramic substrate 2 and made of a metal material, and a solder resist 6 formed on the surface of the ceramic substrate 2 and covering a part of the circuit pattern 4a. The surface roughness Rz of the circuit pattern 4a is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern 4a is 10 or more and 120 or less.SELECTED DRAWING: Figure 14

Description

TECHNICAL FIELD The present invention relates to a circuit board and its manufacturing method, and more particularly to a circuit board having a circuit pattern on a ceramic substrate and its manufacturing method.

2. Description of the Related Art Conventionally, semiconductor modules in which a plurality of semiconductor chips are mounted on a circuit board have been produced. In a general circuit board, a circuit pattern made of a metal material is bonded to the front surface of a ceramic substrate, and a radiator plate is bonded to the rear surface of the ceramic substrate. A part of the circuit pattern is covered with a solder resist, and a semiconductor chip, wire bonding, and the like are provided in a region of the circuit pattern exposed from the solder resist. For example, when a semiconductor chip is provided on the surface of a circuit pattern, a conductive paste such as solder is used to electrically connect the back electrode of the semiconductor chip and the circuit pattern. Moreover, various wiring methods are performed on the circuit pattern, such as electrically connecting the surface electrode of the semiconductor chip and the circuit pattern by wire bonding.

For example, Patent Literature 1 discloses a circuit board in which wettability and corrosion resistance of the surface of a circuit pattern are improved in consideration of contact with wire bonding using leadless solder. The surface of this circuit pattern is chemically polished and then treated with an antirust agent. Further, Patent Document 1 discloses that the surface roughness Ra of the circuit pattern subjected to such processing is 0.1 to 1.0 μm.

Japanese Patent No. 4760251

When mounting a semiconductor module, a heat load is applied to the circuit board due to various mounting processes. The heat load and the like may cause the solder resist to peel off from the circuit pattern. When the solder resist peels off, the insulation between the circuit pattern, the semiconductor chip, the wire bonding and the conductive paste cannot be maintained, and short circuits may occur. That is, the reliability of the semiconductor module may deteriorate.

Therefore, it is desired to provide a highly reliable circuit board by suppressing peeling of the solder resist. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A circuit board in one embodiment comprises a ceramic substrate, a circuit pattern bonded to the surface of the ceramic substrate and made of a metal material, and a part of the circuit pattern formed on the surface of the ceramic substrate. and a solder resist covering the Here, the surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern is 10 or more and 120 or less.

A method for manufacturing a circuit board according to one embodiment comprises: (a) a step of preparing a ceramic substrate; (b) a step of bonding a metal plate made of a metal material to the surface of the ceramic substrate after the step (a); (c) after the step (b), pre-treating the metal plate so that the surface roughness of the metal plate is uniform; (d) after the step (c), the metal plate (e) after the step (d), patterning the metal plate to form a circuit pattern, ( f) After the step (e), forming a solder resist on the surface of the ceramic substrate so as to cover part of the circuit pattern. Here, after the step (d), the surface roughness Rz of the metal plate is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the metal plate is 10 or more and 120 or less. In the step (f), the surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern is 10 or more and 120 or less. done in the state.

A method for manufacturing a circuit board according to one embodiment comprises: (a) a step of preparing a ceramic substrate; (b) a step of bonding a metal plate made of a metal material to the surface of the ceramic substrate after the step (a); (c) after the step (b), pre-treating the metal plate so that the surface roughness of the metal plate is uniform; (d) after the step (c), the metal plate (e) after the step (d), patterning the metal plate to form a circuit pattern, ( f) After the step (e), forming a solder resist on the surface of the ceramic substrate so as to cover part of the circuit pattern. Here, after the step (d), the surface roughness Rz of the metal plate is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the metal plate is 10 or more and 120 or less. Become.

According to one embodiment, it is possible to provide a highly reliable circuit board by suppressing peeling of the solder resist.

FIG. 10 is a cross-sectional view of a main part showing a method of manufacturing a circuit board in a study example; FIG. 2 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 1; FIG. 3 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 2; FIG. 10 is a cross-sectional view of a principal part showing a state where a semiconductor chip is mounted on a circuit board of the study example; 4 is a flow chart showing a method of manufacturing a circuit board according to Embodiment 1. FIG. FIG. 4 is a perspective view showing the method of manufacturing the circuit board according to Embodiment 1; FIG. 7 is a perspective view showing the method of manufacturing the circuit board continued from FIG. 6 ; FIG. 8 is a cross-sectional view of a main part of FIG. 7; FIG. 9 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 8; FIG. 10 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 9; FIG. 11 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 10; FIG. 12 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 11; FIG. 13 is a perspective view showing the method of manufacturing the circuit board continued from FIG. 12; FIG. 14 is a cross-sectional view of a main part showing the method of manufacturing the circuit board continued from FIG. 13; FIG. 15 is a perspective view showing the method of manufacturing the circuit board continued from FIG. 14; FIG. 16 is a cross-sectional view taken along line AA of FIG. 15; 2 is a cross-sectional view showing a state where a semiconductor chip is mounted on the circuit board of Embodiment 1; FIG. FIG. 18 is a cross-sectional view of a main part of FIG. 17; It is a SEM image which shows the surface of the metal plate in a study example. 4 is an SEM image showing the surface of the metal plate in Embodiment 1. FIG. 4 is a table showing experimental data in Embodiment 1. FIG. 4 is a graph showing experimental data in Embodiment 1. FIG.

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

Also, the X-, Y-, and Z-directions described herein cross each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure.

(Embodiment 1)
<Matters studied by the inventors of the present application>
As a method for suppressing the peeling of the solder resist as described above, the inventors of the present application performed a treatment (roughening treatment) to roughen the surface of the metal plate serving as the basis of the circuit pattern, thereby separating the circuit pattern and the solder resist. A method for improving the adhesion of the adhesive was investigated. As a result, it has been found that this method is also effective in comparison with the conventional technique, but the inventors of the present application have found that simply performing the roughening treatment causes various problems. 1 to 4, examples of studies conducted by the inventors of the present application will be described in detail below.

FIG. 1 shows the state immediately after the metal plate 4 is joined to the surface of the ceramic substrate 2 via the brazing material layer 3 and before the roughening treatment. FIG. 2 shows the state after the metal plate 4 has been roughened. The metal plate 4 is, for example, a rolled copper foil formed by rolling.

As shown in FIG. 1, a plurality of rolling marks 20 (a plurality of concave portions) are present on the surface of the metal plate 4, and the depth of each rolling mark 20 is uneven. In this state, as shown in FIG. 2, the metal plate 4 is roughened. The roughening treatment is performed using an aqueous solution composed of, for example, water, hydrogen peroxide, sulfuric acid and phosphoric acid. In this aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, the mass percent concentration of sulfuric acid is 5%, and the mass percent concentration of phosphoric acid is 3%. By this roughening treatment, wet etching progresses along the crystal grain boundaries from the rolling marks 20, and the concave portions on the surface of the metal plate 4 become deeper.

Next, as shown in FIG. 3, an etching process is performed using a resist pattern as a mask to pattern the metal plate 4 and the brazing material layer 3 to form a circuit pattern 4a. Next, a solder resist 6 is formed on the surface of the ceramic substrate 2 so as to partially cover the circuit pattern 4a. Since the solder resist 6 is formed so as to fill in the recesses on the surface of the circuit pattern 4a that have been deepened by the roughening treatment, the adhesion between the solder resist 6 and the circuit pattern 4a is improved, and the solder resist 6 adheres to the circuit pattern 4a. It becomes difficult to peel off from.

Thereafter, by dividing the ceramic substrate 2, a plurality of circuit boards are manufactured. As shown in FIG. 4, when manufacturing a semiconductor module using the circuit board, for example, a semiconductor chip 11 is attached to a region of the circuit pattern 4a exposed from the solder resist 6 via a conductive paste 10. to be installed.

Here, the surface of the circuit pattern 4a is roughened by the roughening treatment, and the concave portion of the surface of the circuit pattern 4a is deepened. Furthermore, the depths of the plurality of recesses are non-uniform. If the conductive paste 10 is formed on the surface of the circuit pattern 4a in such a state, there is a possibility that the conductive paste 10 may not be completely embedded in the concave portions. That is, voids 21 as shown in FIG. 4 may occur.

If such voids 21 are generated, for example, the air accumulated in the voids 21 expands due to the thermal load during mounting of the semiconductor module, and cracks occur in the conductive paste 10 starting from the voids 21 . There is fear. That is, in the study example, although the peeling of the solder resist 6 can be improved by the roughening treatment, there is a problem that the voids 21 are likely to occur.

Therefore, there is a demand for a technique that can suppress the peeling of the solder resist 6 and also suppress the generation of voids 21 . The circuit board 1 described below was proposed by the inventors of the present application in consideration of the problems in the studied examples.

<Circuit board in Embodiment 1>
5 to 16, a method for manufacturing the circuit board 1 according to the first embodiment will be described, and a circuit manufactured by the manufacturing method will be described with reference to FIGS. 17, 18, and 20 to 22. Features of the substrate 1 will be described. FIG. 5 is a flow chart showing a method for manufacturing the circuit board 1. As shown in FIG. 6 to 16 will be used as necessary when describing steps S1 to S9 shown in FIG.

First, in step S1, a ceramic substrate 2 as shown in FIG. 6 is prepared. The ceramic substrate 2 is made of a sintered body of a material having a high thermal conductivity and a high heat radiation effect, such as a sintered body of silicon nitride.

In step S2, as shown in FIG. 7, a metal plate 4 is bonded to the front surface of the ceramic substrate 2 with a brazing material layer 3 interposed therebetween, and a radiator plate ( metal plate) 5 are joined. The metal plate 4 and the heat sink 5 are, for example, rolled copper foils formed by rolling. More specifically, the metal material forming the metal plate 4 and the heat sink 5 is, for example, copper (Cu) or a copper alloy containing copper as a main component, such as Cu--Zr or Cu--Ni.

The brazing material forming the brazing material layer 3 is made of a conductive material such as Ag--Cu containing Ti, Zr or Hf. The metal plate 4 and the heat sink 5 are joined to the ceramic substrate 2 by brazing. First, after a brazing material is applied to the surface of the ceramic substrate 2, the metal plate 4 is adhered to the brazing material, and heat treatment is performed at, for example, 700 to 900° C. depending on the composition ratio of Ag/Cu. It is bonded to the surface of the ceramics substrate 2 via the brazing material layer 3 . By performing the same method for the heat sink 5 , the heat sink 5 is bonded to the back surface of the ceramic substrate 2 with the brazing material layer 3 interposed therebetween.

FIG. 8 is a cross-sectional view of the main part, enlarging the surface of the metal plate 4 of FIG. As shown in FIG. 8 , a plurality of rolling marks 20 are present on the surface of the metal plate 4 .

In step S<b>3 , the metal plate 4 is subjected to a treatment (pretreatment) for uniformizing the surface roughness of the metal plate 4 . That is, since the depths of the plurality of rolling marks 20 (the depths of the plurality of recesses) are uneven, the plurality of rolling marks 20 are removed as much as possible to make the depths of the plurality of recesses uniform.

The pretreatment is performed using, for example, a first aqueous solution composed of water, hydrogen peroxide and sulfuric acid. In this first aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, and the mass percent concentration of sulfuric acid is 8%. The first aqueous solution may contain phosphoric acid with a mass percent concentration of 0.3% or less. In such a first aqueous solution, the effect of chemically polishing the metal plate 4 in the depth direction is small, and the effect of chemically polishing the metal plate 4 in the planar direction is large. Therefore, the effect of making the surface roughness of the metal plate 4 uniform is increased.

FIG. 9 shows the state of the metal plate 4 after pretreatment. By wet-etching the metal plate 4 with the first aqueous solution for a predetermined period of time, the thickness of the metal plate 4 becomes slightly thinner and the surface roughness of the metal plate 4 becomes uniform as compared with that in FIG.

In step S<b>4 , the metal plate 4 is subjected to roughening treatment for roughening the surface of the metal plate 4 . In other words, the roughening process is a process for increasing the surface roughness of the metal plate 4 .

The roughening treatment is performed using, for example, a second aqueous solution composed of water, hydrogen peroxide, sulfuric acid and phosphoric acid. In this second aqueous solution, the mass percent concentration of hydrogen peroxide is 3%, the mass percent concentration of sulfuric acid is 5%, and the mass percent concentration of phosphoric acid is 3%. The mass percent concentration of phosphoric acid contained in the second aqueous solution is preferably higher than the mass percent concentration of phosphoric acid contained in the second aqueous solution. In such a second aqueous solution, the effect of chemical polishing in the depth direction of the metal plate 4 is large, so the depth of the plurality of concave portions is increased.

FIG. 10 shows the state of the metal plate 4 after roughening treatment. By wet-etching the metal plate 4 with the second aqueous solution for a predetermined time, the surface roughness of the metal plate 4 is increased. Here, the roughening treatment was performed until the surface roughness Rz of the metal plate 4 became 2.0 μm or more and 6.5 μm or less.

The surface roughness of the metal plate 4 is made uniform by the pretreatment, and the surface roughness Rz of the metal plate 4 is increased by the roughening treatment in a state where the depths of the plurality of concave portions are made uniform. For this reason, since it is difficult to form a portion where the recess is extremely deep, voids are less likely to occur when the conductive paste is formed.

In steps S5 and S6, the metal plate 4 is patterned to form the circuit pattern 4a. First, in step S5, as shown in FIG. 11, a resist pattern RP1 is formed on the surface of the metal plate 4 by photolithography so as to be in direct contact with the metal plate 4 and partially cover the metal plate 4. Form.

Next, in step S6, as shown in FIG. 12, the circuit pattern 4a is formed by etching the metal plate 4 exposed from the resist pattern RP1. Subsequently, the brazing material layer 3 formed under the etched metal plate 4 is also etched to remove the brazing material layer 3 and expose the ceramic substrate 2 . After that, the resist pattern RP1 is removed using a sodium hydroxide aqueous solution or the like.

By roughening the surface of the metal plate 4 by the roughening process in step S4, the adhesion between the metal plate 4 and the resist pattern RP1 used in steps S5 and S6 can be enhanced. Therefore, problems such as displacement of the resist pattern RP1 or peeling of the resist pattern RP1 during the etching process can be prevented.

In step S7, the ceramic substrate 2 is subjected to a laser scribing process. As shown in FIG. 13, a plurality of circuit patterns 4a are formed on the surface of the ceramic substrate 2. As shown in FIG. The ceramic substrate 2 is finally divided, and grooves are formed in the ceramic substrate 2 by previously irradiating the laser along the scribe lines SL where the division is made. Formation of this groove facilitates the division processing in step S9 that will be described later.

In step S8, as shown in FIG. 14, a solder resist 6 is formed on the surface of the ceramic substrate 2 so as to partially cover the circuit pattern 4a. First, a solder resist 6 is formed by, for example, screen printing or coating so as to cover the entire surface of the ceramic substrate 2 . Next, a part of the solder resist 6 is removed by performing exposure processing and development processing.

Note that the solder resist 6 may be formed as follows. For example, the solder resist 6 may be formed by forming a solder resist pattern using a printing plate corresponding to the region where the solder resist 6 is to be formed, and exposing the solder resist pattern. In this case, development processing can be omitted.

The solder resist 6 thus formed is in direct contact with the circuit pattern 4a. The surface roughness Rz of the circuit pattern 4a is 2.0 μm or more and 6.5 μm or less due to the pretreatment and roughening treatment. Accordingly, since the solder resist 6 is in contact with the circuit pattern 4a with high adhesion, the solder resist 6 is difficult to peel off from the circuit pattern 4a.

In step S9, as shown in FIG. 15, a plurality of circuit boards 1 are manufactured by dividing the ceramic substrate 2 along the scribe lines SL. FIG. 16 is a cross-sectional view taken along line AA of FIG. 15 and shows one circuit board 1. As shown in FIG. A region of the circuit pattern 4a exposed from the solder resist 6 includes, for example, a region for forming a semiconductor chip via a conductive paste.

After that, in step S10, the plurality of circuit boards 1 are subjected to visual inspection and the like. The circuit board 1 determined to be non-defective is subjected to packing work and the like, and the circuit board 1 is shipped.

<Main Features of Circuit Board 1>
FIG. 17 shows a state in which a semiconductor chip 11 and a heat sink 12 are mounted on the circuit board 1 of FIG. 16, and FIG. 18 is a fragmentary sectional view enlarging the periphery of the semiconductor chip 11 of FIG. As shown in FIGS. 17 and 18, the semiconductor chip 11 is mounted via the conductive paste 10 on the area exposed from the solder resist 6 in the circuit pattern 4a. The conductive paste 10 is made of lead-free solder, for example. Also, the heat sink 12 is bonded to the heat sink 5 . Moreover, although not shown, other wiring forms are also performed on the circuit pattern 4a, such as electrically connecting the surface electrodes of the semiconductor chip 11 and the circuit pattern 4a with terminals for external connection such as wire bonding. there is

As described with reference to FIG. 4 in the study example above, the circuit board 1 is required to suppress peeling of the solder resist 6 and suppress the generation of voids 21 . The inventors of the present application focused on the surface roughness Rz and the glossiness (60°) as indicators for countering these problems, and found that the surface roughness Rz and the glossiness (60°), peeling of the solder resist 6 and voids An experiment was conducted on the relationship with the occurrence of 21.

FIGS. 19 and 20 are SEM images showing the surface of the metal plate 4 after the roughening treatment in step S4, FIG. 19 showing a study example, and FIG. 20 showing the first embodiment. 19 and 20 respectively show an SEM image with a magnification of 250 times (with a scale of 200 μm per scale) and an SEM image with a scale of 2500 × with a scale of 20.0 μm per scale. ) and 21 and 22 are tables and graphs showing experimental data in Embodiment 1. FIG.

Comparing FIGS. 19 and 20, in Embodiment 1, the surface roughness of the metal plate 4 is made uniform by performing the pretreatment in step S3 before the roughening treatment in step S4. I was able to confirm that.

Further, as shown in FIGS. 21 and 22, when the glossiness (60°) is 120 or less, peeling of the solder resist 6 can be suppressed, and when the surface roughness Rz is 6.5 μm or less, voids 21 It was found that the occurrence of Also, if the surface roughness Rz is too small, the solder resist 6 is likely to peel off. In order to secure the adhesion between the solder resist 6 and the circuit pattern 4a, the surface roughness Rz is preferably 2.0 μm or more. Moreover, if the glossiness (60°) is 10 or more, it is possible to suppress the surface roughness Rz from becoming too large.

The surface roughness Rz described in this application conforms to JISB0601:2001, and the glossiness (60°) described in this application conforms to JIS Z8741. In addition, a surface roughness meter (TOUCH50: manufactured by Tokyo Seimitsu) is used as a measuring device for surface roughness Rz, and a handy type gloss meter (PG-IIM: manufactured by Nippon Denshoku Kogyo) is used as a measuring device for glossiness. It was used. The surface roughness Rz and the glossiness (60°) of the metal plate 4 are measured at a total of five points, ie, the central portion (one point) and the edge portion (four points). The central portion is the position where the diagonal lines from the four corners on the surface of the metal plate 4 intersect, and the edge is the position 15 mm inward from each corner of the metal plate 4 in the direction toward the central portion. Each numerical value of surface roughness Rz and glossiness (60°) described in the present application is an average value of the above five points.

In summary, after performing the pretreatment in step S3 and the roughening treatment in step S4, the surface roughness Rz of the metal plate 4 is preferably 2.0 μm or more and 6.5 μm or less. The glossiness (60°) of the plate is preferably 10 or more and 120 or less.

The formation of the solder resist 6 in step S8 is such that the surface roughness Rz of the circuit pattern 4a is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern 4a is 10 or more and 120°. It is done under the following conditions: Also when the semiconductor chip 11 is mounted on the circuit pattern 4a via the conductive paste 10, the surface roughness Rz and glossiness (60°) of the circuit pattern 4a are within the above range.

As described above, the pretreatment of step S3 and the roughening treatment of step S4 are performed on the metal plate 4, and the circuit pattern 4a formed by patterning the metal plate 4 is used to obtain a solder resist. 6 can be suppressed, and the generation of voids 21 can be suppressed when the conductive paste 10 is formed. Therefore, according to Embodiment 1, it is possible to provide a highly reliable circuit board 1 .

Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments, and can be variously modified without departing from the scope of the invention.

REFERENCE SIGNS LIST 1 circuit board 2 ceramic substrate 3 brazing material layer 4 metal plate 4a circuit pattern 5 heat sink (metal plate)
6 solder resist 10 conductive paste 11 semiconductor chip 12 heat sink 20 rolling marks 21 void RP1 resist pattern SL scribe line

Claims (10)

a ceramic substrate;
a circuit pattern bonded to the surface of the ceramic substrate and made of a metal material;
a solder resist formed on the surface of the ceramic substrate and covering a portion of the circuit pattern;
with
The surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less,
The circuit board, wherein the glossiness (60°) of the circuit pattern is 10 or more and 120 or less. In the circuit board according to claim 1,
A circuit board, wherein a region of the circuit pattern exposed from the solder resist includes a region for mounting a semiconductor chip via a conductive paste. In the circuit board according to claim 1 or 2,
The circuit board, wherein the solder resist is in direct contact with the circuit pattern. In the circuit board according to any one of claims 1 to 3,
The circuit board, wherein the metal material is copper or a copper-based alloy. (a) preparing a ceramic substrate;
(b) a step of joining a metal plate made of a metal material to the surface of the ceramic substrate after the step (a);
(c) after the step (b), pre-treating the metal plate so that the surface roughness of the metal plate is uniform;
(d) after the step (c), roughening the metal plate so as to increase the surface roughness of the metal plate;
(e) forming a circuit pattern by patterning the metal plate after the step (d);
(f) forming a solder resist on the surface of the ceramic substrate so as to cover part of the circuit pattern after the step (e);
with
After the step (d), the surface roughness Rz of the metal plate becomes 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the metal plate becomes 10 or more and 120 or less,
In the step (f), the surface roughness Rz of the circuit pattern is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the circuit pattern is 10 or more and 120 or less. A method of manufacturing a circuit board, which is carried out. In the method for manufacturing a circuit board according to claim 5,
The step (e) is
(e1) forming a resist pattern on the surface of the metal plate so as to be in direct contact with the metal plate and partially cover the metal plate;
(e2) forming a circuit pattern by etching the metal plate exposed from the resist pattern after the step (e1);
(e3) removing the resist pattern after the step (e2);
A method of manufacturing a circuit board, comprising: In the method for manufacturing a circuit board according to claim 5 or 6,
The method of manufacturing a circuit board, wherein the area of the circuit pattern exposed from the solder resist includes an area for mounting a semiconductor chip via a conductive paste. In the method for manufacturing a circuit board according to any one of claims 5 to 7,
In the step (f), the method of manufacturing a circuit board, wherein the solder resist is in direct contact with the circuit pattern. In the method for manufacturing a circuit board according to any one of claims 5 to 8,
The method for manufacturing a circuit board, wherein the metal material is copper or an alloy mainly composed of copper. (a) preparing a ceramic substrate;
(b) a step of joining a metal plate made of a metal material to the surface of the ceramic substrate after the step (a);
(c) after the step (b), pre-treating the metal plate so that the surface roughness of the metal plate is uniform;
(d) after the step (c), roughening the metal plate so as to increase the surface roughness of the metal plate;
(e) forming a circuit pattern by patterning the metal plate after the step (d);
(f) forming a solder resist on the surface of the ceramic substrate so as to cover part of the circuit pattern after the step (e);
with
After the step (d), the surface roughness Rz of the metal plate is 2.0 μm or more and 6.5 μm or less, and the glossiness (60°) of the metal plate is 10 or more and 120 or less. Substrate manufacturing method.

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