JP2023041449A - Display device - Google Patents

Abstract

To provide a display device capable of suppressing an off-leak current in a selector circuit.SOLUTION: A display device 1 includes: a plurality of pixels 110 arranged in a matrix; a plurality of data voltage lines Sig arranged at each of pixel columns different from one another in the plurality of pixels 110 and for writing data voltage Vdat corresponding to image data; a data driver 13 that supplies the data voltage Vdat to the plurality of data voltage lines Sig; and selector circuit 120 that is connected between the plurality of data voltage lines Sig and the data driver 13 and has a plurality of selection transistors TSeg for switching the data voltage line Sig to which the data voltage Vdat from the data driver 13 is supplied. Each of the plurality of selection transistors TSeg has an oxide semiconductor layer to be a channel layer 232.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to display devices.

Conventionally, a selector circuit that distributes a signal voltage (data voltage) corresponding to a gradation value output from a signal output circuit (data driver) to a plurality of signal lines (a plurality of data voltage lines) in a time division manner has been used. A display device provided with such a display device is known (see, for example, Patent Literature 1). The selector circuit has a plurality of thin film transistors.

JP 2011-221255 A

By the way, in a display device including a selector circuit, after the data voltage line is charged with the data voltage, until the pixel (pixel circuit) is started to be charged with the data voltage (the write transistor is turned on), the data voltage is turned on. The data voltage line becomes floating. Therefore, when an off-leak current occurs in the thin film transistor of the selector circuit, the charge on the data voltage line in the floating state leaks through the thin film transistor in the off state, and the potential of the data voltage line may fluctuate.

If the data voltage on the data voltage line fluctuates before the data voltage starts to be charged to the pixel, the pixel cannot be charged with the desired data voltage, and the display brightness corresponding to the data voltage output by the data driver cannot be achieved. occurs.

Thus, holding the data voltage in the data voltage line in the floating state, that is, suppressing the off-leakage current is important for the display brightness. Patent Document 1 does not disclose suppression of off-leakage current of the selector circuit.

Accordingly, the present disclosure provides a display device capable of suppressing off-leakage current in the selector circuit.

A display device according to an aspect of the present disclosure includes a plurality of pixels arranged in a matrix, and a plurality of data for writing data voltages corresponding to image data arranged in different pixel columns in the plurality of pixels. a voltage line, a data driver for supplying the data voltage to the plurality of data voltage lines, and a data driver connected between the plurality of data voltage lines and the data driver for supplying the data voltage from the data driver. a selector circuit having a plurality of select transistors for switching voltage lines, each of the plurality of select transistors having an oxide semiconductor layer serving as a channel layer.

According to the display device according to one embodiment of the present disclosure, it is possible to realize a display device capable of suppressing off-leakage current in a selector circuit.

1 is a block diagram showing an example of a functional configuration of a display device according to Embodiment 1. FIG. FIG. 2 is an enlarged view of the dashed line area in FIG. 3 is a circuit diagram showing an example of the configuration of a pixel circuit of the display device according to Embodiment 1. FIG. 4 is a cross-sectional view schematically showing an example of the configuration of a pixel circuit of the display device according to Embodiment 1. FIG. 5 is a timing chart of various control signals of the display device according to Embodiment 1. FIG. FIG. 6 is an enlarged view of a region corresponding to the dashed line region in FIG. 1 in the display device according to the second embodiment. FIG. 7 is a timing chart of various control signals of the display device according to the second embodiment. FIG. 8 is a perspective view showing the appearance of the display device according to each embodiment. FIG. 9 is a diagram for explaining the off-leakage current of a polysilicon semiconductor TFT.

(Circumstances leading to this disclosure)
Prior to explaining the present disclosure, the circumstances leading to the present disclosure will be described.

A display device including a selector circuit normally charges a data voltage line of each sub-pixel (each sub-pixel circuit) with a data voltage in a time division manner during one horizontal period. A pixel is composed of a plurality of sub-pixels. Next, by turning on the write signal (for example, the control signal WS shown in FIG. 1), the data voltage of the data voltage line is charged to the storage capacitor of the pixel (pixel circuit). Charging is done simultaneously in each sub-pixel.

As described in "Problem to be Solved by the Invention", the data voltage line charged with the data voltage through the selector circuit is in a floating state until the pixel starts to be charged. Maintaining the data voltage charged on the line becomes important for display brightness. In this specification, the floating state means that the data voltage line is electrically cut off.

From the viewpoint of emphasizing high-speed operation, a polysilicon semiconductor TFT (Thin Film Transistor) is generally used as the thin film transistor that constitutes the selector circuit. However, the polysilicon semiconductor TFT has a relatively large off-leakage current due to leakage caused by crystal defects, etc., and the charged charge of the data voltage line in the floating state leaks through the polysilicon semiconductor TFT in the off state. Potential fluctuations can occur.

As a result, the data voltage charged to the data voltage line fluctuates before the writing transistor of the pixel is turned on, causing a problem that the pixel cannot be charged with a desired data voltage. Such an off-leakage current of the selector circuit is a factor of display luminance deviation (luminance unevenness), so it is desirable to suppress it.

Here, the temperature dependence of the off-leakage current of the polysilicon semiconductor TFT will be described with reference to FIG. FIG. 9 is a diagram for explaining the off-leakage current of a polysilicon semiconductor TFT. FIG. 9 shows the relationship between the off-leakage current (SEL_Ioff) of the polysilicon semiconductor TFT and the panel temperature (that is, the temperature of the polysilicon semiconductor TFT). The vertical axis shown in FIG. 9 indicates the off-leak current ratio (SEL_Ioff ratio) of the polysilicon semiconductor TFT, and the horizontal axis indicates the temperature. RT (Room Temperature) on the horizontal axis indicates room temperature (for example, 20 to 30° C.), and the off-leakage current ratio is the off-leakage when the temperature is room temperature +α (RT+α) based on the off-leakage current at room temperature. Indicates the current ratio. α is a positive number.

As shown in FIG. 9, in polysilicon semiconductor TFTs, the off-leakage current tends to increase as the temperature increases. Also, an increase in off-leakage current can occur to the same extent in polysilicon semiconductor TFTs connected to the data voltage lines of R (Red), G (Green), and B (Blue).

In this way, polysilicon semiconductor TFTs are considered unsuitable for display devices that can be used in high-temperature ranges (for example, vehicle-mounted display devices) from the viewpoint of suppressing the off-leakage current of the selector circuit.

The off-leakage current of a polysilicon semiconductor TFT tends to depend on process control (control of Si crystallinity) at the time of manufacturing, and there is a limit to how much the existing technology can reduce it. In addition, the correction system (external IC) for correcting the off-leakage current of the polysilicon semiconductor TFT increases in cost due to an increase in the scale of the mounted circuit, the complexity of the system, and the like.

Factors that cause an off-leakage current include subthreshold leakage current (drain-source leakage), gate leakage current (gate insulating film leakage), GIDL (Gate-Induced-Drain-Leakage current) current, and junction leakage. Generation of current (crystalline defect leakage current) is exemplified.

Therefore, the inventors of the present application conducted extensive research on a display device having a selector circuit capable of suppressing the off-leakage current of the selector circuit, and invented the display device described below.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. It should be noted that each embodiment described below is a specific example of the present disclosure. Therefore, numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, and the like shown in the following embodiments are examples and are not intended to limit the present disclosure. Therefore, among the constituent elements in each of the following embodiments, the constituent elements not described in the independent claims of the present disclosure will be described as optional constituent elements.

Each figure is a schematic diagram and is not necessarily strictly illustrated. Moreover, in each figure, the same code|symbol is attached|subjected to the substantially same structure, and the overlapping description is abbreviate|omitted or simplified.

In addition, in this specification, terms that indicate the relationship between elements such as identical and parallel, numerical values, and numerical ranges are not expressions that express only strict meanings, but substantially equivalent ranges, such as numbers % (for example, about 10%).

(Embodiment 1)
[1-1. Configuration of display device]
First, the configuration of the display device according to the present embodiment will be described with reference to FIGS. 1 to 3. FIG. FIG. 1 is a block diagram showing an example of a functional configuration of a display device 1 according to this embodiment. FIG. 2 is an enlarged view of a region including the dashed line region R in FIG. In FIG. 2, each sub-pixel is written as a "pixel" for convenience. In the following description, for the sake of brevity, the same reference numerals may be used to refer to a signal and a wiring that transmits the signal. Note that each transistor below will be described as an example configured by an n-type thin film transistor (n-type TFT), but may be configured by a p-type thin film transistor (p-type TFT).

As shown in FIG. 1, the display device 1 includes a display panel 10, a control section 20, and a power supply 30. The display panel 10 also has a display section 11 , a first gate driver 12 a , a second gate driver 12 b , a data driver 13 , and a selector circuit (data selector circuit) 120 . 1 shows only the pixels 110 (corresponding to the sub-pixels 110R shown in FIG. 2) connected to the data voltage line R_Sig among the data voltage lines B_Sig, G_Sig and R_Sig.

The display unit 11 has a plurality of pixels 110 arranged in a matrix, each having light emitting elements EL _B , _ELG and EL _R (see FIG. 3). Each row of the matrix is provided with a control signal line (gate control line) commonly connected to a plurality of pixels 110 arranged in the same row, and each column of the matrix is provided with a plurality of pixels 110 arranged in the same column. Data voltage lines B_Sig, G_Sig and R_Sig commonly connected to 110 are provided. Hereinafter, when the data voltage lines B_Sig, G_Sig, and R_Sig are not distinguished, or the data voltage lines B_Sig, G_Sig, and R_Sig are collectively referred to as the data voltage lines Sig.

The data voltage line B_Sig is connected to each sub-pixel 110B belonging to a pixel column including one or more sub-pixels 110B (see FIG. 2), and has the function of supplying the data voltage Vdat_b (see FIG. 3) to each sub-pixel 110B. have Note that the sub-pixel 110B is, for example, a sub-pixel that emits blue. Each sub-pixel 110B connected to one data voltage line B_Sig constitutes one sub-pixel column (first sub-pixel column).

The data voltage line G_Sig is connected to each sub-pixel 110G belonging to a pixel column including one or more sub-pixels 110G (see FIG. 2), and has the function of supplying a data voltage Vdat_g (see FIG. 3) to each sub-pixel 110G. have The sub-pixel 110G is, for example, a sub-pixel emitting green. Each sub-pixel 110G connected to one data voltage line G_Sig constitutes one sub-pixel column (second sub-pixel column).

The data voltage line R_Sig is connected to each sub-pixel 110R belonging to a pixel column including one or more sub-pixels 110R, and has a function of supplying a data voltage Vdat_r (see FIG. 3) to each sub-pixel 110R. The sub-pixel 110R is, for example, a sub-pixel that emits red. Each sub-pixel 110R connected to one data voltage line R_Sig constitutes one sub-pixel column (third sub-pixel column).

One pixel row includes a first sub-pixel row, a second sub-pixel row, and a third sub-pixel row.

In this way, the data voltage lines Sig are arranged for different sub-pixel columns in the plurality of pixels 110, and are provided for charging (writing) the data voltages corresponding to the image data to the sub-pixels 110B, 110G, and 110R. be done. Note that hereinafter, it is also described as writing to charge.

As shown in FIG. 2, the selector circuit 120 is connected between the data voltage line Sig and the data driver 13, and switches the data voltage line Sig supplying the data voltage from the data driver 13 in a time division manner. The selector circuit 120 has a plurality of switch units 120a. For example, the switch unit 120a is connected between a data voltage line Sig and a data IC (Integrated Circuit) 13a, and transfers data from one data IC 13a constituting the data driver 13 to one of the selected data voltage lines Sig. It has the function of selectively supplying voltage. The switch unit 120a has selection transistors TSeg _B , TSeg _G , and TSeg _R which are thin film transistors arranged for each pixel column and arranged for each sub-pixel column. The select transistors TSeg _B , TSeg _G , and TSeg _R are switch transistors that switch connections between the data voltage lines Sig and the data driver 13 . In the following, when the select transistors TSeg _B , TSeg _G , and TSeg _R are not distinguished, or the select transistors TSeg _B , TSeg _G , and TSeg _R are collectively referred to as the select transistor TSeg.

One of the source and drain electrodes of the select transistor TSeg _B is connected to the data voltage line B_Sig, and the other of the source and drain electrodes is connected to the data IC 13a. Also, the gate electrode of the select transistor TSeg _B is connected to the selector control line SEL1.

One of the source and drain electrodes of the select transistor TSeg _G is connected to the data voltage line G_Sig, and the other of the source and drain electrodes is connected to the data IC 13a. Also, the gate electrode of the select transistor TSeg _G is connected to the selector control line SEL2.

One of the source and drain electrodes of the select transistor TSeg _R is connected to the data voltage line R_Sig, and the other of the source and drain electrodes is connected to the data IC 13a. Also, the gate electrode of the select transistor TSeg _R is connected to the selector control line SEL3.

An oxide semiconductor TFT is used for each of the selection transistors TSeg _B , TSeg _G , and TSeg _R. In other words, no polysilicon semiconductor TFT is used for each of the select transistors TSeg _B , TSeg _G and TSeg _R. Oxide semiconductor TFTs have a characteristic of low leak current (off-leak current) compared to polysilicon semiconductor TFTs. The leakage current of oxide semiconductor TFTs is generally about two orders of magnitude lower than that of polysilicon semiconductor TFTs.

Note that an oxide semiconductor material containing at least one of indium (In), gallium (Ga), and zinc (Zn) can be used as the material of the oxide semiconductor layer that constitutes the oxide semiconductor TFT. For example, the oxide semiconductor layer is a compound of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) (eg, indium gallium zinc oxide (InGaZnO: IGZO)), In, Sn (or Tin), Zn, and O compounds (for example, (InSnZnO: ITZO)), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin oxide (ITO), or indium oxide (InO) The oxide semiconductor layer may be made of other metal oxides, and the material is not particularly limited.

Since the selector circuit 120 includes oxide semiconductor TFTs, the off-leakage current from each select transistor TSeg is suppressed in the floating state after each data voltage line Sig is charged with the data voltages Vdat_b, Vdat_g, and Vdat_r. , the potential fluctuation of each data voltage line Sig can be suppressed. Therefore, in the display device 1, the data voltages Vdat_b, Vdat_g, and Vdat_r of the data voltage lines Sig are less likely to fluctuate before writing to the pixels 110, and the pixels 110 are charged to the desired data voltages Vdat_b, Vdat_g, and Vdat_r. can do. Note that hereinafter, when the data voltages Vdat_b, Vdat_g, and Vdat_r are not distinguished, or the data voltages Vdat_b, Vdat_g, and Vdat_r are collectively referred to as the data voltage Vdat.

Note that polysilicon semiconductor TFTs are used for the selection transistors TSeg _B , TSeg _G , and TSeg _R of the selector circuit 120 from the viewpoint of emphasizing high-speed operation, and oxide semiconductor TFTs are usually used. do not have. In the present embodiment, the light-emitting elements EL _B , _ELG , and _ELR are organic EL (Electro Luminescence) light-emitting elements, and the brightness is controlled by the pixel current. shift) has a large effect on the display brightness. For example, the display panel 10 including an organic light emitting diode (OLED) has a greater influence on the display luminance due to the gray scale deviation of the data voltage Vdat than the liquid crystal panel which adjusts the display luminance by voltage.

Therefore, in the display device 1 according to the present embodiment, the selection transistors TSeg _B , TSeg _G and TSeg _R uses an oxide semiconductor TFT instead of a polysilicon semiconductor TFT.

_In the selector circuit 120 _, the data IC 13a ( _data driver 13) is supplied to the data voltage line Sig in a time division manner. The selector circuit 120 is a column switching circuit (sub-pixel column switching circuit) that switches electrical connection between the data IC 13a and the data voltage line Sig. Note that the selector control lines SEL1, SEL2, and SEL3 are hereinafter simply referred to as selector control lines SEL.

A control signal SEL for controlling the selector circuit 120 is supplied from the control section 20 to the selector control line SEL. For example, the selector control line SEL1 is connected to the gate electrode of the select transistor TSeg _B , and a control signal SEL1 for controlling on/off of the select transistor TSeg _B is supplied from the control unit 20 to the selector control line SEL1. Further, for example, the selector control line SEL2 is connected to the gate electrode of the select transistor TSeg _G , and a control signal SEL2 for controlling on/off of the select transistor TSeg _G is supplied from the control unit 20 to the selector control line SEL2. be. Further, for example, the selector control line SEL3 is connected to the gate electrode of the select transistor TSeg _R , and a control signal SEL3 for controlling on/off of the select transistor TSeg _R is supplied from the control unit 20 to the selector control line SEL3. be. The selector control line SEL is an example of a first selector control line, and the control signal SEL is an example of a selector control signal.

For example, when the control signal SEL1 input to the selector control line SEL1 changes from low level to high level, the selection transistor TSeg _B is turned on, and the data voltage Vdat_b from the data IC 13a is applied to the data voltage line B_Sig. supplied. Next, when the control signal SEL2 input to the selector control line SEL2 changes from low level to high level after the control signal SEL1 input to the selector control line SEL1 changes from high level to low level, the selection transistor TSeg _B is turned off. In addition, since the select transistor TSeg _G is turned on, the data voltage Vdat_g from the data IC 13a is supplied to the data voltage line G_Sig. Next, when the control signal SEL3 input to the selector control line SEL3 changes from low level to high level after the control signal SEL2 input to the selector control line SEL2 changes from high level to low level, the selection transistor TSeg _G is turned off. In addition, since the select transistor TSeg _R is turned on, the data voltage Vdat_r from the data IC 13a is supplied to the data voltage line R_Sig.

In this manner, the switch section 120a performs the operation of holding the data voltage Vdat in the data voltage line Sig connected to the switch section 120a in a time division manner. Thus, one data IC 13a can cause each of the data voltage lines Sig to hold the data voltage Vdat corresponding to the pixel current supplied to each of the light emitting elements _ELB , _ELG , and _ELR .

Note that the switch section 120a is not limited to selectively switching between the three data voltage lines Sig, and may be configured to selectively switch between two or more data voltage lines Sig. Such a switch section 120a has the same number of selection transistors TSeg as the number of data voltage lines Sig to be switched.

Referring to FIG. 1 again, the control unit 20 is a circuit that controls the display panel 10, receives a video signal from the outside, and controls the display unit 11 so that an image represented by the video signal is displayed on the display unit 11. The first gate driver 12a, the second gate driver 12b, the data driver 13, and the selector circuit 120 are controlled. For example, the control unit 20 supplies a control signal SEL for controlling the selector circuit 120 to the selector control line SEL. The control unit 20 is connected to the selector control line SEL.

The power supply 30 supplies power for operating the display device 1 to each part of the display device 1 . The power supply 30 supplies operating power to the display unit 11, the first gate driver 12a, the second gate driver 12b, the data driver 13, the control unit 20, and the selector circuit 120, for example. Also, the power supply 30 supplies the display unit 11 with, for example, an initialization voltage VINI, a reference voltage (reference voltage) VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH.

The first gate driver 12a and the second gate driver 12b supply various control signals for controlling the operation of the pixels 110 to the pixels 110 via control signal lines. The first gate driver 12a and the second gate driver 12b function as scanning line driving circuits.

Note that the control signal lines include the write signal line WS, the initialization signal line INI, and the reference signal line REF. The write signal line WS is an example of a gate control line, is arranged for each pixel row different from each other in the plurality of pixels 110, and is used to select a pixel row (for example, a sub-pixel row) to which a data voltage corresponding to image data is written. of control signals WS are supplied. The write signal lines WS include, for example, write signal lines WS1, WS2, WSn−1, and WSn (n is the number of rows, eg, an integer of 2 or more). The initialization signal line INI is arranged for each different pixel row in the plurality of pixels 110, and is supplied with a control signal INI for initializing the potentials of the light emitting elements _ELB , _ELG , and _ELR . The reference signal line REF is arranged for each pixel row different from each other in the plurality of pixels 110, and is a control signal for supplying the reference voltage VREF to the gate electrodes of the drive transistors TD _R , TD _G , and TD _B (see FIG. 3). REF is supplied.

The first gate driver 12a includes an INI signal gate driver 12a1, a Ref signal gate driver 12a2, and a WS signal gate driver 12a3. Each of the INI signal gate driver 12a1, the Ref signal gate driver 12a2, and the WS signal gate driver 12a3 includes a plurality of shift registers. The shift register is composed of, for example, a CMOS (Complementary metal-oxide-semiconductor) circuit or a polysilicon thin film transistor in which thin film transistors used are either N-channel or P-channel, but is limited to this. not.

The second gate driver 12b includes an INI signal gate driver 12b1, a Ref signal gate driver 12b2, and a WS signal gate driver 12b3.

The INI signal gate drivers 12a1 and 12b1 are connected to the gate electrodes of the initialization transistors T1 _R , T1 _G and T1 _B (see FIG. 3) via an initialization signal line INI. It is a gate driver for performing an initialization operation for initializing potentials of respective electrodes (for example, anodes) of the elements EL _R , _ELG and EL _B. The INI signal gate drivers 12a1 and 12b1 control on/off of the initialization transistors T1 _R , T1 _G and T1 _B by the control signal INI. The INI signal gate drivers 12a1 and 12b1 receive the control signal INI from both sides of the initialization signal line INI. Note that the initialization operation is performed before the threshold compensation operation.

The Ref signal gate drivers 12a2 and 12b2 are connected to the gate electrodes of the compensation transistors T2 _R , T2 _G and T2 _B (see FIG. 3) via the reference signal line REF, and the drive transistors TD _R and TD _G are connected to the respective gate electrodes. and a gate driver for performing a threshold compensation operation for compensating the threshold voltage of the _TDB . The Ref signal gate drivers 12a2 and 12b2 control the on/off of the compensation transistors T2 _R , T2 _G and T2 _B with the control signal REF. The Ref signal gate drivers 12a2 and 12b2 each receive the control signal REF from both sides of the reference signal line REF.

Note that hereinafter, when the drive transistors TD _R , TD _G , and TD _B are not distinguished, or the drive transistors TD _R , TD _G , and TD _B are collectively referred to as the drive transistor TD.

The WS signal gate drivers 12a3 and 12b3 are connected to the gate electrodes of the write transistors _T3R , _T3G and _T3B (see FIG. 3) via write signal lines WS, and the data voltages Vdat_r, Vdat_g and Vdat_b are connected. are held in the holding capacitors _CSR , CS _G and CS _B, respectively. The WS signal gate drivers 12a3 and 12b3 supply control signals WS for turning on and off the write transistors _T3R , _T3G and _T3B to the write signal lines WS. The WS signal gate drivers 12a3 and 12b3 receive the control signal WS from both sides of the write signal line WS.

In the following description, when the storage capacitors _CSR , _CSG , and _CSB are not distinguished, the storage capacitors _CSR , _CSG , and _CSB are collectively referred to as the storage capacitor CS. The holding capacitor CS is an example of a capacitive element.

Hereinafter, when the write transistors T3 _R , T3 _G , and T3 _B are not distinguished, or the write transistors T3 _R , T3 _G , and T3 _B are collectively referred to as the write transistor T3.

Referring to FIG. 1 again, the data driver 13 supplies the data voltage corresponding to the light emission luminance to the pixels 110 via the data voltage line Sig. A data voltage is a voltage signal based on the display gradation of the pixel 110 . The data driver 13 outputs the data voltage to the data voltage line Sig via the selector circuit 120 in a time-division manner, thereby driving the circuit elements of the light-emitting pixels. The data driver 13 functions as a signal line driving circuit.

Next, the plurality of pixels 110 will be described with reference to FIG. FIG. 3 is a circuit diagram showing an example of the configuration of the pixel circuit of the display device 1 according to this embodiment.

As shown in FIG. 3, the pixel (pixel circuit) 100 includes sub-pixels (sub-pixel circuits) 110R, 110G, and 110B. The sub-pixels 110R, 110G, and 110B have the same configuration as each other except for the light-emitting elements _ELB , _ELG , and _ELR . The configuration of the pixel circuit will be described below, focusing on the sub-pixel 110R. Hereinafter, when the light-emitting elements EL _B , _ELG , and _ELR are not distinguished, or the light-emitting elements EL _B , _ELG , and _ELR are collectively referred to as the light-emitting elements EL.

The sub-pixel 110R has an initialization transistor T1 _R , a compensation transistor T2 _R , a write transistor T3 _R , a storage capacitor _CSR , a drive transistor TD _R , and a light emitting element EL _R. The initialization transistor T1 _R , the compensation transistor T2 _R , the write transistor T3 _R , and the drive transistor _TDR are examples of thin film transistors forming the pixel 110 . The sub-pixel 110R also has control signal lines (initialization signal line INI, reference signal line REF, write signal line WS), data voltage line R_Sig, positive power line VCC, and cathode power line VCATH. Note that the initialization transistor T1 _R and the compensation transistor T2 _R are not essential components.

At least one of the initialization transistor T1 _R , compensation transistor T2 _R , write transistor T3 _R , and drive transistor TD _R has a semiconductor layer (channel layer) made of polysilicon or amorphous silicon. For example, the initialization transistor T1 _R , compensation transistor T2 _R , write transistor T3 _R , and drive transistor TD _R may all have semiconductor layers formed of polysilicon or amorphous silicon. At least one of the initialization transistor T1 _R , compensation transistor T2 _R , write transistor T3 _R , and drive transistor _TDR may have a semiconductor layer (channel layer) made of an oxide semiconductor. . For example, the pixel 110 may be formed by mixing a polysilicon semiconductor TFT and an oxide semiconductor TFT. For example, a polysilicon semiconductor TFT is used for one of the write transistor T3 _R and the drive transistor TD _R , and an oxide semiconductor TFT is used for the other of the write transistor T3 _R and the drive transistor TD _R. good too.

Thus, each of the plurality of pixels 110 may include a plurality of thin film transistors, with at least one thin film transistor using a polysilicon semiconductor TFT and at least one other thin film transistor using an oxide semiconductor TFT. . Moreover, each of the plurality of pixels 110 thus includes a thin film transistor, and the thin film transistor has a channel layer formed of polysilicon or amorphous silicon.

The initialization transistor _T1R is turned on according to the control signal INI, and supplies the initialization voltage VINI to the source electrode (source node) of the drive transistor _TDR . A gate electrode of the initialization transistor _T1R is connected to each of the INI signal gate drivers 12a1 and 12b1.

The compensation transistor _T2R is turned on according to the control signal REF, and supplies the reference voltage VREF to the gate electrode (gate node) of the driving transistor _TDR . This corresponds to initializing the potential of the electrode (eg, anode) of the light emitting element _ELR . The gate electrode of the compensation transistor _T2R is connected to each of Ref signal gate drivers 12a2 and 12b2.

The write transistor _T3R is turned on according to the control signal WS, and causes the holding capacitor _CSR to hold the data voltage Vdat_r. The gate electrode of the write transistor T3- _R is connected to the WS signal gate drivers 12a3 and 12a3.

The write transistor _T3R is connected between the data voltage line R_Sig and the gate electrode of the drive transistor _TDR . Specifically, one of the source and drain electrodes of the write transistor _T3R is connected to the data voltage line R_Sig, the other of the source and drain electrodes is connected to one of the source and drain electrodes of the compensation transistor _T2R , and It is connected to the gate electrode of the drive transistor _TDR .

The holding capacitor _CSR holds the data voltage Vdat_r supplied via the data voltage line R_Sig.

One of the source and drain electrodes of the drive transistor _TDR is connected to the positive power supply line VCC, the other of the source and drain electrodes is connected to the anode of the light emitting element _ELR , and the data voltage stored in the storage capacitor _{CSR is} A current is supplied to the light emitting element EL _R according to Vdat_r. As a result, the light emitting element EL _R emits light with luminance corresponding to the data voltage Vdat_r.

The light-emitting element EL _R is a self-luminous light-emitting element, and is an organic EL light-emitting element (organic EL element) in the present embodiment. An anode electrode of the light emitting element EL _R is connected to one of a source electrode and a drain electrode of the driving transistor _TDR . A cathode voltage (negative power supply voltage) is applied to the cathode electrode of the light emitting element EL _R by a cathode power supply line (negative power supply line) VCATH.

Note that the gate potential _VgR shown in FIG. 3 indicates the potential of the gate electrode of the drive transistor _TDR , and the source potential _VsR indicates the potential of the source electrode of the drive transistor _TDR .

Here, the cross-sectional configuration of the pixel circuit of the display device 1 will be described with reference to FIG. FIG. 4 is a cross-sectional view schematically showing an example of the configuration of the pixel circuit of the display device 1 according to this embodiment. The display panel 10 is an organic EL panel having a top emission structure.

As shown in FIG. 4, in the display panel 10, the TFT layer 10a is formed on the substrate 211, the interlayer insulating layer 10b is formed on the TFT layer 10a, and the EL layer 10c is formed on the interlayer insulating layer (flattening layer) 10b. is formed. A protective film, a sealing resin, and a sealing substrate may be laminated in this order on the EL layer 10c (not shown).

Substrate 211 is, for example, a glass substrate or a glass film. A plurality of pixels (pixel circuits) 110 are formed on the substrate 211 .

The TFT layer 10a has channel layers 232 and 242, insulating layers 212, 213, 214 and 215, gate electrodes 231 and 241, drain electrodes 233 and 243, and source electrodes 234 and 244b.

The insulating layer 212 is provided so as to cover the surface of the substrate 211 . A channel layer 242 , a drain electrode 243 , and a source electrode 244 are provided over the insulating layer 212 .

The insulating layer 213 is provided so as to cover the channel layer 242 , the drain electrode 243 , the source electrode 244 , and the insulating layer 212 . Gate electrodes 231 and 241 are provided over the insulating layer 213 .

The insulating layer 214 is provided to cover the gate electrodes 231 and 241 and the insulating layer 213 . The insulating layer 214 is a gate insulating layer. A channel layer 232 , a drain electrode 233 , and a source electrode 234 are provided over the insulating layer 214 .

The insulating layer 215 is provided so as to cover the channel layer 232 , the drain electrode 233 , the source electrode 234 , and the insulating layer 214 . An interlayer insulating layer 10 b is provided on the insulating layer 215 .

The EL layer 10c is composed of a metal layer 216 that is an anode, a light-emitting layer 217, an insulating layer 218, and a metal layer 219 that is a cathode. The insulating layer 218 is a bank (partition wall) that partitions the substrate 211 on which the light emitting layer 217 is formed. The insulating layer 218 is made of, for example, an organic material. The insulating layer 218 is made of a photosensitive thermosetting resin. Further, the surface of the insulating layer 218 may be subjected to liquid-repellent treatment using fluorine plasma or the like.

The select transistor TSeg is composed of a gate electrode 231 , a channel layer 232 , a drain electrode 233 , a source electrode 234 and part of the insulating layer 214 . The channel layer 232 is composed of an oxide semiconductor layer. It can also be said that the select transistor TSeg has an oxide semiconductor layer that serves as the channel layer 232 . Also, the thin film transistor that constitutes the pixel 110 is composed of, for example, the gate electrode 241, the channel layer 242, the drain electrode 243, the source electrode 244, and part of the insulating layer 213. FIG. The channel layer 242 is composed of a polysilicon semiconductor layer. It can also be said that the thin film transistor forming the pixel 110 has a polysilicon semiconductor layer that serves as the channel layer 242 .

The channel layer 232 of the select transistor TSeg is provided in the insulating layer 214 (an example of the first layer) formed on the substrate 211, and the channel layer 242 of the thin film transistor is provided in the insulating layer 213 (second layer) formed on the substrate 211. layer) and is provided in an insulating layer 213 different from the insulating layer 214 . That is, the channel layers 232 and 242 are formed in different layers when the display panel 10 is viewed in cross section.

[1-2. Timing chart]
FIG. 5 is a diagram showing a timing chart of various control signals of the display device 1 according to this embodiment. Specifically, (a) of FIG. 5 shows a timing chart of gate control signals (control signals INI, REF, and WS), and (b) of FIG. 5 shows a timing chart of selector control signals (control signals SEL1 to SEL3 ) is shown in the timing chart. Note that the timing chart shown in FIG. 5 is a timing chart for one pixel row.

As shown in (a) of FIG. 5, time t1 to time t4 is the extinguishing period. At time t1, the control signal REF goes from low level to high level to turn on the compensation transistors T2 _R , T2 _G and T2 _B , thereby starting the extinguishing period. Time t2 to time t3 is an initialization period during which the control signal REF is at low level, the control signal INI is at high level, and the initialization operation is performed. Time t3 to time t4 is a threshold compensation period (Vth compensation period) during which the control signal REF is at high level, the control signal INI is at low level, and the threshold compensation operation is performed.

Time t4 to time t5 shown in (b) of FIG. 5 are periods in which the data voltage is supplied to each of the data voltage lines Sig in time series. From time t4 to time t5, the data voltage line Sig is selectively charged with the data voltage Vdat by the selector circuit 120 before the data write period. For example, from time t4 to time t5, the data voltages connected to the data IC 13a are synchronized with the timing at which the data voltages Vdat_b, Vdat_g, and Vdat_r of the data IC 13a are sequentially output by the control signal SEL supplied from the control unit 20. By selectively switching the lines B-Sig, G-Sig, and R-Sig, the data voltages Vdat_b, Vdat_g, and Vdat_r are applied to the data voltage lines B-Sig, G-Sig, and R-Sig, respectively. are charged.

From time t5 to time t6, the control signal SEL is at low level, so the data voltage line Sig is in a floating state. Also, from time t5 to time t6, since the control signal WS is at high level, the write transistors T3 _R , T3 _G , and T3 _B are turned on, and the data voltage line Sig is applied to the storage capacitors CS _R , CS _G , and CS _B, respectively. , the data voltage Vdat held in each is written. A period from time t5 to time t6 is a data write period. The data write period is a period that can directly affect the pixel current (sub-pixel current) that controls the gradation display.

Note that the light-off period is a period for initial setting, specifically a period in which the sub-pixel circuit is not lit (that is, black display). Assuming that there are n pixel rows and one horizontal period is 1H, the off period is a period defined by n×H, for example. Note that "black display" is not limited to being completely black (non-luminous), but includes being substantially black, and may also include, for example, having a predetermined luminance or less.

Between time t4 and time t5, a period P1 is a period from when the data voltage line B_Sig is charged with the data voltage Vdat_b to when the data write period starts, and the data voltage line B_Sig is in a floating state. It is a period of time. The period P1 is also a period during which the data voltage lines G_Sig and R_Sig are charged with the data voltages Vdat_g and Vdat_b, respectively. When an off-leak current occurs in the select transistor TSeg _B in period P1, the data voltage Vdat_b charged in the data voltage line B_Sig fluctuates. Therefore, it is desired that the off-leak current in the select transistor TSeg _B is suppressed. In this embodiment, since the select transistor TSeg _B has the oxide semiconductor layer that serves as the channel layer 232, off-leakage current can be suppressed as compared with the case where the select transistor TSeg B has the polysilicon semiconductor layer that serves as the channel layer 232. be.

A period P2 is a period from when the data voltage line G_Sig is charged with the data voltage Vdat_g to when the data write period is started, and is a period during which the data voltage line G_Sig is in a floating state. The period P2 is also a period during which the data voltage line R_Sig is charged with the data voltage Vdat_r. In the period P2, when an off-leak current occurs in the select transistor TSeg _G , the data voltage Vdat_g charged in the data voltage line G_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _G. In this embodiment, since the select transistor TSeg _G has an oxide semiconductor layer that serves as the channel layer 232, off-leakage current can be suppressed as compared with the case where the select transistor TSeg G has a polysilicon semiconductor layer that serves as the channel layer 232. be.

A period P3 is a period from when the data voltage line R_Sig is charged with the data voltage Vdat_r to when the data write period is started, and is a period in which the data voltage line R_Sig is in a floating state. If an off-leak current occurs in the select _transistor TSeg _R in the period P3, the data voltage Vdat_r charged in the data voltage line R_Sig fluctuates. In this embodiment, the select transistor TSeg _R has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSegR has a polysilicon semiconductor layer that serves as the channel layer 232. be.

As described above, in the present embodiment, since each of the select transistors TSeg _B , TSeg _G , and TSeg _R is an oxide semiconductor TFT, the off-leakage current in each of the periods P1 to P3 can be suppressed. .

Further, in the display device 1 according to the present embodiment, the off-leakage current can be suppressed only by changing the channel layer 232 of each select transistor TSeg included in the selector circuit 120 from a polysilicon semiconductor layer to an oxide semiconductor layer. can. That is, the display device 1 can suppress the off-leakage current at low cost without increasing the scale of the mounted circuit or complicating the system.

[1-3. effects, etc.]
As described above, the display device 1 according to the present embodiment includes the plurality of pixels 110 arranged in a matrix, and the data voltage Vdat corresponding to the image data, which is arranged for each pixel column different from each other in the plurality of pixels 110 . a plurality of data voltage lines Sig for writing data, a data driver 13 for supplying a data voltage Vdat to the plurality of data voltage lines Sig, and a data driver 13 connected between the plurality of data voltage lines Sig and the data driver 13 . and a selector circuit 120 having a plurality of selection transistors TSeg for switching the data voltage line Sig that supplies the data voltage Vdat from . Each of the multiple select transistors TSeg has an oxide semiconductor layer that serves as the channel layer 232 .

Accordingly, in the display device 1, since the plurality of select transistors TSeg have the oxide semiconductor layer that serves as the channel layer 232, off-leakage is reduced compared to the case where the plurality of select transistors TSeg has the polysilicon semiconductor layer that serves as the channel layer 232. Current can be suppressed. Therefore, the display device 1 can suppress the off-leakage current of the selector circuit 120 .

Also, each of the plurality of pixels 110 has a thin film transistor, and the thin film transistor has a polysilicon semiconductor layer that serves as the channel layer 242 .

This enables the pixel 110 to be driven at high speed.

Also, each of the plurality of pixels 110 has a light emitting element EL and a storage capacitor CS that holds the data voltage Vdat supplied via the data voltage line Sig. The thin film transistor has a drive transistor TD that supplies a current corresponding to the data voltage Vdat to the light emitting element EL, and a write transistor T3 connected between the data voltage line Sig and the gate electrode of the drive transistor TD. One of the drive transistor TD and the write transistor T3 has a polysilicon semiconductor layer that serves as the channel layer 242, and the other of the drive transistor TD and the write transistor T3 has an oxide semiconductor layer that serves as the channel layer 242. have

This makes it possible to suppress off-leak current in the pixel 110 (in the pixel circuit) while maintaining high-speed operation in the pixel 110 .

The display device 1 also includes a substrate 211 on which a plurality of pixels 110 are formed. The channel layers 232 of the plurality of select transistors TSeg are provided in the insulating layer 215 formed on the substrate 211, and the channel layers 242 of the thin film transistors are the insulating layers 213 and 215 formed on the substrate 211. is provided in an insulating layer 213 different from the

This makes it possible to easily form the select transistor TSeg and the thin film transistor included in the pixel 110 which are made of different materials.

Also, the light-emitting element EL is an organic EL element.

As a result, off-leakage current of the selector circuit 120 can be suppressed in the display panel 10 (organic EL panel) having organic EL elements that are greatly affected by grayscale deviation (data voltage Vdat deviation) with respect to the data voltage Vdat. Therefore, the display device 1 can effectively suppress the display brightness deviation caused by the off-leakage current of the selector circuit 120 .

(Embodiment 2)
The display device according to the present embodiment will be described below with reference to FIGS. 6 and 7. FIG. In the following, differences from the first embodiment will be mainly described, and descriptions of the same or similar contents as those of the first embodiment will be omitted or simplified.

[2-1. Configuration of display device]
First, the configuration of the display device according to this embodiment will be described with reference to FIG. FIG. 6 is an enlarged view of a region corresponding to the dashed line region R in FIG. 1 in the display device according to the present embodiment. The configuration of the switch section 320a according to the present embodiment is different from that of the switch section 120a according to the first embodiment. Specifically, in the switch unit 120a according to the first embodiment, one thin film transistor (eg, select transistor TSeg _B ) is arranged between one data voltage line (eg, data voltage line B_Sig) and the data IC 13a. However, the switch section 320a according to the present embodiment has two thin film transistors connected in parallel between one data voltage line and the data IC 13a.

As shown in FIG. 6, the switch section 320a has six selection transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB . Each of the select transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB is an oxide semiconductor TFT having an oxide semiconductor layer in the channel layer 232 . The selection transistors TSeg _BA , TSeg _GA , and TSeg _RA are examples of first selection transistors, and the selection transistors TSeg _BB , TSeg _GB , and _TSeg RB are examples of second selection transistors. An example. In the following description, if the select transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB are not distinguished, or if the select transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB are also collectively referred to as selection transistor TSeg.

The select transistors TSeg _BA and TSeg _BB are connected in parallel between the data voltage line B_Sig and the data IC 13a. The input sides of the selection transistors TSeg _BA and _TSeg BB connected in parallel are connected to the data IC 13a, and the output sides of the selection transistors TSeg _BA and _TSeg BB connected in parallel are connected to the data voltage. It is connected with the line B_Sig. One of the source and drain electrodes of the selection transistors TSeg _BA and TSeg _BB connected in parallel is connected to the data IC 13a, and the other of the source and drain electrodes is connected to the data voltage line B_Sig. It can also be said.

A gate electrode of the select transistor TSeg _BA is connected to the selector control line SEL1A, and a gate electrode of the select transistor TSeg _BB is connected to the selector control line SEL1B. That is, the selection transistors TSeg _BA and TSeg _BB can be turned on and off independently of each other. The selector control lines SEL1A and SEL1B are connected to the control section 20. FIG.

The select transistors TSeg _G A and TSeg _G B are connected in parallel between the data voltage line G_Sig and the data IC 13a. The input sides of the select transistors TSeg _GA and TSeg _GB connected in parallel are connected to the data IC 13a, and the output sides of the select transistors TSeg _GA and TSeg _GB connected in parallel are connected to the data voltage. It is connected with the line G_Sig. One of the source and drain electrodes of the selection transistors TSeg _GA and TSeg _GB connected in parallel is connected to the data IC 13a, and the other of the source and drain electrodes is connected to the data voltage line G_Sig. It can also be said.

A gate electrode of the select transistor TSeg _G A is connected to the selector control line SEL2A, and a gate electrode of the select transistor TSeg _G B is connected to the selector control line SEL2B. That is, the selection transistors TSeg _GA and TSeg _GB can be turned on and off independently of each other. The selector control lines SEL2A and SEL2B are connected to the control section 20. FIG.

The selection transistors TSeg _RA and TSeg _RB are connected in parallel between the data voltage line R_Sig and the data IC 13a. The input sides of the select transistors TSeg _RA and TSeg _RB connected in parallel are connected to the data IC 13a, and the output sides of the select transistors TSeg _RA and _TSeg RB connected in parallel are connected to the data voltage. It is connected with the line R_Sig. One of the source and drain electrodes of the select transistors TSeg _RA and TSeg _RB connected in parallel is connected to the data IC 13a, and the other of the source and drain electrodes is connected to the data voltage line R_Sig. It can also be said.

A gate electrode of the select transistor TSeg _RA is connected to the selector control line SEL3A, and a gate electrode of the select transistor TSeg _RB is connected to the selector control line SEL3B. That is, the selection transistors TSeg _RA and TSeg _RB can be turned on and off independently of each other. The selector control lines SEL3A and SEL3B are connected to the control section 20. FIG.

The control unit 20 selects the select transistors TSeg _BA , TSeg _GA and TSeg _RA and the select transistors TSeg _BB , TSeg _GB and TSeg RB by the control signals SEL1A, SEL1B, SEL2A, SEL2B, SEL3A and _SEL3B . selectively turn on. The control unit 20 determines the selection transistors TSeg to be turned on without depending on the brightness (gradation value) of the video indicated by the video signal received from the outside. In addition, the control unit 20 turns on only one select transistor TSeg of the two select transistors TSeg connected in parallel within one frame. In other words, the control unit 20 does not turn on two select transistors TSeg connected in parallel in one frame at the same time or in chronological order. The control unit 20 selectively turns on the selection transistors TSeg _BA , TSeg _GA and TSeg _RA and the selection transistors TSeg _BB , TSeg _GB and TSeg _RB based on preset rules. The details of the control method of the control unit 20 will be described later.

Hereinafter, when the control signals SEL1A, SEL1B, SEL2A, SEL2B, SEL3A, and SEL3B are not distinguished, or the control signals SEL1A, SEL1B, SEL2A, SEL2B, SEL3A, and SEL3B are collectively referred to as the control signal SEL.

[2-2. Timing chart]
A timing chart of the display device including the selector circuit having the switch section 320a configured as described above will be described with reference to FIG. FIG. 7 is a timing chart of various control signals of the display device according to this embodiment. Specifically, (a) of FIG. 7 shows a timing chart of gate control signals (control signals INI, REF, and WS), and (b) of FIG. 7 shows a timing chart of selector control signals (control signals SEL1A to SEL3B ) is shown in the timing chart. Also, FIG. 7 shows a timing chart for two frames in one pixel row.

Time t1 to time t7 shown in FIG. 7 is the first frame (first frame period), time t7 to time t8 is the blanking period, and time t8 to time t14 is the second frame (second frame period). period). The first frame and the second frame are consecutive frames. The timing chart shown in (a) of FIG. 7 is substantially the same as the timing chart shown in (a) of FIG. 5, and the description thereof will be omitted.

As shown in FIG. 7B, the control unit 20 sequentially turns on the select transistors TSeg _BA , TSeg _GA , and TSeg _RA among the select transistors TSeg during time t4 to time t5 of the first frame. Control signals SEL1A, SEL2A, and SEL3A among the control signals SEL output control signals that sequentially become high level.

In the first frame, the control section 20 controls the switch section 320a so that only one of the two selection transistors connected in parallel is turned on. At this time, the control unit 20 supplies an off voltage of 0V or less to the gate electrodes of the select transistors TSeg _BB , TSeg _GB , and TSeg _RB that remain off in the first frame. Based on the control signals SEL1B, SEL2B, and SEL3B, the control unit 20 supplies an off voltage of 0 V or less to the gate electrode of the select transistor that is not turned on (not driven) among the two select transistors connected in parallel. It can be said that

Between time t4 and time t5, the period P1A is the period from when the data voltage line B_Sig is charged with the data voltage Vdat_b to when the data write period starts, and the data voltage line B_Sig is in a floating state. It is a period of time. In period P1A, when an off-leak current occurs in the select transistor TSeg _BA , the data voltage Vdat_b charged in the data voltage line B_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _BA . In the present embodiment, the select transistor TSeg _BA has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSeg BA has a polysilicon semiconductor layer that serves as the channel layer 232. is.

A period P2A is a period from when the data voltage line G_Sig is charged with the data voltage Vdat_g to when the data write period is started, and is a period in which the data voltage line G_Sig is in a floating state. In period P2A, when an off-leak current occurs in the select transistor TSeg _GA , the data voltage Vdat_g charged in the data voltage line G_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _GA . In the present embodiment, the select transistor TSeg _GA has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSegGA has a polysilicon semiconductor layer that serves as the channel layer 232. is.

A period P3A is a period from when the data voltage line R_Sig is charged with the data voltage Vdat_r to when the data write period is started, and is a period in which the data voltage line R_Sig is in a floating state. In the period P3A, when an off-leak current occurs in the select transistor TSeg _RA , the data voltage Vdat_r charged in the data voltage line R_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _RA . In the present embodiment, the select transistor TSeg _RA has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case of having a polysilicon semiconductor layer that serves as the channel layer 232. is.

Next, during time t11 to time t12 of the second frame, the control unit 20 outputs the control signal SEL so as to sequentially turn on the selection transistors TSeg _BB , TSeg _G B, and TSeg _RB among the selection transistors TSeg. Among them, the control signals SEL1B, SEL2B, and SEL3B output control signals that sequentially become high level.

In the second frame, the control section 20 controls the switch section 320a so that only the other of the two selection transistors connected in parallel is turned on. At this time, the control unit 20 supplies an off voltage of 0V or less to the gate electrodes of the select transistors TSeg _BA , TSeg _GA , and TSeg _RA that remain off in the second frame. It can also be said that the control unit 20 supplies an off voltage of 0 V or less to the gate electrode of the select transistor that is not turned on among the two select transistors connected in parallel based on the control signals SEL1A, SEL2A, and SEL3A.

Between time t11 and time t12, a period P1B is a period from when the data voltage line B_Sig is charged with the data voltage Vdat_b to when the data write period starts, and the data voltage line B_Sig is in a floating state. It is a period of time. In the period P1B, when an off-leak current occurs in the select transistor TSeg _BB , the data voltage Vdat_b charged in the data voltage line B_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _BB . In the present embodiment, the select transistor _TSegBB has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSegBB has a polysilicon semiconductor layer that serves as the channel layer 232. is.

A period P2B is a period from when the data voltage line G_Sig is charged with the data voltage Vdat_g to when the data write period is started, and is a period in which the data voltage line G_Sig is in a floating state. In the period P2B, when an off-leak current occurs in the select transistor TSeg _G B, the data voltage Vdat_g charged in the data voltage line G_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _G B. In this embodiment, the select transistor TSeg _G B has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSeg GB has a polysilicon semiconductor layer that serves as the channel layer 232. is.

A period P3B is a period from when the data voltage line R_Sig is charged with the data voltage Vdat_r to when the data write period is started, and is a period in which the data voltage line R_Sig is in a floating state. In period P3B, when an off-leak current occurs in the select transistor TSeg _RB , the data voltage Vdat_r charged in the data voltage line R_Sig fluctuates. Therefore, it is desirable to suppress the off-leak current in the select transistor TSeg _RB . In the present embodiment, the select transistor TSeg _RB has an oxide semiconductor layer that serves as the channel layer 232, so that off-leakage current can be suppressed compared to the case where the select transistor TSeg RB has a polysilicon semiconductor layer that serves as the channel layer 232. is.

In this manner, the control unit 20 controls the selector circuit 120 so that different selection transistors out of the two selection transistors connected in parallel are turned on in the first frame and the second frame. For example, the control unit 20 alternately drives (turns on) one and the other of the two selection transistors connected in parallel every frame, but the method of controlling the selector circuit 120 is not limited to this.

For example, the control unit 20 determines whether or not the cumulative drive time of one select transistor has reached a specific cumulative drive time (for example, a threshold value), and if the cumulative drive time reaches the specific cumulative drive time, , the selection transistor to be driven may be switched from one of the two selection transistors connected in parallel to the other. A specific cumulative driving time is preset. For example, a specific cumulative drive time may be set based on the Vth (threshold voltage) shift limit of the select transistor. Further, for example, the control unit 20 may switch the selection transistor to be driven every horizontal period (1H period). Further, for example, the control unit 20 may switch the selection transistor to be driven for each of multiple frames or multiple horizontal periods.

Note that the cumulative driving time of each of the plurality of selection transistors TSeg may be counted by the control section 20, for example. Alternatively, the control unit 20 may determine whether or not to switch the selection transistor to be driven based on the cumulative drive rank instead of the cumulative drive time.

Note that the control unit 20 controls the selection transistors TSeg _BA , TSeg _BB , TSeg GA, TSeg _GB , TSeg _RA , and _TSeg in periods other than time t4 to time t5 and time t11 to time t12. Each of _RB is controlled to be off. The control unit 20 applies an off-voltage to the gate electrode of each of the selection transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB to turn off each selection transistor in the period. apply. The off voltage may be 0V or a voltage of 0V or less. Further, the off-voltages applied to the selection transistors TSeg _BA , TSeg _BB , TSeg _GA , TSeg _GB , TSeg _RA , and TSeg _RB may be the same voltage or can be different.

[2-3. effects, etc.]
As described above, the plurality of selection transistors TSeg of the display device according to the present embodiment are first selection transistors (for example, select transistor TSeg _B A, etc.) and a second select transistor (eg, select transistor TSeg _B B, etc.).

Accordingly, when only one of the first selection transistor and the second selection transistor is operated when the data voltage line Sig and the data driver 13 are connected, the first selection transistor and the second selection transistor are operated. Since the operation time of each select transistor can be reduced, the life of the multiple select transistors TSeg can be extended. Note that the life here means that the Vth of the plurality of select transistors TSeg shifts by a predetermined voltage or more.

The display device further includes a control section 20 that selectively turns on the first selection transistor and the second selection transistor based on the control signal SEL.

This makes it possible to reduce the operation time of each of the first select transistor and the second select transistor compared to the case where there is one select transistor TSeg provided between the data voltage line Sig and the data driver 13. Therefore, it is possible to extend the life of the plurality of selection transistors TSeg.

Further, the control unit 20 supplies an off voltage of 0 V or less to the gate electrodes of the select transistors that are not turned on among the first select transistor and the second select transistor based on the control signal SEL.

As a result, while the off voltage is being supplied to the gate electrode, the Vth of the selection transistor TSeg to which the off voltage is supplied can be shifted to the low voltage side. While a positive voltage is supplied to the gate electrode of the select transistor TSeg and the select transistor TSeg is turned on, Vth shifts to the high voltage side. Therefore, by applying an off voltage to the selection transistor TSeg that is not turned on, the Vth shifted to the high voltage side of the selection transistor TSeg can be brought closer to the original Vth. Therefore, the life of the plurality of select transistors TSeg can be further extended, leading to improvement in reliability of the display device.

(Other embodiments)
As described above, the display device and the like according to the present disclosure have been described based on each embodiment, but the display device according to the present disclosure is not limited to the above embodiments. Another embodiment realized by combining arbitrary components in each embodiment, and a modification obtained by applying various modifications that a person skilled in the art can think of without departing from the scope of the present disclosure for each embodiment For example, the present disclosure also includes various devices incorporating the display device according to the present embodiment.

For example, the display device 1 according to the present disclosure may be implemented as a thin display device as shown in FIG. 8, for example. FIG. 8 is a perspective view showing the appearance of the display device 1 according to the embodiment. Such a display device 1 can suppress the occurrence of display luminance deviation in the display section 11 due to off-leakage current.

Further, the application of the display device according to each of the above embodiments is not particularly limited. The display device may be used for personal digital assistants, personal computers, televisions, and the like, and may be used for digital signage and the like. The display device may be used, for example, in applications that do not require high-speed driving. Here, high-speed driving means, for example, that the frame rate is 60 fps (frames per second) or higher. Moreover, the display device may be used, for example, for applications in a high temperature range. Oxide semiconductor layers generally have lower temperature dependence of off-leakage current than polysilicon semiconductor layers. That is, the oxide semiconductor layer has a smaller off-leakage current from room temperature to high temperature than the polysilicon semiconductor layer. Therefore, in a display device including such an oxide semiconductor layer, even when the temperature of the display device is high, display luminance deviation due to off-leakage current can be suppressed. In addition, an application used in a high temperature range is, for example, an in-vehicle display device (a display device mounted on an instrument panel or a navigation system), but is not limited to this.

Further, the present disclosure described above may be implemented as a single display panel. The present disclosure may be implemented in a configuration that does not include a power supply and controller. Such a display panel includes a plurality of pixels arranged in a matrix, a plurality of data voltage lines arranged for different pixel columns in the plurality of pixels and used to write data voltages corresponding to image data, and a plurality of data voltage lines. and a selector having a plurality of selection transistors connected between the plurality of data voltage lines and the data driver for switching the data voltage lines that supply the data voltages from the data driver. circuit, and each of the plurality of select transistors is configured to have an oxide semiconductor layer serving as a channel layer. Note that the ICs forming the control unit may be mounted on the display panel.

Further, in each of the above-described embodiments, an example in which the display device includes the first gate driver and the second gate driver has been described. At least one of the gate drivers should be provided. The display device may be configured such that the gate control signal is input from one side.

Further, in each of the above-described embodiments, an example in which the light-emitting element included in the display device is an organic EL element has been described, but the present invention is not limited to this. The light-emitting element may be another self-luminous light-emitting element. The light emitting element may be, for example, a light emitting element using a QLED (Quantum-dot Light Emitting Diode). Also, the display panel may be a non-luminous panel, such as a liquid crystal panel.

Further, in each of the above embodiments, the display panel has a top emission structure, but it may have a bottom emission structure.

Further, each component such as the first gate driver, the second gate driver, the data driver, and the control section in each of the above-described embodiments is configured by dedicated hardware or It may be implemented by executing a software program. Each component may be implemented by a program execution unit such as a processor reading and executing a software program recorded in a recording medium such as a hard disk or semiconductor memory. The processor is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or LSI (Large Scale Integration). Further, the IC may be directly mounted on the TFT substrate of the display panel by COG (Chip On Glass) technology, or may be mounted as FFC (Flexible Flat Cable) or FPC (Flexible Printed Cable) by COF (Chip On Film) technology. ), etc., may be mounted on a flexible wiring board.

Further, in each of the above-described embodiments, an example in which the display device includes the first gate driver and the second gate driver has been described. At least one of the gate drivers should be provided. The display device may be configured such that the gate control signal is input from one side.

Further, the first gate driver and the second gate driver in each of the above embodiments may be realized by one IC, respectively, or the WS signal gate driver, the Ref signal gate driver, and the INI Signal gate drivers may be implemented by different ICs.

Also, the control unit and the data driver in each of the above embodiments may be realized by one IC, or may be realized by different ICs.

The functions and configurations of the initialization transistors _T1G and _T1B in each of the above embodiments are, for example, the same as those of the initialization transistors _T1R , and the functions and configurations of the compensation transistors _T2G and _T2B are, for example, compensation The function and configuration of the write transistors _T3G and T3B are the same as the transistor _T2R , the functions and configurations of the write transistors T3G and _T3B are the same as those of the write transistor _T3R , and the functions and configurations of the drive transistors _TDG and _TDB are the same as those of the drive transistor TD It may be the same as _R.

Further, the functions and configurations of the light emitting elements EL _G and EL _B in each of the above embodiments may be the same as those of the light emitting element EL _R , for example.

Also, the functions and configurations of the holding capacitors CS _G and CS _B in each of the above embodiments may be the same as those of the holding capacitor _CSR , for example.

Moreover, although the display device in each of the above embodiments has been described as an example of displaying a color image, it is not limited to this, and may display a monochrome image, for example.

Also, the write signal lines and the selector control lines in each of the above embodiments may be provided parallel to the pixel rows, for example.

Further, in the above-described second embodiment, an example has been described in which the number of select transistors connected in parallel between one data voltage line and the data driver is two. is not particularly limited, and may be, for example, three or more.

The present disclosure is useful, for example, for display devices using organic EL elements.

1 display device 10 display panel 10a TFT layer 10b interlayer insulating layer 10c EL layer 11 display section 12a first gate driver 12a1, 12b1 INI signal gate driver 12a2, 12b2 Ref signal gate driver 12a3, 12b3 WS signal gate driver 12b second gate driver 13 data driver 13a data IC
20 control unit 30 power supply 110 pixels 110B, 110G, 110R sub-pixels 120 selector circuits 120a, 320a switch unit 211 substrates 212, 213, 214, 215, 218 insulating layers 216, 219 metal layers 217 light-emitting layers 231, 241 gate electrodes 232, 242 Channel layer 233, 243 Drain electrode 234, 244 Source electrode Sig, B_Sig, G_Sig, R_Sig Data voltage line CS, _CSR , CS _G , CS _B storage capacitor EL, EL _R , EL _G , EL _B light emitting element INI Initialization Signal line, control signal P1, P1A, P1B, P2, P2A, P2B, P3, P3A, P3B Period R Dashed line area REF Reference signal line, control signal SEL, SEL1, SEL2, SEL3, SEL1A, SEL1B, SEL2A, SEL2B, SEL3A , SEL3B selector control line, control signals T1 _R , T1 _G , T1 _B initialization transistors T2 _R , T2 _G , T2 _B compensation transistors T3, T3 _R , T3 _G , T3 _B write transistors TD, TD _R , TD _G , TD _B drive transistors TSeg, TSeg _R , TSeg _RA , TSeg _RB , TSeg _G , TSeg _GA , TSeg _GB , TSeg _B , TSeg _BA , TSeg _BB Selection transistors Vdat, Vdat_r, Vdat_g, Vdat_b Data voltage WS, WS1, TS2, TSn-1, TSn Write signal line, control signal

Claims (8)

a plurality of pixels arranged in a matrix;
a plurality of data voltage lines arranged for different pixel columns in the plurality of pixels for writing data voltages corresponding to image data;
a data driver that supplies the data voltages to the plurality of data voltage lines;
a selector circuit connected between the plurality of data voltage lines and the data driver and having a plurality of selection transistors for switching data voltage lines for supplying the data voltages from the data driver;
Each of the plurality of selection transistors has an oxide semiconductor layer serving as a channel layer. each of the plurality of pixels has a thin film transistor,
2. The display device according to claim 1, wherein the thin film transistor has a polysilicon semiconductor layer serving as a channel layer. each of the plurality of pixels,
a light emitting element;
a capacitive element that holds a data voltage supplied via a data voltage line;
the thin film transistor includes a drive transistor that supplies a current corresponding to the data voltage to the light emitting element, and a write transistor connected between the data voltage line and a gate electrode of the drive transistor,
One of the drive transistor and the write transistor has a polysilicon semiconductor layer serving as a channel layer, and the other of the drive transistor and the write transistor has an oxide semiconductor layer serving as a channel layer. 3. The display device according to 2. A substrate on which the plurality of pixels are formed,
the channel layers of the plurality of select transistors are provided in a first layer formed on the substrate;
4. The display device according to claim 2, wherein the channel layer of the thin film transistor is provided in a second layer formed on the substrate and different from the first layer. 5. The plurality of select transistors includes a first select transistor and a second select transistor connected in parallel between the plurality of data voltage lines and the data driver, respectively. 2. The display device according to item 1. 6. The display device according to claim 5, further comprising a control section that selectively turns on said first selection transistor and said second selection transistor based on a selector control signal. The control unit supplies an off voltage of 0 V or less to the gate electrodes of the select transistors that are not turned on among the first select transistor and the second select transistor based on the selector control signal. 7. The display device according to 6. The display device according to claim 3, wherein the light emitting element is an organic EL (Electro Luminescence) element.

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