JP2023040469A - Electro-optical device and electronic apparatus - Google Patents

Abstract

To provide an electro-optical device in which the output voltage of a temperature detection circuit is not easily affected by the parasitic capacitance between a temperature detection element and wiring, and an electronic apparatus.SOLUTION: In an electro-optical device 100, on the outside of a display area 10a, a temperature detection element 11 is provided in which a plurality of diodes D are electrically connected in series by relay parts P1, P2. On the outside of the display area 10a, common potential wiring 8a provided with an opening 8a0 is provided, and the temperature detection element 11 is located inside the opening 8a0 in plan view. With this, a parasitic capacitance with a large capacitance is not present between the relay parts P1,P2 and the common potential wiring 8a. On the inside of the opening 8a0 in plan view, an island-like light-shielding layer 8e on the same layer as the common potential wiring 8a is provided separate from the common potential wiring 8a.SELECTED DRAWING: Figure 7

Description

The present invention relates to an electro-optical device provided with a temperature detection element and an electronic device.

2. Description of the Related Art In an electro-optical device such as a liquid crystal device, a technique has been proposed in which a temperature detecting element is provided outside the display area and driving conditions of the electro-optical device are corrected based on the detection result of the temperature detecting element. In this case, if a signal wiring for supplying an AC signal is provided in the vicinity of the temperature detecting element, the temperature detecting element may be affected by the potential change of the signal wiring, and the temperature detection accuracy may be lowered. Therefore, it has been proposed to provide a constant potential wiring to which a constant potential is applied between the temperature detecting element and the signal wiring as a shield layer.

Japanese Unexamined Patent Application Publication No. 2010-73810

However, even when the constant potential wiring is used as the shield layer, noise may occur in the constant potential applied to the constant potential wiring used as the shield layer when the electro-optical device is driven. As a result, when the temperature detection element is affected by noise through the parasitic capacitance between the constant potential wiring and the temperature detection element, the temperature detection accuracy of the temperature detection element is lowered. Therefore, when the wiring overlaps the temperature detecting element in plan view, there is a problem that the temperature detecting element is easily affected by the parasitic capacitance between the temperature detecting element and the wiring.

In order to solve the above-described problems, one aspect of the electro-optical device according to the present invention provides wiring having an opening provided outside a display area, and wiring provided outside the display area and inside the opening in a plan view. and a temperature detection element.

Another aspect of the electro-optical device according to the present invention includes a temperature detection element provided outside a display area, and wiring having a portion overlapping the temperature detection element in plan view, the temperature detection element a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series, wherein the first diode and the second diode are the first diode; The electrodes are arranged along one direction, and the widths of the semiconductor layers forming the first diode and the semiconductor layers forming the second diode in the direction along the second direction intersecting the first direction are the same. It is characterized by having a portion narrower than the width in the direction along the second direction.

Still another aspect of the electro-optical device according to the present invention includes a temperature detecting element provided outside a display area, a wiring having a portion overlapping the temperature detecting element in a plan view, and an N-channel outside the display area. a complementary transistor having a type transistor and a P-channel type transistor, wherein the temperature sensing element includes a first diode, a second diode, and a series electrical connection between the first diode and the second diode. and an electrode that is electrically connected to the semiconductor layer forming the first diode and the semiconductor layer forming the second diode is separated from the semiconductor layer forming the N-channel transistor and the P-channel transistor It is characterized by being equal to or less than the distance from the semiconductor layer that constitutes the transistor.

Still another aspect of the electro-optical device according to the present invention includes: a plurality of data lines provided in a display area; a common potential wiring having a portion overlapping each of the plurality of data lines in plan view; a temperature detection element overlapping the wiring in plan view on the outside; a selection circuit electrically connected to each of the plurality of data lines; and a control circuit controlling the selection circuit for each horizontal scanning period during a precharge period. and, in the plurality of horizontal scanning periods, a first horizontal scanning period in which a precharge signal is supplied to a part of the plurality of data lines, and another horizontal scanning period different from the part of the plurality of data lines. and a second horizontal scanning period in which the precharge signal is supplied to some data lines.

Still another aspect of the electro-optical device according to the present invention includes: a plurality of data lines provided in a display area; a common potential wiring having a portion overlapping each of the plurality of data lines in plan view; a temperature detection element overlapping the wiring in plan view on the outside; a selection circuit electrically connected to each of the plurality of data lines; and a control circuit controlling the selection circuit for each horizontal scanning period during a precharge period. and a first horizontal scanning period during which the precharge signal is supplied to all of the plurality of data lines and a second horizontal scanning period during which the precharge signal is not supplied to all of the plurality of data lines during the plurality of horizontal scanning periods. and a horizontal scanning period.

An electro-optical device according to the present invention is used in electronic equipment.

1 is a plan view showing a configuration example of an electro-optical device according to Embodiment 1 of the present invention; FIG. FIG. 2 is an explanatory view schematically showing a cross section of the electro-optical device shown in FIG. 1; FIG. 3 is a circuit block diagram showing the electrical configuration of the first substrate shown in FIG. 2; 4 is an explanatory diagram of the data line driving circuit and the like shown in FIG. 3; FIG. 2 is a timing chart when an image is displayed in the electro-optical device shown in FIG. 1; FIG. 4 is an explanatory diagram of the temperature detection circuit shown in FIG. 3; FIG. 7 is an explanatory view schematically showing a cross section of the temperature detection element and the like shown in FIG. 6; Explanatory drawing of the comparative example with respect to Embodiment 1 of this invention. FIG. 5 is a diagram showing the relationship between precharge and the output voltage of the temperature detection circuit; 4 is a graph showing the influence of the parasitic capacitance of the temperature detection element shown in FIG. 3 on the output voltage of the temperature detection circuit; FIG. 5 is an explanatory diagram of an electro-optical device according to Embodiment 2 of the present invention; FIG. 12 is an explanatory diagram schematically showing a cross section of the temperature detection element and the like shown in FIG. 11; FIG. 10 is an explanatory diagram of an electro-optical device according to a modification of the second embodiment of the invention; FIG. 9 is an explanatory diagram of an electro-optical device according to Embodiment 3 of the present invention; FIG. 15 is a cross-sectional view of the temperature detection element shown in FIG. 14; FIG. 11 is an explanatory diagram of an electro-optical device according to Modification 1 of Embodiment 3 of the present invention; FIG. 11 is an explanatory diagram of an electro-optical device according to Modification 2 of Embodiment 3 of the present invention; FIG. 11 is an explanatory diagram of precharging in odd-numbered frames of the electro-optical device according to Embodiment 4 of the present invention; FIG. 11 is an explanatory diagram of precharging in an even-numbered frame of the electro-optical device according to Embodiment 4 of the present invention; FIG. 11 is an explanatory diagram of precharging of an electro-optical device according to Embodiment 5 of the present invention; 1 is a block diagram showing a configuration example of a projection display device to which the present invention is applied; FIG. FIG. 22 is an explanatory diagram of the optical path shift element shown in FIG. 21;

Embodiments of the present invention will be described with reference to the drawings. Note that in the drawings referred to in the following description, each layer and each member has a different scale so that each layer and each member can be recognized on the drawing. Further, when describing the arrangement of layers formed on the first substrate, the upper layer side or surface side means the side opposite to the side of the first substrate where the main body of the first substrate is located (the side where the counter substrate and the liquid crystal layer are located). , and the lower layer side means the side on which the substrate body of the first substrate is located. When describing the arrangement of the layers formed on the second substrate, the upper layer side or surface side means the side opposite to the side of the counter substrate on which the main substrate is located (the side on which the first substrate and the liquid crystal layer are located). , the lower layer side means the side on which the substrate main body of the second substrate is located. In addition, in the present invention, “planar view” means a state seen from the normal direction to the first substrate 10 or the second substrate 20 .

1. Embodiment 1
1-1. 1. Specific Configuration of Electro-Optical Device 100 FIG. 1 is a plan view showing a configuration example of an electro-optical device 100 according to Embodiment 1 of the present invention. FIG. 2 is an explanatory diagram schematically showing a cross section of the electro-optical device 100 shown in FIG. The electro-optical device 100 shown in FIGS. 1 and 2 is a liquid crystal device and has an electro-optical panel 100p made of a liquid crystal panel. In the electro-optical device 100 , the first substrate 10 and the second substrate 20 are bonded together with a predetermined gap by a sealing material 107 , and the sealing material 107 is provided in a frame shape along the outer edge of the second substrate 20 . It is The sealing material 107 is an adhesive made of photocurable resin, thermosetting resin, or the like, and is mixed with a gap material 107a such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. In the electro-optical device 100 , an electro-optical layer 50 made of a liquid crystal layer is provided in a region between the first substrate 10 and the second substrate 20 and surrounded by the sealing material 107 . A discontinuous portion 107c used as a liquid crystal injection port is formed in the sealing material 107, and the discontinuous portion 107c is closed with a sealing material 108 after the liquid crystal material is injected. Note that the discontinuous portion 107c is not formed when the liquid crystal material is sealed by the dropping method. Both the first substrate 10 and the second substrate 20 are rectangular, and a display region 10a is provided as a rectangular region substantially in the center of the electro-optical device 100 . Corresponding to such a shape, the sealing material 107 is also provided in a substantially rectangular shape, and the outer side of the display region 10a is a rectangular frame-shaped outer peripheral region 10c.

In the display region 10a, when the two sides extending in the X direction are the first side 10a1 and the second side 10a2, and the two sides extending in the Y direction are the third side 10a3 and the fourth side 10a4, the first substrate 10, a data line driving circuit 101 is provided between the edge of the first substrate 10 and the first side 10a1 of the display area 10a, and the edge of the first substrate 10 and the first side 10a1 of the display area 10a. An inspection circuit 105 is provided between the two sides 10a2. Scanning line driving circuits 104 are provided between the edge of the first substrate 10 and the third side 10a3 of the display area 10a and between the edge of the first substrate 10 and the fourth side 10a4 of the display area 10a. be provided. Mounting terminals 102 to which the wiring board 70 is electrically connected are arranged at the end of the first substrate 10 on the side of the data line driving circuit 101 . A driving IC 75 including a control circuit 76 for outputting image signals VID1, VID2, . . . , VID2n and selection signals SEL1, SEL2, . The wiring board 70 is electrically connected to the upper circuit 60 via the connector 61 . An image control circuit 65 is provided in the upper circuit 60 . The host circuit 60 is also provided with a temperature detection drive circuit 66 that drives the temperature detection circuit 1, which will be described later. The high-level circuit 60 is provided in a high-level device for the electro-optical device 100 in an electronic device to be described later.

The first substrate 10 has a translucent substrate body 10w such as a quartz substrate or a glass substrate. Pixel electrodes 9a electrically connected to each of the plurality of pixel transistors are formed in a matrix. A first alignment film 16 is formed on the upper layer side of the pixel electrode 9a. On the side of the one surface 10s of the first substrate 10, in the square frame-shaped region 10b extending along between the display region 10a and the sealing material 107, portions extending along each side of the display region 10a are provided. A dummy pixel electrode 9b is formed at the same time as the pixel electrode 9a.

The second substrate 20 has a translucent substrate body 20w such as a quartz substrate or a glass substrate, and a common electrode 21 is formed on one surface 20s of the second substrate 20 . The common electrode 21 is formed on substantially the entire surface of the second substrate 20 on the one surface 20s side. On the side of one surface 20s of the second substrate 20, in the frame-shaped region 10b, a light-shielding partition 29 is formed on the lower layer side of the common electrode 21, and a second alignment film 26 is laminated on the surface of the common electrode 21. ing. The display area 10 a is defined by the inner edge of the parting 29 . A translucent planarizing film 22 is formed between the parting 29 and the common electrode 21 . The light shielding layer forming the parting 29 may be formed as a black matrix portion that overlaps the inter-pixel region 10f sandwiched between the adjacent pixel electrodes 9a. The parting 29 is formed at a position overlapping the dummy pixel electrode 9b in plan view. The parting 29 is made of a light shielding metal film or black resin.

The first alignment film 16 and the second alignment film 26 are, for example, inorganic alignment films made of oblique vapor deposition films such as SiO _X (x≦2), TiO ₂ , MgO, Al ₂ O ₃ and are called columns. The columnar bodies are composed of columnar structure layers formed obliquely with respect to the first substrate 10 and the second substrate 20 . Therefore, the first alignment film 16 and the second alignment film 26 align nematic liquid crystal molecules with negative dielectric anisotropy used in the electro-optic layer 50 obliquely with respect to the first substrate 10 and the second substrate 20 . and the liquid crystal molecules are pretilted. Thus, the electro-optical device 100 is configured as a normally black VA (Vertical Alignment) mode liquid crystal device.

Inter-substrate conduction electrode portions 14 t are formed outside the sealing material 107 on the first substrate 10 at positions overlapping four corner portions 24 t of the second substrate 20 . The inter-substrate conduction electrode portion 14t is electrically connected to the wiring 6g, and the wiring 6g is electrically connected to a terminal 102g of the terminals 102 for supplying the common potential LCCOM. An inter-substrate conduction material 109 containing conductive particles is arranged between the inter-substrate conduction electrode portion 14t and the corner portion 24t. , are electrically connected to the first substrate 10 via the inter-substrate conductive material 109 . Therefore, the common electrode 21 is applied with the common potential LCCOM from the first substrate 10 side.

The plurality of terminals 102 includes terminals 102d, 102h, 102f, 102t, 102s, 102g, 102c and 102a. A terminal 102 d is a terminal for supplying a start pulse SP to the scanning line driving circuit 104 . A terminal 102 h is a terminal for supplying the clock signal CLY to the scanning line driving circuit 104 . A terminal 102 f is a terminal for supplying an output control signal ENBY to the scanning line driving circuit 104 . A terminal 102 t is a terminal for supplying a high-level constant potential VDDY to the scanning line driving circuit 104 . A terminal 102 s is a terminal for supplying a low-level constant potential VSSY to the scanning line driving circuit 104 . A terminal 102g is a terminal for supplying a common potential LCCOM. Cathode terminal 102c and anode terminal 102a are terminals electrically connected to cathode wiring Lc and anode wiring La, respectively, of temperature detection circuit 1, which will be described later with reference to FIG.

The electro-optical device 100 of this embodiment is a transmissive liquid crystal device. Therefore, the pixel electrode 9a and the common electrode 21 are formed of a translucent conductive layer such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. In such a transmissive liquid crystal device, for example, light source light incident from the second substrate 20 side is modulated while being emitted from the first substrate 10 to display an image. If the pixel electrodes 9a are made of a reflective metal such as aluminum, the electro-optical device 100 can be a reflective liquid crystal device.

1-2. 3. Electrical Configuration of Electro-Optical Device 100 FIG. 3 is a circuit block diagram showing the electrical configuration of the first substrate 10 shown in FIG. In FIG. 3, the first substrate 10 has a display area 10a in which a plurality of pixels 100a are arranged in a matrix in a substantially central area. In the first substrate 10, inside the display area 10a, there are a plurality of scanning lines 3a extending in the X direction from the scanning line driving circuit 104 and a plurality of data lines 3a extending in the Y direction from the data line driving circuit 101. Lines 6a are provided, and pixels 100a are formed corresponding to the intersections of the scanning lines 3a and the data lines 6a. The multiple data lines 6a are electrically connected to an inspection circuit 105 arranged on the second side 10a2 side of the display area 10a. A pixel transistor 30 made of an N-channel transistor and a pixel electrode 9a electrically connected to the pixel transistor 30 are formed in each of the plurality of pixels 100a. The data line 6a is electrically connected to the source region of the pixel transistor 30, the scanning line 3a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9a is electrically connected to the drain region of the pixel transistor 30. It is connected to the. The data line driving circuit 101 supplies the image signal VID to the data line 6a and the scanning signal G to the scanning line 3a.

Further, the data line driving circuit 101 is used as part of a precharge circuit 106 that applies a precharge signal to the data lines 6a during a precharge period set at the beginning of each horizontal scanning period, as will be described later. Although not shown, the inspection circuit 105 is a transistor array. The transistor of the inspection circuit 105 has one source/drain region electrically connected to the data line 6a, the other source/drain region electrically connected to an inspection line (not shown), and a gate connected to the inspection circuit 105. It is electrically connected to a control signal line (not shown) inside.

In each pixel 100a, the pixel electrode 9a faces the common electrode 21 of the second substrate 20 described with reference to FIG. Each pixel 100a is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuations in the image signal VID held by the liquid crystal capacitor 50a. In the present embodiment, in order to configure the storage capacitor 55, the common potential wiring 8a extending over the plurality of pixels 100a is formed as a capacity line on the first substrate 10. A common potential LCCOM is supplied. The common potential wiring 8a is provided so as to overlap at least one of the scanning lines 3a and the data lines 6a in plan view. FIG. 3 illustrates a mode in which the common potential wiring 8a overlaps both the scanning lines 3a and the data lines 6a in plan view. The common potential wiring 8a may be configured to overlap the data line 6a of the scanning line 3a and the data line 6a in plan view. In either case, the common potential wiring 8a has a portion overlapping with the data line 6a. In the first substrate 10, the temperature detection circuit 1 is configured outside the display area 10a. In FIG. 3, the scanning line driving circuit 104 arranged on the left side of the display area 10a drives the odd scanning lines 3a, and the scanning line driving circuit 104 arranged on the right side of the display area 10a drives the even scanning lines 3a. , but the same scanning line 3a may be driven by the scanning line driving circuits 104 arranged on the left and right sides, respectively.

1-3. Configuration Example of Data Line Driving Circuit 101 and the Like FIG. 4 is an explanatory diagram of the data line driving circuit 101 and the like shown in FIG. FIG. 5 is a timing chart when displaying an image in the electro-optical device 100 shown in FIG. As shown in FIG. 4, on the first substrate 10, the data line driving circuit 101 is arranged on the side of the first side 10a1 of the display area 10a. Data line driving circuit 101 includes a demultiplexer, and the demultiplexer includes selection circuit 101a as a sample and hold circuit. A data line 6a extends from the selection circuit 101a in the Y direction, that is, toward the second side 10a2 of the display area 10a. The selection circuit 101a includes a transistor 30e that controls electrical connection between the data line 6a and the image signal wiring 6j. In this embodiment, the demultiplexer comprises, for example, eight transistors 30e. Transistor 30e is an N-channel transistor. Therefore, since 1920/8=240 in the FHD standard, 240 demultiplexers are provided. The data line driving circuit 101 transmits an image signal VID from the driving IC 75 shown in FIG.
supply to At this time, the transistor 30e of the selection circuit 101a transmits the image signal VID to each data line 6a based on the selection signals SEL1, SEL2, . It will be supplied in a time-sharing manner.

More specifically, when the electro-optical device 100 displays an image, as shown in FIG. 5, the scanning line driving circuit 104 generates the scanning signals G1 and G2 in the N-th frame period defined by the vertical synchronization signal Vsync. , G3 . . . Gm are sequentially and exclusively set to the selection level every horizontal scanning period H. In the horizontal scanning period H, the selection signals SEL1, SEL2, . supply.

For example, in the horizontal scanning period H when the scanning signal G1 is at the selection level, when the selection signal SEL1 is at the selection level, the scanning line 3a in the first row and the first row in the X direction in each of the plurality of demultiplexers. Voltages corresponding to the image signals VID1, VID2, . Next, when the selection signal SEL2 is at the selection level, it corresponds to the intersection of the scanning line 3a of the first row and the data line 6a positioned second in the first direction in each of the plurality of demultiplexers. Voltages corresponding to the image signals VID1, VID2, . . . VIDn are written to the pixels 100a. Similarly, when the selection signals SEL3 to SEL8 become the selection level, voltages corresponding to the image signals VID1 to VIDn are written to the corresponding pixels 100a.

As for driving the electro-optical device 100, preliminary writing is performed before writing the image signal voltage to the data line 6a in order to improve the display quality. This is generally called precharge. Therefore, at the beginning of the horizontal scanning period H, there is provided a precharge period tp during which the selection signals SEL1, SEL2, . During the precharge period tp, all the select signals SEL1, SEL2, . Therefore, since the control circuit 76 controls the selection circuit 101a during the precharge period tp, the control circuit 76 and the selection circuit 101a constitute a precharge circuit.

Such an operation is performed in each horizontal period H. FIG. A similar operation is performed in the (N+1)th frame after the Nth frame. At that time, the image signal polarity for each pixel 100a may be switched. The image signal polarity is the polarity of the image signal voltage with reference to the common potential LCCOM. For example, if the image signal voltage is positive with respect to the common potential LCCOM, it is positive, and if the image signal voltage is negative with respect to the common potential LCCOM, it is negative. For example, if positive polarity writing is performed in the Nth frame, negative polarity writing is performed in the next (N+1)th frame. On the other hand, if negative polarity writing is performed in the Nth frame, positive polarity writing is performed in the next (N+1)th frame. By performing such polarity reversal, deterioration of the electro-optic layer 50 can be prevented.

As described above, in this embodiment, precharging assists the writing of the image signal voltage, or when a white window is displayed on a halftone background, the upper and lower parts of the white window are visually recognized as having a different gradation from the surroundings. reduce the crosstalk that is generated. The precharge signal PRC is often set near the lowest voltage in the voltage range of the image signal VID, for example. For example, in the normally black mode electro-optical device 100, the common potential LCCOM is set to a fixed potential of 7 V, the image signal voltage in negative polarity display is 2 V (white) to 7 V (black), and the image signal voltage in positive polarity display. is set to 7V (black) to 12V (white), and the precharge signal is set to about 2V to 4V. In practice, the common potential LCCOM is adjusted in consideration of the push-down voltage between the transistor 30e of the selection circuit 101a and the pixel transistor 30, but it can be ignored in the explanation of the embodiment.

Precharging is generally performed at the beginning of the horizontal scanning period H. Therefore, the potential of the data lines 6a changes to about 2 V all at once, and the parasitic capacitance causes relatively large noise with respect to the potential of the common potential wiring 8a. Specifically, as shown by LCCOM in FIG. 5, in synchronism with precharging, spike noise directed toward the lower potential side than the common potential LCCOM rises in the common potential wiring 8a. Noise also occurs when image signals are written to each pixel, but it is relatively small due to the time-division operation. In recent years, the number of data lines 6a in the display area 10a has increased due to the increase in definition, and this spike noise cannot be suppressed.

1-4. Configuration of Temperature Detection Circuit 1 FIG. 6 is an explanatory diagram of the temperature detection circuit 1 shown in FIG. FIG. 6 shows the circuit configuration when the temperature detection circuit 1 detects the temperature.

As shown in FIG. 3, a temperature detection circuit 1 is provided outside the display area 10a of the first substrate 10 to detect the temperature of the electro-optical panel 100p. The temperature detection circuit 1 includes a temperature detection element 11 and an electrostatic protection circuit 12 for protecting the temperature detection element 11 from surge current. In the first substrate 10, the temperature detection element 11 is arranged near the display area 10a, and the electrostatic protection circuit 12 is provided between the temperature detection element 11 and the end portion of the first substrate 10 where the terminals 102 are arranged. It is

As shown in FIG. 6, the temperature detection element 11 includes, for example, multiple diodes D electrically connected in series. FIG. 6 illustrates a form in which three diodes D (D1 to D3) are electrically connected in series for ease of explanation. may be electrically connected to According to such a temperature detecting element 11, when a constant current is passed through the temperature detecting element 11, the sensitivity of the forward voltage to temperature can be made about -10 mV/°C. An anode 11a of the temperature detecting element 11 is electrically connected to an anode wiring La extending from an anode terminal 102a. A cathode 11c of the temperature detection element 11 is electrically connected to a cathode wiring Lc extending from a cathode terminal 102c. A ground potential GND is supplied to the cathode wiring Lc.

Therefore, when the electro-optical device 100 is mounted on an electronic device, a voltage of 100 nA to several is supplied from the temperature detection drive circuit 66 of the host circuit 60 to the temperature detection circuit 1 via the wiring board 70, the anode terminal 102a and the cathode terminal 102c. Most of the drive current IF flows through the temperature detection element 11 when a very small forward drive current IF of about μA is supplied. Here, the forward voltage of the temperature detection element 11 can be considered to have a good linear relationship with temperature. Therefore, if the temperature detection drive circuit 66 detects the output voltage VF between the anode terminal 102a and the cathode terminal 102c when the temperature detection element 11 is supplied with a drive current IF consisting of a constant current of about 100 nA to several μA, , the temperature of the display area 10a of the electro-optical panel 100p can be detected. More specifically, the output voltage VF changes with good linearity with respect to temperature in the specified temperature range when the electro-optical device 100 is used as a light valve or the like of a projection display device (to be described later). By doing so, the temperature of the electro-optical panel 100p can be detected. At this time, since the temperature detection element 11 is arranged near the display area 10a, the temperature detection element 11 can properly detect the temperature of the display area 10a. Therefore, if the image signal is corrected or the like based on the temperature detection by the temperature detection circuit 1, the electro-optical device 100 can be driven under appropriate conditions corresponding to the temperature of the display area 10a. Images can be displayed. Note that the temperature detection drive circuit 66 includes a constant current circuit 661 and a stabilizing capacitor 662 . A stabilizing capacitor 662 is provided between the constant current circuit 661 and the ground potential GND, and stabilizes the measured value of the output voltage VF. The capacitance of the stabilizing capacitor 662 is, for example, 0.1 μF.

In this embodiment, the electrostatic protection circuit 12 includes a transistor Tr connected between the anode wiring La and the cathode wiring Lc, and the transistor Tr is electrically connected in parallel to the temperature detection element 11. . One source/drain region 31i of the transistor Tr is electrically connected to the cathode wiring Lc between the cathode terminal 102c and the cathode 11c of the temperature detecting element 11, and the other source/drain region 31j of the transistor Tr is connected to the anode. The terminal 102a and the anode 11a of the temperature detection element 11 are electrically connected to the anode wiring La. In this embodiment, the transistor Tr is an N-channel transistor, like the pixel transistor 30 .

In the electrostatic protection circuit 12, a first capacitive element C1 and a second capacitive element C2 electrically connected in series are electrically connected between an anode line La and a cathode line Lc. More specifically, one electrode of the second capacitive element C2 is electrically connected to the anode line La, one electrode of the first capacitive element C1 is electrically connected to the cathode line Lc, and the first capacitive element The other electrode of C1 and the other electrode of the second capacitive element C2 are electrically connected. One electrode of the first capacitive element C1 is electrically connected to the cathode wiring Lc between the cathode terminal 102c and one source/drain region 31i of the transistor Tr, and one electrode of the second capacitive element C2 is: Of the anode wiring La, the anode terminal 102a and the other source/drain region 31j of the transistor Tr are electrically connected to the anode wiring La. The capacitance of the first capacitive element C1 and the second capacitive element C2 is, for example, 5 pF.

The anode wiring La has a first resistance element R1 between the anode terminal 102a and the connection position between the anode wiring La and the second capacitive element C2. The cathode wiring Lc connects the cathode terminal 102c, the cathode wiring Lc, and the first It has a second resistance element R2 between it and the connection position with the capacitive element C1. A connection node Cn between the first capacitive element C1 and the second capacitive element C2 is electrically connected to the gate electrode 33t of the transistor Tr. The first resistance element R1 and the second resistance element R2 are, for example, 10 kΩ.

The electrostatic protection circuit 12 has a resistive element R3 electrically connected in parallel to the first capacitive element C1. More specifically, the gate line Lg extending from the gate electrode 33t of the transistor Tr is electrically connected to the connection node Cn between the first capacitive element C1 and the second capacitive element C2, and further connects the resistance element R3. It is electrically connected to the cathode wiring Lc through the . The resistance element R3 is, for example, 500 kΩ. The transistor Tr functions as a discharge path. Since the gate electrode 33t of the transistor Tr is electrically connected to the cathode line Lc through the resistance element R3, the gate electrode 33t and the cathode line Lc are at the same potential in a static state. That is, the gate-source voltage of the transistor Tr is 0V. Therefore, the transistor Tr is turned off, and ideally no current flows between the source and the drain. Therefore, when the temperature is detected by the temperature detection element 11, the driving current IF supplied to the anode line La flows through the temperature detection element 11 without flowing through the transistor Tr.

Thus, the electrostatic protection circuit 12 includes the transistor Tr electrically connected in parallel to the temperature detecting element 11, the first capacitive element C1 electrically connected to the transistor Tr, and the first capacitive element C1. and a resistive element R3 electrically connected in parallel. The electrostatic protection circuit 12 also includes a second capacitive element C2 electrically connected in series with the first capacitive element C1. Therefore, when a surge current caused by static electricity enters from the anode terminal 102a in a manufacturing process or the like, the static electricity protection circuit 12 protects the temperature detecting element 11 from static electricity.

More specifically, in the electrostatic protection circuit 12, the gate-source voltage of the transistor Tr is 0 V in the static state, and the transistor Tr is off. Here, when a surge current due to static electricity enters from the anode terminal 102a, the transistor Tr, which is the potential of the connection node Cn between the first capacitive element C1 and the second capacitive element C2, is suppressed while the voltage fluctuation is suppressed by the first resistive element R1. , the potential of the gate electrode 33t rises. As a result, the transistor Tr is turned on, and the surge current flows to the cathode terminal 102c through the transistor Tr and the cathode line Lc. At this time, the first resistance element R1 reduces the surge current entering from the anode terminal 102a, and the second resistance element R2 reduces the surge current entering from the cathode terminal 102c. Also, the period during which the transistor Tr is turned on is determined by the first capacitive element C1, the second capacitive element C2, the resistance element R3, the gate capacitance of the transistor Tr, and the like. After discharging, the gate-source voltage of the transistor Tr returns to 0V by the resistance element R3. Therefore, since the surge current flowing through the temperature detection element 11 is suppressed by the electrostatic protection circuit 12, the temperature detection element 11 can be protected.

1-5. Configuration Example of Temperature Detecting Element 11 and the Like FIG. 7 is an explanatory view schematically showing a cross section of the temperature detecting element 11 and the like shown in FIG. As shown in FIG. 7, in the first substrate 10, a translucent insulating layer 41 made of a silicon oxide film or the like is formed on the substrate main body 10w. A transistor 30 is formed. A light shielding layer (not shown) may be formed between the substrate body 10w and the insulating layer 41 so as to overlap the semiconductor layer 31a and the like in a plan view. It should be noted that the gate insulating layer 32 is drawn only on the pixel transistor 30 for easy identification in the drawing.

The pixel transistor 30 includes a semiconductor layer 31a and a gate electrode 33g formed by a part of the scanning line 3a intersecting the semiconductor layer 31a. It has a translucent gate insulating layer 32 . The gate electrode 33g is, for example, a laminated film of tungsten silicide and conductive polysilicon. The semiconductor layer 31a is made of a polysilicon film. The pixel transistor 30 has an LDD (Lightly Doped Drain) structure. More specifically, in the pixel transistor 30, the source region 31s includes a high-concentration region 31s1 separated from the channel region 31g and a low-concentration region 31s2 sandwiched between the channel region 31g and the high-concentration region 31s1. The region 31d includes a high-concentration region 31d1 separated from the channel region 31g and a low-concentration region 31d2 sandwiched between the channel region 31g and the high-concentration region 31d1. The gate insulating layer 32 is made of, for example, a silicon oxide film. A light-shielding layer formed between the substrate body 10w and the insulating layer 41 is used as the scanning line 3a, and the gate electrode 33g is connected to the light-shielding layer through a contact hole (not shown) passing through the gate insulating layer 32 and the insulating layer 41. may be electrically connected to

Translucent insulating layers 42, 43 and 44 made of a silicon oxide film or the like are laminated in this order on the upper layer side of the gate electrode 33g. 3 is configured.

Data lines 6 a and relay electrodes 6 b are formed between the insulating layers 42 and 43 . The data line 6 a is electrically connected to the source region 31 s of the pixel transistor 30 via a contact hole 42 s penetrating the gate insulating layer 32 and the insulating layer 42 . The relay electrode 6b is electrically connected to the drain region 31d of the pixel transistor 30 via a contact hole 42d passing through the gate insulating layer 32 and the insulating layer 42. As shown in FIG. The data line 6a and the relay electrode 6b are made of a conductive layer simultaneously formed on the same layer, and are low-resistance wiring mainly made of aluminum, for example.

Between the insulating layers 43 and 44, a common potential wiring 8a and a relay electrode 8d are formed. The common potential wiring 8a and the relay electrode 8d are made of conductive layers simultaneously formed on the same layer. The relay electrode 8 d is connected to the relay electrode 6 via a contact hole 43 d penetrating the insulating layer 43 .
b. Although not shown, the common potential wiring 8a is electrically connected to one electrode of the holding capacitor 55, and the other electrode of the holding capacitor 55 is electrically connected to the relay electrodes 6b and 8d. Common potential wiring 8a is also electrically connected to wiring 6g in FIG.

A pixel electrode 9 a is formed on the insulating layer 44 . The pixel electrode 9a is electrically connected to the relay electrode 8d through a contact hole 44d passing through the insulating layer 44. As shown in FIG. Accordingly, the pixel electrode 9a is electrically connected to the other electrode of the storage capacitor 55 and further electrically connected to the drain region 31d of the pixel transistor 30. As shown in FIG.

Although illustration is omitted, on the first substrate 10, the manufacturing process of the pixel transistor 30 and the like is used to form a transistor for a driving circuit constituting an inverter circuit and the like in the scanning line driving circuit 104, a data line driving circuit, and the like. A transistor for a driving circuit which constitutes the selection circuit 101a of 101 is also constructed.

The diode D of the temperature detection element 11 is formed on the first substrate 10 by using the manufacturing process of the pixel transistor 30, the driver circuit transistor, and the like. More specifically, in the first substrate 10, a plurality of semiconductor layers 31h separated from each other like islands are provided above the insulating layer 41, and each of the plurality of semiconductor layers 31h has an N-type region and an N-type region. A P-type region is provided. In this embodiment, the N-type region includes a high-concentration N-type region N+ and a low-concentration N-type region N-, and the P-type region includes a high-concentration P-type region P+ and a low-concentration P-type region P-. The lightly doped N-type region N- and the lightly doped P-type region P- form a PN junction. The diode D can also be composed of a high-concentration P-type region P+, a low-concentration N-type region N-, and a high-concentration N-type region N+. In either case, whether or not it is the diode D can be determined by measuring its electrical characteristics.

Electrodes 6e1 and 6e2 are formed on the upper layer of the insulating layer 42, and the plurality of electrodes 6e1 and 6e2 are connected to the high-concentration P-type region P+ of the semiconductor layer 31h through contact holes 42p and 42n penetrating the insulating layer 42, respectively. and the high-concentration N-type region N+ of the adjacent semiconductor layer 31h. The relay portion P1 is a portion that electrically connects the PN junction of the first diode D1 and the PN junction of the second diode D2. The relay portion P2 is a portion that electrically connects the PN junction of the second diode D2 and the PN junction of the third diode D3, and includes the N-type region of the second diode D2, the electrode 6e2 and the third diode D2. Contains the P-type region of D3. Therefore, the electrode 6e1 is included in the relay portion P1 that electrically connects the first diode D1 and the second diode D2, and the electrode 6e2 is included in the relay portion P2 that electrically connects the second diode D2 and the third diode D3. included in Here, the electrode 6e1 corresponds to a portion that electrically connects the semiconductor layer 31h of the first diode D1 and the semiconductor layer 31h of the second diode D2, and the electrode 6e2 corresponds to the semiconductor layer 31h of the second diode D2 and the semiconductor layer 31h of the second diode D2. It corresponds to a portion electrically connecting the semiconductor layer 31h of the third diode D3.

The high-concentration P-type region P+ of the semiconductor layer 31h arranged at one end is electrically connected to the anode wiring La through the contact hole 42p, and the semiconductor layer 31h arranged at the other end is electrically connected to the anode wiring La through the contact hole 42p. A cathode line Lc is electrically connected to the high-concentration N-type region N+ through a contact hole 42n.

Since the semiconductor layer 31h is formed in the same layer as the semiconductor layer 31a at the same time, the thickness and the like are the same as those of the semiconductor layer 31a. The N-type region and the P-type region are formed using the manufacturing process of the driving transistor and the pixel transistor 30 that constitute the scanning line driving circuit 104 and the like shown in FIG. The electrodes 6e1 and 6e2 are formed simultaneously in the same layer as the data line 6a, for example.

Although illustration is omitted, the transistor Tr, the first resistance element R1, the second resistance element R2, and the resistance element R3 of the electrostatic protection circuit 12 are formed using the respective conductive layers and the like shown in FIG. For example, the first resistive element R1, the second resistive element R2, and the resistive element R3 are made of a conductive polysilicon film or the like. For example, it is provided in the same layer as the gate electrode 33g and the semiconductor layer 31a. The first resistance element R1, the second resistance element R2, and the resistance element R3 are not limited to this, and may be made of a metal material such as tungsten silicide or aluminum. The transistor Tr is formed in the same layer as the pixel transistor 30 at the same time. The first capacitive element C1 and the second capacitive element C2 are simultaneously formed in the same layer as the holding capacitor 55 .

As shown in FIGS. 4 and 7, the common potential wiring 8a is a wiring that extends from the terminal 102g to the display area 10a and the scanning line driving circuit 104 through the formation area of the temperature detecting element 11. FIG. Here, the common potential wiring 8a is provided with an opening 8a0 outside the display area 10a, and the temperature detecting element 11 is formed inside the opening 8a0 in plan view. In this embodiment, a light shielding layer 8e overlapping the temperature detection element 11 in plan view is formed inside the opening 8a0 in plan view. The light-shielding layer 8e is a light-shielding conductive layer formed at the same time as the common potential wiring 8a. Also, the light shielding layer 8e is a film formed simultaneously in the same layer as the common potential wiring 8a, but is provided apart from the common potential wiring 8a.

The parting 29 of the second substrate 20 is formed in a region overlapping the temperature detection element 11 in plan view, and the parting 29 is further formed in a region overlapping the data line driving circuit 101 and the scanning line driving circuit 104 in plan view. It is

In the first substrate 10 configured as described above, the data line 6a and the electrodes 6e1 and 6e2 formed between the insulating layer 42 and the insulating layer 43 correspond to the first conductive layer. 44 correspond to the second conductive layer, and the pixel electrode 9a and the dummy pixel electrode 9b formed on the insulating layer 44 correspond to the third conductive layer. corresponds to

1-6. Effects of Embodiment 1 FIG. 8 is an explanatory diagram of a comparative example with respect to Embodiment 1 of the present invention. FIG. 9 is a diagram showing an example of the relationship between precharge and the output voltage VF of the temperature detection circuit 1. In FIG. FIG. 10 is a graph showing the influence of the parasitic capacitance Cb of the temperature detecting element 11 shown in FIG. 6 on the output voltage VF. Specifically, FIG. 10 shows the relationship between the output voltage VF of the temperature detection circuit 1 and the capacitance of the parasitic capacitance Cb between the temperature detection element 11 and the common potential wiring 8a. In FIG. 10, the parasitic capacitance Cb includes the capacitance parasitic between the relay portion P1 including the electrode 6e1 of the diode D of the temperature detecting element 11 and the common potential wiring 8a, and the parasitic capacitance between the relay portion P2 including the electrode 6e2 and the common potential wiring 8a. is a parasitic capacitance between One pole of the diode D electrically connected to the electrode 6e1 is the same node as the electrode 6e1. Similarly, one pole of diode D electrically connected to electrode 6e2 is the same node as electrode 6e2.

In the comparative example shown in FIG. 8, the opening 8a0 is not formed in the common potential wiring 8a, and the temperature detection element 11 overlaps the common potential wiring 8a in plan view. Therefore, in the comparative example, a parasitic capacitance Cb (see FIG. 6) having a large electrostatic capacitance exists between the relay portions P1 and P2 of the diode D and the common potential wiring 8a. The parasitic capacitance Cb is greatly affected by the electrodes 6e1 and 6e2 arranged above the semiconductor layer 31h.

On the other hand, as shown in FIG. 7, in the electro-optical device 100 according to the first embodiment of the present invention, the common potential wiring 8a is formed with an opening 8a0 at a position overlapping the temperature detecting element 11 in plan view. ing. Therefore, the temperature detection element 11 does not overlap the common potential wiring 8a in plan view. Therefore, in the electro-optical device 100 according to the first embodiment of the present invention, there is no parasitic capacitance having a large electrostatic capacitance between the electrodes 6e1, 6e2 of the diode D and the common potential line 8a. and the common potential line 8a, there is no parasitic capacitance Cb having a large capacitance. Therefore, as will be described below, when spike noise occurs in the potential of the common potential wiring 8a due to precharging, in the comparative example, the potential change of the common potential wiring 8a is caused by the temperature detecting element 11 via the parasitic capacitance Cb. However, in the first embodiment, the above effect is less likely to occur.

For example, when the drive current of the temperature detection circuit 1 including the temperature detection element 11 consisting of six diodes D is set to 100 nA, the following problems occur. As shown in FIG. 9, when precharging of the electro-optical device 100 is stopped from time t0 to t1, the output voltage VF of the temperature detection circuit 1 substantially matches the forward voltage expected in the six diodes D. bottom. Next, when precharging is performed between times t1 and t2, the output voltage VF of the temperature detection circuit 1 drops by ΔVF1 and saturates. When precharging is stopped after time t2, the output voltage VF of the temperature detection circuit 1 returns to the output voltage VF from time t0 to t1. Further, this ΔVF1 is reduced by electrically floating the conductive layer which is arranged above the temperature detection element 11 of the first substrate 10 and to which the common potential LCCOM is applied.

Therefore, assuming a parasitic capacitance Ca (see FIG. 6) and a parasitic capacitance Cb (see FIG. 6), the diode D is modeled based on the measured data, and a circuit simulator is used to detect the parasitic capacitance of the common potential wiring 8a. The effect on the output voltage VF of the temperature detection circuit 1 via the capacitances Ca and Cb was calculated. Note that the stabilizing capacitance 662 shown in FIG. 6 was set to 100 pF in order to shorten the calculation time. Although the response time of the output voltage VF is different from the actual electro-optical device 100, it is sufficient to verify the behavior of the output voltage VF. Although the output voltage VF drops and saturates after the start of precharging, minute voltage fluctuations synchronized with precharging remain. Therefore, the average voltage for 0.01 sec, which is sufficiently longer than one horizontal period, is defined as the output voltage VF. In addition, the calculation assumed room temperature.

The potential of the common potential wiring 8a is basically a fixed potential as the common potential LCCOM, eg, 7 V, but the following noise is periodically superimposed with precharging. Here, one horizontal scanning period of 3 μsec is close to one horizontal period when, for example, a WUXGA standard electro-optical panel is driven at 240 frames per second. The reason why the polarity of the voltage of the noise is negative is that spike noise is generated in the common potential line 8a toward the lower potential side than the common potential LCCOM.
1 horizontal scanning period=3 μsec
Noise voltage = -1.5V
Fall time of noise voltage = 100 nsec
Noise voltage rise time = 300 nsec

As a result of calculation, 0.5 pF was assumed as the parasitic capacitance Ca (see FIG. 6), but the effect on the output voltage VF of the temperature detecting element 11 was small.

On the other hand, the calculation result shown in FIG. 10 was obtained as the relationship between the capacitance of the parasitic capacitance Cb and the output voltage VF. In FIG. 10, solid lines L100, L200, L400 and L800 show the calculation results of the output voltage VF of the temperature detection circuit 1 when the driving current IF is 100 nA, 200 nA, 400 nA and 800 nA.

For example, if a parasitic capacitance Cb of 0.03 pF exists between the relay portions P1, P2, . . . A possible calculation result was obtained. If the output voltage VF fluctuates by 100 mV, the temperature detection error will reach 10° C. if the temperature detection element 11 has a sensitivity of about −10 mV/° C., making it difficult to control the temperature of the electro-optical device 100 .

Further, from FIG. 10, it can be said that reducing the parasitic capacitance Cb or increasing the driving current IF is effective in solving the above problem. Therefore, if the parasitic capacitance Cb between the relay portions P1, P2, . . . Variations in the output voltage VF can be suppressed as shown. That is, even if the potential of the common potential wiring 8a changes due to precharging, the output voltage VF of the temperature detection circuit 1 fluctuates less, so that the temperature detection accuracy of the temperature detection element 11 can be improved.

If the drive current IF is increased, the potential change of the common potential wiring 8a is less likely to affect the output voltage VF of the temperature detection circuit 1. Since the variation ΔVF of the forward voltage of the temperature detecting element 11 with respect to the variation ΔIF of the driving current at 11 becomes large, the reliability of the detected temperature is lowered. Therefore, it is not preferable to simply increase the driving current of the diode D, because the temperature detection circuit 1 is difficult to use.

Further, when the drive current IF is increased, the output voltage VF, which is the operating point, rises, and the compliance voltage (operating point voltage upper limit) of the constant current circuit may not be observed. For example, in a discharge type constant current circuit using a transistor, an operational amplifier, a shunt regulator, etc., the operating point voltage upper limit for constant current operation when using a 5V power supply is about 3.7V. From FIG. 10, for example, if the driving current IF is 400 nA, the operating point voltage at room temperature is about 3.8 V, so a constant current circuit driven by a 5 V power supply cannot be used. In this case, the number of diodes in series is reduced in order to lower the operating point voltage, that is, the output voltage VF. In addition, if the number of series diodes is to be maintained, a new drive voltage source for the external circuit must be provided, resulting in an increase in cost. From this point of view, since the first embodiment is configured to reduce the parasitic capacitance Cb, the potential change of the common potential wiring 8a does not affect the output voltage VF of the temperature detection circuit 1 without increasing the driving current IF. less likely to be affected. Therefore, the temperature detection circuit 1 using the temperature detection element 11 with good sensitivity can be driven by the temperature detection drive circuit 66 which can be configured at low cost.

Further, in the present embodiment, since the island-shaped light shielding layer 8e is provided in the opening 8a0, even when the opening 8a0 is provided, incident light is prevented from becoming stray light and the pattern of the diode D is projected. Also, by providing the island-shaped light shielding layer 8 e , the temperature of the electro-optic layer 50 can be easily transmitted to the temperature detecting element 11 .

2. Embodiment 2
FIG. 11 is an explanatory diagram of an electro-optical device 100 according to Embodiment 2 of the present invention. FIG. 11 shows a planar configuration of the vicinity of the temperature detection element 11 of the electro-optical device 100 according to the second embodiment of the invention. FIG. 12 is an explanatory diagram schematically showing a cross section of the temperature detecting element 11 and the like shown in FIG. 11. As shown in FIG. Since the basic configuration of this embodiment is the same as that of the first embodiment, common parts are denoted by the same reference numerals and descriptions thereof are omitted.

As shown in FIGS. 11 and 12, in the present embodiment, a conductive layer 9b0 forming dummy pixel electrodes 9b is arranged on the surface of the insulating layer 44 around the display region 10a of the first substrate 10. As shown in FIGS. . The conductive layer 9b0 has a shape in which, for example, a plurality of rectangular patterns similar to those of the pixel electrodes 9a are arranged and connected to each other at the central portions of the four sides that form a rectangle. Also, the conductive layer 9b0 overlaps the temperature detection element 11 in plan view. Conductive layer 9b0 is electrically connected to common potential wiring 8a through contact hole 44e penetrating insulating layer 44. Referring to FIG. Therefore, the common potential LCCOM is applied to the conductive layer 9b0. According to such a configuration, the voltage applied to the electro-optic layer 50 can be kept at 0 V around the display area 10a, so deterioration of the electro-optic layer 50 is suppressed.

Here, the common potential wiring 8a is provided with an opening 8a0 in a region overlapping with the temperature detection element 11 in plan view, as in the first embodiment. A light shielding layer 8e overlapping the temperature detecting element 11 in plan view is provided inside the opening 8a0, and the light shielding layer 8e is electrically floating. The conductive layer 9b0 is electrically connected to the common potential wiring 8a and overlaps the temperature detection element 11 in a plan view. Therefore, a parasitic capacitance exists between the conductive layer 9b0 and the relay portions P1 and P2 of the temperature detecting element 11. FIG. However, as is apparent from the comparative example of FIG. is increased by As a result, the parasitic capacitance formed between the relay portions P1, P2 of the temperature detection element 11 and the conductive layer 9b0 can be reduced. Therefore, even if spike noise occurs in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed. Therefore, the temperature detection accuracy in the electro-optical device 100 is high, so that the electro-optical device 100 can appropriately perform temperature control.

2-1. Modification of Embodiment 2 FIG. 13 is an explanatory diagram of an electro-optical device 100 according to a modification of Embodiment 2 of the present invention. FIG. 13 schematically shows a cross section of the temperature detection element 11 and the like of the electro-optical device 100 according to the modification of the second embodiment of the invention. Since the basic configuration of this embodiment is the same as those of Embodiments 1 and 2, common parts are denoted by the same reference numerals and descriptions thereof are omitted.

As shown in FIG. 13, in the present embodiment, a conductive layer 9b0 forming dummy pixel electrodes 9b is arranged on the surface of an insulating layer 44 around the display region 10a of the first substrate 10, as in the second embodiment. It is The conductive layer 9b0 has a shape in which, for example, a plurality of rectangular patterns similar to those of the pixel electrodes 9a are arranged and connected to each other at the central portions of the four sides that form a rectangle.

Here, between the electro-optic layer 50 and the common potential wiring 8a, the insulating layers 44 and 45 are provided between the common potential wiring 8a and the conductive layer 9b0, and the relay layer is provided between the insulating layers 44 and 45. An electrode 7a is provided. Accordingly, the pixel electrode 9a is electrically connected to the relay electrode 7a through the contact hole 45d penetrating the insulating layer 45, and the relay electrode 7a is electrically connected to the relay electrode 8d through the contact hole 44d penetrating the insulating layer 44. electrically connected.

Between the insulating layer 44 and the insulating layer 45, a conductive layer 7e0 forming the wiring 7e is provided. Therefore, the conductive layer 9b0 is electrically connected to the conductive layer 7e0 through the contact hole 45e penetrating the insulating layer 45, and the conductive layer 7e0 is electrically connected to the common potential wiring 8a through the contact hole 44e penetrating the insulating layer 44. is electrically connected to Therefore, the common potential LCCOM is supplied to the dummy pixel electrode 9b and the wiring 7e. According to such a configuration, the voltage applied to the electro-optic layer 50 can be kept at 0 V around the display area 10a, so deterioration of the electro-optic layer 50 can be suppressed. In addition, since the common potential wiring 8a electrically connected to the capacity line in the display area 10a and the terminal 102g can be electrically connected with a low resistance by the wiring 7e, there is an effect of stabilizing the potential.

Here, the common potential wiring 8a is provided with an opening 8a0 in a region overlapping with the temperature detection element 11 in plan view, as in the first embodiment. A light shielding layer 8e overlapping the temperature detection element 11 in plan view is provided inside the opening 8a0, and the light shielding layer 8e is in an electrically floating state. The conductive layer 7e0 is electrically connected to the common potential wiring 8a and overlaps the temperature detection element 11 in plan view. Therefore, a parasitic capacitance exists between the conductive layer 7e0 and the relay portions P1 and P2 of the temperature detecting element 11. FIG. However, as is apparent from the comparative example of FIG. increased by thickness. As a result, the parasitic capacitance formed between the relay portions P1 and P2 of the diode D of the temperature detection element 11 and the conductive layer 7e0 can be reduced. Therefore, even if spike noise occurs in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed. Therefore, the temperature detection accuracy of the electro-optical device 100 is high, so that the electro-optical device 100 can appropriately perform temperature control, and the like, which is the same effect as in the second embodiment.

3. Embodiment 3
FIG. 14 is an explanatory diagram of the electro-optical device 100 according to Embodiment 3 of the present invention. FIG. 14 shows a planar configuration of the vicinity of the temperature detection element 11 of the electro-optical device 100 according to Embodiment 3 of the present invention. FIG. 15 is a cross-sectional view of temperature detection element 11 shown in FIG. Since the basic configuration of this embodiment is the same as those of Embodiments 1 and 2, common parts are denoted by the same reference numerals and descriptions thereof are omitted. In FIGS. 14 and 15, the number of diodes D electrically connected in series in the temperature detecting element 11 is three for easy understanding of the configuration.

As shown in FIGS. 14 and 15, in the temperature detection element 11, the direction in which the diodes D are arranged is defined as a first direction E, and the direction orthogonal to the first direction E is defined as a second direction F. are arranged in the first direction E, and the adjacent diodes D are electrically connected by the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2. In this embodiment, the first direction E is the Y direction and the second direction F is the X direction. One electrode of the diode D electrically connected to the electrode 6e1 is the same node as the electrode 6e1. Similarly, the other electrode of diode D electrically connected to electrode 6e2 is the same node as electrode 6e2.

Here, W1 is the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, and W2 is the electrode width in the second direction F of the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2. Then, as shown below, the electrode width W2 has a portion narrower than the pattern width W1.
W1 > W2

For example, when the pattern width W1 is 100 μm, the electrode width W2 is 5 μm. Since the current value flowing through the temperature detection element 11 is small, there is no problem even if the electrode width W2 is reduced. The configuration is the same between the second diode D2 and the third diode D3. Therefore, since the areas of the electrodes 6e1 and 6e2 are reduced when viewed from above, the parallel plate-like parasitic capacitance formed between the relay portions P1 and P2 including the electrodes 6e1 and 6e2, respectively, and the common potential wiring 8a can be reduced. can. Therefore, even if spike noise is generated in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

Here, the opening 8a0 of the common potential wiring 8a may be provided so as to expose all the diodes D as indicated by the dotted line L1 in FIG. , P2 may be mainly exposed. In the latter case, the anode wiring La electrically connected to the first diode D1 and the cathode wiring Lc electrically connected to the third diode D3 overlap the common potential wiring 8a in plan view. From the verification by the circuit model described above, it is the parasitic capacitance Cb between the relay portions P1, P2 and the common potential line 8a that greatly affects the variation of the output voltage VF of the temperature detection circuit 1. FIG. Therefore, even if the anode wiring La and the cathode wiring Lc overlap with the common potential wiring 8a, the effect is small.

Further, in the verification using the circuit model described above, it was found that it is important to reduce the parasitic capacitance between the relay portions P1 and P2 and the noise source. A cathode line Lc having a potential of GND is extended in the first direction E. As shown in FIG. That is, for the relay portions P1 and P2, the cathode wiring Lc may be used as a shield for wiring (not shown). At this time, if the cathode wiring Lc is provided in a separate system from the ground potential GND potential wiring of the electro-optical panel 100p, the cathode wiring Lc becomes a constant potential wiring with low noise, so that the shielding effect is high.

Further, for the relay portions P1 and P2, the constant potential wiring 6s that supplies the low-level constant potential VSSY is used as a shield against wiring (not shown), and extends in the first direction E along the arrangement direction of the diodes D. good too. Alternatively, a wiring that supplies a high level constant potential VDDY may be used as a shield.

Further, as shown in FIG. 15, by shortening the interval S0, which is the interval between the semiconductor layers 31h in the first direction E, within the range allowed by design rules, the lengths L6e1 and 6e2 of the electrodes 6e1 and 6e2 can be shortened. preferable. If the lengths L6e1 and L6e2 of the electrodes 6e1 and 6e2 are shortened, the lengths LP1 and LP2 of the relay portions P1 and P2 are shortened. Therefore, the area of the electrode 6e1 of the relay portion P1 and the area of the electrode 6e2 of the relay portion P2 are reduced, and the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential line 8a can be reduced. Therefore, even if spike noise is generated in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

3-1. Modification 1 of Embodiment 3
FIG. 16 is an explanatory diagram of an electro-optical device 100 according to Modification 1 of Embodiment 3 of the present invention. FIG. 16 shows a planar configuration near the temperature detection element 11 of the electro-optical device 100 according to Modification 1 of Embodiment 3 of the present invention. Since the basic configuration of this embodiment is the same as that of the third embodiment, common parts are denoted by the same reference numerals and descriptions thereof are omitted. In FIG. 16, the number of diodes electrically connected in series in the temperature detecting element 11 is three, and a part of the common potential wiring 8a is omitted for the sake of easy understanding of the configuration.

As shown in FIG. 16, when the direction in which the diodes D are arranged is defined as a first direction E, and the direction orthogonal to the first direction E is defined as a second direction F, the semiconductor layer 31h forming the diodes D is arranged in the first direction. Adjacent diodes D arranged in direction E are electrically connected by electrode 6e1 of relay portion P1 and electrode 6e2 of relay portion P2. In this embodiment, the first direction E is the Y direction and the second direction F is the X direction.

Here, W1 is the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, and W2 is the electrode width in the second direction F of the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2. Then, as in the third embodiment, the electrode width W2 has a portion narrower than the pattern width W1.
W1 > W2

For example, when the pattern width W1 is 100 μm, the electrode width W2 is 5 μm. Since the current value flowing through the temperature detection element 11 is small, there is no problem even if the electrode width W2 is reduced. Therefore, the area of the electrode 6e1 of the relay portion P1 and the area of the electrode 6e2 of the relay portion P2 are reduced, and the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential line 8a can be reduced. Therefore, even if spike noise occurs in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

Also, the interval S0, which is the interval between the semiconductor layers 31h in the first direction E, is shortened within the range permitted by the rules. More specifically, the selection circuit 101a of the data line drive circuit 101 includes complementary transistors of an N-channel transistor 30n1 and a P-channel transistor 30p1. Similarly to the selection circuit 101a, the inverter circuit 104a of the scanning line driving circuit 104 also includes an N-channel transistor 30n2 and a P-channel transistor 30p2. Here, in order to shorten the circuit length, the distance S1 between the semiconductor layer constituting the N-channel transistor 30n1 and the semiconductor layer constituting the P-channel transistor 30p1, and the distance P between the semiconductor layer constituting the N-channel transistor 30n2 and the semiconductor layer constituting the N-channel transistor 30n2. All the spaces S2 between the semiconductor layers forming the channel type transistor 30p2 are set to be narrow. A similar action may be performed in test circuit 105 as well. With this configuration, the peripheral circuit area outside the display area 10a of the electro-optical panel 100p can be reduced, so that the electro-optical panel 100p can be miniaturized. As a result, the electro-optical panel 100p can be manufactured at low cost. In this embodiment, as shown below, the spacing S0 in the diode D is less than the spacing S1 between the N-channel transistor 30n1 and the P-channel transistor 30p1 and the spacing S2 between the N-channel transistor 30n2 and the P-channel transistor 30p2. is set to
S0≦S1, S2

The design rule of the electro-optical panel 100p can be regarded as the minimum value (not shown) of the spacing S1, S2, or other spacing between the semiconductor layers of adjacent transistors of different conductivity types. Therefore, if the value is S3, the relationship with the interval S0 is as follows.
S0≦S3

The interval S3 is mainly determined by the impurity implantation mask pattern rule. For example, when forming a P-type region, it is necessary to create a mask pattern that sufficiently covers the N-type region and is sufficiently separated from the P-type region.

Therefore, with respect to the temperature detection element 11, the semiconductor layer 31h is arranged in the first direction E at an interval S0 that is allowed by the design rule of the electro-optical panel 100p. As a result, the lengths L6e1 and L6e2 of the electrodes 6e1 and 6e2 shown in FIG. 15 can be shortened. Therefore, the area of the electrode 6e1 of the relay portion P1 and the area of the electrode 6e2 of the relay portion P2 are reduced, and the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential line 8a can be reduced. Therefore, even if spike noise occurs in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

Note that the opening 8a0 of the common potential wiring 8a may be provided so that all the diodes D and the common potential wiring 8a do not overlap as indicated by the dotted line L1, or may be provided as a relay portion as indicated by the dashed line L2. The common potential wiring 8a may be provided so as not to overlap P1 and P2.

In addition, in this embodiment, on the side of the temperature detection element 11, the signal wiring 6d for supplying the start pulse SP extending along the first direction E, the signal wiring 6h for supplying the clock signal CLY, and A cathode line Lc extends in the first direction E between the temperature detection element 11 and the signal line 6f for supplying the output control signal ENBY. Further, the cathode wiring Lc extends in the first direction E along the temperature detecting element 11 on the opposite side of the temperature detecting element 11 in the second direction F from the signal wirings 6d, 6h, and 6f. Therefore, for the relay portions P1 and P2, the cathode wiring Lc can be used as a shield against the AC signal wiring. In this case, if the cathode wiring Lc is provided in a separate system from the ground potential GND potential wiring of the electro-optical panel 100p, the cathode wiring Lc becomes a constant potential wiring with low noise, which is effective. In addition, it is preferable to extend the cathode wiring Lc in the first direction E on both sides of the temperature detection element 11 . With such a configuration, the capacitive coupling between the data line driving circuit 101 side and the relay portions P1 and P2 can be suppressed, so that the effect of the data line driving circuit 101 on the output voltage VF of the temperature detection circuit 1 is small. can.

3-2. Modification 2 of Embodiment 3
FIG. 17 is an explanatory diagram of an electro-optical device 100 according to Modification 2 of Embodiment 3 of the present invention. FIG. 17 shows a planar configuration near the temperature detection element 11 of the electro-optical device 100 according to Modification 2 of Embodiment 3 of the present invention. Since the basic configuration of this embodiment is the same as that of the third embodiment, common parts are denoted by the same reference numerals and descriptions thereof are omitted. In addition, in FIG. 17, the number of diodes D electrically connected in series in the temperature detecting element 11 is set to three for easy understanding of the configuration.

As shown in FIG. 17, when the direction in which the diodes D are arranged is defined as a first direction E, and the direction orthogonal to the first direction E is defined as a second direction F, the semiconductor layer 31h forming the diodes D is arranged in the first direction. Adjacent diodes D arranged in direction E are electrically connected by electrode 6e1 of relay portion P1 and electrode 6e2 of relay portion P2. In this embodiment, the first direction E is the X direction and the second direction F is the Y direction. Let W1 be the pattern width, which is the dimension of the semiconductor layer 31h in the second direction F, and W2 be the electrode width in the direction along the second direction F of the electrode 6e1 of the relay portion P1 and the electrode 6e2 of the relay portion P2. Then, as in the third embodiment, the electrode width W2 has a portion narrower than the pattern width W1.
W1 > W2

Therefore, the area of the electrode 6e1 included in the relay portion P1 and the area of the electrode 6e2 included in the relay portion P2 are reduced, and the parasitic capacitance Cb between the relay portions P1 and P2 and the common potential line 8a can be reduced. Therefore, even if spike noise occurs in the common potential line 8a when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

Further, the common potential wiring 8a is formed with an opening 8a0 overlapping the temperature detecting element 11 in plan view. In this embodiment, the opening 8a0 reaches the end of the common potential wiring 8a and is open at the end of the common potential wiring 8a. In this manner, the opening 8a0 may have a notch shape provided on the side of the common potential wiring 8a. Such a configuration occurs when it is desired to dispose the common potential wiring 8a as a low resistance wiring. Further, a part of the diode D forming the temperature detection element 11 may be arranged outside the imaginary line 8a1 that can be drawn from the extending direction of the side of the common potential wiring 8a in the opening 8a0. In this embodiment, the virtual line 8a1 can be drawn like the dashed line in FIG. 17, for example.

Further, in this embodiment, the signal wirings 6d, 6h, and 6f are arranged close to the temperature detecting element 11. As shown in FIG. A signal having a voltage amplitude larger than the voltage fluctuation of the common potential wiring 8a due to precharging is applied to the signal wirings 6d, 6h, and 6f. The voltage amplitude of the signal is, for example, 15.5V. In this embodiment, signal wirings 6d, 6h, and 6f extend along a second direction F orthogonal to a first direction E in which diodes D are arranged. Therefore, the signal wirings 6d, 6h and 6f do not extend along the relay portions P1 and P2 of the diode D. As shown in FIG. In other words, the relay portions P1 and P2 of the diode D do not face the signal wirings 6d, 6h and 6f in plan view. Therefore, since the parasitic capacitance between the signal lines 6d, 6h, 6f and the relay portions P1 and P2 can be reduced, fluctuations in the output voltage VF of the temperature detection circuit 1 due to the signal lines 6d, 6h, 6f are suppressed. In addition, since it is not necessary to arrange the shield lines along the relay parts P1 and P2, the arrangement of the temperature detection element 11 is improved.

Further, in this embodiment, the cathode wiring Lc is arranged between the signal wirings 6d, 6h, and 6f extending along the second direction F and the temperature detecting element 11 on the cathode side 11c of the temperature detecting element 11. has been extended to Therefore, for the relay portions P1 and P2, the cathode wiring Lc can be used as a shield for the signal wirings 6d, 6h and 6f.

4. Embodiment 4
FIG. 18 is an explanatory diagram of precharging in odd-numbered frames of the electro-optical device 100 according to the fourth embodiment of the present invention. FIG. 19 is an explanatory diagram of precharging in an even-numbered frame of the electro-optical device 100 according to Embodiment 4 of the present invention. Since the basic configuration of this embodiment is the same as that of the first embodiment, common parts are denoted by the same reference numerals and descriptions thereof are omitted.

In this embodiment, in the plurality of horizontal scanning periods, a first horizontal scanning period in which a precharge signal is supplied to some of the plurality of data lines 6a, and a portion of the plurality of data lines 6a different from the first horizontal scanning period. and a second horizontal scanning period for supplying a precharge signal to the data line 6a.

More specifically, the selection circuit 101a is composed of N-channel transistors as shown in FIG. As shown in FIG. 18, in the first horizontal scanning period Ha1 of the odd-numbered frame, during the precharge period tp, the control circuit 76 shown in FIG. On the other hand, the even-numbered selection signals SEL2, SEL4, SEL6 and SEL8 are set to the non-selection level. Therefore, the odd series data lines 6a are precharged, and the even series data lines 6a are not precharged.

In the subsequent second horizontal scanning period Ha2 of the odd-numbered frame, during the precharge period tp, the control circuit 76 shown in FIG. The selection signals SEL2, SEL4, SEL6 and SEL8 are set to the selection level. Therefore, the even series data lines 6a are precharged, and the odd series data lines 6a are not precharged.

Further, as shown in FIG. 19, in the first horizontal scanning period Hb1 of the even-numbered frame, during the precharge period tp, the control circuit 76 shown in FIG. level, the even-numbered selection signals SEL2, SEL4, SEL6, and SEL8 are set to the selection level. Therefore, the even series data lines 6a are precharged, and the odd series data lines 6a are not precharged. In the subsequent second horizontal scanning period Hb2 of the even-numbered frame, during the precharge period tp, the control circuit 76 shown in FIG. Signals SEL2, SEL4, SEL6 and SEL8 are set to the non-select level. Therefore, the odd series data lines 6a are precharged, and the even series data lines 6a are not precharged.

Therefore, since the number of data lines 6a to be precharged can be reduced in one horizontal scanning period, the peak voltage value of noise generated in the common potential LCCOM can be reduced in the common potential wiring 8a. . Qualitatively considered from the verification by the circuit model, it can be said that reducing the peak voltage of the noise generated in the common potential LCCOM is preferable for suppressing the fluctuation of the output voltage VF of the temperature detection circuit 1 . That is, when all the data lines 6a are precharged in one horizontal scanning period, the noise peak voltage indicated by the dashed lines in FIGS. 18 and 19 is superimposed on the common potential LCCOM. Since the number of data lines 6a to be precharged in one horizontal scanning period is reduced, the peak voltage of the noise is suppressed as indicated by the solid lines in FIGS. Therefore, even when precharging is performed, fluctuations in the output voltage VF of the temperature detection circuit 1 can be suppressed.

5. Embodiment 5
FIG. 20 is an explanatory diagram of precharging of the electro-optical device 100 according to the fifth embodiment of the invention. Since the basic configuration of this embodiment is the same as that of the first embodiment, common parts are denoted by the same reference numerals and descriptions thereof are omitted.

In this embodiment, the plurality of horizontal scanning periods includes a first horizontal scanning period during which the precharge signal is supplied to all of the plurality of data lines 6a and a second horizontal scanning period during which the precharge signal is not supplied to all of the plurality of data lines 6a. A scanning period is included.

More specifically, as shown in FIG. 20, all the data lines 6a are precharged in the first horizontal scanning period Ha1 of the odd-numbered frame, and all the data lines 6a are precharged in the subsequent second horizontal scanning period Ha2. Do not precharge to Although not shown, in the first horizontal scanning period (corresponding to the first horizontal scanning period Ha1) of the even-numbered frame, none of the data lines 6a are precharged, and the following second horizontal scanning period (second In the horizontal scanning period Ha2), all the data lines 6a are precharged. Therefore, the common potential line 8a can reduce the frequency of noise generated in the common potential LCCOM. Qualitatively considered from the verification by the circuit model, it can be said that reducing the frequency of noise occurring in the common potential LCCOM is preferable for suppressing the fluctuation of the output voltage VF of the temperature detection circuit 1 . That is, a large amount of noise is superimposed during the first horizontal scanning period in which all the data lines 6a are precharged, but no noise is superimposed in the second horizontal scanning period in which all the data lines 6a are not precharged. . A dashed line represents the variation of the common potential LCCOM when all the data lines 6a are precharged. If the frequency of noise occurring in the common potential LCCOM is reduced, fluctuations in the output voltage VF of the temperature detection circuit 1 are suppressed. Therefore, even when precharging is performed, fluctuations in the output voltage VF from the temperature detection circuit 1 can be suppressed.

6. Modifications of Embodiments 3, 4, and 5 In the electro-optical device 100 of the above-described Embodiments 3, 4, and 5, the opening 8a0 is provided in the common potential wiring 8a. In addition, the fluctuation of the output voltage VF of the temperature detection circuit 1 is suppressed by the configuration of the precharging implementation method. However, the third, fourth, and fifth embodiments may be applied to an electro-optical device 100 in which the common potential wiring 8a is not provided with the opening 8a0. That is, by applying the third, fourth, and fifth embodiments to the electro-optical device 100 in which the common potential wiring 8a overlaps the temperature detection element 11 in a plan view, the influence of noise on the temperature detection element 11 is suppressed, and the temperature is reduced. Fluctuations in the output voltage VF of the detection circuit 1 may be suppressed.

7. Other Embodiments of Electro-Optical Device In the first, second, third, fourth, and fifth embodiments, the common potential wiring 8a was exemplified as the wiring, but other wiring can also be applied. For example, since a large amount of noise may be superimposed on the ground potential GND wiring when precharging is performed, in order to reduce the parasitic capacitance between the temperature detection element 11 and the ground potential GND wiring, the first embodiment , 2, 3, 4, 5 may be applied. Also, the present invention may be applied to wiring to which AC signals are supplied. Also, precharging may be performed by replacing the inspection circuit 105 with a precharging circuit.

Further, the electro-optical device 100 is not limited to a liquid crystal device, and may be applied to an electro-optical device 100 other than a liquid crystal device, such as an organic electroluminescence device.

8. Configuration Example of Electronic Apparatus FIG. 21 is a block diagram showing a configuration example of a projection display device 1000 to which the present invention is applied. FIG. 22 is an explanatory diagram of the optical path shift element 110 shown in FIG. In addition, illustration of a polarizing plate and the like is omitted in FIG. 21 . A projection-type display device 1000 shown in FIG. 21 is an example of electronic equipment to which the present invention is applied. It has Each of the electro-optical devices 100R, 100G, and 100B comprises the electro-optical device 100 described with reference to FIGS. 1-20.

The lighting device 190 is a white light source, and for example, a laser light source or a halogen lamp is used. Separating optical system 170 includes three mirrors 171 , 172 , 175 and dichroic mirrors 173 , 174 . The separation optical system 170 separates the white light emitted from the illumination device 190 into the three primary colors of red R, green G, and blue B. Specifically, the dichroic mirror 174 transmits light in the red R wavelength region and reflects light in the green G and blue B wavelength regions. The dichroic mirror 173 transmits light in the blue B wavelength range and reflects light in the green G wavelength range. Light corresponding to red R, green G, and blue B is guided to electro-optical devices 100R, 100G, and 100B, respectively.

Lights modulated by the electro-optical devices 100R, 100G, and 100B enter the dichroic prism 161 from three directions. The dichroic prism 161 constitutes a synthesizing optical system in which red R, green G, and blue B images are synthesized. Therefore, the projection lens system 162 can magnify and project the composite image emitted from the optical path shift element 110 onto a projection target member such as the screen 180 and display a color image on the projection target member such as the screen 180 .

At that time, the control unit 150 can correct the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection result of the temperature detection circuit 1. FIG. Therefore, even if the environmental temperature or the like fluctuates, a high-quality projection image can be displayed. Further, on the side of the dichroic prism 161 from which light is emitted, the projection optical system 160 is provided with an optical path shift element 110 indicated by a dashed line, and the resolution is enhanced by a technique of shifting the position where the projected pixel is visually recognized every predetermined period. When adopting the configuration, it is necessary to drive the liquid crystal layer at high speed. Even in this case, the image signals supplied to the electro-optical devices 100R, 100G, and 100B are corrected based on the temperature detection results of the temperature detection circuit 1, and the electro-optical panel 100p of the electro-optical devices 100R, 100G, and 100B. By adopting a configuration for adjusting the temperature of , the electro-optical layer 50 made of a liquid crystal layer can be driven at high speed.

The optical path shift element 110, as shown in FIG. 21, is an optical element that shifts the light emitted from the dichroic prism 161 in a predetermined direction. In FIG. 22, the position of the projection pixel Pi where the light emitted from each pixel 100a of the electro-optical panel 100p is visible is shifted by the optical path shift element 110 to one side X1 in the X direction by 0.5 pixel pitch (=P/2). ) and shifted to one side Y1 in the Y direction by a distance corresponding to 0.5 pixel pitch (=P/2). The optical path shift element 110 includes a light-transmitting plate, and the actuator shifts the light-transmitting plate around an axis extending in the first direction X and around an axis extending in the second direction Y under a command from the control unit 150. Alternatively, by swinging both, the optical path of the light emitted from each pixel 100a of the electro-optical panel 100p is shifted to the optical path LA and the optical path LB.

9. Other Embodiments of the Electronic Apparatus As for the projection type display device, an LED light source or the like that emits light of each color is used as the light source, and the colored light emitted from the LED light source is supplied to a separate liquid crystal device. may be configured.

An electronic device including the electro-optical device 100 to which the present invention is applied is not limited to the projection display device 1000 of the above embodiment. For example, it may be used in electronic devices such as a projection HUD (head-up display), a direct-view HMD (head-mounted display), a personal computer, a digital still camera, and a liquid crystal television.

Reference Signs List 1 Temperature detection circuit 3a Scanning lines 6a Data lines 6d, 6f, 6h Signal wirings 6e1, 6e2 Electrodes 6g, 7e Wirings 7e0, 9b0 Conductive layers 8a Common potential wirings
8a0... Opening 8a1... Virtual line 8e... Light shielding layer 9a... Pixel electrode 9b... Dummy pixel electrode 10... First substrate 10a... Display area 11... Temperature detection element 11a... Anode 11c... Cathode , 12... Electrostatic protection circuit 20... Second substrate 21... Common electrode 29... Parting line 30... Pixel transistor 30n1, 30n2... N-channel transistor 30p1, 30p2... P-channel transistor 31a, 31h... Semiconductor layer 50 Electro-optical layer 60 Upper circuit 65 Image control circuit 66 Temperature detection drive circuit 70 Wiring board 75 Drive IC 76 Control circuit 100, 100B, 100G, 100R... Electro-optical device 100a... Pixel 100p... Electro-optical panel 101... Data line drive circuit 101a... Selection circuit 102a... Anode terminal 102c... Cathode terminal 104... Scanning line drive circuit 104a... Inverter circuit 106... Precharge circuit 110... Optical path shift element 160... Projection optical system 161... Dichroic prism 162... Projection lens system 180... Screen 190... Illumination device 1000... Projection type display device D... Diode C1 ...first capacitive element, C2...second capacitive element, D1...first diode, D2...second diode, D3...third diode, E...first direction, F...second direction, P1, P2...relay section, R1... first resistance element, R2... second resistance element, R3... resistance element, W1... pattern width, W2... electrode width, Ca, Cb... parasitic capacitance, Ha1, Hb1... first horizontal scanning period, Ha2, Hb2... Second horizontal scanning period, La... anode wiring, Lc... cathode wiring, Cn... connection node

Claims (17)

wiring having an opening outside the display area;
a temperature detection element provided outside the display area and inside the opening in plan view;
An electro-optical device comprising: The electro-optical device according to claim 1,
An electro-optical device according to claim 1, wherein an island-shaped light shielding layer, which is the same layer as the wiring, is provided inside the opening in a plan view so as to be separated from the wiring. 3. The electro-optical device according to claim 1,
comprising a plurality of data lines in the display area;
The electro-optical device according to claim 1, wherein each of the plurality of data lines has a portion overlapping with the wiring in plan view. The electro-optical device according to claim 3,
An electro-optical device, wherein a constant potential is applied to the wiring. 5. The electro-optical device according to claim 4,
a liquid crystal layer;
a conductive layer to which a common potential is applied between the liquid crystal layer and the wiring;
An electro-optical device comprising: The electro-optical device according to any one of claims 1 to 5,
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
the first diode and the second diode are arranged along a first direction;
The width of the electrode in a second direction intersecting the first direction is the width of the semiconductor layer forming the first diode and the width of the semiconductor layer forming the second diode in the second direction. An electro-optical device characterized by having a portion narrower than a. The electro-optical device according to any one of claims 1 to 5,
complementary transistors having an N-channel transistor and a P-channel transistor outside the display area;
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
The distance between the semiconductor layer forming the first diode and the semiconductor layer forming the second diode is equal to or less than the distance between the semiconductor layer forming the N-channel transistor and the semiconductor layer forming the P-channel transistor. An electro-optical device characterized by: The electro-optical device according to any one of claims 1 to 5,
A signal wiring to which an AC signal is supplied is provided outside the display area,
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
the first diode and the second diode are arranged along a first direction;
A cathode wiring electrically connected to the first diode extends along the first direction between the first diode, the second diode, and the signal wiring in plan view. An electro-optical device characterized by: The electro-optical device according to any one of claims 1 to 5,
A signal wiring to which an AC signal is supplied is provided outside the display area,
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
the first diode and the second diode are arranged along a first direction;
The electro-optical device, wherein the signal wiring extends along a second direction that intersects with the first direction. In the electro-optical device according to any one of claims 3 to 5,
a selection circuit that selects the plurality of data lines;
a control circuit that controls the selection circuit for each horizontal scanning period in the precharge period;
An electro-optical device comprising: 11. The electro-optical device according to claim 10,
In the plurality of horizontal scanning periods, a first horizontal scanning period in which a precharge signal is supplied to a part of the plurality of data lines, and data on a part of the plurality of data lines different from the part of the data lines. and a second horizontal scanning period for applying said precharge signal to a line. 11. The electro-optical device according to claim 10,
The plurality of horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to all of the plurality of data lines and a second horizontal scanning period in which a precharge signal is not supplied to all of the plurality of data lines. , and an electro-optical device. a temperature detection element provided outside the display area;
a wiring having a portion overlapping with the temperature detection element in a plan view;
with
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
the anode of the first diode and the cathode of the first diode are arranged along a first direction along with the cathode of the first diode and the anode of the second diode, respectively;
The width of the electrode in a second direction intersecting the first direction is the width of the semiconductor layer forming the first diode and the width of the semiconductor layer forming the second diode in the second direction. An electro-optical device characterized by having a portion narrower than a. a temperature detection element provided outside the display area;
a wiring having a portion overlapping with the temperature detection element in a plan view;
complementary transistors having an N-channel transistor and a P-channel transistor outside the display area;
with
The temperature detection element has a first diode, a second diode, and an electrode electrically connecting the first diode and the second diode in series,
The distance between the semiconductor layer forming the first diode and the semiconductor layer forming the second diode is equal to or less than the distance between the semiconductor layer forming the N-channel transistor and the semiconductor layer forming the P-channel transistor. An electro-optical device characterized by: a plurality of data lines provided in the display area;
a common potential wiring having a portion overlapping with each of the plurality of data lines in plan view;
a temperature detection element that overlaps with the wiring in a plan view outside the display area;
a selection circuit that selects the plurality of data lines;
a control circuit that controls the selection circuit for each horizontal scanning period in the precharge period;
with
In the plurality of horizontal scanning periods, a first horizontal scanning period in which a precharge signal is supplied to a part of the plurality of data lines, and data on a part of the plurality of data lines different from the part of the data lines. and a second horizontal scanning period for applying said precharge signal to a line. a plurality of data lines provided in the display area;
a common potential wiring having a portion overlapping with each of the plurality of data lines in plan view;
a temperature detection element that overlaps with the wiring in a plan view outside the display area;
a selection circuit that selects the plurality of data lines;
a control circuit that controls the selection circuit for each horizontal scanning period in the precharge period;
with
The plurality of horizontal scanning periods include a first horizontal scanning period in which a precharge signal is supplied to all of the plurality of data lines and a second horizontal scanning period in which a precharge signal is not supplied to all of the plurality of data lines. , and an electro-optical device. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 16.

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