JP2023039259A - Rush current prevention circuit - Google Patents

Abstract

To reduce power applied to a current limiting element to the same as or lower than that in startup even in rapid power recovery after an instantaneous interruption or a deep instantaneous voltage drop of a power supply circuit.SOLUTION: A rush current prevention circuit 5 is provided with: a current limiting element FET disposed on a power supply line, and gradually increasing a control voltage at the time of startup and power recovery of a power supply circuit 1 to prevent a rush current to a primary side capacitor CL on the power supply circuit 1 side of a load circuit 2; an integration circuit capacitor C3 and an integration circuit resistor R1 connected in parallel with the power supply circuit 1 to gradually increase a control voltage of the current limiting element FET at the time of startup and power recovery of the power supply circuit 1; and a rapid discharging capacitor C8 connected in series with the integration circuit capacitor C3 and connected in parallel with the integration circuit resistor R1 to discharge together with a discharge of the integration circuit capacitor C3 along with a discharge of the primary side capacitor CL at the time of an instantaneous interruption or an instantaneous voltage drop of the power supply circuit 1.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to an inrush current prevention circuit that prevents an inrush current from flowing into a primary-side capacitor on the power supply circuit side of a load circuit when the power supply circuit is activated and power is restored.

Patent Documents 1 and 2 disclose inrush current prevention circuits that prevent inrush current to a primary capacitor on the power supply circuit side of a load circuit when the power supply circuit is started.

First, the inrush current prevention circuit of the first prior art (Patent Document 1) will be described. FIG. 1 shows the circuit configuration of the inrush current prevention circuit of the first prior art. FIG. 2 shows an example of circuit characteristics of the inrush current prevention circuit of the first prior art. The rush current prevention circuit 3 includes an integration circuit resistor R1, a power voltage dividing resistor R2, an integration circuit capacitor C3, a feedback circuit resistor R4, a feedback circuit capacitor C5, an oscillation prevention resistor R6, and a current limiting element FET. The load circuit 2 has a primary side capacitor CL. In FIG. 2, the input voltage Vin from the power supply circuit 1 is DC48V, the equivalent resistance RL of the load circuit 2 is 48Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1A, and the primary capacitor CL is 100μF. , the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12V.

When the power supply circuit 1 is started, the gate voltage of the current limiting element FET is gradually increased to prevent rush current to the primary side capacitor CL. The integrating circuit capacitor C3, the integrating circuit resistor R1, and the power supply voltage dividing resistor R2 gradually increase the gate voltage of the current limiting element FET when the power supply circuit 1 is started. The integration circuit resistor R1 and the power supply voltage dividing resistor R2 set the upper limit of the gate voltage of the current limiting element FET lower than the input voltage from the power supply circuit 1. FIG. In the left column of FIG. 2, the voltage across the terminals of the power supply voltage dividing resistor R2 reaches the gate ON/OFF threshold voltage Vth=2V of the current limiting element FET 2 ms after the start of the power supply circuit 1, and the power supply circuit 1 starts up. 200 ms later, a steady state is reached. When the power supply circuit 1 is started, the power consumption of the current limiting element FET is 26 W 10 ms after the power supply circuit 1 is started, and the accumulated heat amount of the current limiting element FET is 340 mJ 20 ms after the power supply circuit 1 is started. When the power supply circuit 1 is started, these characteristics of the current limiting element FET correspond to 6 W when converted into the allowable loss of the current limiting element FET.

Next, the inrush current prevention circuit of the second prior art (Patent Document 2) will be described. FIG. 3 shows the circuit configuration of the inrush current prevention circuit of the second prior art. FIG. 4 shows an example of circuit characteristics of the inrush current prevention circuit of the second prior art. The rush current prevention circuit 4 includes an integrating circuit resistor R1, a clamping element D1, a power voltage dividing resistor R2, a switching element D2, an integrating circuit capacitor C3, a rapid discharge resistor R9, a current limiting element FET and a transistor TR. The load circuit 2 has a primary side capacitor CL. In FIG. 4, the input voltage Vin from the power supply circuit 1 is DC48V, the equivalent resistance RL of the load circuit 2 is 48Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1A, and the primary capacitor CL is 100μF. , the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12V.

When the power supply circuit 1 is started, the gate voltage of the current limiting element FET is gradually increased to prevent rush current to the primary side capacitor CL. The integrating circuit capacitor C3, the integrating circuit resistor R1, and the power supply voltage dividing resistor R2 gradually increase the gate voltage of the current limiting element FET when the power supply circuit 1 is started. Switch element D2 conducts between integration circuit capacitor C3 and integration circuit resistor R1. The integration circuit resistor R1 and the power supply voltage dividing resistor R2 set the upper limit of the gate voltage of the current limiting element FET lower than the input voltage from the power supply circuit 1. FIG. In the left column of FIG. 4, the voltage across the terminals of the power supply voltage dividing resistor R2 reaches the gate ON/OFF threshold voltage Vth=2V of the current limiting element FET 2 ms after the start of the power supply circuit 1, and the power supply circuit 1 starts up. 200 ms later, a steady state is reached. When the power supply circuit 1 is started, the power consumption of the current limiting element FET is 26 W 10 ms after the power supply circuit 1 is started, and the accumulated heat amount of the current limiting element FET is 340 mJ 20 ms after the power supply circuit 1 is started. When the power supply circuit 1 is started, these characteristics of the current limiting element FET correspond to 6 W when converted into the allowable loss of the current limiting element FET.

JP-A-2005-045957 JP-A-05-336737

First, the problem to be solved by the first prior art (Patent Document 1) will be described. The integration circuit capacitor C3, integration circuit resistor R1, and power supply voltage dividing resistor R2 gradually decrease the gate voltage of the current limiting element FET in accordance with the discharge of the primary side capacitor CL when the power supply circuit 1 momentarily shuts down or drops. Let Here, the time constant of the CR discharge circuit composed of the integration circuit capacitor C3, the integration circuit resistor R1, and the power supply voltage dividing resistor R2 is several tens of times larger than the time constant of the discharge circuit of the primary side capacitor CL. The amount of voltage drop across the integrating circuit capacitor C3 is only R2/(R1+R2) times the amount of voltage drop across the primary side capacitor CL. Therefore, in the first row in the middle column of FIG. 2, the gate voltage of the current limiting element FET is 11 V even after 10 ms has passed after the momentary interruption of the power supply circuit 1 and after the deep momentary sag, and the gate ON/OFF threshold voltage Vth = 2V. In the second stage in the middle column of FIG. 2, the voltage across the terminals of the primary capacitor CL remains only 5 V as a residual voltage 10 ms after the momentary interruption of the power supply circuit 1 and after the deep voltage drop.

Here, before the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth=2V, the power supply circuit 1 may transition from the momentary interruption state or the deep voltage drop state to the power recovery state. be. Then, in the first stage in the right column of FIG. 2, the drain current of the current limiting element FET (which remains in the barely ON state) reaches 160 A as a re-inrush current immediately after the power supply circuit 1 is restored. . In the second stage in the right column of FIG. 2, the power consumption of the current limiting element FET reaches the maximum power of 2.5 kW within 20 μs after the power supply circuit 1 recovers power. Furthermore, in the third row in the right column of FIG. 2, the amount of heat accumulated in the current limiting element FET reaches 39 mJ 20 μs after the power supply circuit 1 is restored. Therefore, when the power supply circuit 1 rapidly recovers, these characteristics of the current limiting element FET are equivalent to 24 W in terms of the allowable loss of the current limiting element FET, which is four times as large as that at the start of the power supply circuit 1. corresponds to the allowable loss of the current limiting element FET. Then, a large-sized product is required as the current limiting element FET.

Next, the problem to be solved by the second prior art (Patent Document 2) will be described. The integration circuit capacitor C3 and the rapid discharge resistor R9 gradually decrease the gate voltage of the current limiting element FET as the primary side capacitor CL discharges when the power supply circuit 1 is instantaneously interrupted or lowered. The switch element D2 turns on the transistor TR when the voltage between the terminals of the integration circuit capacitor C3 becomes higher than the voltage between the terminals of the power supply voltage dividing resistor R2, thereby switching the integration circuit capacitor C3 and the rapid discharge resistor. Conducts between R9. Here, the time constant of the CR discharge circuit composed of the integration circuit capacitor C3 and the rapid discharge resistor R9 is substantially equal to that of the discharge circuit of the primary side capacitor CL. The amount of voltage drop across the integrating circuit capacitor C3 is only R2/(R1+R2) times the amount of voltage drop across the primary side capacitor CL. Therefore, in the first stage in the middle column of FIG. 4, the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth=2V 8 ms after the momentary interruption of the power supply circuit 1 and after the deep voltage drop. In the second row in the middle column of FIG. 4, the voltage across the terminals of the primary capacitor CL remains only 8 V as a residual voltage 8 ms after the momentary interruption of the power supply circuit 1 and after the deep momentary sag.

Here, before the gate voltage of the current limiting element FET drops to the gate ON/OFF threshold voltage Vth=2V, the power supply circuit 1 may transition from the momentary interruption state or the deep voltage drop state to the power recovery state. be. Then, in the first stage in the right column of FIG. 4, the drain current of the current limiting element FET (which remains in the barely ON state) reaches 130 A as a re-inrush current immediately after the power supply circuit 1 is restored. . In the second row in the right column of FIG. 4, the power consumption of the current limiting element FET reaches the maximum power of 1.8 kW within 20 μs after the power supply circuit 1 recovers power. Furthermore, in the third row in the right column of FIG. 4, the amount of heat accumulated in the current limiting element FET reaches 27 mJ 20 μs after the power supply circuit 1 is restored. Therefore, when the power supply circuit 1 rapidly recovers, these characteristics of the current limiting element FET are equivalent to 18 W when converted into the allowable loss of the current limiting element FET, which is three times as large as when the power supply circuit 1 is started. corresponds to the allowable loss of the current limiting element FET. Then, a large-sized product is required as the current limiting element FET.

Therefore, in order to solve the above problems, the present disclosure maintains the inrush current prevention function at startup of the power supply circuit at the same level as the prior art, and rapidly restores power after an instantaneous interruption or a deep voltage drop in the power supply circuit. An object of the present invention is to reduce the power applied to a current limiting element to the same level or lower than that at the time of startup, even at times.

To solve the above problem, an integrating circuit capacitor and a rapid discharge capacitor are connected in series with each other and in parallel with the primary side capacitor. When the power supply circuit is momentarily interrupted or dropped, the integration circuit capacitor and the rapid discharge capacitor are discharged along with the discharge of the primary side capacitor. Here, the discharge circuit composed of the integrating circuit capacitor and the rapid discharge capacitor is not a CR discharge circuit, but discharges together with the discharge of the primary side capacitor without a CR time constant.

Specifically, the present disclosure is an inrush current prevention circuit that prevents an inrush current from flowing into a primary capacitor on the power supply circuit side of a load circuit when the power supply circuit is started and when power is restored, and is arranged in a power supply line. a current limiting element for preventing rush current to the primary side capacitor by gradually increasing the control voltage when the power supply circuit is started and when the power is restored; an integrating circuit capacitor and an integrating circuit resistor for gradually increasing the control voltage of the current limiting element at the time of start-up and power recovery; connected in series with the integrating circuit capacitor and in parallel with the integrating circuit resistor; and a rapid discharge capacitor that discharges together with the discharge of the integration circuit capacitor in accordance with the discharge of the primary side capacitor at the time of momentary interruption or voltage drop of the circuit.

According to this configuration, the control voltage of the current limiting element can be rapidly lowered to the control ON/OFF threshold voltage Vth or less at the time of momentary interruption or deep voltage drop of the power supply circuit, and the residual voltage of the primary side capacitor can be further reduced. At a high point, the inrush current protection circuit can be deactivated. Therefore, even when the power supply circuit is rapidly restored afterward, the power applied to the current limiting element can be reduced to the level equal to or lower than that at startup.

Further, in the present disclosure, the amount of voltage drop in the integrating circuit capacitor becomes larger than the amount of voltage drop in the rapid discharge capacitor when the power supply circuit is instantaneously interrupted or when the power supply circuit is deep. An inrush current characterized in that the capacitance of the integrating circuit capacitor is set smaller than the capacitance of the rapid discharge capacitor so that the voltage advances the timing of switching the current limiting element from the on state to the off state. It is a prevention circuit.

According to this configuration, the control voltage of the current limiting element can be rapidly lowered to the control ON/OFF threshold voltage Vth or less in a short time at the time of momentary interruption or deep voltage drop of the power supply circuit, and the primary side capacitor remains. The inrush current protection circuit can be deactivated at a higher voltage. Even when the power supply circuit recovers power immediately before the inrush current prevention circuit stops, the maximum value of the re-inrush current to the current limiting element can be kept lower.

Further, the present disclosure is connected between the integration circuit capacitor and the rapid discharge capacitor, and when the power supply circuit is started and when the power is restored, the control terminal of the current limiting element and the integration circuit capacitor and the rapid discharge capacitor are connected. and a switch element that conducts between the integrating circuit capacitor and the rapid discharge capacitor when the power supply circuit is interrupted or dropped. .

According to this configuration, by separating the integrating circuit capacitor and the rapid discharge capacitor when the power supply circuit is started and when the power is restored, it is possible to prevent an inrush current from flowing into the series circuit of these capacitors, and at the same time, the current limiting element. Therefore, the inrush current prevention function of the current limiting element can be maintained.

Further, the present disclosure includes a power supply voltage dividing resistor connected in series with the rapid discharge capacitor without passing through the switch element and connected in parallel with the integration circuit capacitor through the switch element, and a bleeder resistor connected in parallel with the rapid discharge capacitor and connected in parallel with the integration circuit resistor via the switch element, wherein the rapid discharge capacitor, The power supply voltage dividing resistor and the bleeder resistor form a CR charging circuit for the rapid discharge capacitor in the inrush current prevention circuit.

According to this configuration, the rapid discharge capacitor can be charged when the power supply circuit is started and when power is restored, and the rapid discharge capacitor can be discharged when the power supply circuit is interrupted or dropped. Then, the CR charging circuit for the rapid discharge capacitor and the CR charging circuit for the integrating circuit capacitor can be designed independently under the cut-off state of the switch element.

Further, according to the present disclosure, when the power supply circuit is started and power is restored, CR charging of the rapid discharge capacitor is completed, and the voltage between the terminals of the integration circuit capacitor is equal to the input voltage from the power supply circuit*the power supply Inrush current prevention, wherein the switch element conducts between the integration circuit capacitor and the rapid discharge capacitor when the voltage dividing resistance/(the power supply voltage dividing resistance + the bleeder resistance) becomes equal. circuit.

According to this configuration, the upper limit of the control voltage of the current limiting element can be set lower than the input voltage from the power supply circuit when the power supply circuit is activated and when power is restored.

Further, in the present disclosure, when the power supply circuit is started and when the power is restored, the time constant of the CR charging circuit composed of the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor is equal to the integrating circuit capacitor and the integrating circuit capacitor. The inrush current prevention circuit is characterized in that the time constant is set smaller than the time constant of a CR charging circuit composed of circuit resistance.

According to this configuration, it is possible to prevent the control voltage of the current limiting element from becoming higher than the set upper limit voltage when the power supply circuit is started and when power is restored.

In this way, the present disclosure maintains the inrush current prevention function at startup of the power supply circuit at the same level as the prior art, and even at the time of rapid power recovery after an instantaneous interruption or a deep voltage drop in the power supply circuit, The power applied to the current limiting element can be reduced to the same or less than that at startup.

1 is a diagram showing a circuit configuration of an inrush current prevention circuit of the first prior art; FIG. FIG. 10 is a diagram showing an example of circuit characteristics of the inrush current prevention circuit of the first prior art; FIG. 10 is a diagram showing a circuit configuration of an inrush current prevention circuit of the second prior art; FIG. 10 is a diagram showing an example of circuit characteristics of an inrush current prevention circuit of the second prior art; 1 is a diagram showing a circuit configuration of an inrush current prevention circuit of the present disclosure; FIG. FIG. 4 is a diagram showing the startup and power recovery of the inrush current prevention circuit of the present disclosure; FIG. 4 is a diagram showing momentary interruption and deep voltage sag of the inrush current prevention circuit of the present disclosure; It is a figure which shows the circuit characteristic example of the inrush current prevention circuit of this indication.

Embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments described below are examples of implementing the present disclosure, and the present disclosure is not limited to the following embodiments.

(Circuit Configuration of Inrush Current Prevention Circuit of Present Disclosure)
First, the circuit configuration of the inrush current prevention circuit of the present disclosure will be described. FIG. 5 shows the circuit configuration of the inrush current prevention circuit of the present disclosure. The inrush current prevention circuit 5 includes an integration circuit resistor R1, a power voltage dividing resistor R2, an integration circuit capacitor C3, a feedback circuit resistor R4, a feedback circuit capacitor C5, an oscillation prevention resistor R6, a bleeder resistor R7, a rapid discharge capacitor C8, and a current limiting element. An FET and a switch element D are provided. The load circuit 2 has a primary side capacitor CL.

The inrush current prevention circuit 5 prevents an inrush current from flowing into the primary side capacitor CL on the power supply circuit 1 side of the load circuit 2 when the power supply circuit 1 is started and when power is restored. That is, the current limiting element FET is arranged on the power supply line, and when the power supply circuit 1 is started and when power is restored, the control voltage is gradually increased to prevent rush current to the primary side capacitor CL. The integrating circuit capacitor C3 and the integrating circuit resistor R1 are connected in parallel with the power supply circuit 1, and gradually increase the control voltage of the current limiting element FET when the power supply circuit 1 is activated and when power is restored.

Here, in this embodiment, the current limiting element FET is a MOSFET, but as a modification, it may be a bipolar transistor or the like. In this embodiment, the current limiting element FET is arranged on the -IN to -OUT power supply line, but as a modification, the current limiting element FET may be arranged on the +IN to +OUT power supply line. When the power supply circuit 1 outputs AC instead of DC output, a rectifying element (not shown in FIG. 5) may be inserted in front of the input terminals (+IN terminal and -IN terminal) of the inrush current prevention circuit 5. .

The feedback circuit resistor R4 and the feedback circuit capacitor C5 stabilize the charging current of the primary side capacitor CL when the power supply circuit 1 is started and when power is restored. The oscillation prevention resistor R6 prevents the current limiting element FET from oscillating when the power supply circuit 1 is started and when power is restored.

The rapid discharge capacitor C8 is connected in series with the integration circuit capacitor C3 and in parallel with the integration circuit resistor R1. Discharge is performed together with the discharge of the capacitor C3.

Here, the discharge circuit composed of the integration circuit capacitor C3 and the rapid discharge capacitor C8 is not a CR discharge circuit further comprising an integration circuit resistor R1, a power supply voltage dividing resistor R2 and a bleeder resistor R7, but without a CR time constant. , can be discharged integrally with the discharge of the primary side capacitor CL.

Therefore, the gate voltage of the current limiting element FET can be rapidly dropped to the ON/OFF threshold voltage Vth or less at the time of momentary interruption or deep momentary drop of the power supply circuit 1, and the residual voltage of the primary side capacitor CL is higher. , the inrush current prevention circuit 5 can be stopped. Then, even when the power supply circuit 1 is rapidly restored afterward, the power applied to the current limiting element FET can be reduced to the level equal to or lower than that at startup.

When the power supply circuit 1 is interrupted or has a deep voltage drop, the amount of voltage drop across the integrating circuit capacitor C3 becomes greater than the amount of voltage drop across the rapid discharge capacitor C8, and the gate voltage of the current limiting element FET becomes The capacitance of the integrating circuit capacitor C3 is set smaller than the capacitance of the rapid discharge capacitor C8 so as to advance the timing of switching the FET from the ON state to the OFF state.

If the capacitance of the integrating circuit capacitor C3 is set to be larger than the capacitance of the rapid discharge capacitor C8, the amount of voltage drop across the integrating circuit capacitor C3 will be rapidly discharged when the power supply circuit 1 experiences a momentary power failure or a deep voltage drop. It becomes smaller than the amount of voltage drop of the capacitor C8, and the time for the gate voltage of the current limiting element FET to switch the current limiting element FET from the ON state to the OFF state becomes longer.

On the other hand, in the present disclosure, the gate voltage of the current limiting element FET can be rapidly decreased to the ON/OFF threshold voltage Vth or less in a short time at the moment of momentary interruption or deep voltage drop of the power supply circuit 1, and the primary side capacitor The inrush current prevention circuit 5 can be stopped when the residual voltage of CL is higher. Even if the power supply circuit 1 recovers power immediately before the inrush current prevention circuit 5 stops, the maximum value of the re-inrush current to the current limiting element FET can be kept lower.

The switch element D is connected between the integration circuit capacitor C3 and the rapid discharge capacitor C8, and when the power supply circuit 1 is started and when power is restored, the switch element D is connected to the gate terminal of the current limiting element FET and the integration circuit capacitor C3 and the rapid discharge capacitor C8. is cut off between them, and when the power supply circuit 1 momentarily interrupts or drops, the integration circuit capacitor C3 and the rapid discharge capacitor C8 are electrically connected.

If the switch element D conducts between the gate terminal of the current limiting element FET and the integration circuit capacitor C3 and the rapid discharge capacitor C8 when the power supply circuit 1 is started and when the power is restored, the integration circuit capacitor C3 and the rapid discharge capacitor C8 are electrically connected. Since the inrush current of C8 cannot be prevented and the gate voltage of the current limiting element FET is rapidly increased at the same time, the inrush current preventing function of the current limiting element FET cannot be maintained.

On the other hand, in the present disclosure, by separating the integration circuit capacitor C3 and the rapid discharge capacitor C8 when the power supply circuit 1 is started and when power is restored, it is possible to prevent a rush current to flow into the series circuit of these capacitors. At the same time, since the gate voltage of the current limiting element FET does not rise rapidly, the rush current preventing function of the current limiting element FET can be maintained. Then, as described above, when the power supply circuit 1 is instantaneously interrupted or when there is a deep voltage drop, the gate voltage of the current limiting element FET can be rapidly decreased to the ON/OFF threshold voltage Vth or less, and the primary side capacitor CL remains. The inrush current prevention circuit 5 can be stopped when the voltage is higher.

The power supply voltage dividing resistor R2 is connected in series with the rapid discharge capacitor C8 without the switching element D, and is connected in parallel with the integration circuit capacitor C3 with the switching element D therebetween. The bleeder resistor R7 is connected in parallel with the rapid discharge capacitor C8 without the switching element D, and is connected in parallel with the integrating circuit resistor R1 with the switching element D therebetween.

Here, when the power supply circuit 1 is started and when power is restored, the rapid discharge capacitor C8, the power supply voltage dividing resistor R2 and the bleeder resistor R7 constitute a CR charging circuit for the rapid discharge capacitor C8. On the other hand, when the power supply circuit 1 is started and when power is restored, the integrating circuit capacitor C3 and the integrating circuit resistor R1 constitute a CR charging circuit for the integrating circuit capacitor C3. Then, when the power supply circuit 1 is started and when power is restored, the CR charging circuit for the rapid discharge capacitor C8 and the CR charging circuit for the integration circuit capacitor C3 can operate independently with the switch element D cut off.

Therefore, the rapid discharge capacitor C8 can be charged when the power supply circuit 1 is started and when the power is restored, and the rapid discharge capacitor C8 can be discharged when the power supply circuit 1 is interrupted or dropped. Then, the CR charging circuit for the rapid discharge capacitor C8 and the CR charging circuit for the integration circuit capacitor C3 can be designed independently with the switch element D cut off.

When the power supply circuit 1 is started and when the power is restored, the CR charge of the rapid discharge capacitor C8 is completed, and the voltage across the terminals of the integration circuit capacitor C3 becomes the input voltage Vin from the power supply circuit 1*power supply voltage dividing resistor R2/( When equal to the power supply voltage divider resistor R2+bleeder resistor R7), the switch element D conducts between the integration circuit capacitor C3 and the rapid discharge capacitor C8. When the bleeder resistor R7 and the integration circuit resistor R1 are connected in parallel after the switch element D is turned on, the voltage across the terminals of the integration circuit capacitor C3 is the input voltage Vin from the power supply circuit 1*power supply voltage dividing resistor R2/ (Power supply voltage dividing resistor R2 + bleeder resistor R7//Integration circuit resistor R1) and stabilizes (here, "//" indicates parallel connection).

Therefore, when the power supply circuit 1 is started and when the power is restored, the upper limit of the gate voltage of the current limiting element FET (= input voltage Vin from the power supply circuit 1 * power supply voltage dividing resistance R2 / (power supply voltage dividing resistance R2 + bleeder resistance R7 // The integration circuit resistance R1)) can be set lower than the input voltage from the power supply circuit 1 .

When the power supply circuit 1 is started and when power is restored, the time constant of the CR charging circuit composed of the rapid discharge capacitor C8, the power supply voltage dividing resistor R2 and the bleeder resistor R7 is composed of the integrating circuit capacitor C3 and the integrating circuit resistor R1. It is set smaller than the time constant of the CR charging circuit.

Therefore, when the power supply circuit 1 is started and when power is restored, the gate voltage of the current limiting element FET is set to the set upper limit voltage (= input voltage Vin from the power supply circuit 1 * power supply voltage dividing resistor R2 / (power supply voltage dividing resistor R2 + bleeder Resistor R7//integrator circuit resistor R1)) may not be high.

(When the inrush current prevention circuit of the present disclosure is activated and when power is restored)
Based on the circuit configuration of the inrush current prevention circuit of the present disclosure, FIG. 6 shows the time when the inrush current prevention circuit of the present disclosure is started from the stopped state and the time of power recovery. The upper part of FIG. 6 shows the initial start-up and the initial recovery from the state in which the inrush current prevention circuit 5 is stopped. The lower part of FIG. 6 shows the end of startup and the end of power recovery from the state in which the inrush current prevention circuit 5 is stopped.

First, the initial start-up and initial recovery from the state in which the inrush current prevention circuit 5 is stopped will be described. The voltage VR2 between the terminals of the power supply voltage dividing resistor R2 is equal to the input voltage Vin from the power supply circuit 1, and the voltage VGS between the terminals of the integration circuit capacitor C3 (=the gate voltage of the current limiting element FET) is 0 or the ON/OFF threshold. It is equal to or lower than the voltage Vth. The current limiting element FET is set to the OFF state, and the switching element D cuts off between the integrating circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the terminals of the primary capacitor CL is 0 or the residual voltage Vres.

A CR charging circuit composed of the primary side capacitor CL and the load circuit 2 charges the primary side capacitor CL with a time constant CL*Rin. Here, Rin is the sum of the internal resistance of the power supply circuit 1 and the Ron of the current limiting element FET. A CR charging circuit composed of a rapid discharge capacitor C8, a power voltage dividing resistor R2 and a bleeder resistor R7 charges the rapid discharge capacitor C8 with a time constant C8*(R2//R7). A CR charging circuit composed of an integrating circuit capacitor C3 and an integrating circuit resistor R1 charges the integrating circuit capacitor C3 with a time constant C3*R1.

Next, the end of startup and the end of power recovery from the state in which the inrush current prevention circuit 5 is stopped will be described. First, the voltage VR2 across the terminals of the power supply voltage dividing resistor R2 becomes equal to the input voltage Vin from the power supply circuit 1*power supply voltage dividing resistor R2/(power voltage dividing resistor R2+bleeder resistor R7), and then the integration circuit capacitor The voltage VGS across the terminals of C3 (=the gate voltage of the current limiting element FET) is equal to the voltage VR2 across the terminals of the power voltage dividing resistor R2. The current limiting device FET is switched to the ON state and the switch device D conducts between the integrator circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the terminals of the primary side capacitor CL becomes equal to the input voltage Vin from the power supply circuit 1 .

(At the time of instantaneous interruption and deep voltage drop of the inrush current prevention circuit of the present disclosure)
Based on the circuit configuration of the inrush current prevention circuit of the present disclosure, FIG. 7 shows a momentary interruption and a deep voltage drop from a steady state of the inrush current prevention circuit of the present disclosure. The upper part of FIG. 7 shows the initial stage of instantaneous interruption and the initial stage of deep voltage sag from the state in which the inrush current prevention circuit 5 is steady. The lower part of FIG. 7 shows the termination of instantaneous interruption and the termination of deep voltage drop from the state in which the inrush current prevention circuit 5 is steady.

First, the initial stage of instantaneous interruption and the initial period of deep voltage sag from the steady state of the inrush current prevention circuit 5 will be described. Subsequently, the inter-terminal voltage VR2 of the power supply voltage dividing resistor R2 is equal to the steady-state input voltage Vin from the power supply circuit 1*power supply voltage dividing resistor R2/(power supply voltage dividing resistor R2+bleeder resistor R7//integrating circuit resistor R1). The voltage across the terminals of the integration circuit capacitor C3 VGS (=the gate voltage of the current limiting element FET) remains equal to the voltage across the terminals of the power supply voltage dividing resistor R2 during normal operation VR2. The current limiting element FET is maintained in the ON state, and the switch element D conducts between the integrating circuit capacitor C3 and the rapid discharge capacitor C8. The voltage across the terminals of the primary capacitor CL is equal to the steady-state input voltage Vin from the power supply circuit 1 .

A CR discharge circuit composed of the primary side capacitor CL and the equivalent resistance RL of the load circuit 2 discharges the primary side capacitor CL with a time constant CL*RL. The discharge circuit composed of the integration circuit capacitor C3 and the rapid discharge capacitor C8 is integrated with the discharge of the primary side capacitor CL without a CR time constant as the primary side capacitor CL discharges, and the integration circuit capacitor C3 and discharge the rapid discharge capacitor C8. The voltage drop across the integrating circuit capacitor C3 (= C8/(C3+C8) times the voltage drop across the primary capacitor CL, where C8>C3) is the voltage drop across the rapid discharge capacitor C8 (= the voltage drop across the primary capacitor CL C3/(C3+C8) times the voltage drop, where C3<C8.

Next, the termination of instantaneous interruption and the termination of deep voltage drop from the state in which the inrush current prevention circuit 5 is steady will be described. First, the voltage VGS across the terminals of the integrating circuit capacitor C3 (=the gate voltage of the current limiting element FET) becomes equal to the ON/OFF threshold voltage Vth of the current limiting element FET, and the voltage across the terminals of the power supply voltage dividing resistor R2 VR2 becomes equal to the voltage VGS across the integrating circuit capacitor C3. The current limiting device FET is switched to the OFF state and the switch device D conducts between the integrator circuit capacitor C3 and the rapid discharge capacitor C8. A sufficiently large residual voltage Vres remains in the voltage across the terminals of the primary side capacitor CL. After that, the CR discharge circuit composed of the integration circuit capacitor C3 and the power supply voltage dividing resistor R2 additionally discharges the integration circuit capacitor C3 with a time constant C3*R2, and is composed of the rapid discharge capacitor C8 and the bleeder resistor R7. The CR discharge circuit additionally discharges the fast discharge capacitor C8 with a time constant C8*R7.

(Example of circuit characteristics of the inrush current prevention circuit of the present disclosure)
Based on the circuit configuration of the inrush current prevention circuit of the present disclosure, FIG. 8 shows an example of circuit characteristics of the inrush current prevention circuit of the present disclosure. In FIG. 8, the input voltage Vin from the power supply circuit 1 is DC48V, the equivalent resistance RL of the load circuit 2 is 48Ω, the current IL of the equivalent resistance RL of the load circuit 2 is 1A, and the primary side capacitor CL is 100μF. , the gate ON/OFF threshold voltage Vth of the current limiting element FET is 2V, and the gate upper limit voltage VGSmax of the current limiting element FET is 12V. The circuit constants of the inrush current prevention circuit 5 are set as follows.

When the power supply circuit 1 is stable, the integrating circuit resistor R1 needs to pass a current sufficiently large compared to the gate leakage current Igss of the current limiting element FET: (Vin-VGS)/R1>>Igss. When the power supply circuit 1 is stable, the power supply voltage dividing resistor R2 needs to pass a current that is sufficiently larger than the current flowing through the integrating circuit resistor R1: VGS/R2>>(Vin-VGS)/R1. Integrating circuit capacitor C3 sets T3 to the longer of the chattering period at startup of power supply circuit 1 and the stabilization period of input voltage Vin from power supply circuit 1, and starts current limiting element FET. The delay period needs to be set: C3*R1*Vth/Vin=T3.

After setting the integrating circuit resistor R1, the power supply voltage dividing resistor R2, and the integrating circuit capacitor C3, C3<C8, Vin*R2/(R2+R7//R1 )=VGS, Vth<VGS<VGSmax, C8*(R2//R7)<C3*R1, the circuit constants of the rush current prevention circuit 5 must be set.

In the left column of FIG. 8, the voltage across the terminals of the power supply voltage dividing resistor R2 is equal to the input voltage of 48V from the power supply circuit 1 immediately after the power supply circuit 1 is started, and reaches a stable state 100 ms after the power supply circuit 1 is started. do. The gate voltage of the current limiting element FET reaches the ON/OFF threshold voltage Vth=2V of the current limiting element FET 2 ms after the power supply circuit 1 is started, and reaches a stable state 100 ms after the power supply circuit 1 is started. When the power supply circuit 1 is started, the power consumption of the current limiting element FET is 26 W 10 ms after the power supply circuit 1 is started, and the accumulated heat amount of the current limiting element FET is 340 mJ 20 ms after the power supply circuit 1 is started. When the power supply circuit 1 is started, these characteristics of the current limiting element FET correspond to 6 W when converted into the allowable loss of the current limiting element FET.

In the first stage in the middle column of FIG. 8, the gate voltage of the current limiting element FET drops to the ON/OFF threshold voltage Vth=2V 2 ms after the momentary interruption of the power supply circuit 1 and after the deep momentary drop. In the second row in the middle column of FIG. 8, the voltage across the terminals of the primary capacitor CL remains at a sufficiently high residual voltage of 32 V 2 ms after the momentary interruption of the power supply circuit 1 and after the deep momentary sag. It is assumed that the power supply circuit 1 returns to the power restoration state with the current limiting element FET in the barely ON state.

In the first stage in the right column of FIG. 8, the drain current of the current limiting element FET is suppressed to 30 A as a re-inrush current immediately after power supply circuit 1 recovers. In the second stage in the right column of FIG. 8, the power consumption of the current limiting element FET is suppressed to 0.3 kW even at the maximum power within 20 μs after the power supply circuit 1 recovers. In the third row in the right column of FIG. 8, the amount of heat accumulated in the current limiting element FET is suppressed to 4.3 mJ in 20 μs after the power supply circuit 1 is restored. Therefore, when the power supply circuit 1 is rapidly restored, these characteristics of the current limiting element FET correspond to 3 W in terms of the allowable loss of the current limiting element FET, which is a small current compared to when the power supply circuit 1 is started. It corresponds to the allowable loss of the limiting element FET. Then, the current limiting element FET may be of a small type in which only the allowable loss of the current limiting element FET at the start of the power supply circuit 1 is taken into consideration.

The inrush current prevention circuit of the present disclosure supplies AC power or DC power to the internal circuit of a device that operates by connecting to an AC power source or DC power source (the use of the device is not limited to a specific application). Accordingly, the power applied to the current limiting element at the time of momentary interruption or deep voltage drop can be made equal to or less than the power applied to the current limiting element at startup.

1: Power supply circuit 2: Load circuits 3, 4, 5: Rush current prevention circuit R1: Integration circuit resistor D1: Clamp element R2: Power supply voltage dividing resistor D2: Switch element C3: Integration circuit capacitor R4: Feedback circuit resistor C5: Feedback Circuit capacitor R6: Oscillation prevention resistor R7: Bleeder resistor C8: Rapid discharge capacitor R9: Rapid discharge resistor FET: Current limiting element TR: Transistor D: Switching element CL: Primary side capacitor

Claims (6)

An inrush current prevention circuit that prevents an inrush current to a primary side capacitor on the power supply circuit side of a load circuit when the power supply circuit is started and when power is restored,
a current limiting element disposed on a power supply line for gradually increasing a control voltage when the power supply circuit is started and when power is restored, thereby preventing rush current to the primary side capacitor;
an integrating circuit capacitor and an integrating circuit resistor, connected in parallel with the power supply circuit, for gradually increasing the control voltage of the current limiting element when the power supply circuit is activated and when power is restored;
connected in series with the integration circuit capacitor and connected in parallel with the integration circuit resistor, and when the power supply circuit is momentarily interrupted or dropped, the primary side capacitor is discharged along with the discharge of the integration circuit capacitor, a rapid discharge capacitor for discharging;
An inrush current prevention circuit, comprising: When the power supply circuit is instantaneously interrupted or has a deep voltage drop, the amount of voltage drop in the integrating circuit capacitor becomes larger than the amount of voltage drop in the rapid discharge capacitor, and the control voltage of the current limiting element is reduced to the level of the current limit. 2. The inrush according to claim 1, wherein the capacitance of the integrating circuit capacitor is set smaller than the capacitance of the rapid discharge capacitor so as to advance the timing of switching the element from the ON state to the OFF state. Current protection circuit. connected between the integrating circuit capacitor and the rapid discharging capacitor, and cuts off the control terminal of the current limiting element and between the integrating circuit capacitor and the rapid discharging capacitor when the power supply circuit is started and when power is restored; 3. The rush current prevention according to claim 1 or 2, further comprising a switching element that conducts between said integrating circuit capacitor and said rapid discharge capacitor at the time of momentary interruption or momentary drop of said power supply circuit. circuit. a power supply voltage dividing resistor connected in series with the rapid discharge capacitor without passing through the switching element and connected in parallel with the integrating circuit capacitor through the switching element;
a bleeder resistor connected in parallel with the rapid discharge capacitor without passing through the switch element and connected in parallel with the integration circuit resistor through the switch element,
4. The rapid discharge capacitor according to claim 3, wherein the rapid discharge capacitor, the power supply voltage dividing resistor, and the bleeder resistor form a CR charging circuit for the rapid discharge capacitor when the power supply circuit is started and when power is restored. Inrush current prevention circuit. When the power supply circuit is started and when power is restored, the CR charging of the rapid discharge capacitor is completed, and the voltage between the terminals of the integration circuit capacitor is the input voltage from the power supply circuit*the power supply voltage dividing resistor/(the above 5. The inrush current according to claim 4, wherein the switch element conducts between the integration circuit capacitor and the rapid discharge capacitor when the power supply voltage dividing resistance+the bleeder resistance) becomes equal. protection circuit. The time constant of the CR charging circuit composed of the rapid discharge capacitor, the power supply voltage dividing resistor and the bleeder resistor when the power supply circuit is started and when the power is restored is composed of the integration circuit capacitor and the integration circuit resistance. 6. The rush current prevention circuit according to claim 4, wherein the time constant is set smaller than the time constant of the CR charging circuit.

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