JP2023034211A - Lifting device - Google Patents

Abstract

To provide a lifting device capable of reducing an allowable error when the same measured quantity is doubly calculated.SOLUTION: A lifting device 10 of the present invention comprises a first processing unit 51 to calculate a first measured quantity x1 by measuring a prescribed part, and a second processing unit 54 to calculate a second measured quantity x2 by measuring the prescribed part. The first processing unit outputs to the second processing unit a first synchronization signal at a first point in time t1, calculates the first measured quantity x1, and transmits the first measured quantity x1 to the second processing unit. The second processing unit calculates the second measured quantity x2 at a second point in time t2 when the first synchronization signal is inputted, stores it as second comparison object data, calculates a first error which is the error of the first measured quantity x1 against the second comparison object data at a point in time t2b when the first measured quantity x1 is received, and determines that there is abnormality if the first error exceeds a predetermined allowable error va.SELECTED DRAWING: Figure 2

Description

TECHNICAL FIELD The present invention relates to an elevator device that performs abnormality determination based on whether an error when calculating the same measurement quantity twice does not exceed an allowable error.

For example, the speed of an elevator can be calculated from the pulse signal of an encoder placed in a rotating part such as a hoist or speed governor. The calculation is doubled in the part, the calculated speed is transmitted to the other and compared, and if the error exceeds the allowable error, it is judged to be abnormal.

Specifically, the first processing unit transmits the velocity v1 calculated at time t1 to the second processing unit through serial communication. The second processing unit receives the speed v1 from the first processing unit through serial communication, and calculates the speed v2 at the reception time t2b. Then, the second processing unit calculates the error |v1-v2| If so, it is determined to be normal, and if the allowable error va is exceeded, it is determined to be abnormal.

In order to avoid erroneous determination, when the amount of change in the speed of the elevator in the period from time t1 when the first processing unit calculates the speed to time t2b when the second processing unit calculates the speed reaches the maximum speed change width vm. However, it is necessary to set the allowable error va so that vm≦va.

For example, when the elevator is uniformly accelerating at a maximum acceleration α0, the maximum speed change width during the time difference |t1-t2b| is vm=α0×|t1-t2b|.

Japanese Patent No. 5783993

However, when the speed is transmitted from the first processing unit to the second processing unit by serial communication, it takes time to output each bit after extracting each bit of the speed value expressed in binary. The receiving side needs time to combine the input bits into one and reproduce the speed value expressed in binary. That is, this serial communication can take a time on the order of tens of milliseconds. As a result, the time difference |t1−t2b| becomes longer and the maximum speed change width vm becomes larger, so it is necessary to adopt a large value for the allowable error va. As a result, the range of failure to be overlooked becomes large, and the accuracy of speed abnormality determination is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a lifting device capable of reducing the allowable error when calculating the same measurement quantity twice.

The lifting device of the present invention includes:
a first processing unit that measures a predetermined portion and calculates a first measurement amount x1;
a second processing unit that measures the predetermined portion and calculates a second measurement amount x2;
A lifting device comprising
The first processing unit outputs a first synchronization signal to the second processing unit at a first time t1, calculates a first measurement quantity x1, and transmits the first measurement quantity x1 to the second processing unit. ,
The second processing unit calculates a second measurement x2 at a second time t2 when the first synchronization signal is input and stores it as second comparison target data, and at a time t2b when the first measurement x1 is received A first error, which is an error of the first measured quantity x1 with respect to the second data to be compared, is obtained, and if the first error exceeds a preset allowable error va, an abnormality is determined.

The second processing unit outputs a second synchronization signal to the first processing unit at a third time t3, calculates a second measurement amount x2, and transmits the second measurement amount x2 to the first processing unit. ,
The first processing unit calculates the first measured quantity x1 at a fourth time t4 when the second synchronization signal is input, stores the first measured quantity x1 as first comparison target data, and calculates the first measured quantity x1 at a time t4b when the second measured quantity x2 is received. A second error, which is an error of the second measured quantity x2 with respect to the first data to be compared, may be obtained, and if the second error exceeds the allowable error va, it may be determined to be abnormal.

Further, the lifting device of the present invention is
a first processing unit that measures a predetermined portion every first cycle to calculate and store a first measurement quantity x1;
a second processing unit that measures the predetermined portion every second cycle to calculate and store a second measurement amount x2;
A lifting device comprising
The first processing unit outputs a first synchronization signal to the second processing unit at a first time t1, reads the latest first measurement quantity x1, and transmits the first measurement quantity x1 to the second processing unit. death,
The second processing unit reads the latest second measured quantity x2 at a second time t2 when the first synchronization signal is input, stores it as second comparison target data, and receives the first measured quantity x1 at time t2b. , a first error, which is an error of the first measured quantity x1 with respect to the second data to be compared, is obtained, and if the first error exceeds a preset allowable error va, it is judged to be abnormal.

The second processing unit outputs a second synchronization signal to the first processing unit at a third time t3, reads the latest second measurement amount x2, and transmits the second measurement amount x2 to the first processing unit. death,
The first processing unit reads the latest first measured quantity x1 at the fourth time t4 when the second synchronization signal is input, stores it as first comparison target data, and receives the second measured quantity x2 at time t4b. A second error, which is an error of the second measured quantity x2 with respect to the first data to be compared, is obtained, and if the second error exceeds the allowable error va, it is determined to be abnormal. .

After the time t2a at which the second measured quantity x2 read out at the second time t2 is calculated, the second time t2, the time t2a + the second period, and then the time t2b. The second period is set.

After the time t4a at which the first measured quantity x1 read out at the fourth time t4 is calculated, the fourth time t4, the time t4a + the first period, and then the time t4b. The first period is set.

The first processing unit digitally outputs the first synchronization signal and transmits the first measurement quantity x1 by serial communication,
The second processing section may be configured to digitally input the first synchronization signal and receive the first measurement quantity x1 through serial communication.

The second processing unit digitally outputs the second synchronization signal and transmits the second measurement quantity x2 by serial communication,
The first processing section may be configured to digitally input the second synchronization signal and receive the second measurement quantity x2 through serial communication.

The lifting device can be an elevator.

As the first measured quantity x1, the speed at which the car moves is measured to calculate the first speed v1, and as the second measured quantity x2, the speed at which the car moves is measured to calculate the second speed v2.

The first processing unit and the second processing unit are
A terminal floor forced reduction device that detects overspeed of the car in the end region of the hoistway and stops the car in an emergency, and/or detects overspeed of the car with the car door open and stops the car in an emergency. It can be provided in the door open running protection device to stop.

The lifting device can be a passenger conveyor.

Conventionally, the calculation time of the first measured quantity x1 is the transmission time t1 of the first measured quantity x1 or the periodic calculation time just before that, and the calculation time of the second measured quantity x2 is the reception of the first measured quantity x1. The time t2b or the periodical calculation time just before that was used. In the present invention, the calculation time of the first measured quantity x1 is the output time t1 of the first synchronization signal or the periodic calculation time just before that, and the calculation time of the second measured quantity x2 is the input time of the first synchronization signal. t2 or the periodical calculation time just before that. Therefore, in the present invention, the difference between the calculation times of the first measured quantity x1 and the second measured quantity x2 can be shortened compared to the conventional case. This is because the input/output time can be shortened more than the transmission/reception time by applying serial communication to the transmission/reception of the first measurement quantity x1 and applying digital input/output to the input/output of the first synchronization signal.

Since the difference between the calculation times of the first measured quantity x1 and the second measured quantity x2 can be shortened, the allowable error va of the double calculated first velocity v1 and second velocity v2 can also be reduced. can increase

FIG. 1 is a block diagram showing the essential configuration of an elevator. FIG. 2 is a sequence diagram according to the first embodiment of the present invention, in which the first processing unit outputs the first synchronization signal and the second processing unit performs speed comparison. FIG. 3 is a sequence diagram according to the first embodiment of the present invention, in which the second processing unit outputs the second synchronization signal and the first processing unit performs speed comparison. FIG. 4 is a sequence diagram according to the second embodiment of the present invention, in which the first processing unit outputs the first synchronization signal and the second processing unit performs speed comparison. FIG. 5 is a sequence diagram according to the second embodiment of the present invention, in which the second processing unit outputs the second synchronization signal and the first processing unit performs speed comparison.

A lifting device according to an embodiment of the present invention will be described with reference to the drawings. As the lifting device, the elevator 10 is taken as an example in this embodiment, but the lifting device may be a passenger conveyor such as an escalator or a moving walkway. Further, the driving device 20 is exemplified as a predetermined part for measuring the moving speed, and the rotation of the driving device 20 is output as a pulse signal by the monitoring encoder 30 to measure the speed. 20, and speed can be measured by methods other than encoders and pulse signals.

FIG. 1 is a block diagram showing the essential configuration of an elevator 10 of the present invention. As shown in the figure, an elevator 10 has a car 11 suspended from one end of a main rope 12 and a counterweight 13 suspended from the other end of the main rope 12 . The main rope 12 is hung on a sheave provided coaxially with a driving device 20 composed of a motor, a brake, and the like, and the driving device 20 rotates forward and backward to move the car 11 up and down within the shaft.

A monitoring encoder 30 is attached to the driving device 20 and outputs a pulse signal according to the rotation of the driving device 20 . In FIG. 1, the monitoring encoder 30 is arranged in the driving device 20 as a predetermined portion capable of measuring the moving speed. It can also be placed on a rotating part such as a wheel (tension pulley) (neither shown). As shown in FIG. 1, the pulse signal output from the monitoring encoder 30 is input to the control device 40 described below.

The control device 40 includes an operation control section 41 , a safety circuit 42 and a processing section 50 . The operation control unit 41 controls the driving device 20 and the like. The safety circuit 42 is controlled by the operation control unit 41 and the processing unit 50, and performs switching to enable or cut off power supply to the power supply path to the brake and to the motor.

The processing section 50 has a first processing section 51 and a second processing section 54 . Each of the first processing unit 51 and the second processing unit 54 is composed of a microcontroller (MCU) including a CPU, ROM, RAM and the like.

The first processing unit 51 and the second processing unit 54 each receive a pulse signal output from the monitoring encoder 30, calculate the speed of the elevator 10 (car 11) from the pulse signal, and use the calculated speed as a predetermined reference. If it is excessive relative to the speed, it is determined as overspeed. When it is determined that the vehicle is overspeeding, an abnormal signal is output to the operation control unit 41 and the safety circuit 42 .

When the abnormality signal is input, the safety circuit 42 stops the driving device 20 in an emergency by cutting off the energization of the brake and the motor. When the abnormality signal is input, the operation control unit 41 causes the elevator 10 to shift to an operation suspension state, and notifies the management room of the elevator 10 or the remote management office of the abnormality.

As described above, even if one of the first processing unit 51 and the second processing unit 54 malfunctions, the emergency stop by judging the overspeed is ensured by the other. Reliability is improved by duplication.

In addition, the processing unit 50 detects an overspeed of the car 11 in the end region of the hoistway, and detects an overspeed of the car 11 to make an emergency stop of the car 11, and an overspeed control of the car 11 when the car door is open. can be placed in a safety device (not shown), such as a door open protection device (UCMP) that detects this and brings the car 11 to an emergency stop.

Consider determining by the second processing unit 54 if there are any indications that the first processing unit 51 is malfunctioning. It is also considered that the first processing unit 51 determines whether there is a sign that the second processing unit 54 is malfunctioning.

Whether or not there is an indication of malfunction is determined by whether or not the calculated velocity is normal. Therefore, whether or not the speed calculated by the first processing unit 51 is normal is determined by comparing it with the speed calculated by the second processing unit 54 . Also, it is determined whether or not the speed calculated by the second processing unit 54 is normal by comparing it with the speed calculated by the first processing unit 51 .

The first processing section 51 and the second processing section 54 comprise digital input/output circuits 52 and 55 and serial communication circuits 53 and 56, respectively. Then, the first speed v1 calculated by the first processing unit 51 is transmitted to the second processing unit 54, compared with the second speed v2 calculated by the second processing unit 54, and the speed difference is determined by the predetermined allowable error va If it exceeds , it is determined that the speed is abnormal, and an abnormal signal is output to the operation control unit 41 and the safety circuit 42 . Further, the second speed v2 calculated by the second processing unit 54 is transmitted to the first processing unit 51, and compared with the first speed v1 calculated by the first processing unit 51, the speed difference is determined by the predetermined allowable error va If it exceeds , it is determined that the speed is abnormal, and an abnormal signal is output to the operation control unit 41 and the safety circuit 42 .

In this way, both the first processing unit 51 and the second processing unit 54 do not determine that there is an abnormality in the speed, so that the operating state of the elevator is maintained (there is no emergency stop or suspension of operation). . It should be noted that it is desirable to perform the speed abnormality determination even when the car 11 is not running.

The details of the process of comparing speeds as described above will be described separately for a first embodiment and a second embodiment.

<1. First Embodiment>
<1.1 Sequence in FIG. 2>
A more detailed flow of the above control will be described with reference to the sequence diagram 2. FIG. First, as shown in the sequence diagram 2, the first processing unit 51 immediately outputs the first synchronization signal through the digital input/output circuit 52 after calculating the first speed v1 from the pulse signal of the monitoring encoder 30 at the first time t1. digital output (first time t1: step S11).

Simultaneously with the output of the first synchronization signal, the first processing section 51 transmits the first speed v1 to the second processing section 54 via the serial communication circuit 53 by serial communication.

The first synchronization signal is input to the second processing section 54 via the digital input/output circuit 55 . The second processing unit 54 immediately calculates the second velocity v2 from the pulse signal of the monitoring encoder 30 when the first synchronization signal is input (step S21: the input time is the second time t2). The second processing unit 54 stores the second velocity v2 calculated at the second time t2 as second comparison target data.

The second processing unit 54 then receives the first speed v1 from the first processing unit 51 via the serial communication circuit 56 . When the second processing unit 54 receives the first velocity v1 (the reception time is time t2b), the second processing unit 54 reads out the second comparison target data stored in step S21, and calculates the first error | v1-v2| (| . Then, the second processing unit 54 determines that the first error |v2-v1| is normal if the first error |v2-v1| On the other hand, if the allowable error va is exceeded, the second processing unit 54 determines that there is an abnormality, and outputs an abnormality signal to the operation control unit 41 and the safety circuit 42 .

Using these sequences as a unit sequence, they are repeatedly executed while shifting the time.

<1.2 Sequence of FIG. 3>
2, the first processing unit 51 receives the second speed v2 calculated by the second processing unit 54, and the first speed v1 calculated by the first processing unit 51 and A comparison sequence (FIG. 3) is performed. In this process, as shown in FIG. 3, the second processing unit 54 calculates the second velocity v2 at the third time t3, and immediately digitally outputs the second synchronization signal to the first processing unit 51, The speed v2 is transmitted to the first processing unit 51 by serial communication (step S31). Further, the first processing unit 51 calculates the first speed v1 at the fourth time t4 when the second synchronization signal is digitally input, stores the first speed v1 as first comparison target data (step S41), and serially calculates the second speed v2. When it is received by communication (the time of reception is time t4b), the second velocity v2 is compared with the first data to be compared, the second error with respect to the first data to be compared is obtained (step S42), and the second error is the allowable error va. If it exceeds, it is determined that the speed is abnormal.

Using these sequences as a unit sequence, they are repeatedly executed while shifting the time.

<1.3 Effect of Sequence in FIGS. 2 and 3>
In the sequence of FIG. 2, the second processing unit 54 compares the first velocity v1 with the second velocity v2 at time t2b. The first velocity v1 is calculated at the first time t1. The second velocity v2 is calculated at the second time t2 and stored as the second comparison target data. The calculated time difference between the first velocity v1 and the second time t2 is |t1-t2|. The first time t1 is the time at which the first processing unit 51 calculates the first speed v1 and also the time at which the first synchronization signal is digitally output. The second time t2 is the time when the second processing unit 54 calculates the second velocity v2 and is also the time when the first synchronization signal is digitally input.

Digital I/O can take less than 1 millisecond to input or output a single bit of binary representation.

Before introducing the first synchronization signal as in the sequence of FIG. 2, the second velocity v2 was calculated at time t2b. The calculated time difference between the first velocity v1 and the second velocity v2 was |t1−t2b|. The first time t1 is the time at which the first processing unit 51 calculates the first speed v1, and is also the time at which it is transmitted by serial communication. The time t2b is the time when the second processing unit 54 calculates the second speed v2, and is also the time when the first speed v1 is received through serial communication.

In the case of serial communication, transmission of speed information requires time to output each bit after extracting each bit of the speed information expressed in binary. Receipt of the speed information requires time to combine the input bits into one and reproduce the binary speed value. These combined times can be tens of milliseconds.

|v1 calculation time−v2 calculation time| is |t1−t2b| before the introduction of the first synchronization signal, but is shortened to |t1−t2| after the introduction. As a result, it is possible to reduce the allowable error va to satisfy |v1-v2|≤va. In other words, the speed abnormality can be overlooked by a small amount, so that the speed abnormality determination accuracy can be improved.

This is because the shortening of |v1 calculation time−v2 calculation time| reduces the maximum speed change width vm in the period of “v1 calculation time to v2 calculation time”, and it is possible to reduce the allowable error va that should satisfy vm≦va. Because you can.

For example, the maximum speed change width vm can be estimated as α0×|v1 calculation time−v2 calculation time| even if the elevator continues to run at maximum acceleration α0 during the period of “v1 calculation time to v2 calculation time”.

The effects described above can be similarly applied to the sequence of FIG.

<2. Second Embodiment>
In the first embodiment, the first processing unit 51 calculates and transmits the first velocity v1 at the digital output time of the first synchronization signal in the sequence of FIG. The second processing unit 54 calculates the second velocity v2 at the digital input time of the first synchronization signal and uses it as second comparison target data.

In the second embodiment, as shown in the sequence diagram 4, the first processing unit 51 calculates and stores the first velocity v1 for each first period, and the second processing unit 54 calculates the second velocity v1 for each second period. 2 Velocity v2 is calculated and stored. Then, the first processing unit 51 transmits the read latest first velocity v1 at the digital output time of the first synchronization signal. The second processing unit 54 uses the latest second velocity v2 read at the digital input time of the first synchronization signal as the second comparison target data.

<2.1 Sequence in FIG. 4>
Specifically, as shown in the sequence diagram 4, the first processing unit 51 calculates and stores the first velocity v1 from the pulse signal of the monitoring encoder 30 every first period (P1). At that time, the first velocity v1 calculated and stored last time is overwritten. The second processing unit 54 calculates and stores the second velocity v2 from the pulse signal of the monitoring encoder 30 every second period (P2). At that time, the second velocity v2 calculated and stored last time is overwritten.

At the first time t1, the first processing unit 51 digitally outputs the first synchronization signal through the digital input/output circuit 52, reads out the latest stored first speed v1, and transmits the first speed v1 through serial communication. (step S51). Assume that the time when the read first velocity v1 is calculated is time t1a.

When the first synchronization signal is digitally input (the input time is the second time t2), the second processing unit 54 reads the stored latest second speed v2 and stores it as the second comparison target data ( step S61). Assume that the time when the read second velocity v2 is calculated is time t2a.

Subsequently, the second processing unit 54 receives the first velocity v1 via the serial communication circuit 56 (the reception time is time t2b after "time t2a+second period"). Triggered by the reception of the first speed v1, the second processing unit 54 reads out the second comparison target data stored in step S61 and compares it with the first speed v1 (step S62). If the first error |v1−v2| exceeds a predetermined allowable error va, it is determined that the speed is abnormal, and an abnormal signal is output to the operation control unit 41 and the safety circuit 42 .

Using these sequences as a unit sequence, they are repeatedly executed while shifting the time.

<2.2 Sequence of FIG. 5>
Further, in parallel with the sequence of FIG. 4 described above, as shown in the sequence of FIG. 5, the second processing unit 54 digitally outputs the second synchronization signal, and stores The second velocity v2 is transmitted to the first processing unit 51 by serial communication. After receiving the second velocity v2, the first processing unit 51 compares it with the latest data of the stored first velocity v1 to obtain a second error |v1-v2|. It is determined that the speed is abnormal (step S71, steps S81 to S82 in the sequence diagram 5).

Using these sequences as a unit sequence, they are repeatedly executed while shifting the time.

<2.3 Effect of Sequences in FIGS. 4 and 5>
In the sequence of FIG. 4, the second processing unit 54 compares the first velocity v1 with the second velocity v2 at time t2b. The first velocity v1 is calculated at time t1a. The second velocity v2 is stored as second comparison data after being calculated at time t2a. The calculated time difference between the first velocity v1 and the second time t2 is |t1a−t2a|. This time t1a is just before the first time t1 at which the first processing unit 51 digitally outputs the first synchronization signal. The time t2a is just before the second time t2 when the second processing unit 54 digitally inputs the first synchronization signal.

Digital I/O can take less than 1 millisecond to input or output a single bit of binary representation.

Before introducing the first synchronization signal as in the sequence of FIG. 4, the second velocity v2 was calculated at time t2b. The calculated time difference between the first velocity v1 and the second velocity v2 was |t1a−(t2a+second period)|. This time t1a is just before the first time when the first processing unit 51 transmits the first speed v1 through serial communication. The time (t2a+second period) is just before the time t2b when the second processing unit 54 receives the first speed v1 through serial communication.

In the case of serial communication, transmission of speed information requires time to output each bit after extracting each bit of the speed information expressed in binary. Receipt of the speed information requires time to combine the input bits into one and reproduce the binary speed value. These combined times can be tens of milliseconds.

|v1 calculation time−v2 calculation time| was |t1a−(t2a+second cycle)| before the introduction of the first synchronization signal, but after the introduction, it was shortened to |t1a−t2a|. . As a result, it is possible to reduce the allowable error va to satisfy |v1-v2|≤va. In other words, the speed abnormality can be overlooked by a small amount, so that the speed abnormality determination accuracy can be improved.

This is because the shortening of |v1 calculation time−v2 calculation time| reduces the maximum speed change width vm in the period of “v1 calculation time to v2 calculation time”, and it is possible to reduce the allowable error va that should satisfy vm≦va. Because you can.

For example, the maximum speed change width vm can be estimated as α0×|v1 calculation time−v2 calculation time| even if the elevator continues to run at maximum acceleration α0 during the period of “v1 calculation time to v2 calculation time”.

The effects described above can be similarly applied to the sequence of FIG.

<2.4 Conditions for Effect>
In the sequence of FIG. 4 in the second embodiment, in order to shorten the measurement time difference between the first velocity v1 and the second velocity v2 by introducing the first synchronization signal, it is necessary to satisfy the following equation: is.
t2a ≤ t2 < t2a + second cycle (1)
t2a+n×second period≦t2b<t2a+(n+1)×second period (2)
n is one of natural numbers 1, 2, 3, . Sequence FIG. 4 shows the case of n=1.

When (1) and (2) are established, before the introduction of the first synchronization signal, the second velocity v2 calculated at time "t2a+n×second cycle" and the first velocity v1 calculated at time "t1a" are will be compared. However, by introducing the first synchronization signal, it is possible to compare the second velocity v2 calculated at time "t2a" and the first velocity v1 calculated at time "t1a". It is possible to shorten the measurement time difference of the two velocities v2.

On the other hand, when the second period is long, the following formula holds.
t2a ≤ t2 < t2a + second cycle (3)
t2a ≤ t2b < t2a + second cycle (4)
In this case, the second velocity v2 calculated at time "t2a" and the first velocity v1 calculated at time "t1a" are compared regardless of whether or not the first synchronization signal is introduced. The measurement time difference between the first velocity v1 and the second velocity v2 does not change. Therefore, even if the first synchronization signal is introduced into the embodiment having such a long second period, the measurement time difference between the first velocity v1 and the second velocity v2 cannot be shortened.

Therefore, in the present invention, when the above-described equations (1) and (2) are established and the first synchronization signal is introduced, the time difference between the first velocity v1 and the second velocity v2 is shortened. .

Moreover, even in the pattern shown in the sequence diagram 5, the condition that the following equation holds is required.
t4a ≤ t4 < t4a + first cycle (1')
t4a+n×first cycle≦t4b<t4a+(n+1)×first cycle (2′)

The above description is intended to illustrate the present invention and should not be construed as limiting the technical scope of the claims. Further, the configuration of each part of the present invention is not limited to the above-described embodiment, and of course various modifications are possible within the technical scope described in the claims.

For example, the first processing unit 51 and the second processing unit 54 may receive two systems of pulse signals from the monitoring encoder 30 and calculate the speed. Further, the first processing unit 51 and the second processing unit 54 may receive pulse signals from different encoders attached to the same predetermined portion.

In the first embodiment and the second embodiment, the object is the speed at which the predetermined part moves, but the present invention is established even if the object is the general measurement quantity of the predetermined part. By shortening the difference between the x1 calculation time and the x2 calculation time for x1 and x2 in which the same measurement quantity is calculated twice, the maximum width of change in the measurement quantity in the period between the two times can be shortened. This is because the effect of the present invention can be exhibited by targeting such a measurement quantity as .

In the first and second embodiments, it is described that transmission and reception of the calculated speed are performed by serial communication, but they may be performed by parallel communication instead of serial communication. This is because, at the time of transmission, each bit of the speed value expressed in binary is extracted and then output. Also, when receiving, it is common that each input bit is grouped into one and then reproduced as a speed value expressed in binary. Such a common point indicates that it takes more time than the digital output or digital input of the synchronizing signal, and conversely, it indicates the effect of shortening the time by introducing the synchronizing signal. In addition to serial communication and parallel communication, any communication method having such common points can be adopted.

10 Elevator (lifting device)
20 drive unit 30 monitoring encoder 40 control unit 41 operation control unit 42 safety circuit 50 processing unit 51 first processing unit 52 digital input/output circuit (first processing unit)
53 serial communication circuit (first processing unit)
54 second processing unit 55 digital input/output circuit (second processing unit)
56 serial communication circuit (second processing unit)

Claims (12)

a first processing unit that measures a predetermined portion and calculates a first measurement amount x1;
a second processing unit that measures the predetermined portion and calculates a second measurement amount x2;
A lifting device comprising
The first processing unit outputs a first synchronization signal to the second processing unit at a first time t1, calculates a first measurement quantity x1, and transmits the first measurement quantity x1 to the second processing unit. ,
The second processing unit calculates a second measurement x2 at a second time t2 when the first synchronization signal is input and stores it as second comparison target data, and at a time t2b when the first measurement x1 is received Obtaining a first error, which is an error of the first measured quantity x1 with respect to the second data to be compared, and determining an abnormality when the first error exceeds a preset allowable error va;
lift device. The second processing unit outputs a second synchronization signal to the first processing unit at a third time t3, calculates a second measurement amount x2, and transmits the second measurement amount x2 to the first processing unit. ,
The first processing unit calculates the first measured quantity x1 at a fourth time t4 when the second synchronization signal is input, stores the first measured quantity x1 as first comparison target data, and calculates the first measured quantity x1 at a time t4b when the second measured quantity x2 is received. Obtaining a second error that is an error of the second measured quantity x2 with respect to the first data to be compared, and determining an abnormality when the second error exceeds the allowable error va;
The lifting device according to claim 1. a first processing unit that measures a predetermined portion every first cycle to calculate and store a first measurement quantity x1;
a second processing unit that measures the predetermined portion every second cycle to calculate and store a second measurement quantity x2;
A lifting device comprising
The first processing unit outputs a first synchronization signal to the second processing unit at a first time t1, reads the latest first measurement quantity x1, and transmits the first measurement quantity x1 to the second processing unit. death,
The second processing unit reads the latest second measured quantity x2 at a second time t2 when the first synchronization signal is input, stores it as second comparison target data, and receives the first measured quantity x1 at time t2b. A first error that is an error of the first measurement quantity x1 with respect to the second comparison target data is obtained, and if the first error exceeds a preset allowable error va, it is determined to be abnormal.
lift device. The second processing unit outputs a second synchronization signal to the first processing unit at a third time t3, reads the latest second measurement amount x2, and transmits the second measurement amount x2 to the first processing unit. death,
The first processing unit reads the latest first measured quantity x1 at the fourth time t4 when the second synchronization signal is input, stores it as first comparison target data, and receives the second measured quantity x2 at time t4b. A second error that is the error of the second measurement x2 with respect to the first comparison target data is obtained, and if the second error exceeds the allowable error va, it is determined to be abnormal.
The lifting device according to claim 3. After the time t2a at which the second measured quantity x2 read out at the second time t2 is calculated, the second time t2, the time t2a + the second period, and then the time t2b. wherein the second cycle is set;
The lifting device according to claim 3 or 4. After the time t4a at which the first measured quantity x1 read out at the fourth time t4 is calculated, the fourth time t4, the time t4a + the first period, and then the time t4b. wherein the first period is set;
The lifting device according to claim 4. The first processing unit digitally outputs the first synchronization signal and transmits the first measurement quantity x1 by serial communication,
The second processing unit digitally inputs the first synchronization signal and receives the first measurement quantity x1 through serial communication.
The lifting device according to any one of claims 1 to 6. The second processing unit digitally outputs the second synchronization signal and transmits the second measurement quantity x2 by serial communication,
The first processing unit digitally inputs the second synchronization signal and receives the second measurement quantity x2 by serial communication.
The lifting device according to claim 2, claim 4 or claim 6. the lifting device is an elevator,
The lifting device according to any one of claims 1 to 8. As the first measured quantity x1, the speed at which the car moves is measured to calculate the first speed v1, and as the second measured quantity x2, the speed at which the car moves is measured to calculate the second speed v2.
The lifting device according to claim 9. The first processing unit and the second processing unit are
A terminal floor forced reduction device that detects overspeed of the car in the end region of the hoistway and stops the car in an emergency, and/or detects overspeed of the car with the car door open and stops the car in an emergency. Provided in the door open running protection device to stop,
The lifting device according to claim 10. the lifting device is a passenger conveyor,
The lifting device according to any one of claims 1 to 8.

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