JP2023021932A - Image sensing device - Google Patents

Abstract

To provide an image sensing device capable of combining a variety of subpixels.SOLUTION: An image sensing device 100 can include at least one pixel group PXG between a row and a column arranged to intersect each other. The pixel group PXG can include at least one floating diffusion FD1, and n (n is odd number larger than 1) photoelectric conversion elements PD1, PD2, and PD4 commonly connected to the floating diffusion FD 1 to each generate charges for exposure light.SELECTED DRAWING: Figure 2a

Description

TECHNICAL FIELD The present technology relates to an image sensing device, and more particularly, to an image sensing device capable of binning various numbers of sub-pixels.

An image sensing device is a device that converts an optical image into an electrical signal. Recently, with the development of computer and communication industries, the performance has been improved in the fields of smart phones, digital cameras, camcorders, PCS (personal communication system), game machines, surveillance cameras, medical micro cameras, robot industry, infrared sensing devices, etc. The demand for image sensing devices in the world is increasing.

A CMOS (Complementary Metal Oxide Semiconductor) image sensing device can be driven by a simple method, can be integrated into a single chip, so it can be easily miniaturized, and has the advantages of very low power consumption due to high integration. be. In addition, CMOS image sensing devices are widely used these days because manufacturing costs can be reduced by using CMOS process technology.

Due to the increasing demand for smartphones with high-performance cameras, the image sensing device responsible for the smartphone camera function is required to have more rich color expression, focus detection capability during night photography, and noise suppression technology. there is To this end, binning techniques have been proposed in which a greater number of pixels are combined to receive more charge within the same exposure time.

Embodiments of the present invention provide an image sensing device that can combine various numbers of sub-pixels.

An image sensing apparatus according to an embodiment of the present invention may include at least one pixel group connected between cross-arranged rows and columns. A pixel group includes at least one floating diffusion and n (n is an odd number greater than 1) photoelectric conversion elements that are commonly connected to the floating diffusion and each generate an electric charge with respect to exposure light. can contain.

As an exemplary embodiment, an even number of floating diffusions are provided per pixel group, and the even number of floating diffusions are electrically connected.

As an illustrative example, rows are partitioned into at least three sub-rows and columns are partitioned into at least one sub-column. Accordingly, pixel groups are defined by a plurality of sub-pixels each connected to the intersection of sub-rows and sub-columns.

A photoelectric conversion element is formed in each sub-pixel, a floating diffusion is positioned between at least three sub-pixels, and a gate of a transfer transistor is disposed between the floating diffusion adjacent to the photoelectric conversion element.

A pixel signal generating circuit for generating a pixel output signal for at least one pixel group, the pixel output signal being determined based on a sum of charges generated by the photoelectric conversion elements included in the at least one pixel group. be.

An image sensing device according to an embodiment of the present invention includes a substrate including a first surface and a second surface facing each other, and first electrodes formed on the first surface of the substrate and arranged side by side along a column direction. , a first sub-column containing second and third sub-pixels, a second sub-column containing fourth, fifth and sixth sub-pixels arranged side by side along the column direction, and along the column direction an extended pixel group in which third sub-columns including seventh, eighth and ninth sub-pixels arranged side by side are sequentially arranged along a row direction perpendicular to the column direction; a first floating diffusion formed at the contact portions of the fourth and fifth sub-pixels, and a second floating diffusion formed at the contact portions of the second, third, fifth and sixth sub-pixels; A third floating diffusion formed at a contact portion of seventh and eighth sub-pixels symmetrical with respect to the boundary line between the first floating diffusion, the second sub-column and the third sub-column, and a second floating diffusion. A diffusion and a fourth floating diffusion formed at a contact portion of eighth and ninth sub-pixels symmetrical with respect to a boundary line of the second sub-column and the third sub-column may be included. Each of the first to ninth sub-pixels includes a transfer gate configured to surround one of the first to fourth floating diffusions, and a photoelectric conversion element formed on one side of the transfer gate. can be done. Each of the first to fourth floating diffusions is surrounded by three transfer gates.

The transfer gates formed on the first to third subpixels of the first subcolumn may have the same shape as the transfer gates formed on the seventh to ninth subpixels of the third subcolumn. .

Also, the transfer gates formed on the fourth and fifth sub-pixels of the second sub-column are different from the transfer gates formed on the seventh to ninth sub-pixels of the third sub-column. Symmetry can be done about the boundary of the third sub-column.

The first to fourth floating diffusions are electrically connected.

Further including a pixel signal generation circuit integrated outside the extended pixel structure, the pixel signal generation circuit can generate a pixel output signal based on the amount of charge generated in the first to fourth floating diffusions.

An extended color filter disposed on the second side of the substrate and having a size corresponding to the extended pixel structure can be further included.

According to embodiments of the present invention, the area of pixel groups can be adjusted without limiting the number of pixel groups corresponding to one color filter. Furthermore, even if an even number or an odd number of sub-pixels form a group corresponding to one color filter, the light-receiving area can be made uniform in any direction.

In addition, by summing the charges of various numbers of sub-pixels using the binning mode, high signal to noise ratio (SNR) characteristics can be improved, and excellent image quality characteristics can be provided even during night photography.

1 is a block diagram showing an image sensing device according to an embodiment of the present invention; FIG. FIG. 4 is an equivalent circuit diagram showing a pixel group according to one embodiment of the present invention; FIG. 4 is an equivalent circuit diagram showing a pixel group according to one embodiment of the present invention; FIG. 4 is a plan view showing pixel groups according to an embodiment of the present invention; FIG. 4 is a plan view showing pixel groups according to an embodiment of the present invention; Figure 3b is a cross-sectional view showing the first active region along line IIIa-IIIa' of Figure 3a; Figure 3b is a cross-sectional view showing the second active region along line IIIb-IIIb' of Figure 3a; FIG. 3b is a cross-sectional view showing the light-receiving region along the line IIIc-IIIc' of FIG. 3a; FIG. 3b is a cross-sectional view showing the light-receiving region along the line IIId-IIId' of FIG. 3a; 1 is a plan view showing a pixel array according to one embodiment of the present invention; FIG. 6 is a perspective view of an image sensing device having the pixel array of FIG. 5; FIG. 1 is a plan view showing an extended pixel array according to one embodiment of the present invention; FIG. FIG. 8 is a perspective view of an image sensing device having the extended pixel array of FIG. 7; FIG. 4 is a plan view showing an extended pixel group according to another embodiment of the present invention; FIG. 4 is a plan view showing an extended pixel group according to another embodiment of the present invention; 1 is a perspective view of an image sensing device having extended pixel groups and extended color filters according to an embodiment of the present invention; FIG.

The advantages and features of the present invention, as well as the manner in which they are achieved, will become apparent from the detailed description of the embodiments, taken in conjunction with the accompanying drawings. However, the present invention may be embodied in various different forms and should not be construed as limited to the embodiments disclosed below. However, the examples are provided so that the disclosure of the invention will be complete and will allow those of ordinary skill in the art to which the invention pertains to accurately recognize the categories of the invention. The invention is only defined by the categories of claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

FIG. 1 is a block diagram showing an image sensing device according to one embodiment of the present invention.

As shown in FIG. 1, image sensing device 100 may include pixel array 10 and control circuit block 60 .

The pixel array 10 may include multiple row lines, multiple column lines and multiple pixel groups PXG. In one embodiment, a plurality of row lines R1-Rn are arranged in parallel along a first direction D1 of the drawing, and a plurality of column lines C1-Cm extend in a second direction D2 of the drawing. In one embodiment, the first direction D1 and the second direction D2 may be perpendicular to each other. Each pixel group PXG may be located at each intersection of a plurality of row lines R1-Rn and a plurality of column lines C1-Cm. A plurality of pixel groups PXG connected to the same row lines R1-Rn can be exposed simultaneously, and the pixel output signals of the pixel groups PXG connected to the selected column line are applied to the selected column line. can be transmitted to the control circuit block 60 via the

Each pixel group PXG may include at least one photoelectric conversion element (not shown). Pixel group PXG in this embodiment is associated with at least one color filter (not shown). A photoelectric conversion device can convert light transmitted from an external object into an electrical signal. A photoelectric conversion element can receive light transmitted from an object and generate an electric charge corresponding to the amount of received light. A detailed configuration of the pixel group PXG according to various embodiments of the present invention will be described in more detail below.

The control circuit block 60 can include row drivers 20 , column drivers 30 , output circuits 40 and timing controllers 50 .

A row driver 20 can control a plurality of row lines R1-Rn. The row driver 20 can generate various control signals required for row selection to sequentially select a plurality of row lines R1 to Rn.

A column driver 30 can control a plurality of column lines C1-Cm. The column driver 30 can generate various control signals required for column selection. Also, the column driver 30 may include a Correlated Double Sampler (not shown) and an Analog-to-Digital Converter (not shown). A correlated double sampler can detect pixel output signals (or pixel output voltages) of pixel groups connected between a selected row line and a selected column line by correlated double sampling. The analog-to-digital converter can convert the pixel output signals of the selected pixel group PXG into digital signals and transmit them to the output circuit 40 .

The output circuit 40 may include a latch circuit or a buffer circuit, an amplifier circuit, etc. that can temporarily store a digital signal. Also, the output circuit 40 can temporarily store or amplify the digital signal received from the column driver 30 to generate image data.

The timing controller 50 can provide the row driver 20, the column driver 30, and the output circuit 40 with timing control signals for determining their operation timings. The timing controller 50 can receive control instructions provided from the outside and generate timing control signals based on the control instructions.

Control commands are provided from an image processor 70 located outside the image sensing device 100 . The image processor 70 can process the image data transmitted from the output circuit 40 and output it to a display device or store it in a storage device such as a memory.

2a and 2b are equivalent circuit diagrams showing pixel groups according to one embodiment of the present invention.

As shown in FIG. 2a, the pixel group PXG can include a pixel signal generating circuit 110, a light receiving circuit 120 and at least one floating diffusion. For example, one pixel group PXG may include an even number of floating diffusions. In this embodiment, a pixel group PXG including a first floating diffusion FD1 and a second floating diffusion FD2 will be described as an example.

The pixel signal generation circuit 110 can generate the pixel output signal Vout based on the amount of photocharge obtained from the light receiving circuit 120 . As will be described later, the light receiving circuit 120 may be a circuit that generates electric charge according to the light exposure time.

As an exemplary embodiment, pixel signal generation circuit 110 may include at least one pixel transistor. For example, the pixel transistors can include reset transistor RX, dual conversion transistor DCX, drive transistor DX and select transistor SX.

The reset transistor RX, dual conversion transistor DCX, drive transistor DX, and select transistor SX are responsive to row-related signals provided from the row driver 20 (see FIG. 1), such as reset signal RS, dual conversion signal DCS, and select signal SEL. can operate.

A reset transistor RX may be electrically connected between the pixel power terminal V1_T and the dual conversion transistor DCX. The reset transistor RX can reset the first floating diffusion FD1 and the second floating diffusion FD2 according to the reset signal RS. The reset transistor RX receives a reset signal RS as a gate signal and provides a pixel power supply voltage V1 to the first and second floating diffusions FD1 and FD2, thereby operating the first and second floating diffusions FD1 and FD2. can be reset. The pixel power voltage V1 can include the power voltage VDD or the pumping voltage VPP.

A dual conversion transistor DCX may be connected to a second floating diffusion FD2 electrically connected to the first floating diffusion FD1. A dual conversion transistor DCX can be driven according to a dual conversion signal DCS provided from the row driver 20 . For example, the gate of the dual conversion transistor DCX receives the dual conversion signal DSC, the drain is connected to the second floating diffusion FD2, and the source is floating. In some cases, the dual conversion transistor DCX can be omitted.

As another example, as shown in FIG. 2b, a dual conversion transistor DCX may be connected between the first floating diffusion FD1 and the second floating diffusion FD2. The dual conversion transistor DCX shown in FIG. 2b can receive the dual conversion signal DCS as a gate signal. A drain of the dual conversion transistor DCX may be connected to the first floating diffusion FD1, and a source may be connected to the second floating diffusion FD2. When the dual conversion transistor DCX is connected between the first and second floating diffusions FD1 and FD2, the first and second floating diffusions FD1 and FD2 are not directly connected by a conductive line and the dual conversion transistor DCX is driven. can be selectively linked by

The dual conversion transistor DCX is turned on together with the reset transistor RX to discharge residual charges of the first and second floating diffusions FD1 and FD2. In addition, the dual conversion transistor DCX can change the charge amount of the first and second floating diffusions FD1 and FD2 according to the imaging environment (low illumination or high illumination) of the object. Accordingly, the pixel group PXG can be converted to a high conversion gain (HCG) mode or a low conversion gain (LCG) mode depending on the driving of the dual conversion transistor DCX.

The drive transistor DX can be driven based on the charge amount of the first and/or second floating diffusions FD1 and FD2. As an example, the driving transistor DX is driven as a source follower that amplifies the effective voltage according to the amount of charges accumulated in the first and/or second floating diffusions FD1 and FD2 to generate the pixel output signal Vout. can.

The selection transistor SX may be connected between the driving transistor DX and the column line CL. The selection signal SEL is a signal that is sequentially enabled for each column of the pixel array 10 and is input to the gate of the selection transistor SX. When the selection signal SEL is enabled, the selection transistor SX is turned on to transmit the pixel output signal Vout generated by the driving transistor DX to the selected column line CL.

The pixel transistors RX, DCX, DX, and SX forming the pixel signal generation circuit 110 may include, for example, NMOS transistors, and the connection structure of the pixel transistors may vary.

The photodetector circuit 120 can include at least one photodetector that includes a plurality of photoelectric conversion elements that generate charges with exposed light. The light receiving part may be connected to one floating diffusion. In one embodiment, the light receiver can include an odd number of photoelectric conversion elements greater than one.

As an exemplary embodiment, if the pixel group PXG includes first and second floating diffusions FD1, FD2, the light receiving circuit 120 of the pixel group PXG includes a first receiver 120a and a second receiver 120b. be able to.

The first light receiving part 120a is connected to the first floating diffusion FD1 and may include an odd number of photoelectric conversion elements PD1, PD2 and PD4, for example, first, second and fourth photoelectric conversion elements. In addition, the first light receiving unit 120a further includes first, second and fourth transfer transistors TX1, TX2 and TX4 respectively connected to the first, second and fourth photoelectric conversion elements PD1, PD2 and PD4. can contain. Based on the first, second and fourth transfer signals TS1, TS2 and TS4, the first, second and fourth transfer transistors TX1, TX2 and TX4 are switched to the first, second and fourth transfer transistors TX1, TS2 and TS4. Charges generated by the photoelectric conversion elements PD1, PD2, and PD4 can be transferred to the first floating diffusion FD1. Therefore, the drains of the first, second and fourth transfer transistors TX1, TX2 and TX4 correspond to the first floating diffusion FD1, and the sources of the first, second and fourth transfer transistors TX1, TX2 and TX4 correspond to It corresponds to the first, second and fourth photoelectric conversion elements PD1, PD2 and PD4. The first, second and fourth transfer signals TS1, TS2, TS4 are provided by the row driver 20 (see FIG. 1) and can have the same enable timing or different enable timings.

The second receiver 120b may have substantially the same structure as the first light receiver 120a. For example, the second receiver 120b may include third, fifth and sixth photoelectric conversion elements PD3, PD5 and PD6, and third, fifth and sixth transfer transistors TX3, TX5 and TX6. can. Similar to the driving of the first light receiving section 120a, the second receiving section 120b drives the third, fifth and sixth photoelectric conversion signals according to the third, fifth and sixth transfer signals TS3, TS5 and TS6. Charges generated by the conversion elements PD3, PD5, and PD6 can be transferred to the second floating diffusion FD2.

As shown in FIG. 2a, the first and second floating diffusions FD1 and FD2 are electrically connected, and the total amount of charge generated in each of the first and second floating diffusions FD1 and FD2 is the driving transistor. It can be transmitted to the gate of DX. As another example, as shown in FIG. 2b, the charge amounts of the first and second floating diffusions FD1 and FD2 can be selectively summed by driving the dual conversion signal DCS. As another example, by selectively driving the transfer transistors TX1 to TX6, the amount of charge in the first and second floating diffusions FD1 and FD2 can be adjusted. Furthermore, by selectively driving the transfer transistors TX1 to TX3 of the first light receiving section 120a and the transfer transistors TX4 to TX6 of the second light receiving section 120b, a pixel group can be configured with 3×1 sub-pixels. can. In this way, the summed charge amount of the first and second floating diffusions FD1 and FD2 can be converted as the pixel output signal Vout through the pixel signal generation circuit 110. FIG. Also, the pixel output signal Vout can be converted into an image signal by the column driver 30, the output circuit 40 and the image processor 70 shown in FIG.

The driving of the pixel signal generating circuit 110 and the light receiving circuit 120 is described in detail in Korean Patent Application No. 2021-00194335, the contents of which are fully incorporated into the present invention.

In addition, although the pixel signal generation circuit 110 of the present embodiment includes one pixel group PXG, it may be shared by a plurality of pixel groups PXG, and various circuit configurations and arrangements are possible. can have Although the transfer transistors TX1 to TX6 are illustrated as the light receiving circuit 120 in this embodiment, it is clear that the transfer transistors TX1 to TX6 can also be analyzed as pixel transistors.

3a and 3b are plan views showing pixel groups according to one embodiment of the present invention. 4a is a cross-sectional view showing the first active region along line IIIa-IIIa' of FIG. 3a, and FIG. 4b is a cross-sectional view showing the second active region along line IIIb-IIIb' of FIG. 3a. be. 4c is a cross-sectional view showing the light receiving region along the line IIIc-IIIc' of FIG. 3a, and FIG. 4d is a cross-sectional view showing the light receiving region along the line IIId-IIId' of FIG. 3a. For reference, this embodiment will be described by taking a pixel group PXG consisting of 3×2 sub-pixels as an example. The pixel group of FIG. 3a can be a plan view based on the equivalent circuit of FIG. 2a, and the pixel group of FIG. 3b can be a plan view based on FIG. 2b.

As shown in FIGS. 3a and 4a-4d, the pixel group PXG can include a light receiving area SA having a first active area ACT1, a second active area ACT2 and a plurality of sub-pixels sp1-sp6.

A first active area ACT1, a second active area ACT2 and a light receiving area SA may each be formed in the substrate 200. FIG. The first active area ACT1, the second active area ACT2, and the light receiving area SA can be defined by isolation structures ISO formed in the substrate 200, respectively.

The substrate 200 can include a first side 200a and a second side 200b that face each other. For example, on a first side 200a of the substrate 200, eg, the front side of the substrate 200, the transistors comprising the pixel signal generating circuits 110 (see FIG. 2a or 2b) can be arranged.

On the second side 200b of the substrate 200, eg, the rear side of the substrate 200, color filters (not shown) and microlenses (not shown) can be arranged. For example, light transmitted from an external object can be incident through the second surface 200 b of the substrate 200 .

As an illustrative example, the substrate 200 may be a semiconductor substrate including Group 4 materials on the periodic table. Substrate 200 can comprise, for example, a single crystal silicon substrate. The substrate 200 may be a substrate thinned by a thinning process. Substrate 200 may also include a single crystal silicon layer, including an epitaxially grown layer. Also, the substrate 200 may include conductive impurities or conductive wells.

For example, the device isolation structure ISO may contact at least one of the first surface 200a and the second surface 200b of the substrate 200 . The device isolation structure ISO may include a deep trench isolation (DTI) structure including a trench penetrating the substrate 200 and an insulator buried in the trench. The DTI-type device isolation structure ISO can be formed by, for example, BDTI (back deep trench isolation) or FDTI (front deep trench isolation). Also, the device isolation structure ISO may have a structure in which the DTI structure and the junction isolation structure are mixed.

The first active area ACT1 and the light receiving area SA, the second active area ACT2 and the light receiving area SA, and the sub-pixels of the light receiving area SA may be separated by the same type of element isolation structure ISO. can. As another example, between the first active region ACT1 and the light receiving region SA, between the second active region ACT2 and the light receiving region SA, and between the sub-pixels sp1 to sp6 of the light receiving region SA have different element isolation structures. can be electrically isolated by physical ISO.

As an exemplary embodiment, the first active area ACT1 and the second active area ACT2 may extend parallel to each other along the first direction D1, eg, the row direction, with the light receiving area SA interposed therebetween.

As shown in FIGS. 3a and 4a, the first active area ACT1 can be the area in which the dual conversion transistor DCX and the reset transistor RX are formed.

A first conductivity type well 205a, for example a p-well, is formed in the substrate 200 corresponding to the first active area ACT1 so that the dual conversion transistor DCX and the reset transistor RX, which are NMOS transistors, are integrated in the first active area ACT1. can be formed. For reference, the first active area ACT1 is associated with an optical black area (not shown) that defines a color filter (not shown).

The dual conversion gate 220a and the reset gate 220b may be formed in predetermined portions of the first active area ACT1. The dual conversion gate 220a and the reset gate 220b may be spaced apart by a predetermined distance. Between the dual conversion gate 220a and the surface of the first active area ACT1 (ie, the first surface 200a), and between the reset gate 220b and the surface of the first active area ACT1 (ie, the first surface 200a), A gate insulating layer 210 may be interposed between them. Junction regions 240a, 240b, 240c are formed in the first active regions ACT1 of both the dual conversion gate 220a and the reset gate 220b to form the dual conversion transistor DCX and the reset transistor RX. Junction regions 240a, 240b, 240c may include impurities of a second conductivity type (eg, n-type) opposite the first conductivity type. Junction region 240a may be the source of dual conversion transistor DCX, and junction region 240b may be the drain of dual conversion transistor DCX and the source of reset transistor RX. Junction region 240c may be the drain of reset transistor RX. The source 240a of dual conversion transistor DCX can be electrically floating according to FIG. 2a. The gate 220a of the dual conversion transistor DCX (hereinafter referred to as the dual conversion gate) can be configured to have a larger line width than the gate 220b of the reset transistor RX (hereinafter referred to as the reset gate), but is limited to this. not something. An unexplained reference numeral 230 may be a gate sidewall spacer. For example, the first active area ACT1 may be formed in a pattern corresponding to each pixel group PXG, but is not limited thereto.

As shown in FIGS. 3a and 4b, the second active area ACT2 may be the area where the drive transistor DX and the select transistor SX are formed. Since the drive transistor DX and the select transistor SX are also composed of NMOS transistors, as shown in FIG. 2a or 2b, the second active area ACT2 can also include the first conductivity type well 205a. Similar to the first active area ACT1, the second active area ACT2 can also be formed at a position corresponding to the optical black area (not shown).

A gate 220c (hereinafter referred to as a drive gate) of the drive transistor DX and a gate 220d (hereinafter referred to as a select gate) of the select transistor SX can be positioned above the second active region ACT2 with the gate insulating film 210 interposed therebetween. . As described above, the drive transistor DX must be driven as a source follower that amplifies the charges generated by the floating diffusions FD1 and FD2. It is required to have a relatively large driving force. Accordingly, the drive gate 220c is formed to have a line width relatively larger than that of the selection gate 220d, and is formed to have a line width relatively larger than that of the dual conversion gate 220a and the reset gate 220b. .

Junction regions 240d, 240e and 240f are formed in the second active regions ACT2 of both the drive gate 220c and the select gate 220d to form the drive transistor DX and the select transistor SX. Junction regions 240d, 240e, 240f may also include impurities of a second conductivity type (eg, n-type) opposite the first conductivity type. Junction region 240d may be the drain of drive transistor DX, and junction region 240e may be the source of drive transistor DX and the drain of select transistor SX. Junction region 240f may also be the source of the select transistor. In addition, the second active area ACT2 may also have a pattern shape divided according to each pixel group PXG, but is not limited thereto.

As shown in FIGS. 3a, 4c and 4d, the light receiving area SA is the area where the light receiving circuit 120 (see FIG. 2a or 2b) and the first and second floating diffusions FD1 and FD2 are integrated. could be.

As an exemplary embodiment, the light receiving area SA may include first to sixth sub-pixels sp1 to sp6 arranged in a 3×2 matrix.

For example, one row R can include first to third subrows SR1 to SR3. The first sub-pixel sp1 and the fourth sub-pixel sp4 can be arranged side by side in the first sub-row SR1. The second sub-pixel sp3 and the fifth sub-pixel sp5 can be arranged side by side in the second sub-row SR2. The third sub-pixel sp3 and the sixth sub-pixel sp6 can be arranged side by side in the third sub-row SR3.

On the other hand, a column C perpendicular to the row R may include first and second sub-columns SC1 and SC2 arranged adjacently in parallel. The first to third sub-pixels sp1-sp3 can be arranged side by side on the first sub-column SC1. The fourth to sixth sub-pixels sp4-sp6 can be arranged side by side on the second sub-column SC2.

Also, the first to sixth sub-pixels sp1 to sp6 can be completely separated electrically by various types of isolation structures ISO. Photoelectric conversion elements PD1 to PD6 and gates 220-1 to 220-6 of transfer transistors (hereinafter referred to as transfer gates) can be formed in the space defined by the sub-pixels sp1 to sp6. Here, the sub-pixel sp can be understood as a region in which one photoelectric conversion element and one transfer gate are integrated, and FIGS. It can be understood as one transfer transistor TX.

For reference, the first, second and fourth sub-pixels sp1, sp2, sp4 correspond to the first light receiving portion 120a shown in FIG. 2a or FIG. 2b, the third, fifth and sixth sub-pixels sp3, sp5 and sp6 correspond to the second receiver 120b shown in FIG. 2a or 2b.

Each of the photoelectric conversion elements PD1 to PD6 can generate electric charges according to the amount of light incident thereon through the second surface 200b of the substrate 200, as described above. Photodiodes, phototransistors, photogates, pinned photodiodes (PPDs), or combinations thereof are used for the photoelectric conversion elements PD1 to PD6. be.

As an exemplary embodiment, each of the photoelectric conversion elements PD1-PD6 can be formed in the substrate 200 partitioned into sub-pixels sp1-sp6. The photoelectric conversion elements PD1 to PD6 can include, for example, a second conductivity type impurity region n and a first high-concentration conductivity type impurity region p+. For example, the first high concentration conductivity type impurity region p+ is formed on the surface of the second surface 200b of the substrate 200 while being in contact with the second conductivity type impurity region n.

A first floating diffusion FD1 may be formed at contact portions of the first, second, fourth and fifth sub-pixels sp1, sp2, sp4 and sp5. A second floating diffusion FD2 may be formed at the contact portions of the second, third, fifth and sixth sub-pixels sp2, sp3, sp5 and sp6. The first and second floating diffusions FD1 and FD2 can include second conductivity type impurity regions, eg, n-type impurity regions.

Also, the first floating diffusion FD1 is surrounded by first, second and fourth transfer gates 220-1, 220-2, 220-4. For example, the first transfer gate 220-1 and the second transfer gate 220-2 may be folded and symmetrical about the boundary line BR1 between the first sub-row SR1 and the second sub-row SR2. . That is, the second transfer gate 220-2 may have a shape obtained by rotating the first transfer gate 220-1 counterclockwise by 90 degrees. Also, the first transfer gate 220-1 and the fourth transfer gate 220-4 may have fold symmetry about the boundary line BC1 between the first sub-column SC1 and the second sub-column SC2. That is, the fourth transfer gate 220-4 may have a shape obtained by rotating the first transfer gate 220-1 clockwise by 90 degrees.

On the other hand, the second floating diffusion FD2 is surrounded by third, fifth and sixth transfer gates 220-3, 220-5 and 220-6. For example, the third transfer gate 220-3 and the sixth transfer gate 220-6 may have fold symmetry about the boundary line BC1 between the first sub-column SC1 and the second sub-column SC2. That is, the sixth transfer gate 220-6 may have a shape obtained by rotating the third transfer gate 220-3 counterclockwise by 90 degrees. In addition, the fifth transfer gate 220-5 and the sixth transfer gate 220-6 can be folded symmetrical about the boundary line BR2 between the second sub-row SR2 and the third sub-row SR3. That is, the sixth transfer gate 220-6 may have a shape obtained by rotating the fifth transfer gate 220-5 clockwise by 90 degrees.

In the case of the first and third sub-rows SR1 and SR3, the transfer gates 220-1 and 220-4, 220-3 and 220-6 located in the same sub-row are symmetrical about the second direction D2. can be arranged. On the other hand, the second transfer gate 220-2 and the fifth transfer gate 220-5 located in the second sub-row SR2 can be arranged symmetrically with respect to the diagonal direction D3 of the drawing. For example, the second transfer gate 220-2 and the fifth transfer gate 220-5 can be arranged in two-fold symmetry with respect to the first direction D1 and the second direction D2.

Accordingly, the second transfer gate 220-2 and the third transfer gate 220-3 located in the first sub-column SC1 may have the same shape. A fourth transfer gate 220-4 and a fifth transfer gate 220-5 located in the second sub-column SC2 may have the same shape.

Therefore, each of the sub-pixels sp1-sp6 includes transfer gates 220-1-220-6 and photoelectric conversion elements PD1-PD6 acting as sources on one side of the transfer gates 220-1-220-6, Floating diffusion FD1 or floating diffusion FD2 can be the drains of transfer transistors TX1-TX6.

According to the present embodiment, even if an odd number of photoelectric conversion elements PD are connected to the floating diffusion FD1 or the floating diffusion FD2 through the transfer transistors TX, an even number of photoelectric conversion elements PD can be seen from the entire light receiving area SA of the pixel group PXG. Since the floating diffusions FD1 and FD2 are provided, an even number of the photoelectric conversion elements PD1 to PD6 are provided, and the photoelectric conversion elements PD1 to PD6 can be arranged symmetrically in any direction.

As described above, the sub-pixels sp1-sp6 in which the photoelectric conversion elements PD1-PD6 are formed can be electrically isolated by the completely isolated element isolation structure ISO. As shown in FIG. 4C, the element isolation structure ISO in the portion where the first and second floating diffusions FD1 and FD2 are formed is separated from the bottom surfaces of the first and second floating diffusions FD1 and FD2 by a predetermined distance. It extends to the bottom surface 200b of the substrate 200 from the separated portion.

An unexplained drawing symbol DFD is a dummy floating diffusion, and subpixels sp1 are provided outside the first and third subrows SR1 and SR3 in order to uniform the light receiving areas of the respective photoelectric conversion elements PD1 to PD6. , sp3, sp4, sp6, respectively. The dummy floating diffusion DFD is formed in the same manner as the first and second floating diffusions FD1 and FD2, but can be electrically floating.

Also, the first floating diffusion FD1 and the second floating diffusion FD2 can be arranged side by side along the second direction D2. As an example, based on the equivalent circuit shown in FIG. 2a, the first floating diffusion FD1 and the second floating diffusion FD2 can be electrically connected by a first conductive line L1. For example, the first conductive line L1 can be located at the boundary of the second sub-pixel sp2 and the fifth sub-pixel sp5.

Also, the first floating diffusion FD1 and the drain 240b of the dual conversion transistor DCX may be electrically connected by a second conductive line L2. For example, the second conductive line L2 can be located at the boundary of the first sub-pixel sp1 and the fourth sub-pixel sp4.

The second floating diffusion FD2 and the drive gate 220c can be electrically connected by a third conductive line L3. For example, the third conductive line L3 can be located at the boundary of the third sub-pixel sp3 and the sixth sub-pixel sp6.

Even if the first to third conductive lines L1 to L3 are made of an opaque material, they are positioned above the device isolation structure ISO that separates the sub-pixels. Does not affect the fill-factor.

Also, the first to third conductive lines L1 to L3 may be located at the same level. As another example, at least one of the first through third conductive lines L1-L3 may be positioned at a different level from the rest of the conductive lines. In this embodiment, the "levels" of the conductive lines L1, L2, L3 can refer to the distances separated from the first surface 200a of the substrate 200. FIG.

Also, when configuring the pixel group PXG based on the equivalent circuit shown in FIG. 2B, the first floating diffusion FD1 and the second floating diffusion FD2 can be electrically separated as shown in FIG. 3B. In other words, the first conductive line L1 shown in FIG. 3a can be omitted. Alternatively, the pixel group PXG may further include a fourth conductive line L4 electrically connecting the source 240a of the dual conversion transistor DCX and the second floating diffusion FD2. By driving the dual conversion transistor DCX, the first floating diffusion FD1 and the second floating diffusion FD2 can be selectively connected. The fourth conductive line L4 can also be placed on top of the isolation structure ISO or in a portion corresponding to the optical black region (not shown) to reduce the effect of the fill factor of the pixel group PXG.

FIG. 5 is a plan view showing a pixel array according to an embodiment of the present invention, and FIG. 6 is a perspective view showing an image sensing device having the pixel array of FIG.

As shown in FIGS. 5 and 6, the image sensing device 100a may include a pixel array 10a and a color filter layer 300a.

The pixel array 10a may include a plurality of pixel groups PXG1-PXG6 arranged in a matrix between a plurality of rows R1, R2 and a plurality of columns C1, C2, C3. A plurality of pixel groups PXG1-PXG6 can be integrated on the first side 200a of the substrate 200. FIG. Each of the pixel groups PXG1-PXG6 can include sub-pixels sp1-sp6 arranged in a 3×2 matrix format as shown in FIG. 3a or 3b.

As an illustrative example, the first through third pixel groups PXG1-PXG3 are arranged side-by-side along a first row R1 and are provided by row driver 20 (see FIG. 1). can be collectively selected by a signal for selecting . The fourth through sixth pixel groups PXG4 through PXG6 can be arranged side by side along a second row R2 arranged parallel to the first row R1. The fourth to sixth pixel groups PXG4 to PXG6 can be collectively selected by a signal for selecting the second row R2 provided from the row driver 20. FIG.

Meanwhile, the first and fourth pixel groups PXG1 and PXG4 may be arranged side by side in the first column C1. Pixel output signals of the first pixel group PXG1 or the fourth pixel group PXG4 are read out according to the signal for selecting the first column C1 provided by the column driver 30 (see FIG. 1).

The second and fifth pixel groups PXG2, PXG5 can be arranged side by side in a second column C2. Pixel output signals of the second pixel group PXG2 or the fifth pixel group PXG5 are read out according to the signal for selecting the second column C2 provided from the column driver 30 .

The third and sixth pixel groups PXG3, PXG6 can be arranged side by side in a third column C3. Pixel output signals of the third pixel group PXG3 or the sixth pixel group PXG6 are read out according to the signal for selecting the third column C3 provided from the column driver 30 .

The active areas ACT1, ACT2 in which the pixel signal generation circuits 110 (see FIG. 2a or 2b) are formed extend along the first direction D1, for example, around the periphery of the light receiving area SA of the pixel group PXG. For example, the first active area ACT1 in which the reset transistor RX and the dual conversion transistor DCX that control the first to third pixel groups PXG1 to PXG3 are formed is located outside the first row R1 in the first to third pixel groups. It can be arranged to face the pixel groups PXG1 to PXG3. A first active area ACT1, in which a reset transistor RX and a dual conversion transistor DCX for controlling the fourth to sixth pixel groups PXG4 to PXG6 are formed, is formed outside the second row R2 to the fourth to sixth pixel groups. It can be arranged to face PXG4-PXG6.

Meanwhile, the second active area ACT2 in which the driving transistor DX and the selection transistor SX are formed may be arranged to correspond to each pixel group between the first row R1 and the second row R2.

As an exemplary embodiment, the drive transistor DX and select transistor SX integrated in the second active area ACT2 located between the first pixel group PXG1 and the fourth pixel group PXG4 are integrated in the first and fourth pixel groups PXG4. It can be shared as the pixel signal generation circuits 110 (see FIG. 2a or 2b) of the groups PXG1, PXG4. The embodiment of FIG. 5 shows an example in which the pixel groups arranged adjacent to each other in the second direction D2 (e.g., column direction) share the driving transistor DX and the selection transistor SX, but the present invention is not limited to this. , the dual conversion transistor DCX and reset transistor RX can also be shared by adjacent pixel groups by various design modifications. The arrangement of the pixel signal generation circuit 110 can be changed in various forms within a range that does not affect the light receiving area. A pixel output signal for the selected pixel group PXG can be generated.

A color filter layer 300 a may be located on the second surface 200 b of the substrate 200 . The color filter layer 300a may include a plurality of color filters 320 and optical black regions 330a. Each color filter 320 is defined by an optical black area 330a. The plurality of color filters 320 may include primary color filters. The plurality of color filters 320 may include first to third color filters 320a-320c having different colors. For example, the first through third color filters 320a-320c may include green (G), red (R), and blue (B) color filters, respectively. The first to third color filters 320a to 320c may be arranged in a Bayer pattern, but are not limited thereto. Alternatively, the first through third color filters 320a-320c may include cyan, magenta, or yellow color filters.

As an illustrative example, pixel groups PXG1-PXG6 are associated with color filters 320a-320c, respectively. The color filters 320a-320c may have sizes corresponding to the light receiving areas SA of the pixel groups PXG1-PXG6. For example, if the first pixel group PXG1 is arranged corresponding to the first color filter 320a, the pixel output signal Vout of the first pixel group PXG1 is the first color information about the object (not shown). can be output. As a result, a pixel output signal corresponding to one of color filters 320a, 320b, and 320c can be generated based on the charges collected from the six photoelectric conversion elements PD1-PD6. 6, D4 corresponds to the depth direction of the substrate 200. As shown in FIG.

FIG. 7 is a plan view of an extended pixel array according to an embodiment of the present invention, and FIG. 8 is a perspective view of an image sensing device having the extended pixel array of FIG.

As shown in FIGS. 7 and 8, the image sensing device 100b of this embodiment may include a pixel array 10b and a color filter layer 300b.

The pixel array 10b of this embodiment may include a plurality of extended pixel groups EPX1-EPX3 arranged in a matrix. Each of the extended pixel groups EPX1-EPX3 may include sub-pixels sp1-sp12 arranged in a 6×2 matrix, for example, and may all have the same structure. The structure of the extended pixel group will be described below using the first extended pixel group EPX1 as an example.

The first extended pixel group EPX1 of this embodiment may include first and fourth pixel groups PXG1 and PXG4 arranged adjacently in the second direction D2. The configuration of the first pixel group PXG1 is similar to that in FIG. 5, and the configuration of the fourth pixel group PXG4 is also substantially similar to the fourth pixel group PXG4 shown in FIG.

Also, in the pixel signal generation circuit 110 (see FIG. 2A), the first active area ACT1 in which the reset transistor RX and the dual conversion transistor DCX are formed is the upper end of the first pixel group PXG1, as in FIG. placed in the department. A second active area ACT2 in which the driving transistor DX and the selection transistor SX are formed in the pixel signal generation circuit 110 (see FIG. 2a) is arranged between the first pixel group PXG1 and the fourth pixel group PXG4. be.

The first extended pixel group EPX1 may include floating diffusions FD1, FD2 of the first pixel group PXG1 and floating diffusions FD3, FD4 of the fourth pixel group PXG4 electrically coupled. For convenience of explanation, the portions of the first floating diffusion FD1 and the second floating diffusion FD2 of the fourth pixel group PXG4 shown in FIG. are displayed as a floating diffusion FD3 and a fourth floating diffusion FD4.

More specifically, the first pixel group PXG1 belonging to the first extended pixel group EPX1 includes the drain 240b of the dual conversion transistor DCX, the first floating diffusion FD1, and the first A conductive line La may be included to connect the floating diffusion FD1 and the second floating diffusion FD2, and the second floating diffusion FD2 and the drive gate 220c.

On the other hand, the fourth pixel group PXG4 belonging to the first extended pixel group EPX1 electrically connects the drive gate 220c and the third floating diffusion FD3, the third floating diffusion FD3 and the fourth floating diffusion FD4, respectively. A connecting conductive line Lb may be included.

Conductive lines La, Lb allow the charge collected from the 6×2 sub-pixels to be transferred to the drive gate 220c to generate the pixel output signal. At this time, as described above, the charge amount collected in the first to fourth floating diffusions FD1 to FD4 can be adjusted by driving the transfer transistor provided in each sub-pixel.

As another example, an enable signal is applied to the gates 220-1 to 220-3 and 220-7 to 220-9 of the transfer transistors TX1 to TX3 and TX7 to TX9 located in the first sub-column SC1, and the By applying a disable signal to the gates of the transfer transistors TX4 to TX6 and TX10 to TX12 located in SC2, an extended pixel group EPX can be configured with 6×1 sub-pixels.

Also, the color filter layer 300b can be located on the second surface 200b of the substrate 200, similar to FIG. Color filter layer 300b may include a plurality of color filters 325 and optical black regions 330b. Each color filter 325 may include first to third color filters 325a, 325b, 325c arranged in the same manner as in FIG. The first to third color filters 325a, 325b, and 325c of the present embodiment may have sizes corresponding to the extended pixel groups EPX1, EPX2, and EPX3, respectively. This allows the pixel signal output from the charges collected by the 6×1 or 6×2 sub-pixels to represent the information of the corresponding color filter 325 .

FIG. 9 is a plan view showing an extended pixel group according to another embodiment of the present invention, and FIG. 10 is a plan view showing an extended pixel group according to another embodiment of the present invention. FIG. 11 is a perspective view of an image sensing device with extended pixel groups and extended color filters according to an embodiment of the present invention.

As shown in FIGS. 9 and 11, the image sensing device 100c may include a pixel array 10c and a color filter layer 300c.

The pixel array 10c may include a plurality of extended pixel groups TRX1-TPX4 arranged in a matrix.

Extended pixel group TPX in this example can include a greater number of sub-pixels than pixel group PXG in FIG. An extended pixel group TPX may contain, for example, an odd number of sub-pixels.

As an example, the extended pixel group TPX may include three cross-arrayed sub-rows SR1-SR3 and 3×3 sub-pixels sp1-sp9 each connected to the intersections of the three sub-columns SC1-SC3. .

The first, fourth and seventh sub-pixels sp1, sp4, sp7 can form a first sub-row SR1 and the second, fifth and eighth sub-pixels sp2, sp5, sp8 can form a second sub-row SR2. configurable, the third, sixth and ninth sub-pixels sp3, sp6, sp9 may constitute the third sub-row SR3.

The first to third sub-pixels sp1, sp2 and sp3 can form a first sub-column SC1, the fourth to sixth sub-pixels sp4, sp5 and sp6 can form a second sub-column SC2, and the seventh to third sub-pixels sp4, sp5 and sp6 can form a second sub-column SC2. Nine sub-pixels sp7, sp8, sp9 can constitute a third sub-column SC3.

The extended pixel group TPX can include, for example, first to fourth floating diffusions FD1 to FD4. The first floating diffusion FD1 can be formed at the contact portions of at least three adjacent sub-pixels, such as the contact portions of the first, second, fourth and fifth sub-pixels sp1, sp2, sp4, sp5. A second floating diffusion FD2 can also be formed at the contact portions of at least three adjacent sub-pixels, eg the contact portions of the second, third, fifth and sixth sub-pixels sp2, sp3, sp5, sp6. The third floating diffusion FD3 is formed at the contact portions of the seventh and eighth sub-pixels sp7 and sp8 which are symmetrical with respect to the boundary line between the first floating diffusion FD1, the second sub-column SC2 and the third sub-column SC3. can be formed. The fourth floating diffusion FD4 is formed at the contact portions of the eighth and ninth sub-pixels sp8 and sp9 which are symmetrical with respect to the boundary line between the second floating diffusion FD2 and the second sub-column SC2 and third sub-column SC3. can be formed.

The first transfer gate 220-1 and the second transfer gate 220-2 of the first sub-column SC1 can be arranged to surround the first floating diffusion FD1, and the third transfer gate 220-3 can be arranged to surround the second can be arranged so as to surround the floating diffusion FD2. The arrangement of the first to third transfer gates 220-1 to 220-3 is substantially the same as the arrangement of the first to third transfer gates 220-1 to 220-3 shown in FIG.

The fourth transfer gate 220-4 of the second sub-column SC2 can be arranged to surround the first floating diffusion FD1 together with the first and second transfer gates 220-1, 220-2. The fifth and sixth transfer gates 220-5, 220-6 can be arranged to surround the second floating diffusion FD2 together with the third transfer gate 220-3. The arrangement of the fourth to sixth transfer gates 220-4 to 220-6 is substantially the same as the arrangement of the fourth to sixth transfer gates 220-4 to 220-6 shown in FIG.

On the other hand, the seventh to ninth photoelectric conversion elements PD7 to PD9 and the seventh to ninth transfer gates 220-7 to 220-9, which correspond to the third sub-column SC3, correspond to the first to the first photoelectric conversion elements PD7 to PD9 of the first sub-column SC1. The arrangement is substantially the same as that of the three photoelectric conversion elements PD1 to PD3 and the first to third transfer gates 220-1 to 220-3. For example, a seventh transfer gate 220-7 and an eighth transfer gate 220-8 can be arranged to surround the third floating diffusion FD3, and a ninth transfer gate 220-9 can surround the fourth floating diffusion FD4. can be arranged to enclose the Such an extended pixel group TPX may further include at least one sub-column SC than the pixel group PXG of FIG.

On the other hand, the tenth to twelfth sub-pixels sp10, sp11, and sp12 corresponding to the fourth sub-column SC4 belong to the second pixel group PXG2 together with the sub-pixels of the third sub-column SC3 in FIG. The extended pixel group TPX in FIGS. 9 and 10 can belong to another adjacent extended pixel group TPX. Together, the third and fourth floating diffusions FD3, FD4 can be shared by different extended pixel groups TPX.

Here, although the pixel signal generation circuits 110-1 and 110-2 are shown to correspond to pixel groups PXG1 to PXG6 in FIG. operable in conjunction to control one extended pixel group TPX, or the pixel signal generation circuitry can be reconfigured to correspond to one extended pixel group TPX.

The light-receiving areas of the 3×3 sub-pixels sp1 to sp9 are symmetrical with respect to the first direction D1, the second direction D2 and the diagonal direction D3. Uniform light reception becomes possible.

As another example, as shown in FIG. 10, the photoelectric conversion elements PD7 to PD9 and the transfer gates 220-7 to 220-9 of the seventh to ninth sub-pixels sp7 to sp9 corresponding to the third sub-column SC3 are Boundary lines between the second and third sub-columns SC2 and SC3 with respect to the photoelectric conversion elements PD4-PD6 and the transfer gates 220-4-220-6 of the fourth through sixth sub-pixels sp4-sp6 of the second sub-column SC2 can be folded symmetrically about . That is, the photoelectric conversion elements PD7 to PD9 of the seventh to ninth sub-pixels sp7 to sp9 and the transfer gates 220-7 to 220-9 correspond to the photoelectric conversion elements PD4 to PD6 of the fourth to sixth sub-pixels sp4 to sp6. and 180° symmetrical with the transfer gates 220-4 to 220-6. This allows the seventh transfer gate 220-7 to surround the third floating diffusion FD3, and the eighth and ninth transfer gates 220-8, 220-9 to surround the fourth floating diffusion FD4. be able to.

In this way, even if the arrangement of the transfer gates 220-7 to 220-9 of the third sub-column SC3 is changed, light is received uniformly in the first direction D1, the second direction D2 and all the diagonal directions D3. A region is provided.

Also, in the previous embodiment, the charges generated in the first and second sub-columns SC1, SC2 are converted as pixel output signals through the pixel signal generation circuit 110-1 of the first pixel group PXG1, The charges generated in sub-column SC3 of 3 were converted as pixel output signals via pixel signal generation circuit 110-2 of the second pixel group PXG2.

However, in the extended pixel group TPX of this embodiment, the charges generated in the first and second sub-columns SC1 and SC2 are transferred to the output node of the first pixel signal generating circuit 110-1 by a known binning technique. It can be shifted to a register (not shown) without intermediate reading. The charges temporarily stored in the register are summed with the charges generated in the third sub-column SC3 and converted as an output signal of the extended pixel group TPX through the pixel signal generation circuit 110-2 of the second pixel group PXG2. can. The first to fourth floating diffusions may be electrically connected directly or indirectly so that the charges of the photoelectric conversion elements PD1 to PD9 forming the extended pixel group TPX are summed. Here, the direct method can be a method of connecting by a conductive line, and the indirect method can be a method in which charges are shifted by serial or parallel registers. At this time, the tenth to twelfth transfer gates 220-10 are arranged so that charges generated in the corresponding fourth sub-column SC4 are not mixed with filters of other colors when pixel output signals of the extended pixel group TPX are generated. . . . 220-12 are all disabled. The method of operation described above only describes one example of a binning technique, and it is clear that a wide variety of known binning techniques are included here.

A color filter layer 300 c may be located on the bottom surface 200 b of the substrate 200 . The color filter layer 300c may include extended first to third color filters 327a, 327b, 327c and an optical black region 330c. The extended first to third color filters 327a, 327b, and 327c may have sizes corresponding to the extended pixel groups TPX.

That is, each of the extended first to third color filters 327a, 327b, and 327c can correspond to 3×3 sub-pixels. Accordingly, a pixel output signal generated in one extended pixel group TPX may be a value obtained by converting photoelectric charges transferred from a total of nine photoelectric conversion elements. According to this embodiment of the present invention, the area of pixel groups can be adjusted without limiting the number of pixel groups corresponding to one color filter. Furthermore, even if an even number or an odd number of sub-pixels form a group corresponding to one color filter, the light-receiving area can be made uniform in any direction.

In addition, by summing the charges of various numbers of sub-pixels using the binning mode, high signal to noise ratio (SNR) characteristics can be improved, and excellent image quality characteristics can be provided even during night photography.

Although preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and within the scope of the technical idea of the present invention, those skilled in the art can Various modifications are possible.

Claims (20)

at least one pixel group connected between cross-arrayed rows and columns;
The pixel group is
at least one floating diffusion;
and n photoelectric conversion elements (where n is an odd number greater than 1) that are commonly connected to the floating diffusion and each generate an electric charge with respect to exposure light. The image sensing device of claim 1, wherein an even number of floating diffusions are provided per pixel group, and the even number of floating diffusions are electrically connected. the rows are partitioned into at least three adjacent and parallel sub-rows;
the column is partitioned into at least one sub-column;
2. The image sensing device of claim 1, wherein the pixel groups are defined by a plurality of sub-pixels each connected to intersections of the sub-rows and the sub-columns. 4. The image sensing device of claim 3, wherein each of said photoelectric conversion elements is integrated in each of said sub-pixels. 4. The image sensing device of claim 3, wherein the floating diffusion is located at a contact portion of at least three adjacent sub-pixels. a gate of a transfer transistor is provided in the sub-pixel between the photoelectric conversion element and the floating diffusion;
4. The image sensing device according to claim 3, wherein said charges generated in said photoelectric conversion element according to said gate signal are transferred to said floating diffusion. 2. The image sensing device of claim 1, further comprising color filters having sizes corresponding to the pixel groups. further comprising pixel signal generation circuitry for generating pixel output signals for the at least one pixel group;
2. The image sensing device of claim 1, wherein the pixel output signal is determined based on the sum of the charge amounts generated by the photoelectric conversion elements included in the at least one pixel group. a substrate including opposing first and second surfaces;
a first sub-column formed on the first surface of the substrate and including first, second and third sub-pixels arranged side by side along the column direction; , a second sub-column containing fifth and sixth sub-pixels, and a third sub-column containing seventh, eighth and ninth sub-pixels arranged side by side along the column direction. extended pixel groups sequentially arranged along the row direction perpendicular to
a first floating diffusion formed at contact portions of the first, second, fourth and fifth sub-pixels;
a second floating diffusion formed at contact portions of the second, third, fifth and sixth sub-pixels;
a third floating diffusion formed at a contact portion of the seventh and eighth sub-pixels symmetrical with respect to a boundary line between the first floating diffusion and the second sub-column and the third sub-column;
the second floating diffusion and a fourth floating diffusion formed at the contact portion of the eighth and ninth sub-pixels symmetrical with respect to the boundary line between the second sub-column and the third sub-column including
each of the first to ninth sub-pixels is configured to surround one of the first to fourth floating diffusions; and
a photoelectric conversion element formed on one side of the transfer gate;
The image sensing device, wherein each of the first to fourth floating diffusions is surrounded by the three transfer gates. a first transfer gate formed in the first sub-pixel, a second transfer gate formed in the second sub-pixel, and a fourth transfer gate formed in the fourth sub-pixel; is formed to surround the first floating diffusion. a third transfer gate formed in the third sub-pixel, a fifth transfer gate formed in the fifth sub-pixel, and a sixth transfer gate formed in the sixth sub-pixel; is formed to surround the second floating diffusion. A seventh transfer gate formed in the seventh sub-pixel and an eighth transfer gate formed in the eighth sub-pixel are formed to surround the third floating diffusion,
10. The image sensing device of claim 9, wherein a ninth transfer gate formed in the ninth sub-pixel is formed to surround the fourth floating diffusion. a seventh transfer gate formed in the seventh sub-pixel is formed to surround the third floating diffusion;
An eighth transfer gate formed in the eighth sub-pixel and a ninth transfer gate formed in the ninth sub-pixel are formed to surround the fourth floating diffusion. Item 10. The image sensing device according to item 9. The transfer gates formed on the first to third sub-pixels of the first sub-column are the same as the transfer gates formed on the seventh to ninth sub-pixels of the third sub-column. 10. The image sensing device of claim 9, having a shape. The transfer gates formed on the fourth and fifth sub-pixels of the second sub-column are opposed to the transfer gates formed on the seventh to ninth sub-pixels of the third sub-column. 10. The image sensing device of claim 9, wherein the second and third sub-columns have a symmetrical shape about a boundary between the second and third sub-columns. 10. The image sensing device of claim 9, wherein the first to fourth floating diffusions are electrically connected. further comprising a pixel signal generation circuit integrated outside the extended pixel structure;
10. The image sensing device according to claim 9, wherein said pixel signal generation circuit generates pixel output signals based on the amount of charge generated by said first to fourth floating diffusions. The pixel signal generation circuit is
a selected one of outside a first sub-row including the first, fourth and seventh sub-pixels and outside a third sub-row including the third, sixth and ninth sub-pixels; a first active region located at one
a second active region located in the remaining one of the outer sides of the first sub-row and the third sub-row;
a reset transistor and a dual conversion transistor formed in the first active region and configured to share a junction region;
a drive transistor and a select transistor formed in the second active region and configured to share a junction region;
18. The image sensing device of claim 17, wherein the driving transistor is turned on based on the amount of charge. The first active area, the first to ninth sub-pixels of the extended pixel structure and the second active area are electrically separated by at least one isolation structure formed in the substrate. ,
19. The image sensing device of claim 18, wherein at least one of the device isolation structures extends to the second surface of the substrate. 10. The image sensing device of claim 9, further comprising an extended color filter disposed on the second surface of the substrate and having a size corresponding to the extended pixel structure.

Images