JP2023010371A - Frequency multiplier and output power detection method - Google Patents

Abstract

To provide a frequency multiplier capable of detecting output power while suppressing attenuation of a high frequency signal.SOLUTION: A frequency multiplier 1 includes an input unit 10 that generates a drive signal Sb in which a bias voltage is superimposed on a fundamental wave signal, a nonlinear circuit unit 40 that generates a distortion signal Sd from the drive signal Sb by a nonlinear element 41, an output unit 50 that outputs a desired harmonic with remaining harmonics attenuated, a detection unit 20 that detects the magnitude of a power supply current Idd flowing from a power supply to the nonlinear circuit unit 40, and generates and outputs an electrical detection value Sdet corresponding to the magnitude of the power supply current Idd, and a blocking unit 30 provided between the detection unit 20 and the nonlinear circuit unit 40 and having a filter 31 including the frequencies of the fundamental wave and the desired harmonic in a blocking band.SELECTED DRAWING: Figure 2

Description

The present invention relates to a frequency multiplier and an output power detection method used in millimeter wave and terahertz band communications.

Communication technologies using millimeter wave bands and terahertz bands (for example, frequency bands from 30 GHz to 10 THz) are being studied as next-generation technologies. A local oscillator (hereinafter abbreviated as LO) signal for millimeter wave and terahertz band communication has a high frequency, so it is difficult to directly generate it with a PLL, and it is also difficult to obtain sufficient phase noise characteristics. Therefore, the LO signal is generated by multiplying the PLL signal whose frequency is set low with a frequency multiplier.
On the other hand, control of the LO output power is extremely important, for example, in controlling the output power of a transmitter and improving the conversion gain and noise characteristics of a mixer-first receiver (see Patent Document 1, for example). In order to control the output power, it is necessary to sense the output power.
When measuring the power of a high-frequency signal, there is a method of branching a part of the high-frequency signal and detecting it with a power detection circuit. For example, Non-Patent Document 1 describes a technique in which a coupler is inserted in the rear stage of a power amplifier to split and extract a part of a signal and input it to a power detection circuit.

U.S. Patent Application Publication No. 2008/0280579

J. Pang et al., "A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance," in IEEE Journal of Solid-State Circuits, vol.54, no. 5, pp.1375-1390, May 2019, doi: 10.1109/JSSC.2018.2886338

However, branching the signal attenuates the power in the signal path, and inserting the coupler causes insertion loss. It is difficult to generate and amplify millimeter-wave and terahertz-band signals, and suppression of attenuation is important.
SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and provides a frequency multiplier and an output power detection method capable of detecting output power while suppressing attenuation of high-frequency signals in millimeter wave and terahertz band communications. The task is to

In order to solve such a problem, a frequency multiplier according to the present invention includes an input unit that generates a drive signal in which a bias voltage is superimposed on a fundamental wave signal, and a nonlinear element that converts the drive signal into a higher harmonic of the fundamental wave. an output unit for outputting a desired harmonic from the harmonics of the distortion signal after attenuating the remaining harmonics; and wiring from a power supply to the nonlinear circuit. a detection unit provided for detecting the magnitude of a power supply current flowing from the power supply to the nonlinear circuit unit and generating and outputting an electrical detection value corresponding to the magnitude of the power supply current; a blocking section provided between the detecting section and the nonlinear circuit section in the wiring to the section, and having a filter containing the frequencies of the fundamental wave and the desired harmonic wave in a blocking band.

Further, an output power detection method according to the present invention is a method for detecting output power in a frequency multiplier according to an embodiment, wherein data of the output power value of the desired harmonic and the value of the power supply current are stored in advance. and calculating the output power based on the electrical detection value and the data output from the detection unit.

According to the present invention, it is possible to provide a frequency multiplier and an output current detection method capable of detecting output power while suppressing attenuation of a high frequency signal.

1 is a block diagram illustrating part of a communication device in which a frequency multiplier according to an embodiment is used; FIG. It is a block diagram showing an example of a configuration of a frequency multiplier according to the embodiment. It is a circuit diagram showing an example of a doubler according to the embodiment. It is a circuit diagram showing an example of a triple multiplier according to the embodiment. 4 is a graph showing an example of correlation between output power and differential current of a doubler according to the embodiment; 5 is a graph showing an example of correlation between output power and differential current of a tripler according to the embodiment; It is a block diagram which shows an example of a structure of the detection value process part which concerns on embodiment. 4 is a table showing an example of data including output power and power supply current; 4 is a table showing an example of data including output power and power supply current; It is a circuit example of a detection unit using a transistor. It is a circuit example of a detection unit that outputs a current as an electrical detection value. 4 is a flow chart showing an example of a method for detecting output power according to the embodiment;

An embodiment of the present invention will be described with reference to the drawings. A frequency multiplier 1 according to the present invention is used, for example, as LO (Local Oscillator) on the receiving side and the transmitting side in a communication apparatus. FIG. 1 is an example used for the LO on the receiving side, and the frequency multiplier 1 receives a signal from the PLL and multiplies the frequency by n times (integer multiples such as double and triple). .

[Frequency multiplier]
As shown in FIG. 2, the frequency multiplier 1 includes an input section 10, a detection section 20, a blocking section 30, a nonlinear circuit section 40, and an output section 50. FIG. The frequency multiplier 1 may further include a detection value processing section 60 .
The frequency multiplier 1 also has a fundamental wave input terminal 81 , a multiplied wave output terminal 82 , a detection output terminal 83 and a bias input terminal 84 . Frequency multiplier 1 may further comprise a data input terminal 85 .

(input section)
The input unit 10 is a circuit that generates a drive signal Sb in which a bias voltage Vb is superimposed on the fundamental wave signal Sin. The drive signal Sb is input to the nonlinear circuit section 40, which will be described later. The bias voltage Vb is a DC voltage, and the operating point of the nonlinear element 41 of the nonlinear circuit section 40 described later can be set by the bias voltage Vb.
A bias voltage Vb is generated outside the frequency multiplier 1 and input from the bias input terminal 84 . A fundamental wave signal Sin having a frequency f is generated by a signal source G1 external to the frequency multiplier 1 and input from a fundamental wave input terminal 81 .

(Non-linear circuit part)
The nonlinear circuit section 40 is a circuit that generates a distortion signal Sd containing harmonics of the fundamental wave from the driving signal Sb by the nonlinear element 41 . The nonlinear element 41 is, for example, a transistor such as an FET. The distortion signal Sd is input to an output section 50 which will be described later. The distortion signal Sd contains multiple harmonics of the fundamental signal Sin.
The wiring from the power source to the nonlinear circuit section 40 is provided independently of other circuits, and passes through the detection section 20 and the blocking section 30 .

(Detection unit)
The detection unit 20 is provided in wiring from the power supply to the nonlinear circuit unit 40, detects the magnitude of the power supply current Idd flowing from the power supply to the nonlinear circuit unit 40, and detects an electrical detection value Sdet corresponding to the magnitude of the power supply current Idd. is a circuit that generates and outputs
The wiring from the power supply to the nonlinear circuit section 40 passes through the detecting section 20 and does not branch to other circuits between the detecting section 20 and the nonlinear circuit section 40 . Therefore, the detection unit 20 can detect the value of the power supply current Idd flowing from the power supply to the nonlinear circuit unit 40 .
The electrical detection value Sdet is a DC voltage or DC current that changes according to the magnitude of the power supply current Idd flowing through the nonlinear circuit section 40, and the value of the power supply current Idd can be known from the electrical detection value Sdet. The electrical detection value Sdet may be output from the detection output terminal 83 to the outside of the frequency multiplier 1, input to the detection value processing unit 60 described later, and after processing such as calculation, the value of the output power Pout may be output as

As will be described later, the value of the power supply current Idd correlates with the output power of the multiplied wave signal Sout. Therefore, according to the frequency multiplier 1, the output power Pout of the multiplied wave signal Sout can be detected from the electrical detection value Sdet.

(Blocking part)
The blocking section 30 is a circuit that blocks AC signals from being propagated between the detecting section 20 and the nonlinear circuit section 40 . Blocking section 30 is provided between detecting section 20 and nonlinear circuit section 40 in the wiring from the power supply to nonlinear circuit section 40 .
The blocking unit 30 has a filter 31 whose blocking band includes at least the frequency range from the frequency f of the fundamental wave signal Sin to the frequency nf of the multiple wave signal Sout.

(output part)
The output unit 50 is a circuit that outputs a desired harmonic from the harmonics contained in the distortion signal Sd as a multiplied wave signal Sout. Output section 50 attenuates remaining harmonics other than the fundamental and the desired harmonic.
The multiplied wave signal Sout is a signal having a frequency nf obtained by multiplying the frequency f of the fundamental wave by n times (integer multiples such as double and triple). The multiplied wave signal Sout is output from the multiplied wave output terminal 82 to the outside of the frequency multiplier 1 .

(Detected value processing unit)
The detection value processing unit 60 is a circuit that performs processing such as calculation using the electrical detection value Sdet to generate and output the value of the output power Pout of the multiple wave signal Sout.
The value of the output power Pout is output from the detection output terminal 83 to the outside of the frequency multiplier 1 . Values used by the detection value processing unit 60 for processing such as calculation can be input from the data input terminal 85 .

Since the frequency multiplier 1 having the configuration described above can detect the output power of the multiplied wave signal Sout from the electrical detection value Sdet, a coupler and a power detection circuit are provided in the path of the multiplied wave signal Sout. No need. Therefore, the multiplied wave signal Sout is not attenuated in order to detect the output power. In particular, it is difficult to generate and amplify high-frequency signals in the millimeter wave and terahertz bands. According to the frequency multiplier 1, the output power can be detected without attenuating the multiplied wave signal Sout.
The detection unit 20 uses a DC voltage or a DC current as the electrical detection value Sdet corresponding to the power supply current Idd. A detection circuit for the power supply current Idd may have a simple configuration, and layout and wiring avoiding high-frequency signal paths are possible. A direct-current signal is less affected by parasitic capacitance and the like on the layout, and there is no big problem even if the wiring is routed. Therefore, it is possible to improve the area efficiency of the layout and reduce the size of the chip.

Also, for example, when a communication device employs a fused array antenna, it is necessary to monitor the LO output power. In particular, when the scale of the phased array antenna increases, it becomes difficult to provide an output power detection circuit. The frequency multiplier 1 can easily detect the LO output power without providing an output power detection circuit in the LO signal path. Further, high-frequency signals of millimeter waves and terahertz bands are not attenuated. Therefore, it is possible to improve the performance of the fixed array antenna.

[Doubler]
Next, the frequency multiplier 1 will be described with a specific circuit example. FIG. 3 shows a circuit diagram of a doubler 1A as an example of outputting a signal of frequency 2f which is twice the fundamental wave. The fundamental wave signal Sin is a pair of fundamental wave signals Sin1 and Sin2 whose phases are 180 degrees different from each other, is generated by an external signal source G1, and is input to the fundamental wave input terminals 81A and 81B.

The input unit 10A generates a pair of drive signals Sb1 and Sb2 by superimposing a pair of bias voltages Vb1 and Vb2 on the pair of fundamental wave signals Sin1 and Sin2. A pair of drive signals Sb1 and Sb2 are input to the nonlinear circuit section 40A.
The input section 10A has capacitors C1, C2 and inductors L1, L2. Drive signals Sb1 and Sb2 are input to one ends of the capacitors C1 and C2, and bias voltages Vb1 and Vb2 are input to one ends of the inductors L1 and L2. The other ends of the capacitors C1 and C2 are connected to the other ends of the inductors L1 and L2, and input to the transistors T1 and T2 of the nonlinear circuit section 40A in the next stage. Capacitors C1 and C2 block direct current and form an impedance matching circuit together with inductors L1 and L2.

The pair of bias voltages Vb1 and Vb2 set the operating points of the pair of transistors T1 and T2 in the next stage. By adjusting the pair of bias voltages Vb1 and Vb2, the output power of the multiple wave signal Sout can be adjusted. Here, the bias voltages Vb1 and Vb2 are adjusted in advance so that the output power of the multiplied wave signal Sout is maximized, are generated outside the doubler 1A, and are input to the bias input terminals 84A and 84B. . The pair of bias voltages Vb1 and Vb2 may have the same magnitude or may have different magnitudes.

The nonlinear circuit section 40A generates a pair of distortion signals from a pair of drive signals Sb1 and Sb2 by a pair of NMOS transistors T1 and T2. A pair of driving signals Sb1 and Sb2 from the input section 10A are input to gates of a pair of transistors T1 and T2, respectively.
The nonlinear circuit section 40A has inductors L3 and L4 and capacitors C3 and C4. The inductor L3 and capacitor C3, and the inductor L4 and capacitor C4 form impedance matching circuits, respectively.

The source of transistor T1 is grounded and the drain is connected to one end of inductor L3 and capacitor C3. The other end of the inductor L3 is connected to the wiring from the power supply via the blocking section 30A. The other end of the capacitor C3 is one of a pair of output terminals of the nonlinear circuit section 40A and is input to the output section 50A.
Similarly, transistor T2 has its source grounded and its drain connected to one end of inductor L4 and capacitor C4. The other end of the inductor L4 is connected to the wiring from the power supply via the blocking section 30A. The other end of the capacitor C4 is the other of the pair of output terminals of the nonlinear circuit section 40A and is input to the output section 50A.

The detection unit 20A is provided in the wiring between the power supply and the blocking unit 30A, and generates and outputs an electrical detection value Sdet according to the magnitude of the power supply current Idd by the resistance element R1. Here, the electrical detection value Sdet is the voltage value Vdet caused by the voltage drop across the resistance element R1, and is output from the detection output terminal 83 to the outside of the doubler 1A. The value of the power supply current Idd can be obtained from the electrical detection value Vdet by Ohm's law. Considering the influence on other circuits, it is preferable to set the resistance value of the resistive element R1 as small as possible within the range where the required electrical detection value Vdet can be generated.
The wiring from the power source to the nonlinear circuit section 40A does not branch to other circuits between the detection section 20A and the nonlinear circuit section 40A. Therefore, the detection section 20A can detect the value of the power supply current Idd flowing from the power supply to the nonlinear circuit section 40A. The wiring from the resistance element R1 to the detection output terminal 83 is such that, for example, when the electrical detection value Vdet is input to the MOS transistor outside the doubler 1A, the power supply current Idd is large because no direct current flows. does not affect performance. The input current to the element or the like to which the electrical detection value Vdet is input is preferably smaller than, for example, 1/100 of the power supply current Idd.

The blocking section 30A is provided in the wiring between the nonlinear circuit section 40A and the detecting section 20A, and blocks the propagation of AC signals between the detecting section 20A and the nonlinear circuit section 40A. Here, the filters that block AC signals are the transmission lines TL1 and TL2. The blocking section 30A has separate transmission lines TL1 and TL2 for the transistors T1 and T2 of the nonlinear circuit section 40A. That is, the transmission line TL1 is connected to the drain of the transistor T1 via the inductor L3, and the transmission line TL2 is connected to the drain of the transistor T2 via the inductor L4.

The transmission lines TL1 and TL2 are designed so that the characteristic impedance _Z0 is as small as possible. The closer the characteristic impedance _Z0 is to 0Ω, the better, for example, it is preferably smaller than 1Ω. By reducing the characteristic impedance _Z0 , the input impedance of the transmission lines TL1 and TL2 for high frequency signals can be reduced. Therefore, even if the frequency f of the fundamental wave signal Sin is a high-frequency signal such as 100 GHz, the blocking unit 30A can effectively block signals in the frequency range from the fundamental wave signal Sin to the multiplied wave signal Sout. can be done.
For the transmission lines TL1 and TL2, the resistance in series with the transmission lines TL1 and TL2 should be as small as possible and the capacitance between the transmission lines TL1 and TL2 and the ground line should be as large as possible in order to bring the characteristic impedance _Z0 close to 0Ω. laid out. For the layout of the transmission lines TL1 and TL2, for example, a thick wiring layer is secured as a direct current path, and a plurality of types of capacitors formed in a comb shape or between layers are stacked and arranged in parallel. .

The filter 31 whose rejection band includes the frequency range from f to nf of the rejection unit 30 may be a filter by other means such as a microstrip line whose capacitance and inductance are adjusted.

The output section 50A receives a pair of distortion signals output from the pair of drains of the transistors T1 and T2 of the nonlinear circuit section 40A via capacitors C3 and C4, and outputs a signal obtained by doubling the fundamental wave. A multiplied wave signal Sout with a frequency of 2f is output from a multiplied wave output terminal 82 to the outside of the doubler 1A.
The output unit 50A attenuates the remaining harmonics and the fundamental wave contained in the pair of distortion signals, excluding the second harmonic, and outputs the second harmonic as a doubled signal. Since each signal of the fundamental wave and odd-order harmonics has a phase difference of 180 degrees between the drain of the transistor T1 and the drain of the transistor T2, it can be attenuated by connecting the signal lines from the capacitors C3 and C4. can be done. Even-order harmonics of the fourth order and higher are weaker signals than second-order harmonics, and the output unit 50A attenuates the fundamental wave and odd-order harmonics to efficiently extract the second-order harmonics. can be done. Vb1 and Vb2 may be adjusted so that the fourth and higher harmonics are further weakened.

[triple multiplier]
FIG. 4 shows a circuit diagram of a triple multiplier 1B as an example of outputting a signal of frequency 3f which is three times the fundamental wave. The circuit of the tripler 1B differs from that of the doubler 1A in the output section 50B. Since the other circuits are common to the doubler 1A, description thereof is omitted.
The output section 50B receives a pair of distortion signals Sd1 and Sd2 output from the drains of the pair of transistors T1 and T2 of the nonlinear circuit section 40A via capacitors C3 and C4, and outputs a signal obtained by multiplying the fundamental wave by three. . A multiplied wave signal Sout with a frequency of 3f is output from a multiplied wave output terminal 82 to the outside of the triple multiplier 1B.

The output section 50B has capacitors C5 and C6, inductors L5 and L6, and a transformer X1. A signal line from the capacitor C3 is connected to one end of the inductor L5 and one end of the primary side of the transformer X1. A signal line from the capacitor C4 is connected to one end of the inductor L6 and the other end of the primary side of the transformer X1. The other ends of inductors L5 and L6 are grounded through capacitors C5 and C6. The center tap of transformer X1 on the primary side is grounded. One end of the secondary side of the transformer X1 is connected to the multiplied wave output terminal 82, and the other end is grounded.

The output unit 50B attenuates the remaining harmonics and the fundamental wave other than the third harmonic contained in the pair of distortion signals Sd1 and Sd2, and outputs the third harmonic as a triple-multiplied signal.
The inductor L5 and capacitor C5 connected in series have a resonance frequency set to the frequency f of the fundamental wave, and can attenuate the fundamental wave. Similarly, inductor L6 and capacitor C6, and center-tapped grounded transformer X1 can attenuate even harmonics. The fifth and higher odd harmonics are weaker than the third harmonic, and the output unit 50B attenuates the fundamental wave and even harmonics to efficiently extract the third harmonic. can be done. Vb1 and Vb2 may be adjusted so that the fifth and higher harmonics are further weakened.

(Correlation between output power and power supply current)
Here, the correlation between the output power Pout of the multiplied wave signal Sout and the power supply current Idd will be described. The multiplied wave signal Sout is extracted from harmonics contained in the distortion signal Sd generated from the drive signal Sb by the nonlinear element 41 of the nonlinear circuit section 40 . In a circuit that attempts to distort the output of a nonlinear element such as an FET, there is a tendency that the power supply current Idd is large when the distortion is large. When the output distortion is large, the harmonic output power is large.
The distortion of the output of the nonlinear element 41 can be adjusted by the amplitude of the input drive signal Sb and the operating point of the nonlinear element 41 . In the frequency multiplier 1, the amplitude of the drive signal Sb can be adjusted by the amplitude of the fundamental wave signal Sin input from the external signal source G1. The operating point of nonlinear element 41 can be adjusted by bias voltage Vb.
Therefore, when the amplitude of the drive signal Sb and the bias voltage Vb are constant, the output power of the multiplied wave signal Sout correlates with the power supply current Idd flowing through the nonlinear circuit section 40 . This correlation was confirmed by the doubler 1A and the tripler 1B.

5A and 5B show an example of the correlation between the output power of the multiplied wave signal Sout and the differential current Idiff. The difference current Idiff is a current obtained by subtracting the standby current Istb from the power supply current Idd when the fundamental wave signal Sin is input and the multiplied wave signal Sout is output. The standby current Istb is the power supply current when the bias voltage Vb is applied and the fundamental wave signal Sin is not input. The vertical axis of FIGS. 5A and 5B is the differential current Idiff (unit [mA]), and the horizontal axis is the output power Pout (unit [dBm]). It should be noted that the value in units of [dBm] can be converted by the formula 10·log ₁₀ P with respect to the power of P [mW]. For example, 1 mW corresponds to 0 dBm, and 0.1 mW corresponds to -10 dBm.
It can be seen from FIGS. 5A and 5B that there is a correlation that the difference current Idiff increases as the output power Pout increases. That is, the value of the output power Pout can be detected from the value of the differential current Idiff. Depending on the bias voltage Vb, the standby current Istb may become as large as the power supply current Idd when the fundamental wave signal Sin is being input. In such a case, if the difference current Idiff, which is the current obtained by subtracting the standby current Istb from the power supply current Idd, is used, it is possible to increase the variation width of the current with respect to the variation width of the output power Pout, thereby improving the accuracy of the calculation. can.

Since the standby current Istb is a constant value, it can be said that the output power Pout correlates with the power supply current Idd. The electrical detection value Sdet is a value corresponding to the magnitude of the power supply current Idd. Therefore, according to the frequency multiplier 1, the output power Pout can be detected from the electrical detection value Sdet.
In the doubler 1A and tripler 1B, the electrical detection value Sdet is output from the detection output terminal 83 to the outside of the doubler 1A and tripler 1B. In this case, a circuit outside the doubler 1A and the tripler 1B can adjust the amplitude of the fundamental wave signal Sin and the bias voltage Vb using the electrical detection value Sdet. Also, the external circuit can perform processing such as calculating the value of the output power Pout from the electrical detection value Sdet.

(Detected value processing unit)
Processing such as calculating the value of the output power Pout from the electrical detection value Sdet may be performed inside the frequency multiplier 1 . In this case, the frequency multiplier 1 includes a detection value processing section 60, and as shown in FIG. to the outside of the frequency multiplier 1.
FIG. 6 is a block diagram showing an example of the detection value processing section 60. As shown in FIG. The detection value processing section 60 has an input/output section 61 , a storage section 62 and a calculation section 63 . Values used for calculating values such as the output power Pout from the electrical detection value Sdet can be input from the data input terminal 85 .

The input/output unit 61 acquires the electrical detection value Sdet and the value Dprev input from the outside, and outputs the values received from the storage unit 62 and the calculation unit 63 to the outside.
The electrical detection value Sdet is a non-quantified DC voltage or DC current. The input/output unit 61 can quantify the DC voltage or the DC current and send it to the storage unit 62 and the calculation unit 63 . The input/output unit 61 can also send the value Dprev input from the outside to the storage unit 62 and the calculation unit 63 .

The storage unit 62 stores data of a plurality of different values of the output power Pout and the values of the power supply current Idd that are acquired in advance. The storage unit 62 also stores the value of the standby current Istb.
At this time, since different power supply currents Idd correspond to different output powers Pout, the storage unit 62 stores a plurality of pairs of output powers Pout and power supply currents Idd. Preferably, as many pairs as possible are stored. Furthermore, a difference current Idiff obtained by subtracting the standby current Istb from the power supply current Idd may be stored.
7A and 7B show examples of data stored in the storage unit 62. FIG. FIG. 7A shows an example of a doubler 1A, and FIG. 7B shows an example of a tripler 1B, which are simulation values. 7A and 7B are partially shown. The data to be stored may be values actually measured in advance.

The calculation unit 63 converts the electrical detection value Sdet output from the detection unit 20 into the value of the power supply current Idd, and calculates the output power Pout based on the data in the storage unit 62 .
Conversion of the electrical detection value Sdet to the value of the power supply current Idd is performed by a preset conversion formula. The conversion formula differs depending on the circuit and elements of the detection unit 20 . For example, in the case of the detection unit 20A shown in FIGS. 3 and 4, the power supply current Idd is proportional to the electrical detection value Vdet.

The calculation unit 63 calculates the output power Pout as follows, for example, based on the correlation between the power supply current Idd and the output power Pout. The calculation unit 63 searches for data in the storage unit 62 that matches the value of the power supply current Idd. If there is matching data, the corresponding value of the output power Pout is sent to the input/output unit 61 . If there is no matching data, the calculation unit 63 obtains the value of the output power Pout by interpolating from the data, and sends the obtained value of the output power Pout to the input/output unit 61 . Interpolation means, for example, linearly interpolating between adjacent data and substituting the value of the power supply current Idd into the equation of the interpolated straight line.
Calculation of the output power Pout may be similarly performed based on the correlation between the differential current Idiff and the output power Pout.

(Modified example of detector)
The detection unit 20 may be any circuit that outputs a voltage or current corresponding to the power supply current Idd. 8A and 8B are examples of circuits different from the detection section 20A already described.
The detection unit 20B shown in FIG. 8A is a circuit that connects the gate and drain of the transistor T3 and outputs the drain voltage as the electrical detection value Vdet. A detection unit 20C shown in FIG. 8B is a circuit that connects the gates of the transistors T4 and T5 and outputs the drain current of the transistor T5 as an electrical detection value Idet.

[Detection method]
Next, a method for detecting output power according to the present invention will be described.
The method of detecting the output power is the method of detecting the output power in the frequency multiplier 1 already described, and as shown in FIG. including.

(Preparation process)
The preparation step S1 is a step of obtaining in advance data on the value of the output power Pout and the value of the power supply current Idd.
As for the data, a plurality of sets are acquired by making a set of the output power Pout and the power supply current Idd. The data may include the standby current Istb. The data may be acquired by actual measurement, may be acquired by simulation, or may be acquired by combining actual measurement and simulation.

(Recording process)
The recording step S2 is a step of recording the data previously obtained in the preparation step S1 on an external recording medium. The recording medium may be inside or outside the frequency multiplier 1 .
The data to be recorded may include the difference current Idiff obtained by subtracting the standby current Istb from the power supply current Idd.

(Detection process)
The detection step S3 is a step of detecting the power supply current Idd flowing from the power supply to the nonlinear circuit section 40 in the frequency multiplier 1 actually operating.
The detection of the power supply current Idd is performed by providing the detection section 20 in the wiring from the power supply to the nonlinear circuit section 40 . The detection unit 20 generates an electrical detection value Sdet corresponding to the magnitude of the power supply current Idd, and outputs the detection value processing unit 60 or the frequency multiplier 1 to the outside.

(Calculation process)
The calculation step S4 is a step of calculating the output power Pout using the electrical detection value Sdet.
The calculation step S4 converts the electrical detection value Sdet into the value of the power supply current Idd in order to use the data recorded in the recording step S2. Conversion of the detected electrical value Sdet to the value of the power supply current Idd is performed by a previously prepared conversion formula. The conversion formula differs depending on the circuit and elements of the detection unit 20 .
In the frequency multiplier 1, the output power Pout correlates with the power supply current Idd. Therefore, the output power Pout is calculated from the value of the power supply current Idd detected in the detection step S3 based on the set data of the output power Pout and the power supply current Idd obtained in the preparation step S1 and recorded in the recording step S2. can be done.

The output power Pout is calculated by subtracting the standby current Istb recorded in the recording step S2 from the power supply current Idd detected in the detection step S3 to obtain the difference current Idiff, and the difference current Idiff and the output power in the data recorded in the recording step S2. You may perform based on correlation with Pout.

The frequency multiplier according to the present invention has an input section 10 that generates a drive signal Sb in which a bias voltage Vb is superimposed on a fundamental wave signal, and a distortion signal containing harmonics of the fundamental wave from the drive signal Sb by a nonlinear element 41. A nonlinear circuit unit 40 for generating Sd, an output unit 50 for outputting a desired harmonic from the harmonics of the distortion signal Sd after attenuating the remaining harmonics, and a wiring from the power supply to the nonlinear circuit unit 40, A detection unit 20 that detects the magnitude of the power supply current Idd flowing from the power supply to the nonlinear circuit unit 40, generates and outputs an electrical detection value Sdet corresponding to the magnitude of the power supply current Idd, and the power supply to the nonlinear circuit unit 40. and a blocking section 30 provided between the detecting section 20 and the nonlinear circuit section 40 in the wiring of (1) and having a filter 31 including the frequencies of the fundamental wave and desired harmonics in the blocking band.

With such a configuration, in the frequency multiplier, the nonlinear circuit section 40 generates a distortion signal Sd containing harmonics of the fundamental wave from the drive signal Sb generated by the input section 10, and the output section 50 generates a desired harmonic from the distortion signal Sd. It can emit waves. Blocking unit 30 blocks a frequency such as a fundamental wave between detecting unit 20 and nonlinear circuit unit 40, and detecting unit 20 detects an electrical A detected value Sdet can be output. Since the value of the power supply current Idd correlates with the output power of the multiplied wave signal Sout, the frequency multiplier 1 can detect the output power Pout from the electrical detection value Sdet.

In the frequency multiplier according to the present invention, the output section 50 preferably outputs the second harmonic or the third harmonic.
With such a configuration, the frequency multiplier can be a doubler 1A that outputs the second harmonic and a tripler 1B that outputs the third harmonic.

The frequency multiplier according to the present invention includes a storage unit 62 for storing previously acquired data of a desired harmonic output power Pout and a power supply current Idd, and an electrical detection value output from the detection unit 20. It is preferable to further include a calculation unit 63 that converts Sdet into the value of the power supply current Idd and calculates the output power Pout based on the data.
With such a configuration, the frequency multiplier can calculate the output power Pout based on the data obtained in advance and the electrical detection value Sdet.

The data of the storage unit 62 includes the standby current Istb, which is the power supply current when the fundamental wave signal is not input, and the calculation of the output power Pout of the calculation unit 63 is performed by obtaining the standby current Istb from the power supply current Idd in the data. It is preferably based on the correlation between the subtracted current, the differential current Idiff, and the output power Pout.
With this configuration, the frequency multiplier can increase the variation width of the current with respect to the variation width of the output power Pout by subtracting the standby current Istb, and can improve the accuracy of the calculation based on the correlation.

A method for detecting output power according to the present invention is a method for detecting output power in a frequency multiplier according to the present invention, in which data on a value of output power Pout and a value of power supply current Idd of desired harmonics are obtained in advance. Including a preparation step S1, the output power Pout is calculated based on the electrical detection value Sdet output from the detection unit 20 and the data.
With such a configuration, the output power detection method can acquire data in advance in the preparation step S1 and calculate the output power Pout based on the data and the electrical detection value Sdet.

In the output power detection method according to the present invention, the data in the preparation step S1 includes the standby current Istb, which is the power supply current when the fundamental wave signal is not input, and the calculation of the output power Pout is performed by the power supply It is preferably based on the correlation between the differential current Idiff, which is the current Idd minus the standby current Istb, and the output power Pout.
With such a configuration, the method of detecting the output power can increase the variation width of the current with respect to the variation width of the output power Pout by subtracting the standby current Istb, and can improve the accuracy of the calculation based on the correlation.

Although the bias voltage Vb generated externally is input to the frequency multiplier 1 , the bias voltage Vb may be generated inside the frequency multiplier 1 .
Further, when the frequency multiplier 1 includes the detection value processing unit 60, the detection value processing unit 60 calculates and outputs the output power Pout from the electrical detection value Sdet. The detection value processing unit 60 may output the acquired electrical detection value Sdet as it is.
Further, it has been explained that the data stored in the storage unit 62 are values obtained by actual measurement or simulation. At this time, the output power Pout may be a measured or simulated value, and the standby current Istb and power supply current Idd may be values converted from the electrical detection value Sdet obtained by actually operating the frequency multiplier 1 .

Also, when calculating the output power Pout from the correlation between the power supply current Idd or the differential current Idiff and the output power Pout, searching for matching data in the storage unit 62 has been described. Although different from this, a relational expression of correlation may be derived in advance and stored in the storage unit 62, and the output power Pout may be calculated according to the relational expression.
Further, it has been explained that the calculation unit 63 converts the electrical detection value Sdet into the power supply current Idd. Different from this, the electrical detection value Sdet corresponding to the power supply current Idd and the standby current Istb is acquired in advance and stored, and based on the correlation between the electrical detection value Sdet and the output power Pout, the electrical detection value Sdet You may make it calculate the output electric power Pout from.

1 frequency multiplier 1A doubler 1B tripler 10 input unit 10A input unit (doubler, tripler)
20 detector 20A detector (doubler, tripler)
30 Blocking unit 30A Blocking unit (double multiplier, triple multiplier)
31 filter 40 nonlinear circuit section 40A nonlinear circuit section (double multiplier, triple multiplier)
41 non-linear element 50 output section 50A output section (double multiplier)
50B output section (triple multiplier)
60 detection value processing unit 61 input/output unit 62 storage unit 63 calculation unit 81 fundamental wave input terminal 82 multiplied wave output terminal 83 detection output terminal 84 bias input terminal 85 data input terminal

Claims (6)

an input unit that generates a drive signal in which a bias voltage is superimposed on a fundamental wave signal;
a nonlinear circuit section for generating a distortion signal including harmonics of the fundamental wave from the drive signal by a nonlinear element;
an output unit for outputting a desired harmonic from the harmonics of the distorted signal with remaining harmonics attenuated;
provided in a wiring from a power supply to the nonlinear circuit unit, detects the magnitude of a power supply current flowing from the power supply to the nonlinear circuit unit, and generates and outputs an electrical detection value corresponding to the magnitude of the power supply current a detection unit;
a blocking unit provided between the detection unit and the nonlinear circuit unit in the wiring from the power supply to the nonlinear circuit unit, and having a filter including the frequencies of the fundamental wave and the desired harmonic wave in a stopband. frequency multiplier. 2. The frequency multiplier according to claim 1, wherein said output unit outputs a second harmonic or a third harmonic in said harmonic. a storage unit for storing data of the output power value of the desired harmonic and the value of the power supply current obtained in advance;
3. The frequency according to claim 1 or 2, further comprising: a calculation unit that converts the electrical detection value output from the detection unit into a value of the power supply current and calculates the output power based on the data. multiplier. The data in the storage unit includes a standby current that is the power supply current when the fundamental wave signal is not input,
4. The frequency multiplier according to claim 3, wherein the calculation of the output power of said arithmetic unit is based on the correlation between said output power and a differential current, which is a current obtained by subtracting said standby current from said power supply current, in said data. A method for detecting output power in the frequency multiplier according to claim 1,
A preparation step of obtaining in advance data of the output power value of the desired harmonic and the value of the power supply current,
An output power detection method, wherein the output power is calculated based on the electrical detection value and the data output from the detection unit. The data of the preparation step includes a standby current that is the power supply current when the fundamental wave signal is not input,
6. The output power detection method according to claim 5, wherein the calculation of the output power is based on a correlation between the output power and a differential current obtained by subtracting the standby current from the power supply current in the data.

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