JP2023005071A - Image pickup device and imaging apparatus - Google Patents

Abstract

To read a signal out of an embedded photodiode.SOLUTION: An image pickup device comprises: a photoelectric conversion part which converts light to electric charges; an accumulation part which accumulates the electric charges generated by the photoelectric conversion part; a detection part which detects variation in a resistance value in the accumulation part; and a reading part which reads a signal based on the electric charges of the photoelectric conversion part when the detection part detects the variation in the resistance value in the accumulation part.SELECTED DRAWING: Figure 3

Description

The present invention relates to an imaging device and an imaging device.

Conventionally, in an image sensor used in an imaging device (e.g., digital camera) having an imaging function, a technology has been proposed in which a photoelectric conversion film and a readout circuit for reading out the charges generated by the photoelectric conversion film are stacked (e.g., , see Patent Document 1).
However, in the image sensor as described above, when measuring the amount of charge generated by the photodiode by counting the number of times that the charge is accumulated in the photodiode, since the embedded photodiode cannot be used, the Si/insulating film interface There is a problem that the dark current from the is very large.

JP 2019-212991 A

The imaging device of the present invention includes a photoelectric conversion portion that converts light into electric charge, an accumulation portion that accumulates the electric charge generated by the photoelectric conversion portion, a detection portion that detects a change in resistance value in the accumulation portion, and the a reading unit that reads out a signal based on the charge of the photoelectric conversion unit when a change in the resistance value of the storage unit is detected by the detection unit.

It is a figure showing an example of composition of an image sensor concerning a 1st embodiment of the present invention. It is a figure showing an example of functional composition of an image sensor concerning a 1st embodiment of the present invention. 3 is a diagram showing an example of the functional configuration of the pixel-by-pixel circuit according to the first embodiment of the present invention; FIG. It is a pixel sectional view concerning a 1st embodiment of the present invention. 1 is a diagram showing an example of a circuit configuration of a pixel-by-pixel circuit according to the first embodiment of the present invention; FIG. It is a figure which shows an example of the time change of the signal based on the 1st Embodiment of this invention. It is a figure which shows an example of the circuit structure of the circuit for every pixel based on the 2nd Embodiment of this invention. FIG. 10 is a diagram showing an example of time change of a signal according to the second embodiment of the present invention; It is a figure which shows an example of the circuit structure of the circuit for every pixel based on the 3rd Embodiment of this invention. FIG. 10 is a diagram showing an example of time change of a signal according to the third embodiment of the present invention;

[First embodiment]
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of an imaging device 1 according to the first embodiment of the present invention.
The imaging device 1 is provided in an imaging apparatus, captures an image of a subject, and generates pixel data of the captured image.
The imaging device 1 includes a pixel chip 11 and a circuit chip 12 .

The pixel chip 11 has a plurality of pixels 21 . Each pixel 21 provided in the pixel chip 11 generates an electric charge according to the amount of incident light.
The circuit chip 12 includes a readout circuit for each pixel that reads out the amount of charge generated by the pixel 21 .
In this embodiment, the pixel chip 11 and the circuit chip 12 are joined together for each pixel.

FIG. 2 is a diagram showing an example of the functional configuration of the imaging device 1 according to one embodiment of the present invention. An example of the functional configuration of the imaging device 1 will be described with reference to the figure.
The imaging device 1 includes pixels 21, ADC (Analog to Digital Converter) 22, memory 23, data bus 24, peripheral circuit 25, and control circuit 28 as functions thereof.
The pixel 21, the ADC 22, and the memory 23 are the pixel-by-pixel circuit 20 provided for each pixel 21 of the image pickup device 1, and the peripheral circuit 25 and the control circuit 28 are the device-by-device circuit 29 provided for each image pickup device 1. be. A part of the data bus 24 is provided for each pixel 21 and another part is provided for each image sensor 1 .

Pixel 21 includes a photodiode. A photodiode included in the pixel 21 generates an electric charge according to the amount of incident light. The pixel 21 outputs the amount of charge generated by the photodiode to the ADC 22 as a voltage value.

The ADC 22 converts a voltage value (analog value) indicating the amount of charge input from the pixel 21 into a digital value. ADC 22 outputs the converted value to memory 23 . In this embodiment, the ADC 22 is provided for each pixel 21 .

The memory 23 stores a value indicating the amount of charge input from the ADC 22 . In this embodiment, the memory 23 is provided for each pixel 21 .

Data bus 24 obtains a value indicative of the amount of charge stored in memory 23 . The data bus 24 outputs the acquired value to the peripheral circuit 25 .

The peripheral circuit 25 receives the values of the memory 23 provided for each pixel 21 via the data bus 24, and outputs them to the outside of the image sensor through a predetermined interface.

A control circuit 28 controls the pixels 21 , the ADC 22 and the memory 23 . The control circuit 28 controls, for example, the time during which light enters the pixel 21 . Further, the control circuit 28 reads out the charge stored in each pixel 21 by controlling the pixel 21 . Furthermore, the control circuit 28 controls the ADC 22, the memory 23, and the data bus 24 to cause the peripheral circuit 25 to output image data for each frame.

FIG. 3 is a diagram showing an example of the functional configuration of the pixel-by-pixel circuit 20 according to the first embodiment of the present invention. The per-pixel circuit 20 includes a pixel 21 , an ADC 22 and a memory 23 .
The pixel 21 includes a photodiode (photoelectric conversion portion and storage portion) 31 . The photodiode 31 converts incident light into electric charge and accumulates the electric charge. In this example, photodiode 31 is a buried photodiode.

The ADC 22 includes a detection section 32 and a reading section 33 .
The detector 32 includes a JFET (Junction Field Effect Transistor) 321 and a current source 322 . The detector 32 detects a change in the resistance value of the photodiode 31 by including a JFET 321 and a current source 322 . The photodiode 31 changes its resistance value according to the amount of accumulated charge.

A change in the resistance value of the photodiode 31 according to the amount of charge will be described with reference to FIG.
FIG. 4 is a cross-sectional view of a pixel according to the first embodiment of the invention. FIG. 4A is a diagram showing a cross section of the pixel 21 when the photodiode 31 is depleted. FIG. 4B is a diagram showing a cross section of the pixel 21 in a state where charges are accumulated in the photodiode 31. As shown in FIG. The configuration of the photodiode 31 and the JFET 321 and the change in the resistance of the photodiode 31 according to the amount of charge will be described with reference to FIG.

As shown in FIG. 4A, the photodiode 31 has a p-type semiconductor region 311 and an n-type semiconductor region 312 .
A terminal 321S that is the source terminal of the JFET 321 and a terminal 321D that is the drain terminal of the JFET 321 are connected to the p-type semiconductor region 311 . Terminal 321G, which is the gate terminal of JFET 321, is n-type semiconductor region 312. FIG. That is, the detection section 32 is formed using at least part of the semiconductor region forming the photodiode 31 .
A current source 322 is connected to the terminal 321S, and the terminal 321D is grounded. JFET 321 conducts a current between its source and drain according to the amount of charge stored in n-type semiconductor region 312, which is terminal 321G.
In a state (during depletion) in which no charge is accumulated in photodiode 31, the depletion layer formed in p-type semiconductor region 311 is formed in a region indicated by width W1. When depleted, the source-drain current of JFET 321 is small.

A change in the depletion layer when light is incident on the photodiode 31 and charges are accumulated will be described with reference to FIG. 4B. When light enters the n-type semiconductor region 312, the number of electrons accumulated in the n-type semiconductor region 312 increases, and the number of holes in the p-type semiconductor region 311 coupled with electrons increases. As the number of holes in the p-type semiconductor region 311 coupled with electrons increases, the width of the depletion layer decreases. In the example shown in the figure, the depletion layer formed in the p-type semiconductor region 311 is reduced to width W2.
In the region between the two electrodes (terminal 321S and terminal 321D) connected to the p-type semiconductor region 311, the conductance is proportional to the number of holes included in the AA' cross section. As the number of electrons accumulated in the n-type semiconductor region 312 increases and the number of holes in the p-type semiconductor region 311 coupled with electrons increases, the resistance decreases. Since the two electrodes connected to the p-type semiconductor region 311 correspond to between the source and the drain of the JFET 321, the resistance value between the source and the drain of the JFET 321 is the depletion layer caused by the photodiode 31 accumulating charges. Change with change.

In this example, the terminals 321S and 321D are connected to the p-type semiconductor region 311, and the current source 322 is provided to allow a constant current to flow between the source and the drain. In other words, the configuration is such that a voltage drop is detected by causing a current to flow between the source and the drain, but the present invention is not limited to this example. Other configurations may be used to detect changes in the resistance value of the photodiode 31 .

Returning to FIG. 3 , when the detector 32 detects a change in the resistance value of the photodiode 31 , the readout section 33 reads out a signal based on the charge of the photodiode 31 . The reading unit 33 outputs the read signal to the memory 23 .

5A, 5B, and 6 are diagrams for explaining a specific circuit configuration and operation according to the first embodiment of the present invention. A specific circuit configuration and operation according to the first embodiment will be described with reference to FIGS.
5A and 5B are diagrams showing an example of the circuit configuration of the pixel-by-pixel circuit 20 and the connection between the pixel-by-pixel circuit 20 and the data bus 24 according to the first embodiment of the present invention. . In this example, the readout section 33 includes a comparator 331 , an OR circuit 332 and a reset transistor 334 .

The comparator 331 has a negative input terminal, a positive input terminal, and an output terminal. A reference potential V _REF is applied to the positive input terminal of the comparator 331 . A negative input terminal of the comparator 331 is connected to a connection point between the JFET 321 and the current source 322 . The potential at the connection point between JFET 321 and current source 322 is described as "pd_out". The output terminal of the comparator 331 outputs L when the potential “ _{pd_out} ” input to the negative input terminal is higher than the reference potential VREF, and outputs H when it is lower than the reference potential _VREF . A signal output from the comparator 331 is referred to as a "detect" signal. The “detect” signal is output to the input terminal of the OR circuit 332 and the memory 23 .

A “detect” signal output from the comparator 331 and a “hold_rst” signal controlled by the control circuit 28 are input to the OR circuit 332 . The OR circuit 332 outputs H when either the input "detect" signal or the "hold_rst" signal is H.

The reset transistor 334 resets the photodiode 31 by supplying a reset voltage V _RST to the photodiode 31 . Reset transistor 334 is controlled by OR circuit 332 .
Note that readout portion 33 may include level shifter 333 in order to match the output potential of OR circuit 332 with _reset voltage VRST. When the output of the OR circuit 332 is H, the level shifter 333 converts the output potential of the OR circuit 332 into the reset voltage V _RST and inputs it to the gate of the reset transistor 334 .

The memory 23 has a counter 231 . A “detect” signal is input to the counter 231 . The counter 231 counts the number of times the rising edge of the "detect" signal is input. A “zero_clr” signal and a “read” signal are input to the counter 231 by the control circuit 28 . A "read" signal input from the control circuit 28 is shared for each row on the pixel array.
The counter 231 resets the count value to zero when the "zero_clr" signal is input. When the "read" signal is input, the counter 231 outputs the counter value to the data bus 24 as the "data_out" signal. The wiring of the data bus 24, which is the output destination of the "data_out" signal, is shared by each column on the pixel array.

FIG. 6 is a diagram showing an example of time change of a signal according to the first embodiment of the present invention. This figure shows the temporal changes of the "hold_rst" signal, the "zero_clr" signal, the "detect" signal, and the "read" signal when the light incident on the photodiode 31 is read by the readout unit 33 .
At time t11, the control circuit 28 controls the "hold_rst" signal to H. When the "hold_rst" signal is controlled to H, the reset transistor 334 is turned on and the potential of the photodiode 31 is _reset to the voltage VRST.
At time t12, the control circuit 28 outputs the "zero_clr" signal. When the "zero_clr" signal is output, the counter 231 is reset to zero.

At time t13, the control circuit 28 controls the "hold_rst" signal to L. When the "hold_rst" signal is controlled low, reset transistor 334 is turned off. When the reset transistor 334 turns off, the resistance value of the JFET 321 decreases according to the amount of light incident on the photodiode 31 . In this example, one frame is from time t13 to time t16, and the image sensor 1 detects the amount of light incident on the photodiode 31 during one frame.

The resistance of JFET 321 decreases according to the amount of light incident on photodiode 31 . Since the amount of current flowing through the JFET 321 is controlled to be constant, the potential applied to the negative input terminal of the comparator 331 decreases.
At time t14, when the potential applied to the negative input terminal of the comparator 331 falls below the reference potential _VREF , the "detect" signal becomes H.

Since the output terminal of the comparator 331 is connected to the counter 231, the counter 231 counts up when the "detect" signal becomes H. Further, since the output terminal of the comparator 331 is connected to the input terminal of the OR circuit 332, when the "detect" signal becomes H, the OR circuit 332 outputs H and the reset transistor 334 is turned on. When the reset transistor 334 is turned on, the potential of the photodiode 31 is _reset to the voltage VRST, the resistance of the JFET 321 increases, the potential of the negative input terminal of the comparator 331 increases, and the "detect" signal becomes L.
From time t13 to time t16, the pixel-by-pixel circuit 20 repeats count-up and reset a plurality of times.

At time t16, the control circuit 28 controls the "hold_rst" signal to H for all pixels. One frame ends when the "hold_rst" signal is controlled to H. The control circuit 28 selects rows in order from the top on the pixel array and outputs a "read" signal to the selected rows, so that the photodiodes 31 are read during one frame (time t13 to time t16). The amount of incident light is read out row by row. Specifically, the control circuit 28 reads the value stored in the counter 231 as the amount of incident light during one frame. That is, the reading unit 33 reads out a signal based on the charge of the photodiode 31 by measuring the number of times that the charge accumulated in the photodiode 31 has accumulated a predetermined amount.
At time t17, control circuit 28 resets counter 231 to zero by outputting a "zero_clr" signal at every pixel to prepare for the next frame.

[Summary of the first embodiment]
According to the embodiment described above, the imaging device 1 includes the photodiode 31 , the detection section 32 and the readout section 33 . Also, the photodiode 31 is a buried photodiode. When the detection unit 32 detects a change in the resistance value of the photodiode 31 , the readout unit 33 reads out a signal based on the charge of the photodiode 31 . Further, the resistance value of the photodiode 31 changes when light is incident. Therefore, when light is incident on the photodiode 31 , the imaging device 1 can read out the charges accumulated in the photodiode 31 . That is, signals can be read out from the embedded photodiodes.
Further, according to the embodiment described above, the image sensor 1 includes the photodiode 31, which is an embedded photodiode, so that dark current can be suppressed.

Further, according to the embodiments described above, in the imaging device 1 , the detection section 32 is formed using at least part of the semiconductor region forming the photodiode 31 . Specifically, the JFET 321 included in the detection section 32 includes a p-type semiconductor region 311 and an n-type semiconductor region 312 that constitute the photodiode 31 . Therefore, the imaging device 1 can easily configure the detection section 32 and easily read out signals from the embedded photodiodes.

Further, according to the embodiments described above, in the image sensor 1, the resistance value of the photodiode 31 changes according to the change in the depletion layer of the photodiode 31. FIG. The detection unit 32 detects changes in the resistance value of the photodiode 31 . The reading unit 33 reads a signal from the photodiode 31 when the detecting unit 32 detects a change in resistance value. Therefore, according to this embodiment, the readout section 33 can be easily configured, and signals can be easily read out from the embedded photodiodes.

Further, according to the embodiments described above, in the image pickup device 1, the readout section 33 measures the number of times that the detection section 32 accumulates a predetermined amount of charge accumulated in the photodiode 31. FIG. The reading unit 33 reads a signal based on the charge of the photodiode 31 by measuring the number of times. Therefore, the imaging device 1 can easily read out signals from the embedded photodiodes.

Further, according to the embodiment described above, the reading unit 33 measures the number of times that the electric charge accumulated in the photodiode 31 is accumulated by the predetermined amount. can be obtained. Therefore, the imaging device 1 is no longer limited by the saturation electron number of the photodiode 31 .

Further, according to the embodiments described above, the readout section 33 does not include a readout circuit such as a floating diffusion or a transfer transistor. Therefore, the readout section 33 is configured with fewer components than when a readout circuit such as a floating diffusion or a transfer transistor is provided. Therefore, the imaging device 1 can be miniaturized.

[Second embodiment]
7 and 8 are diagrams for explaining the specific circuit configuration and operation of the imaging device 1A according to the second embodiment of the present invention. A specific circuit configuration and operation of the pixel-by-pixel circuit 20A included in the image sensor 1A according to the second embodiment will be described with reference to FIGS. 7 and 8. FIG.
FIG. 7 is a diagram showing an example of the circuit configuration of the pixel-by-pixel circuit 20A according to the second embodiment of the present invention. The pixel-by-pixel circuit 20A is different from the pixel-by-pixel circuit 20 in that the pixel-by-pixel circuit 20A is provided with a readout section 33A instead of the readout section 33, and is provided with a memory 23A instead of the memory 23. FIG. Configurations similar to those of the pixel-by-pixel circuit 20 may be denoted by the same reference numerals, and description thereof may be omitted.

The reading unit 33A includes a comparator 335, an OR circuit 336, a comparator 337, a ramp generator 338, and a pulse generation circuit 339.
The comparator 335 has a negative input terminal, a positive input terminal, and an output terminal. A reference potential V _REF is applied to the positive input terminal of the comparator 335 . A negative input terminal of the comparator 335 is connected to a connection point between the JFET 321 and the current source 322 . The output terminal of the comparator 335 outputs L when the potential " _{pd_out} " input to the negative input terminal is higher than the reference potential VREF, and outputs L when the potential input to the positive input terminal is lower than the reference potential _VREF . output H to . A signal output from the comparator 335 is output to an input terminal of the OR circuit 336 .

The output signal of the comparator 335 and the “force_read” signal controlled by the control circuit 28 are input to the OR circuit 336 . The OR circuit 336 outputs H when any of the input signals is H. The output signal of OR circuit 336 is referred to as the "ramp_start" signal. The “ramp_start” signal is input to ramp generator 338 .

A ramp generator 338 generates a ramp signal. Ramp generator 338 comprises an input terminal 3381 , an input terminal 3382 and an output terminal 3383 . An output signal of the OR circuit 336 and a “ramp_start” signal are input to the input terminal 3381 . A “ramp_stop” signal controlled by the control circuit 28 is input to the input terminal 3382 .
The ramp generator 338 outputs a "ramp" signal from the output terminal 3383 when H is input to the input terminal 3381, and outputs a ramp signal from the output terminal 3383 when L is input to the input terminal 3382. to stop.
Here, the "ramp" signal output by the ramp generator 338 is controlled to gradually decrease in voltage from a predetermined value larger than the maximum value of "pd_out" applied to the negative input terminal of the comparator 337. signal. The potential of the "ramp" signal is also referred to as ramp potential.

The comparator 337 has a negative input terminal, a positive input terminal, and an output terminal. A negative input terminal of the comparator 337 is connected to a connection point between the JFET 321 and the current source 322 . A positive input terminal of the comparator 337 is connected to the output terminal 3383 of the ramp generator 338 . The output terminal of the comparator 337 outputs L when the potential "pd_out" input to the negative input terminal is higher than the potential of the "ramp" signal output from the ramp generator 338, and outputs H when it is lower. . A signal output by the comparator 337 is referred to as a "count" signal. The "count" signal is output to the input terminal of the pulse generation circuit 339 and the memory 23A.

A “count” signal is input to the pulse generation circuit 339 . The pulse generation circuit 339 outputs a pulse with a predetermined time width to the OR circuit 332 as a trigger and the fall of the "count" signal.

The memory 23A has a counter 232 . A “clk” signal, a “zero_clr” signal, a “read” signal and a “count” signal are input to the counter 232 . The counter 232 stores the number of rising edges of the "clk" signal input during the interval in which the "count" signal is controlled to H. When the "read" signal is input, the counter 232 outputs the stored value to the peripheral circuit 24 as "data_out".

FIG. 8 is a diagram showing an example of time change of a signal according to the second embodiment of the present invention. The figure shows the "hold_rst" signal, the "zero_clr" signal, the "clk" signal, the "pd_out" signal, the "count" signal, the "force_read" signal, and the FIG. 4 is a diagram showing temporal changes of a “ramp” signal and a “read” signal;
At time t21, the control circuit 28 controls the "hold_rst" signal to H. When the "hold_rst" signal is controlled to H, the reset transistor 334 is turned on and the potential of the photodiode 31 is _reset to the voltage VRST.
At time t22, the control circuit 28 outputs the "zero_clr" signal. When the "zero_clr" signal is output, the counter 232 is reset to zero.

At time t23, the control circuit 28 controls the "hold_rst" signal to L. When the "hold_rst" signal is controlled low, reset transistor 334 is turned off. When the reset transistor 334 turns off, the resistance value of the JFET 321 decreases according to the amount of light incident on the photodiode 31 . In this example, a section from time t23 to time t32 is one frame, and the imaging element 1 detects the amount of light incident on the photodiode 31 during one frame.

The resistance of JFET 321 decreases according to the amount of light incident on photodiode 31 . Therefore, when light is incident on the photodiode 31, the potential of "pd_out" drops, and the potential applied to the negative input terminal of the comparator 335 and the negative input terminal of the comparator 337 drops.

At time t24, when the potential applied to the negative input terminal of the comparator 335 falls below the reference potential _VREF , the comparator 335 outputs H.
When the comparator 335 outputs H, the OR circuit 336 outputs H, and H is input to the input terminal 3381 of the ramp generator 338 . When H is input to the input terminal 3381 of the ramp generator 338 , a “ramp” signal is output to the output terminal 3383 of the ramp generator 338 . When the "ramp" signal is output, the potential of the positive input terminal of the comparator 337 becomes lower than the potential of the negative input terminal, and the output terminal of the comparator 337 outputs H. That is, when the "ramp" signal is output, the "count" signal becomes H. Since the output terminal of the comparator 337 is connected to the counter 232 , the counter 232 is added to the number of rising edges of the “clk” signal input while the “count” signal is controlled to H. Also, since the output terminal of the comparator 337 is connected to the input terminal of the OR circuit 332 via the pulse generation circuit 339, when the "count" signal falls, the OR circuit 332 outputs H and the reset transistor 334 turns on. do. When the reset transistor 334 turns on, the potential of the photodiode 31 is _reset to the voltage VRST.

At time t25, when the potential applied to the positive input terminal of the comparator 337 becomes smaller than the potential applied to the negative input terminal, L is output to the output terminal of the comparator 337 . When L is output to the output terminal of the comparator 337, the counter 232 stops counting rising edges of the input "clk" signal. Also, when the "count" signal becomes L, the "ramp_stop" signal is input to the input terminal 3382 of the ramp generator 338, and the ramp generator 338 is reset. When the ramp generator 338 is reset, the potential "ramp" signal at the output terminal 3383 becomes a predetermined potential.

From time t24 to time t29, the circuit for each pixel 20A repeats counting up of the counter 232 and resetting of the photodiode 31. FIG.

At time t30, the control circuit 28 controls the "force_read" signal to H. For example, the control circuit 28 controls the "force_read" signal to H after a predetermined time has passed since the "hold_rst" signal was controlled to L. When the "force_read" signal is controlled to H, H is input to the input terminal 3381 of the ramp generator 338 and the "ramp" signal is output to the output terminal 3383 of the ramp generator 338 . When the "ramp" signal is output, the potential of the positive input terminal of the comparator 337 becomes lower than the potential of the negative input terminal, and the output terminal of the comparator 337 outputs H. That is, when the "ramp" signal is output, the counter 232 is added to the number of rising edges of the "clk" signal input while the "count" signal is controlled to H. Since the output terminal of the comparator 337 is connected to the counter 232, the counter 232 counts up when the "count" signal becomes H. Also, since the output terminal of the comparator 337 is connected to the input terminal of the OR circuit 332, when the "count" signal becomes H, the OR circuit 332 outputs H and the reset transistor 334 is turned on. When the reset transistor 334 turns on, the potential of the photodiode 31 is _reset to the voltage VRST.

At time t31, when the potential applied to the positive input terminal of the comparator 337 becomes smaller than the potential applied to the negative input terminal, L is output to the output terminal of the comparator 337 . When L is output to the output terminal of the comparator 337, the counter 232 stops counting rising edges of the input "clk" signal. That is, when the control circuit 28 outputs the "force_read" signal, the reading unit 33A reads the charge amount when the charge accumulated in the photodiode 31 is less than the predetermined amount.

Also, since the output terminal of the comparator 337 is connected to the input terminal of the OR circuit 332, when the "count" signal becomes H, the OR circuit 332 outputs H and the reset transistor 334 is turned on. When the reset transistor 334 turns on, the potential of the photodiode 31 is _reset to the voltage VRST, the resistance of the JFET 321 increases, the potential of the negative input terminals of the comparators 335 and 337 increases, and the "count" signal becomes L. become. When the "count" signal goes low, the "ramp_stop" signal is input to the input terminal 3382 of the ramp generator 338, and the ramp generator 338 is reset. When ramp generator 338 is reset, the potential "ramp" signal at output terminal 3383 goes to zero.

At time t32, the control circuit 28 selects rows in order from the top of the pixel array and controls the "read" signal of the selected row to H. When the "read" signal is controlled to H, the counter 232 outputs the value stored in the counter 232 to the data bus 24 as "data_out".

[Summary of the second embodiment]
According to the embodiment described above, the imaging device 1A includes the reading section 33A. The imaging device 1 is provided with the readout section 33A to read out the charge amount when the charge accumulated in the photodiode 31 is less than a predetermined amount. Therefore, according to this embodiment, signals can be read out from the embedded photodiodes more accurately.

Further, according to the embodiment described above, the image pickup element 1A is provided with the readout section 33A to read out the charge amount of the charge accumulated in the photodiode 31, so that the dark current can be reduced even in the embedded photodiode. .

[Third embodiment]
9 and 10 are diagrams for explaining the specific circuit configuration and operation of the imaging device 1B according to the third embodiment of the present invention. A specific circuit configuration and operation of the pixel-by-pixel circuit 20B included in the image sensor 1B according to the third embodiment will be described with reference to FIGS. 9 and 10. FIG.
FIG. 9 is a diagram showing an example of the circuit configuration of the pixel-by-pixel circuit 20B according to the third embodiment of the invention. The pixel-by-pixel circuit 20B is different from the pixel-by-pixel circuit 20 in that it includes a pixel 21B instead of the pixel 21, a readout unit 33B instead of the readout unit 33, and a memory 23B instead of the memory 23. FIG. Configurations similar to those of the pixel-by-pixel circuit 20 may be denoted by the same reference numerals, and description thereof may be omitted.

The pixel 21</b>B includes a photodiode 31 , a floating diffusion (accumulation portion) 41 , and a transfer transistor (transfer portion) 42 .
The transfer transistor 42 is controlled by the control circuit 28 . Specifically, the transfer transistor 42 transfers charges generated by the photodiode 31 to the floating diffusion 41 based on a transfer signal controlled by the control circuit 28 .
The floating diffusion 41 stores charges generated and accumulated by the photodiode 31 and transferred via the transfer transistor 42 .

The readout section 33B includes a comparator 51, an OR circuit 52, a readout control circuit 53, a reset transistor 54, a transistor 55, a transistor 56, and a comparator 57.
The comparator 51 has a negative input terminal, a positive input terminal, and an output terminal. A reference potential V _REF1 is applied to the positive input terminal of the comparator 51 . A negative input terminal of the comparator 51 is connected to a connection point between the JFET 321 and the current source 322 . The output terminal of the comparator 51 outputs L when the potential input to the negative input terminal is higher than the reference potential _VREF1 , and H when the potential input to the positive input terminal is lower than the reference potential _VREF1 . Output. A signal output from the comparator 51 is output to an input terminal of the OR circuit 52 .

The output signal of the comparator 51 and the “force_read” signal controlled by the control circuit 28 are input to the OR circuit 52 . The OR circuit 52 outputs H when any of the input signals is H. The output signal of the OR circuit 52 is described as a "trigger" signal.

The read control circuit 53 is controlled by the control circuit 28 and controls each circuit included in the read section 33B. Specifically, the read control circuit 53 controls the transfer transistor 42 , the reset transistor 54 , the comparator 57 and the counter 233 based on the “trigger” signal, which is the output signal from the OR circuit 52 , and the control signal from the control circuit 28 . and control.

The reset transistor 54 resets the floating diffusion 41 by supplying the reset voltage V _RST to the floating diffusion 41 . Reset transistor 54 is controlled by read control circuit 53 .

Transistor 55 is a p-channel FET. The gate terminal of the transistor 55 is connected to the floating diffusion 41 , the source terminal is connected to the power supply, and the drain terminal is connected to the negative input terminal of the comparator 57 .
Transistor 56 is an n-channel FET. A reference potential V _REF2 is applied to the gate terminal of the transistor 56 , the source terminal is grounded, and the drain terminal is connected to the negative input terminal of the comparator 57 .

The comparator 57 has a negative input terminal, a positive input terminal, and an output terminal. A negative input terminal of the comparator 57 is connected to a connection point between the drain of the transistor 55 and the drain of the transistor 56 . A positive input terminal of the comparator 57 is controlled by the readout control circuit 53 and receives a ramp signal. The output terminal of the comparator 57 outputs L when the potential input to the negative input terminal is higher than the potential of the ramp signal, and outputs H when it is lower. A signal output from the comparator 57 is referred to as a "count" signal. The "count" signal is output to memory 23B.

The memory 23B has a counter 233 . A “clk” signal, a “load” signal, a “data_in” signal, an “up” signal, a “down” signal, and a “count” signal are input to the counter 233 . When the "count" signal is input, the counter 233 determines whether the "up" signal or the "down" signal is input while the "count" signal is high. Add or subtract the number of rising edges of the clk" signal. Also, when the "load" signal is input, the counter 233 stores the value indicated by the "data_in" signal in synchronization with the rising edge thereof. The counter 233 always outputs the stored counter value on the "data_out" signal. The terminal of the "data_in" signal of the counter 233 is connected to the terminal of the "data_out" signal of the counter 233 of the pixel one above in the pixel array. A predetermined value is input to the "data_in" signal of the pixel at the top of the pixel array, and the "data_out" signal of the pixel at the bottom of the pixel array is output to the peripheral circuit. . Each time the "load" signal rises, the values of the counters 233 of all pixels are transferred to the counters 233 of the pixels one level below in the pixel array, and the counters 233 of the pixels to which the transfer has finished hold a predetermined value. is entered. That is, the value of the counter 233 is read out to the peripheral circuit and reset to a predetermined value by the operation of the shift register.

FIG. 10 is a diagram showing an example of temporal changes in signals according to the third embodiment of the present invention. The figure shows the "load" signal, the "clk" signal, the "pd_out" signal, the "force_read" signal, the "trigger" signal, the "FDRST" signal, and the It is the figure which showed the time change of the "TX" signal, the "down" signal, the "up" signal, and the "ramp" signal.

The image pickup device 1B in this embodiment performs correlated double sampling (hereinafter referred to as CDS) operation for removing variations in output from pixel 21 to pixel 21 . The operation from time t51 to time t56 is the operation of DARK sampling in CDS.

At time t<b>51 , the readout control circuit 53 turns on the transfer transistor 42 to transfer all the charges accumulated in the photodiode 31 to the floating diffusion 41 . This resets the photodiode 31 to zero accumulated charge.
From time t55 to time t56, the control circuit 28 reads out the value of the counter 233 to the peripheral circuit 24 by controlling the "load" signal, and at the same time resets the counter 233 in all pixels to a predetermined value.

At time t61, when the charge accumulated in the photodiode 31 reaches a predetermined amount and the potential of the negative input terminal of the comparator 51 becomes lower than the reference potential V _REF1 applied to the positive input terminal, the comparator 51 changes to H. and the OR circuit 52 outputs H. That is, the "trigger" signal is controlled to H.

When the read control circuit 53 detects that the "trigger" signal has been controlled to H, it performs autonomous A/D conversion from time t62 to time t67.
At time t62, read control circuit 53 turns reset transistor 54 on. The floating diffusion 41 is reset by turning on the reset transistor 54 .

At time t63, read control circuit 53 outputs a "down" signal. Also, the read control circuit 53 gradually lowers the "ramp" voltage from a predetermined voltage. Since the predetermined voltage is a voltage higher than the negative input terminal of the comparator 57, the "count" signal switches to H at time t63.
At time t64, when the "ramp" voltage becomes lower than the negative input terminal, the "count" signal switches to L. From time t63 to time t64 while the "count" signal is high, the counter 233 subtracts the number of rising edges of the input "clk" signal from the value it holds. That is, the value determined by the voltage of the floating diffusion 41 after resetting is subtracted from the counter 233 .

At time t<b>65 , the readout control circuit 53 turns on the transfer transistor 42 to transfer the charge accumulated in the photodiode 31 to the floating diffusion 41 . That is, the transfer transistor 42 transfers the charge of the photodiode 31 to the floating diffusion 41 when the detection unit 32 detects a change in the resistance value of the photodiode 31 .
At time t66, read control circuit 53 outputs an "up" signal. Also, the read control circuit 53 gradually lowers the "ramp" voltage from a predetermined voltage. Since the predetermined voltage is a voltage higher than the negative input terminal of the comparator 57, the "count" signal switches to H at time t65.
At time t67, when the "ramp" voltage becomes lower than the negative input terminal, the "count" signal switches to L. From time t66 to time t67 while the "count" signal is H, the counter 233 adds the number of rising edges of the input "clk" signal to the value it holds. That is, a value determined by both the reset potential of the floating diffusion 41 and the charge transferred from the photodiode 31 is added to the counter 233 .

At time t71, when the charge accumulated in the photodiode 31 reaches a predetermined amount again, the readout control circuit 53 performs an autonomous A /D conversion. Since the operation from time t71 to time t77 is the same as the operation described from time t61 to time t67, the description is omitted.

The readout control circuit 53 performs A/D conversion by an external trigger a predetermined time before the end of the period of one frame, and the charge accumulated in the photodiode 31 does not reach a predetermined amount. is read out by A/D conversion.
At time t81, the control circuit 28 controls the "force_read" signal to H. The OR circuit 52 outputs H when controlled to H by the "force_read" signal. That is, the "trigger" signal is controlled to H. When the read control circuit 53 detects that the "trigger" signal has been controlled to H, it performs A/D conversion by an external trigger from time t62 to time t67. A/D conversion by an external trigger is different from autonomous A/D conversion in that the trigger is controlled by the control circuit 28 instead of the output of the comparator 51, but the operation performed by the read control circuit 53 is the same. be.

At time t82, read control circuit 53 turns reset transistor 54 on. The floating diffusion 41 is reset by turning on the reset transistor 54 .
At time t83, read control circuit 53 outputs a "down" signal. Also, the read control circuit 53 gradually lowers the "ramp" voltage from a predetermined voltage. Since the predetermined voltage is a voltage higher than the negative input terminal of the comparator 57, the "count" signal switches to H at time t63.
At time t84, when the "ramp" voltage becomes lower than the negative input terminal, the "count" signal switches to L. From time t83 to time t84 while the "count" signal is high, the counter 233 subtracts the number of rising edges of the input "clk" signal from the value it holds. That is, the value determined by the voltage of the floating diffusion 41 after resetting is subtracted from the counter 233 .

At time t<b>85 , the readout control circuit 53 turns on the transfer transistor 42 to transfer the charge accumulated in the photodiode 31 to the floating diffusion 41 .
At time t86, read control circuit 53 outputs an "up" signal. Also, the read control circuit 53 gradually lowers the "ramp" voltage from a predetermined voltage. Since the predetermined voltage is a voltage higher than the negative input terminal of the comparator 57, the "count" signal switches to H at time t85.
At time t87, when the "ramp" voltage becomes lower than the negative input terminal, the "count" signal switches to L. From time t86 to time t87 while the "count" signal is H, the counter 233 adds the number of rising edges of the input "clk" signal to the value it holds. That is, a value determined by both the reset potential of the floating diffusion 41 and the charge transferred from the photodiode 31 is added to the counter 233 .

From time t88 to time t89, the control circuit 28 reads the value of the counter 233 to the peripheral circuit 24 by controlling the "load" signal, and at the same time sets the counter 233 to a predetermined value for all pixels for the next frame. reset to

[Summary of the third embodiment]
As described above, according to this embodiment, the floating diffusion 41 and the transfer transistor 42 are provided. The transfer transistor 42 transfers the charge of the photodiode 31 to the floating diffusion 41 when the detection unit 32 detects that the charge of the photodiode 31 has reached a predetermined value. The readout section 33B reads out the charge accumulated in the floating diffusion 41 as the charge of the photodiode 31 . Therefore, according to this embodiment, the charge accumulated in the photodiode 31 can be read out with higher accuracy.

In this embodiment, a "ramp" signal generating circuit is placed in one pixel, and independent A/D conversion is started based on the output of the comparator 51. However, the "ramp" signal generating circuit is controlled by a control circuit. 28, and A/D conversion may be performed repeatedly at predetermined time intervals. In this case, if the output of the comparator 51 is not H, the value of the counter 233 may not be increased or decreased and the transfer transistor 42 may not be turned on.

Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to the above, and various design changes, etc., can be made without departing from the gist of the present invention. It is possible to

1... image sensor,
11... pixel chip,
12... circuit chip,
20... Circuit for each pixel,
21 pixels,
22 ADC,
23... memory,
24 data bus,
25... Peripheral circuit,
28 ... control circuit,
29... Circuit for each element,
31... photodiode,
32 ... detector,
321 JFETs,
322 ... current source,
33 ... reading unit,
41... floating diffusion,
42 ... transfer transistor,
53 ... read control circuit

Claims (7)

a photoelectric conversion unit that converts light into an electric charge;
an accumulation unit for accumulating charges generated by the photoelectric conversion unit;
a detection unit that detects a change in the resistance value of the storage unit;
and a readout unit that reads out a signal based on the charge of the photoelectric conversion unit when the detection unit detects a change in the resistance value of the storage unit. The imaging device according to claim 1, wherein the detection section is formed using at least part of a semiconductor region forming the photoelectric conversion section. 3. The imaging device according to claim 1, wherein the resistance value of the detection section changes in accordance with a change in a depletion layer caused by accumulation of charges in the photoelectric conversion section. 4. The reading unit according to any one of claims 1 to 3, wherein the readout unit reads out a signal based on the charge of the photoelectric conversion unit by measuring the number of times a predetermined amount of charge accumulated in the photoelectric conversion unit is accumulated. image sensor. 5. The imaging device according to claim 4, wherein the reading unit reads the charge amount when the charge accumulated in the photoelectric conversion unit is less than a predetermined amount. a transfer unit that transfers charges from the photoelectric conversion unit to the storage unit,
the transfer unit transfers the charge of the photoelectric conversion unit to the storage unit when the detection unit detects a change in the resistance value of the photoelectric conversion unit;
The imaging device according to any one of claims 1 to 3, wherein the readout section reads out the charge accumulated in the accumulation section as a signal based on the charge of the photoelectric conversion section. An imaging device comprising the imaging device according to claim 1 .

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