JP2023001827A - semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device capable of operating at a high speed.SOLUTION: A semiconductor storage device comprises: a substrate; a plurality of memory layers arranged in a first direction crossing a surface of the substrate; a first wiring provided in a position closer to the substrate than the plurality of memory layers or in a position farther from the substrate than the plurality of memory layers; a transistor layer provided between the plurality of memory layers and the first wiring; and a second wiring extending in the first direction and connected to the plurality of memory layers and the transistor layer. Each of the plurality of memory layers comprises a memory unit, a first semiconductor layer electrically connected between the memory unit and the second wiring, a first electrode facing the first semiconductor layer, a third wiring extending in a second direction crossing the first direction and connected to the first electrode, a second semiconductor layer connected to one end part in a second direction of the third wiring, and a second electrode facing the second semiconductor layer. The transistor layer comprises a third semiconductor layer electrically connected between the first wiring and the second wiring and a third electrode facing the third semiconductor layer.SELECTED DRAWING: Figure 1

Description

This embodiment relates to a semiconductor memory device.

2. Description of the Related Art As semiconductor memory devices become more highly integrated, considerations are being made on making semiconductor memory devices three-dimensional.

U.S. Pat. No. 9,514,792

A semiconductor memory device that operates at high speed is provided.

A semiconductor memory device according to one embodiment includes a substrate, a plurality of memory layers arranged in a first direction intersecting the surface of the substrate, and a position closer to the substrate than the memory layers or closer to the memory layers than the memory layers. a first wiring provided far from a substrate; a transistor layer provided between the plurality of memory layers and the first wiring; and a first wiring extending in the first direction and connected to the plurality of memory layers and the transistor layer. 2 wiring; Each of the plurality of memory layers includes a memory section, a first semiconductor layer electrically connected between the memory section and the second wiring, and a first electrode facing the first semiconductor layer. Further, the plurality of memory layers each extend in a second direction that intersects with the first direction, a third wiring connected to the first electrode, and a third wiring connected to one end of the third wiring in the second direction. It comprises two semiconductor layers and a second electrode facing the second semiconductor layer. The transistor layer includes a third semiconductor layer electrically connected between the first wiring and the second wiring, and a third electrode facing the third semiconductor layer.

1 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to a first embodiment; FIG. FIG. 3 is a schematic circuit diagram for explaining a read operation of the same semiconductor memory device; FIG. 4 is a schematic waveform diagram for explaining a read operation of the same semiconductor memory device; FIG. 4 is a schematic waveform diagram for explaining a read operation of the same semiconductor memory device; 2 is a schematic perspective view showing the configuration of part of the same semiconductor memory device; FIG. 2 is a schematic XY cross-sectional view showing the configuration of part of the same semiconductor memory device; FIG. 2 is a schematic XY cross-sectional view showing the configuration of part of the same semiconductor memory device; FIG. 2 is a schematic XY cross-sectional view showing the configuration of part of the same semiconductor memory device; FIG. FIG. 9 is a schematic XZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along line AA′ and viewed along the direction of the arrow; FIG. 9 is a schematic YZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along line BB' and viewed in the direction of the arrow; FIG. 9 is a schematic YZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along the CC′ line and viewed in the direction of the arrow; 4A and 4B are schematic cross-sectional views for explaining the method of manufacturing the semiconductor memory device according to the first embodiment; It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. 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FIG. 11 is a schematic XZ cross-sectional view showing the configuration of part of a semiconductor memory device according to a second embodiment; 8A to 8C are schematic cross-sectional views for explaining the method of manufacturing the semiconductor memory device according to the second embodiment; It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. It is a typical sectional view for explaining the manufacturing method. FIG. 11 is a schematic perspective view showing the configuration of a semiconductor memory device according to another embodiment;

Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. It should be noted that the following embodiments are merely examples, and are not intended to limit the present invention. Also, the drawings below are schematic, and for convenience of explanation, some configurations and the like may be omitted. Moreover, the same code|symbol may be attached|subjected to the part which is common to several embodiment, and description may be abbreviate|omitted.

In this specification, the term "semiconductor memory device" may mean a memory die, or a memory system including a controller die such as a memory chip, memory card, SSD (Solid State Drive), or the like. There are things to do. Furthermore, it may also mean a configuration including a host computer, such as a smart phone, tablet terminal, or personal computer.

Further, in this specification, when the first configuration is said to be "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, The first configuration may be connected to the second configuration via wiring, semiconductor members, transistors, or the like. For example, if three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even though the second transistor is in the OFF state.

In this specification, a predetermined direction parallel to the upper surface of the substrate is the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is the Y direction, and a direction perpendicular to the upper surface of the substrate is the Y direction. The direction is called the Z direction.

Further, in this specification, the direction along a predetermined plane is the first direction, the direction intersecting the first direction along the predetermined plane is the second direction, and the direction intersecting the predetermined plane is the third direction. It is sometimes called direction. These first, second and third directions may or may not correspond to any of the X, Y and Z directions.

In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called up, and the direction toward the substrate along the Z direction is called down. In addition, when referring to the lower surface or the lower end of a certain structure, it means the surface or the end of the structure on the side of the substrate, and when referring to the upper surface or the upper end, the surface or the end of the structure opposite to the substrate is meant. It means the part. Also, a surface that intersects the X direction or the Y direction is called a side surface or the like.

[First embodiment]
[Circuit configuration]
FIG. 1 is a schematic circuit diagram showing the configuration of the semiconductor memory device according to the first embodiment. As shown in FIG. 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML2, a transistor layer TL, a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML2 and the transistor layer TL, and a plurality of memory layers via the transistor layer TL. It includes a plurality of global bit lines GBL electrically connected to bit lines BL, and plate lines PL connected to a plurality of memory layers ML0 to ML2.

The memory layers ML0 to ML2 each include a plurality of word lines WL0 to WL2 and a plurality of memory cells MC connected to the word lines WL0 to WL2. Each memory cell MC includes a transistor TrC and a capacitor CpC. A source electrode of the transistor TrC is connected to the bit line BL. A drain electrode of the transistor TrC is connected to the capacitor CpC. A gate electrode of the transistor TrC is connected to one of word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the drain electrode of the transistor TrC. The other electrode of capacitor CpC is connected to plate line PL.

Each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML0-ML2.

The memory layers ML0 to ML2 include a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, and TrL2b (hereinafter sometimes referred to as "transistors TrL") provided corresponding to a plurality of word lines WL0 to WL2, respectively. There is.). A drain electrode of the transistor TrL is connected to one of word lines WL0 to WL2. Source electrodes of the transistors TrL are connected to word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter sometimes referred to as "word line selection lines LW"). Gate electrodes of the transistors TrL are connected to layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, and LL2b (hereinafter sometimes referred to as "layer selection lines LL").

The word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML0-ML2. Further, the layer selection lines LL0a, LL1a, LL2a are commonly connected to all the transistors TrL0a, TrL1a, TrL2a corresponding to the memory layers ML0 to ML2, respectively. Similarly, the layer select lines LL0b, LL1b, LL2b are commonly connected to all the transistors TrL0b, TrL1b, TrL2b corresponding to the memory layers ML0 to ML2, respectively.

The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. A source electrode of the transistor TrB is connected to the global bit line GBL. A drain electrode of the transistor TrB is connected to the bit line BL. A gate electrode of the transistor TrB is connected to one of bit line selection lines LB0 to LB2.

Further, the transistor layer TL includes a plurality of transistors TrTa and TrTb (hereinafter sometimes referred to as "transistors TrT") provided corresponding to the plurality of bit line selection lines LB0 to LB2. A drain electrode of the transistor TrT is connected to one of bit line selection lines LB0 to LB2. Source electrodes of the transistors TrT are connected to word line selection lines LW. Gate electrodes of the transistor TrT are connected to wirings LTa and LTb (hereinafter sometimes referred to as "wirings LT"), respectively.

Note that the wiring LTa is commonly connected to all the transistors TrTa. Similarly, the wiring LTb is commonly connected to all the transistors TrTb.

[Read operation]
FIG. 2 is a schematic circuit diagram for explaining the read operation of the semiconductor memory device according to the first embodiment.

For read operation, one of the memory layers ML0 to ML2 is selected. In the illustrated example, the memory layer ML0 is selected. When selecting the memory layers ML0 to ML2, for example, among the plurality of layer selection lines LL0a, LL1a, and LL2a, the layer selection line LL0a corresponding to the memory layer ML0 to be read is supplied with the voltage V _ON ', A voltage V _OFF ' is supplied to the other layer selection lines LL1a and LL2a. Further, for example, among the plurality of layer selection lines LL0b, LL1b, LL2b, the layer selection line LL0b corresponding to the memory layer ML0 to be read is supplied with the voltage V _OFF ', and the other layer selection lines LL1b, LL2b are supplied. is supplied with a voltage V _ON '. Further, the voltage V _ON ' is supplied to the wiring LTa, and the voltage V _OFF ' is supplied to the wiring LTb.

The voltage V _ON ' has, for example, a magnitude sufficient to turn on the transistors TrL and TrT. The voltage V _OFF ' has a magnitude that, for example, turns off the transistors TrL and TrT. For example, if the transistors TrL and _TrT are NMOS _transistors , the voltage VON' is greater than the voltage VOFF'. Further, for example, when the transistors TrL and TrT are PMOS transistors, the voltage V _ON ' is smaller than the voltage V _OFF '.

Further, one of the plurality of word lines WL0 to WL2 is selected for read operation. In the illustrated example, word line WL0 is selected. When selecting the word lines WL0 to WL2, for example, among the plurality of word line selection lines LW0a, LW1a, and LW2a, the word line selection line _LW0a corresponding to the word line WL0 to be read is supplied with the voltage VON. , and other layer selection lines _LW1a and LW2a. Also, for example, a voltage VOFF is supplied to a plurality of word line selection lines LW0b, _LW1b , and LW2b.

The voltage V _ON has, for example, a magnitude sufficient to turn on the transistors TrC and TrB. The voltage VOFF has a magnitude that, for example, turns _off the transistors TrC and TrB. For example, if the transistors TrC and _TrB are NMOS _transistors , the voltage VON is greater than the voltage VOFF. Further, for example, when the transistors TrC and _TrB are PMOS _transistors , the voltage VON is smaller than the voltage VOFF.

Here, a word line WL0 (hereinafter referred to as "selected word line WL0") connected to a memory cell MC (hereinafter referred to as "selected memory cell MC") to be read is provided with transistor TrL0a. A voltage V _ON is supplied via . As a result, the transistor TrC in the selected memory cell MC is turned on. A voltage VON is supplied to the transistor _TrB connected to the selected memory cell MC through the transistor TrTa. As a result, the transistor TrB is turned on, and the capacitor CpC in the selected memory cell MC is electrically connected to the global bit line GBL. Along with this, the voltage of the global bit line GBL fluctuates, or a current flows through the global bit line GBL. Data stored in the selected memory cell MC can be read by detecting this voltage variation or current.

Word lines WL1 and WL2 other than the selected word line WL0 corresponding to the same memory layer ML0 as the selected memory cell MC (hereinafter referred to as "unselected word lines WL1 and WL2", etc.) are connected through transistors TrL0a. , and a voltage V _OFF are supplied. As a result, the transistor TrC in the memory cell MC is turned off. Further, the transistor TrB connected to such a memory cell MC is supplied with the voltage VOFF via the transistor _TrTa . As a result, the transistor TrB is turned off.

The unselected word lines WL0, WL1, WL2 corresponding to the memory layers ML1, ML2 different from the selected memory cell MC are supplied with the voltage VOFF through the transistors _TrL1b , TrL2b. As a result, the transistor TrC in the memory cell MC is turned off.

FIG. 3 is a schematic waveform diagram for explaining an execution example of a read operation. In the example of FIG. 3, the read operations corresponding to the word lines WL0 to WL2 included in the memory layer ML0 are sequentially performed, and the read operations corresponding to the word lines WL0 to WL2 included in the memory layer ML1 are sequentially performed. Further, read operations corresponding to a plurality of word lines WL0 to WL2 included in the memory layer ML2 are sequentially performed.

That is, in the example of FIG. 3, during the period T100, a read operation is performed on a plurality of memory cells MC connected to the word line WL0 included in the memory layer ML0. Also, in period T101, a read operation is performed for a plurality of memory cells MC connected to word line WL1 included in memory layer ML0. Also, in period T102, a read operation is performed for a plurality of memory cells MC connected to word line WL2 included in memory layer ML0.

Further, during the period T110, a read operation is performed on a plurality of memory cells MC connected to the word line WL0 included in the memory layer ML1. Also, during the period T111, the read operation is performed for the plurality of memory cells MC connected to the word line WL1 included in the memory layer ML1. Further, during the period T112, a read operation is performed on a plurality of memory cells MC connected to the word line WL2 included in the memory layer ML1.

Further, during period T120, a read operation is performed for a plurality of memory cells MC connected to word line WL0 included in memory layer ML2. Also, during the period T121, a read operation is performed for a plurality of memory cells MC connected to the word line WL1 included in the memory layer ML2. Also, during period T122, a read operation is performed for a plurality of memory cells MC connected to word line WL2 included in memory layer ML2.

FIG. 4 is a schematic waveform diagram for explaining another execution example of the read operation. In the example of FIG. 4, the read operation corresponding to the word line WL0 included in each of the memory layers ML0 to ML2 is sequentially performed, the read operation corresponding to the word line WL1 included in each of the memory layers ML0 to ML2 is sequentially performed, Furthermore, the read operation corresponding to the word line WL2 included in each of the memory layers ML0-ML2 is sequentially performed.

That is, in the example of FIG. 4, during the period T200, a read operation is performed on a plurality of memory cells MC connected to the word line WL0 included in the memory layer ML0. Also, in period T201, a read operation is performed for a plurality of memory cells MC connected to word line WL0 included in memory layer ML1. Also, in period T202, a read operation is performed for a plurality of memory cells MC connected to word line WL0 included in memory layer ML2.

Also, during the period T210, a read operation is performed for a plurality of memory cells MC connected to the word line WL1 included in the memory layer ML0. Further, during the period T211, a read operation is performed for a plurality of memory cells MC connected to the word line WL1 included in the memory layer ML1. Also, during period T212, a read operation is performed for a plurality of memory cells MC connected to word line WL1 included in memory layer ML2.

Also, in period T220, a read operation is performed for a plurality of memory cells MC connected to word line WL2 included in memory layer ML0. Also, during period T221, a read operation is performed for a plurality of memory cells MC connected to word line WL2 included in memory layer ML1. Also, during period T222, a read operation is performed for a plurality of memory cells MC connected to word line WL2 included in memory layer ML2.

3 and 4 show an example in which voltages are supplied to the word lines WL0 to WL2 in the memory layers ML0 to ML2, which are the targets of the read operation, via the transistors TrL0a, TrL1a, and TrL2a. 3 and 4 show an example of supplying voltages to word lines WL0 to WL2 in other memory layers ML0 to ML2 via transistors TrL0b, TrL1b, and TrL2b. However, for example, the voltages supplied to the transistors TrL0a, TrL1a, and TrL2a in the examples of FIGS. 3 and 4 are supplied to the transistors TrL0b, TrL1b, and TrL2b, and in the examples of FIGS. , may be supplied to the transistors TrL0a, TrL1a, and TrL2a.

[structure]
FIG. 5 is a schematic perspective view showing the configuration of part of the semiconductor memory device according to the first embodiment. FIG. 6 is a schematic XY cross-sectional view showing the configuration of part of the semiconductor memory device. 6 omits a part of the configuration (insulating layers 121 and 151 to be described later). 7 and 8 are schematic XY cross-sectional views showing the configuration of part of the semiconductor memory device. 7 and 8 show XY sections at different height positions. FIG. 9 is a schematic XZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along the line AA' and viewed in the direction of the arrows. FIG. 10 is a schematic YZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along line BB' and viewed along the direction of the arrow. FIG. 11 is a schematic XZ cross-sectional view of the configuration shown in FIGS. 7 and 8 cut along line CC' and viewed along the direction of the arrows.

FIG. 5 shows part of the semiconductor substrate Sub and a memory cell array MCA provided above the semiconductor substrate Sub.

The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer and the electrode layer (not shown) form a control circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in a region immediately below the memory cell array MCA. The sense amplifier circuit is connected to global bit line GBL. In a read operation, the sense amplifier circuit can read data stored in the selected memory cell MC by detecting voltage fluctuation or current of the global bit line GBL.

The memory cell array MCA includes a plurality of memory layers ML0 to ML2 arranged in the Z direction, a transistor layer TL provided therebelow, and a plurality of global bit lines GBL provided therebelow. Insulating layers 103 such as silicon oxide (SiO ₂ ) are provided between the plurality of memory layers ML0 to ML2.

As shown in FIG. 6, the memory layers _ML0 to ML2 include a memory cell region RMC, and a transistor region _RTrL and a hookup region _RHU provided on one side and the other side of the memory cell region _RMC in the Y direction, respectively. And prepare. Each of the transistor regions _{R_TrL} is provided between the memory cell region _RMC and the hookup region _RHU .

A plurality of insulating layers 101 and a plurality of conductive layers 102 arranged alternately in the X direction are provided in the memory cell region _RMC . As shown in FIG. 5, the plurality of insulating layers 101 and the plurality of conductive layers 102 extend in the Y direction and the Z direction, dividing the memory layers ML0 to ML2 and the transistor layers TL in the X direction.

The insulating layer 101 contains, for example, silicon oxide (SiO ₂ ).

The conductive layer 102 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 102 functions, for example, as the plate line PL (FIG. 1).

A plurality of conductive layers 104 provided between the insulating layer 101 and the conductive layer 102 are provided in the memory cell region _RMC . The multiple conductive layers 104 are aligned in the Y direction and extend in the Z direction through the multiple memory layers ML0 to ML2 and the transistor layer TL.

The conductive layer 104 includes, for example, a laminated structure of indium tin oxide (ITO), titanium nitride (TiN) and tungsten (W). The conductive layer 104 functions, for example, as bit lines BL (FIG. 1). A plurality of bit lines BL are provided corresponding to the plurality of transistors TrC included in the memory layers ML0 to ML2.

In the memory cell region RMC, the memory layers _ML0 to ML2 include a plurality of transistor structures 110 provided corresponding to the plurality of conductive layers 104 and a conductive layer provided between the plurality of transistor structures 110 and the insulating layer 101. 120 and a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102 .

For example, as shown in FIGS. 8 and 9, the transistor structure 110 includes an insulating layer 111 provided on the outer peripheral surface of the conductive layer 104, a conductive layer 112 provided on the outer peripheral surface of the insulating layer 111, and the conductive layer 112. An insulating layer 113 is provided on the upper surface, the lower surface and the outer peripheral surface, and a semiconductor layer 114 is provided on the upper surface, the lower surface and the outer peripheral surface of the insulating layer 113 .

Incidentally, in the XY cross section as illustrated in FIG. 8, the outer peripheral surface of the insulating layer 111 may be formed, for example, along a circle having the center position of the conductive layer 104 as the center. The side surfaces of the conductive layer 112, the insulating layer 113, and the semiconductor layer 114 on one side in the X direction (the conductive layer 102 side) may be formed along a circle centered on the center position of the conductive layer 104. Both side surfaces in the Y direction of the conductive layer 112 , the insulating layer 113 , and the semiconductor layer 114 may be formed linearly along the side surface of the insulating layer 115 .

The insulating layer 111 contains, for example, silicon oxide (SiO ₂ ). The insulating layer 111 surrounds the entire outer peripheral surface of the conductive layer 104 .

The conductive layer 112 functions, for example, as a gate electrode of the transistor TrC (FIG. 1). The conductive layer 112 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 112 surrounds the entire outer peripheral surface of the insulating layer 111 . As shown in FIG. 8, the plurality of conductive layers 112 arranged in the Y direction are commonly connected to the conductive layer 120 extending in the Y direction.

The insulating layer 113 functions, for example, as a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 113 contains, for example, silicon oxide (SiO ₂ ). The insulating layer 113 covers both side surfaces of the conductive layer 112 in the Y direction and one side surface in the X direction (the conductive layer 102 side).

The semiconductor layer 114 functions, for example, as a channel region of the transistor TrC (FIG. 1). The semiconductor layer 114 may be a semiconductor containing, for example, at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). However, other oxide semiconductors may be used. The semiconductor layer 114 covers both side surfaces in the Y direction and one side surface in the X direction (the conductive layer 102 side) of the conductive layer 112 with the insulating layer 113 interposed therebetween. As shown in FIG. 9, the plurality of semiconductor layers 114 aligned in the Z direction are commonly connected to the conductive layer 104 extending in the Z direction. As shown in FIG. 7, an insulating layer 115 such as silicon oxide (SiO ₂ ) is provided between two semiconductor layers 114 adjacent in the Y direction.

The conductive layer 120 functions, for example, as word lines WL (FIG. 1). The conductive layer 120 extends in the Y direction and is connected to a plurality of conductive layers 112 arranged in the Y direction, as shown in FIG. 8, for example. The conductive layer 120 has, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The upper and lower surfaces of the conductive layer 120 are covered with an insulating layer 121 such as silicon oxide (SiO ₂ ). The insulating layer 121 is connected to the insulating layers 111 and 113 .

For example, as shown in FIG. 9, the capacitor structure 130 includes a conductive layer 131, a conductive layer 132 provided on the upper surface, the lower surface, and the side surfaces of the conductive layer 131 in the Y direction, and the upper surface, the lower surface, and the Y direction side surfaces of the conductive layer 132. An insulating layer 133 provided on the side surface, a conductive layer 134 provided on the upper surface, the lower surface, and the side surface in the Y direction of the insulating layer 133, and an insulating layer 135 provided on the upper surface, the lower surface, and the side surface in the Y direction of the conductive layer 134. , a conductive layer 136 provided on the upper surface, the lower surface, and the side surfaces in the Y direction of the insulating layer 135, and a conductive layer 137 provided on the upper surface, the lower surface, and the side surfaces in the Y direction of the conductive layer 136.

Conductive layers 131, 132, 136 and 137 function as one electrode of capacitor CpC (FIG. 1). Conductive layers 131 and 137 contain, for example, tungsten (W). Conductive layers 132 and 136 include, for example, titanium nitride (TiN). Conductive layers 131 , 132 , 136 and 137 are connected to conductive layer 102 .

Insulating layers 133 and 135 function as insulating layers for capacitor CpC (FIG. 2). Insulating layers 133 and 135 may be, for example, alumina (Al ₂ O ₃ ) or other insulating metal oxides.

Conductive layer 134 functions, for example, as the other electrode of capacitor CpC (FIG. 2). Conductive layer 134 includes, for example, indium tin oxide (ITO). Conductive layer 134 is insulated from conductive layers 131 , 132 , 136 and 137 via insulating layers 133 and 135 . The conductive layer 134 is connected to the X-direction side surface of the semiconductor layer 114 .

In the transistor region _RTrL , for example, as shown in FIG. 6, a plurality of insulating layers 105 arranged in the X direction are provided. These insulating layers 105 extend in the Z direction through the memory layers ML0 to ML2 and the transistor layers TL.

The insulating layer 105 contains, for example, silicon oxide (SiO ₂ ).

A plurality of conductive layers 106 provided between the insulating layers 105 are provided in the transistor region _RTrL . The multiple conductive layers 106 are aligned in the X direction and extend in the Z direction through the multiple memory layers ML0 to ML2 and the transistor layer TL (see FIG. 10).

The conductive layer 106 includes, for example, a laminated structure of indium tin oxide (ITO), titanium nitride (TiN) and tungsten (W). The conductive layer 106 functions, for example, as word line selection lines LW (FIG. 1). A plurality of word line selection lines LW are provided corresponding to the plurality of transistors TrL included in the memory layers ML0 to ML2.

In the transistor region _RTrL , the memory layers ML0 to ML2 are, for example, as shown in FIG. and a conductive layer 150 extending in a direction.

For example, as shown in FIGS. 8 and 10, the transistor structure 140 includes an insulating layer 141 provided on the outer peripheral surface of the conductive layer 106, a conductive layer 142 provided on the outer peripheral surface of the insulating layer 141, and the conductive layer 142. An insulating layer 143 is provided on the upper surface, the lower surface and the outer peripheral surface, and a semiconductor layer 144 is provided on the upper surface, the lower surface and the outer peripheral surface of the insulating layer 143 .

Incidentally, in the XY cross section as illustrated in FIG. 8, the outer peripheral surface of the insulating layer 141 may be formed, for example, along a circle having the center position of the conductive layer 106 as the center. The side surfaces of the conductive layer 142, the insulating layer 143, and the semiconductor layer 144 on one Y-direction side (the conductive layer 120 side) may be formed along a circle centered on the center position of the conductive layer . Both side surfaces in the X direction of the conductive layer 142 , the insulating layer 143 , and the semiconductor layer 144 may be formed linearly along the side surface of the insulating layer 105 .

The insulating layer 141 contains, for example, silicon oxide (SiO ₂ ). The insulating layer 141 surrounds the entire outer peripheral surface of the conductive layer 106 .

The conductive layer 142 functions, for example, as a gate electrode of the transistor TrL (FIG. 1). The conductive layer 142 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 142 surrounds the entire outer peripheral surface of the insulating layer 141 . As shown in FIG. 8, the plurality of conductive layers 142 arranged in the X direction are commonly connected to the conductive layer 150 extending in the X direction.

The insulating layer 143 functions, for example, as a gate insulating film of the transistor TrL (FIG. 1). The insulating layer 143 contains, for example, silicon oxide (SiO ₂ ). The insulating layer 143 covers both side surfaces in the X direction and one side surface in the Y direction (the side of the conductive layer 120 ) of the conductive layer 142 .

The semiconductor layer 144 functions, for example, as a channel region of the transistor TrL (FIG. 1). The semiconductor layer 144 may be a semiconductor containing, for example, at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). However, other oxide semiconductors may be used. The semiconductor layer 144 covers both side surfaces in the X direction and one side surface in the Y direction (the conductive layer 120 side) of the conductive layer 142 with the insulating layer 143 interposed therebetween. As shown in FIG. 10, the plurality of semiconductor layers 144 aligned in the Z direction are commonly connected to the conductive layer 106 extending in the Z direction. As shown in FIG. 7, an insulating layer 105 is provided between two semiconductor layers 144 adjacent in the X direction. The semiconductor layer 144 is connected to the Y-direction end of the conductive layer 120 .

The conductive layer 150 functions, for example, as a layer selection line LL (FIG. 1). The conductive layer 150 extends in the X direction and is connected to a plurality of conductive layers 142 arranged in the X direction, as shown in FIG. 8, for example. The conductive layer 150 has, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The upper and lower surfaces of the conductive layer 150 are covered with an insulating layer 151 such as silicon oxide (SiO ₂ ). The insulating layer 151 is connected to the insulating layers 141 and 143 .

A plurality of contact electrodes 107 arranged in the X direction are provided in the hookup region _RHU . The contact electrode 107 extends in the Z direction and is connected to the conductive layer 150 at its lower end, as shown in FIG. A plurality of contact electrodes 107 arranged in the X direction are connected to conductive layers 150 provided at different height positions. The contact electrode 107 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

The transistor layer TL is configured similarly to the memory layers ML0 to ML2.

However, the conductive layer 112, the insulating layer 113, and the semiconductor layer 114 in the transistor layer TL function as the gate electrode, gate insulating film, and channel region of the transistor TrB, respectively. Also, the conductive layer 120 in the transistor layer TL functions as bit line selection lines LB0 to LB2. Further, the conductive layer 134 in the transistor layer TL functions as a source electrode of the transistor TrB.

A conductive layer 142, an insulating layer 143, and a semiconductor layer 144 in the transistor layer TL function as a gate electrode, a gate insulating film, and a channel region of the transistor TrT, respectively. Further, the conductive layer 150 in the transistor layer TL functions as the wiring LT.

A plurality of global bit lines GBL are provided below the transistor layer TL, as shown in FIG. The global bit lines GBL extend in the X direction and are arranged in the Y direction. Global bit line GBL includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

A plurality of contact electrodes 108 arranged in the X direction along the global bit lines GBL are provided in regions between the transistor layers TL and the global bit lines GBL. The plurality of contact electrodes 108 extend in the Z direction and are connected at their lower ends to the upper surfaces of the global bit lines GBL. Moreover, the upper end is connected to the lower surface of the conductive layer 134 in the transistor layer TL (see FIG. 9). The contact electrode 108 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

Also, as shown in FIG. 5, an etching stopper 109 is provided between the transistor layer TL and the plurality of global bit lines GBL. The etching stopper 109 is provided corresponding to the insulating layer 101, the conductive layer 102, the conductive layer 104, the insulating layer 105, and the conductive layer 106, and is connected to their lower ends. The etching stopper 109 has a shape that follows the shape of the lower end of the corresponding structure. For example, the etching stopper 109 corresponding to the insulating layer 101 extends in the Y direction corresponding to the insulating layer 101 . Similarly, the etching stopper 109 corresponding to the conductive layer 102 extends in the Y direction corresponding to the conductive layer 102 .

An insulating layer 103a is provided between the transistor layer TL and the etching stopper 109 (see FIG. 9). The insulating layer 103a may contain a material different from that of the other insulating layers 103, for example. For example, the insulating layer 103a may contain carbon-containing silicon oxide (SiOC) or the like.

[Production method]
12 to 66 are schematic cross-sectional views for explaining the method of manufacturing the semiconductor memory device according to the first embodiment. 13, 14, 16, 18, 20, 23, 25, 28, 30, 32, 34, 36, 38, 43, 45, 47, 49 , 51, 54, 58, 60, 61, 63 and 65 show cross sections corresponding to FIG. 12, 19, 21, 22, 29, 31, 33, 35, 37, 39 to 42, 44, 46, 48, 50, and 52 , a section corresponding to FIG. 15, 17, 24, 26, 27, 53, 55-57, 59, 62, 64 and 66 show cross sections corresponding to FIG.

In this manufacturing method, a plurality of global bit lines GBL, etching stoppers 109, insulating layers 103a, contact electrodes 108, etc. are formed as shown in FIG. 12, for example. This step is performed, for example, by photolithography, etching, or the like.

Next, for example, as shown in FIG. 12, a plurality of insulating layers 103 and a plurality of sacrificial layers 120A are alternately formed. The sacrificial layer 120A contains, for example, silicon nitride _{( Si3N4} ). This step is performed by, for example, CVD (Chemical Vapor Deposition).

Next, as shown in FIG. 13, for example, the plurality of insulating layers 103 and the plurality of sacrificial layers 120A are partially removed in the hookup region _RHU to form a stepped structure.

In this step, for example, a resist is formed on the upper surface of the structure as shown in FIG. 12 to expose a portion of the hookup region _RHU . Next, the sacrificial layer 120A is selectively removed by a method such as RIE (Reactive Ion Etching). Next, the insulating layer 103 is selectively removed by a method such as RIE. As a result, a portion of the upper surface of the second sacrificial layer 120A counted from above is exposed.

Next, a portion of the resist is removed by a method such as wet etching. Next, the sacrificial layer 120A is selectively removed by a method such as RIE. Next, the insulating layer 103 is selectively removed by a method such as RIE. As a result, portions of the upper surfaces of the second and third sacrificial layers 120A counted from above are exposed.

In the same manner, partial removal of the resist, selective removal of the sacrificial layer 120A, and selective removal of the insulating layer 103 are repeated. As a result, part of the upper surface of all the sacrificial layers 120A is exposed, forming a stepped structure. After forming the stepped structure, the insulating layer 103 is formed on the uppermost sacrificial layer 120A and the upper surface of the stepped structure.

Next, as shown in FIGS. 14 and 15, openings 115A and 105A are formed at positions corresponding to the insulating layers 115 and 105, respectively. The openings 115A and 105A extend in the Z direction as shown in FIG. expose. This step is performed by, for example, RIE.

Next, as shown in FIGS. 16 and 17, for example, insulating layers 115 and 105 are formed. This step is performed by, for example, CVD.

Next, as shown in FIGS. 18 and 19, for example, openings 104A are formed at positions corresponding to the conductive layers 104. Next, as shown in FIGS. As shown in FIG. 19, the opening 104A extends in the Z direction, penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 120A arranged in the Z direction, and the insulating layer 103a to expose the upper surface of the etching stopper 109. . This step is performed by, for example, RIE.

Next, as shown, for example, in FIGS. 20 and 21, a portion of the sacrificial layer 120A is selectively removed through the opening 104A. In this step, the Y-direction side surface of the insulating layer 115 is exposed inside the opening 104A, thereby dividing the sacrificial layer 120A in the X-direction. This step is performed, for example, by wet etching or the like.

Next, as shown in FIG. 22, for example, a sacrificial layer 104B is formed inside the opening 104A. The sacrificial layer 104B contains, for example, silicon (Si). This step is performed by, for example, CVD.

Next, as shown in FIGS. 23 and 24, an opening 106A is formed at a position corresponding to the conductive layer 106. Next, as shown in FIGS. As shown in FIG. 24, the opening 106A extends in the Z direction, penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 120A arranged in the Z direction, and the insulating layer 103a to expose the upper surface of the etching stopper 109. . This step is performed by, for example, RIE.

Next, as shown in FIGS. 25 and 26, for example, a portion of the sacrificial layer 120A is selectively removed through the opening 106A. In this step, the X-direction side surface of the insulating layer 105 is exposed inside the opening 106A, thereby dividing the sacrificial layer 120A in the Y-direction. This step is performed, for example, by wet etching or the like.

Next, as shown in FIG. 27, for example, a sacrificial layer 106B is formed inside the opening 106A. The sacrificial layer 106B contains, for example, silicon (Si). This step is performed by, for example, CVD.

Next, as shown in FIGS. 28 and 29, for example, openings 102A are formed at positions corresponding to the conductive layers 102. Next, as shown in FIGS. As shown in FIG. 29, the opening 102A extends in the Z direction, penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 120A arranged in the Z direction, and the insulating layer 103a, and divides these structures in the X direction. to expose the upper surface of the etching stopper 109 . This step is performed by, for example, RIE.

Next, as shown, for example, in FIGS. 30 and 31, a portion of the sacrificial layer 120A is selectively removed through the opening 102A. In this step, the X-direction side surface of the sacrificial layer 104B is exposed inside the opening 102A. This step is performed, for example, by wet etching or the like.

Next, for example, as shown in FIGS. 32 and 33, through the opening 102A, the X-direction side surface of the sacrificial layer 104B, the X-direction and Y-direction side surfaces of the insulating layer 115, and the insulating layer 103 (FIG. 33) are formed. A conductive layer 134 is formed on the top surface, the bottom surface, and the side surfaces in the X direction. Also, a sacrificial layer 102B is formed inside the opening 102A. The sacrificial layer 102B contains, for example, silicon (Si). In this step, for example, as shown in FIG. 33, a region between two insulating layers 103 adjacent in the Z direction is filled with a sacrificial layer 102B. On the other hand, the region between two insulating layers 103 adjacent in the X direction is not filled with the sacrificial layer 102B. This process is performed by, for example, ALD (Atomic Layer Deposition) and CVD.

Next, as shown, for example, in FIGS. 34 and 35, portions of the sacrificial layer 102B and the conductive layer 134 are removed through the opening 102A. In this step, for example, part of the sacrificial layer 102B is removed to expose portions of the conductive layer 134 provided on the X-direction side surfaces of the insulating layer 115 (FIG. 32) and the insulating layer 103 (FIG. 33). , remove this part. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 36 and 37, the sacrificial layer 102B, part of the insulating layer 115 (FIG. 34), and part of the insulating layer 103 (FIG. 35) are removed through the opening 102A. . In this step, sacrificial layer 102B is completely removed. Insulating layer 115 (FIG. 34) and insulating layer 103 (FIG. 35) are removed to such an extent that sacrificial layer 104B is not exposed in opening 102A. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 38 and 39, for example, insulating layers 133 and 135 and conductive layers 132 and 136 are formed on the upper surface, the lower surface, the side surfaces in the X direction and the side surfaces in the Y direction of the conductive layer 134 through the opening 102A. , and conductive layers 131 , 137 , 102 are formed. This step is performed by, for example, CVD.

Next, for example, as shown in FIG. 40, the sacrificial layer 104B is removed. This step is performed, for example, by wet etching or the like.

Next, as shown in FIG. 41, for example, through the opening 104A, the X-direction side surfaces of the sacrificial layer 120A and the conductive layer 134, the Y-direction side surface of the insulating layer 115, and the upper and lower surfaces of the insulating layer 103 are coated with A semiconductor layer 114 is formed. Also, a sacrificial layer 112A is formed in a region between two insulating layers 103 adjacent in the Z direction. In this step, for example, as shown in FIG. 41, a region between two insulating layers 103 adjacent in the Z direction is filled with a sacrificial layer 112A. On the other hand, the opening 104A is not filled with the sacrificial layer 112A. This step is performed by, for example, ALD and CVD.

Next, as shown in FIG. 42, for example, portions of the sacrificial layer 112A and the semiconductor layer 114 are removed through the opening 104A. In this step, for example, a portion of the sacrificial layer 112A is removed to expose a portion of the semiconductor layer 114 provided on the inner peripheral surface of the insulating layer 103, and this portion is removed. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 43 and 44, the conductive layer 104 is formed inside the opening 104A. This step is performed by, for example, ALD and CVD.

Next, an opening 101A is formed at a position corresponding to the insulating layer 101, as shown in FIGS. 45 and 46, for example. As shown in FIG. 46, the opening 101A extends in the Z direction, penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 120A arranged in the Z direction, and the insulating layer 103a, and divides these structures in the X direction. to expose the upper surface of the etching stopper 109 . This step is performed by, for example, RIE.

Next, as shown in FIGS. 47 and 48, the sacrificial layer 120A is removed through the opening 101A. This step is performed, for example, by wet etching or the like. In the drawing, the opening formed in the portion where the sacrificial layer 120A was provided is shown as an opening 120B.

Next, as shown, for example, in FIGS. 49 and 50, a portion of the semiconductor layer 114 is removed through the openings 101A and 120B to expose a portion of the sacrificial layer 112A. Also, the sacrificial layer 112A is removed through the openings 101A and 120B to expose the outer peripheral surface of the conductive layer 104. Next, as shown in FIG. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 51 and 52, for example, insulating layers 111, 113 and 121 are formed inside the opening 120B, and conductive layers 112 and 120 are formed. In this step, an insulating layer and a conductive layer are formed in the openings 101A and 120B by, for example, CVD. At this time, the opening 120B is filled with the conductive layer. On the other hand, the opening 101A is not filled with the conductive layer. Next, for example, by wet etching or the like, the portion of the insulating layer and the conductive layer provided on the inner peripheral surface of the insulating layer 103 is removed. After that, the insulating layer 101 is formed inside the opening 101A.

Next, for example, as shown in FIG. 53, the sacrificial layer 106B is removed. This step is performed, for example, by wet etching or the like.

Next, as shown, for example, in FIGS. 54 and 55, a portion of the insulating layer 113 is removed to expose a portion of the conductive layer 120 through the opening 106A. This step is performed, for example, by wet etching or the like.

Next, as shown in FIG. 56, for example, through the opening 106A, the side surfaces of the sacrificial layer 120A and the conductive layer 120 in the Y direction, the side surfaces of the insulating layers 105 and 115 in the X direction, and the upper surface of the insulating layer 103 are exposed. And a semiconductor layer 144 is formed on the lower surface. Also, a sacrificial layer 142A is formed in a region between two insulating layers 103 adjacent in the Z direction. In this step, the region between two insulating layers 103 adjacent in the Z direction is filled with the sacrificial layer 142A. On the other hand, opening 106A is not filled with sacrificial layer 142A. This step is performed by, for example, ALD and CVD.

Next, as shown in FIG. 57, for example, portions of the sacrificial layer 142A and the semiconductor layer 144 are removed through the opening 106A. In this step, for example, a portion of the sacrificial layer 142A is removed to expose a portion of the semiconductor layer 144 provided on the inner peripheral surface of the insulating layer 103, and this portion is removed. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 58 and 59, the conductive layer 106 is formed inside the opening 106A. This step is performed by ALD, CVD, or the like, for example.

Next, as shown in FIG. 60, for example, a plurality of openings op arranged in the X direction are formed in the hookup region _RHU . The opening op extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 120A arranged in the Z direction, as well as the insulating layer 103a, to expose the upper surface of the etching stopper 109 . This step is performed by, for example, RIE.

Next, as shown in FIGS. 61 and 62, the sacrificial layer 120A is removed through the opening op. This step is performed, for example, by wet etching or the like. In the drawing, the opening formed in the portion where the sacrificial layer 120A was provided is shown as an opening 150A.

Next, as shown in FIGS. 63 and 64, a portion of the semiconductor layer 144 is removed through the opening op 150A to expose a portion of the sacrificial layer 142A. Also, the sacrificial layer 142A is removed through the opening op 150A to expose the outer peripheral surface of the conductive layer 106. Next, as shown in FIG. This step is performed, for example, by wet etching or the like.

Next, as shown in FIGS. 65 and 66, insulating layers 141, 143 and 151 are formed in the opening 150A, and conductive layers 142 and 150 are formed. In this step, an insulating layer and a conductive layer are formed in the opening op 150A by, for example, CVD. At this time, the opening 150A is filled with the conductive layer. On the other hand, the opening op is not filled with the conductive layer. Next, for example, by wet etching or the like, the portion of the insulating layer and the conductive layer provided on the inner peripheral surface of the insulating layer 103 is removed. After that, an insulating layer is formed inside the opening op.

[effect]
As described with reference to FIG. 1, the semiconductor memory device according to the present embodiment includes a global bit line GBL, a plurality of bit lines BL electrically connected to the global bit line GBL, and an electric line between them. and a plurality of transistors TrB connected in series. Gate electrodes of these transistors TrB are connected to bit line selection lines LB0 to LB2 provided corresponding to word lines WL0 to WL2. According to such a configuration, for example, as described with reference to FIG. It is possible to electrically disconnect the line BL from the global bit line GBL. As a result, it is possible to reduce the capacitance of the global bit line GBL and speed up the operation of the semiconductor memory device.

Further, as described with reference to FIGS. 8 to 10, in the semiconductor memory device according to this embodiment, the semiconductor layer 114 faces the upper surface, the lower surface, and the side surface in the Y direction of the conductive layer 112, respectively. there is

In such a configuration, channels are formed in the portion of the semiconductor layer 114 facing the top surface of the conductive layer 112, the portion facing the bottom surface, and the portion facing the side surface in the Y direction. Therefore, it is possible to make the ON currents of the transistors TrC and TrB relatively large. This makes it possible to speed up and stabilize the operation.

Also, in such a configuration, two transistors TrC and TrB that are adjacent in the Z direction are adjacent to each other with their channel regions interposed therebetween. In such a configuration, for example, compared to a structure in which two transistors TrC and TrB that are adjacent in the Z direction are adjacent to each other with their gate electrodes interposed therebetween, the capacitance between the gate electrodes can be reduced. . This makes it possible to speed up and stabilize the operation.

Further, as described with reference to FIGS. 12 to 66, the transistor TrB according to this embodiment can be manufactured together with the transistor TrC in the memory cell MC. Therefore, it can be manufactured without substantially increasing the manufacturing cost.

[Second embodiment]
FIG. 67 is a schematic XZ sectional view showing the configuration of part of the semiconductor memory device according to the second embodiment.

In the semiconductor memory device according to the first embodiment, the transistor layer TL is configured similarly to the memory layers ML0 to ML2. For example, in the first embodiment, the conductive layer 134 is provided not only on the memory layers ML0 to ML2 but also on the transistor layer TL. Also, this conductive layer 134 functioned as the source electrode of the transistor TrB. Also, the lower surface of this conductive layer 134 was connected to the contact electrode 108 .

However, such a configuration is merely an example, and the structure of the transistor layer TL can be adjusted as appropriate.

For example, the semiconductor memory device according to the second embodiment has substantially the same configuration as the semiconductor memory device according to the first embodiment. However, in the second embodiment, the conductive layer 134 is not provided in the transistor layer TL, as shown in FIG. 67, for example. Further, in the second embodiment, a semiconductor layer 214 is provided in the transistor layer TL instead of the semiconductor layer 114 . The semiconductor layer 214 is basically configured similarly to the semiconductor layer 114 . However, the side surface of the semiconductor layer 214 on the side of the conductive layer 102 in the X direction is connected not to the conductive layer 134 but to a part of the outer peripheral surface of the contact electrode 208 . The contact electrode 208 is configured in substantially the same manner as the contact electrode 108 .

[Production method]
68 to 74 are schematic cross-sectional views for explaining the method of manufacturing the semiconductor memory device according to the second embodiment. 68-74 show cross sections corresponding to FIG.

In this manufacturing method, a plurality of global bit lines GBL, an etching stopper 109, an insulating layer 103a and the like are formed as shown in FIG. 68, for example. This step is performed, for example, by photolithography, etching, or the like.

Next, for example, as shown in FIG. 69, one sacrificial layer 120A is formed. This step is performed by, for example, CVD.

Next, for example, as shown in FIG. 70, part of the sacrificial layer 120A is removed in the vicinity of the region corresponding to the conductive layer 102. Then, as shown in FIG. This step is performed, for example, by wet etching or the like.

Next, as shown in FIG. 71, for example, an insulating layer 103a is formed in the region from which the sacrificial layer 120A has been removed. This step is performed by, for example, CVD.

Next, as shown in FIG. 72, for example, openings 208A are formed at positions corresponding to the contact electrodes 208. Next, as shown in FIG. The opening 208A extends in the Z direction as shown in FIG. 72 and exposes the upper surface of the global bit line GBL. This step is performed by, for example, RIE.

Next, as shown in FIG. 73, for example, contact electrodes 208 are formed. This step is performed by, for example, CVD.

Next, for example, as shown in FIG. 74, a plurality of insulating layers 103 and a plurality of sacrificial layers 120A are alternately formed. This step is performed by, for example, CVD.

After that, among the manufacturing steps of the semiconductor memory device according to the first embodiment, the steps after the step described with reference to FIG. 13 are performed.

[Other embodiments]
The semiconductor memory devices according to the first embodiment and the second embodiment have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and specific configurations, operations, and the like can be adjusted as appropriate.

For example, in the semiconductor memory devices according to the first and second embodiments, the global bit lines GBL are provided below the memory layers ML0 to ML2. However, such a configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, as shown in FIG. 75, the global bit lines GBL may be provided above the memory layers ML0 to ML2. In such a case, the transistor layers TL and the contact electrodes 108 may also be provided above the memory layers ML0 to ML2. Also, in this case, the contact electrode 108 may be connected to the lower surface of the global bit line GBL at its upper end. Further, the lower end may be connected to the upper surface of the conductive layer 134 in the transistor layer TL.

As described above, in the semiconductor memory devices according to the first and second embodiments, the sense amplifier circuit is provided in the region immediately below the memory cell array MCA on the upper surface of the semiconductor substrate Sub. In such a configuration, by providing the global bit lines GBL below the memory layers ML0 to ML2, the wiring capacity between the sense amplifier circuit and the memory layers ML0 to ML2 can be reduced, and the read operation and the like can be performed at high speed. It is possible to Similarly, for example, in the case where the sense amplifier circuits are provided above the memory cell array MCA, by providing the global bit lines GBL above the memory layers ML0 to ML2, the sense amplifier circuits and the memory layers ML0 to ML2 are separated from each other. It is possible to reduce the wiring capacity between and to perform read operations and the like at high speed. For example, when the memory cell array MCA and the sense amplifier circuit are formed on different substrates and these two substrates are bonded together, the sense amplifier circuit may be provided above the memory cell array MCA.

Also, in the above description, a structure is adopted in which two transistors TrC and TrB that are adjacent in the Z direction are adjacent to each other with their channel regions interposed therebetween. However, for example, a structure may be adopted in which two transistors TrC and TrB that are adjacent in the Z direction are adjacent to each other with their gate electrodes interposed therebetween.

Also, in the above description, an example in which the capacitor CpC is employed as the memory unit connected to the transistor structure 110 has been described. However, the memory unit does not have to be the capacitor CpC. For example, the memory section may include ferroelectrics, ferromagnets, chalcogen materials such as GeSbTe, or other materials, and record data using the properties of these materials. For example, in any of the structures described above, any of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[others]
While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

Sub... Semiconductor substrate ML0 to ML2... Memory layer TL... Transistor layer BL... Bit line WL... Word line PL... Plate line TrC, TrB, TrL, TrT... Transistor 102... Conductive layer 104... Conductive Layers 110...Transistor structure 120...Conductive layer 130...Capacitor structure 140...Transistor structure 150...Conductive layer.

Claims (19)

a substrate;
a plurality of memory layers arranged in a first direction intersecting the surface of the substrate;
a first wiring provided at a position closer to the substrate than the plurality of memory layers or at a position farther from the substrate than the plurality of memory layers;
a transistor layer provided between the plurality of memory layers and the first wiring;
a second wiring extending in the first direction and connected to the plurality of memory layers and the transistor layer;
Each of the plurality of memory layers includes:
a memory unit;
a first semiconductor layer electrically connected between the memory section and the second wiring;
a first electrode facing the first semiconductor layer;
a third wiring extending in a second direction intersecting the first direction and connected to the first electrode;
a second semiconductor layer connected to one end of the third wiring in the second direction;
a second electrode facing the second semiconductor layer,
The transistor layer is
a third semiconductor layer electrically connected between the first wiring and the second wiring;
and a third electrode facing the third semiconductor layer. Each of the plurality of memory layers includes:
a fourth semiconductor layer connected to the other end of the third wiring in the second direction;
2. The semiconductor memory device according to claim 1, further comprising a fourth electrode facing said fourth semiconductor layer. The transistor layer is
a fourth wiring extending in the second direction and connected to the third electrode;
a fifth semiconductor layer connected to one end of the fourth wiring in the second direction;
3. The semiconductor memory device according to claim 1, further comprising a fifth electrode facing said fifth semiconductor layer. The transistor layer is
a sixth semiconductor layer connected to the other end of the fourth wiring in the second direction;
4. The semiconductor memory device according to claim 3, further comprising: a sixth electrode facing said sixth semiconductor layer. 5. The semiconductor memory device according to claim 1, wherein said memory section is a capacitor. 6. The semiconductor memory device according to claim 1, wherein said first semiconductor layer and said third semiconductor layer each contain an oxide semiconductor. The first semiconductor layer and the third semiconductor layer each include at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). 7. The semiconductor memory device according to claim 1, comprising: a substrate;
a plurality of memory layers arranged in a first direction intersecting the surface of the substrate;
a first wiring provided at a position closer to the substrate than the plurality of memory layers or at a position farther from the substrate than the plurality of memory layers;
a transistor layer provided between the plurality of memory layers and the first wiring;
a second wiring extending in the first direction and connected to the plurality of memory layers;
a third wiring extending in the first direction and connected to the plurality of memory layers and the transistor layer;
Each of the plurality of memory layers includes:
a first electrode facing the second wiring;
a first semiconductor layer electrically connected between the first electrode and the third wiring;
a second electrode facing the first semiconductor layer,
The transistor layer is
a third electrode provided at a position overlapping with the first electrode when viewed from the first direction and electrically connected to the first wiring;
a second semiconductor layer electrically connected between the third electrode and the third wiring;
and a fourth electrode facing the second semiconductor layer. 9. The semiconductor memory device according to claim 8, wherein said third electrode faces said second wiring. A contact electrode extending in the first direction,
one end of the contact electrode in the first direction is connected to the first wiring;
10. The semiconductor memory device according to claim 8, wherein the other end of said contact electrode in said first direction is connected to one surface of said third electrode in said first direction. 11. The semiconductor memory device according to claim 8, wherein said first semiconductor layer and said second semiconductor layer each contain an oxide semiconductor. The first semiconductor layer and the second semiconductor layer each include at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). 12. The semiconductor memory device according to claim 8, comprising: a substrate;
a plurality of memory layers arranged in a first direction intersecting the surface of the substrate;
a first wiring provided at a position closer to the substrate than the plurality of memory layers or at a position farther from the substrate than the plurality of memory layers;
a transistor layer provided between the plurality of memory layers and the first wiring;
a second wiring extending in the first direction and connected to the plurality of memory layers and the transistor layer;
Each of the plurality of memory layers includes:
a memory unit;
a first semiconductor layer electrically connected between the memory section and the second wiring;
a first electrode facing the first semiconductor layer,
The transistor layer is
a second semiconductor layer electrically connected between the first wiring and the second wiring;
a second electrode facing the second semiconductor layer,
The second semiconductor layer faces one side and the other side of the second electrode in the first direction. A semiconductor memory device. 14. The semiconductor memory device according to claim 13, wherein the first semiconductor layer faces one side and the other side of the first electrode in the first direction. If a cross section that is perpendicular to the first direction and includes a part of one of the plurality of first semiconductor layers is defined as a first cross section,
13. In the first cross section, one of the plurality of first semiconductor layers faces one side surface and the other side surface of the first electrode in a second direction intersecting with the first direction. 15. The semiconductor memory device according to 14. If a cross section that is perpendicular to the first direction and includes a part of one of the second semiconductor layers is defined as a second cross section,
13. In the second cross section, one of the plurality of second semiconductor layers faces one side surface and the other side surface of the second electrode in a second direction intersecting the first direction. 16. The semiconductor memory device according to any one of items 1 to 15. 17. The semiconductor memory device according to claim 13, wherein said memory section is a capacitor. 18. The semiconductor memory device according to claim 13, wherein said first semiconductor layer and said second semiconductor layer each contain an oxide semiconductor. The first semiconductor layer and the second semiconductor layer each include at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). 19. The semiconductor memory device according to claim 13, comprising:

Images