JP2023000583A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device with a trench gate structure that can average the amount of recesses in polysilicon for forming a gate electrode, and can reduce a variation in threshold voltage Vth.SOLUTION: In etching back a polysilicon film 20 to form a gate electrode 8, ion injection is performed on the polysilicon film 20 to form a doped polysilicon layer 20a, thereby increasing an etching rate. This can reduce time difference until the completion of removal of the doped polysilicon layer 20a even if the center and an outer edge part of a wafer have a difference in etching rate. Consequently, the cause of a variation in the amount of recesses due to the difference in etching rate can be limited to the influence of the difference in etching rate when a non-doped polysilicon layer 20b that is already reduced in thickness is removed, and the variation in the amount of recesses can be reduced between the center and the outer edge part of the wafer.SELECTED DRAWING: Figure 5

Description

The present invention relates to a method of manufacturing a semiconductor device having a semiconductor element with a trench gate structure made of a semiconductor material such as silicon carbide (hereinafter referred to as SiC).

2. Description of the Related Art Conventionally, a semiconductor device having a trench gate structure is known as a structure in which a channel density is increased so that a large current can flow. In this semiconductor device, after forming a gate trench from the surface of a semiconductor layer, the inner wall surface of the gate trench is covered with a gate insulating film, then a polysilicon film is formed to form a gate electrode, and then the polysilicon is etched back. This forms a trench gate structure. Then, etching back is performed so that the polysilicon remains only in the gate trenches to form a recess shape in which the polysilicon surface is recessed from the semiconductor layer surface, and the gate trench entrance side is covered with an interlayer insulating film to close the lid. (See, for example, Patent Document 1).

JP 2019-3967 A

However, when etching back the polysilicon for forming the gate electrode to form a recess shape, the etching rate differs between the wafer center and the outer edge, and it is difficult to control the recess amount uniformly within the wafer surface. is. Variations in the recess depth cause variations in the threshold voltage Vth of the semiconductor element with the trench gate structure, making it impossible to manufacture semiconductor devices that satisfy the required specifications between wafers or between lots, resulting in a drop in yield. There is a problem of connecting to

In view of the above points, the present invention provides a method of manufacturing a semiconductor device having a trench gate structure, which can equalize the recess amount of polysilicon for forming a gate electrode and suppress variations in the threshold voltage Vth. intended to

In order to achieve the above object, the invention according to claim 1 is a method of manufacturing a semiconductor device having a semiconductor element of trench gate structure, comprising: Preparing a structure in which a first conductivity type drift layer (2) having an impurity concentration lower than that of a semiconductor layer is formed, and forming a second conductivity type channel layer (3) on the drift layer. forming a first conductivity type region (4) having a first conductivity type impurity concentration higher than that of the drift layer on the channel layer; and forming a gate trench (6) penetrating the first conductivity type region and the channel layer. ), forming a gate insulating film (7) covering the inner wall surface of the gate trench, forming a gate electrode (8) on the gate insulating film, and forming a gate electrode in the gate trench. forming a covering interlayer insulating film (9); forming a first electrode (10) electrically connected to the first conductivity type region; and forming a second electrode (11) on the back side of the semiconductor layer. including forming. Forming the gate electrode involves forming a polysilicon film (20) on the surface of the gate insulating film so as to fill the inside of the gate trench, and forming a polysilicon film with a thickness greater than the thickness of the polysilicon film. By performing ion implantation in a short range, a non-doped polysilicon layer (20b) is formed under the doped polysilicon layer (20a) while forming the doped polysilicon layer (20a) where the ion implantation is performed. and etching back the doped polysilicon layer and etching back the non-doped polysilicon layer until the top surface is lower than the surface of the first conductivity type region.

As described above, when the gate electrode is formed by etching back the polysilicon film, the etching rate is increased by ion-implanting the polysilicon film to form a doped polysilicon layer. Therefore, even if there is a difference in etching rate between the center and the outer edge of the wafer, the time difference until the removal of the doped polysilicon layer is completed can be reduced. Therefore, the variation in recess depth due to the difference in etching rate can be limited to the effect of the difference in etching rate when removing the already thin non-doped polysilicon layer, and the recess depth between the center and the outer edge of the wafer can be limited. Variation can be reduced. As a result, the recess amount of polysilicon for forming the gate electrode can be made uniform, and variations in the threshold voltage Vth can be suppressed.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment; FIG. It is a figure which showed the manufacturing process of the conventional semiconductor device. FIG. 4 is a cross-sectional view showing the state after etching back of the polysilicon film at the outer edge position (1) and the central position (2) of the wafer, respectively; 4 is a top view of a wafer showing measurement positions of the cross section shown in FIG. 3; FIG. 4A to 4C are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment; FIG. 4 is a cross-sectional view showing a state when the inside of the gate trench is filled with a polysilicon film; FIG. 10 is a cross-sectional view showing a state in which a void is generated in the central portion of the gate trench after etching back; It is a sectional view showing a manufacturing process of a semiconductor device concerning a 2nd embodiment. 10 is a flow chart showing manufacturing steps of a semiconductor device according to a third embodiment;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. A semiconductor device manufactured by the manufacturing method according to this embodiment will be described. Here, a SiC semiconductor device in which a MOSFET is formed as a semiconductor element having a trench gate structure will be described as an example.

A SiC semiconductor device manufactured by the manufacturing method according to the present embodiment includes a vertical MOSFET having a trench gate structure shown in FIG. A vertical MOSFET is formed in a cell region of a SiC semiconductor device, and the SiC semiconductor device is configured by forming an outer peripheral breakdown voltage structure so as to surround the cell region. Only the vertical MOSFET is shown. In the following description, the horizontal direction in FIG. 1 is the width direction of the SiC semiconductor device, and the vertical direction is the thickness direction or depth direction of the SiC semiconductor device.

An SiC semiconductor device uses an n ⁺ -type substrate 1 made of SiC as a semiconductor substrate. An n ⁻ -type drift layer 2 made of SiC is epitaxially grown on the main surface of the n ⁺ -type substrate 1. On the n ⁻ -type drift layer 2, a p-type base region 3 corresponding to a channel layer and a first An n ⁺ -type source region 4 corresponding to a conductivity type region is formed in sequence.

The p-type base region 3 is a portion where a channel region is formed, and is a p-type contact region in which the p-type impurity concentration is partially increased in a surface layer portion at a position different from the location where the n ⁺ -type source region 4 is arranged. 3a is formed. The n ⁺ -type source region 4 has a higher impurity concentration than the n ⁻ -type drift layer 2 .

A gate trench 6 is formed to penetrate through the p-type base region 3 and the n ⁺ -type source region 4 and reach the n ⁻ -type drift layer 2 . The p-type base region 3 and the n ⁺ -type source region 4 are arranged so as to be in contact with the side surfaces of the gate trench 6 . The width direction of the gate trench 6 is the horizontal direction of the paper surface of FIG. 1, which is the width direction of the SiC semiconductor device, the longitudinal direction is the normal direction of the paper surface, and the vertical direction of the paper surface of FIG. 1, which is the thickness direction of the SiC semiconductor device, is the depth direction. It is formed in a line-shaped layout. Although only one trench is shown in FIG. 1, a plurality of gate trenches 6 are arranged in the horizontal direction of the paper at regular intervals to form a stripe shape.

A portion of the p-type base region 3 located on the side surface of the gate trench 6 serves as a channel region connecting the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2 during operation of the vertical MOSFET. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region. A gate electrode 8 made of doped polysilicon is formed on the surface of the gate insulating film 7 . The gate electrode 8 is n-type doped or p-type doped. An interlayer insulating film 9 is formed on the gate insulating film 7 and the gate electrode 8 to fill the inside of the gate trench 6, thereby forming a trench gate structure.

More specifically, the upper surface of the gate electrode 8 is lower than the upper surface of the n ⁺ -type source region 4 forming the entrance of the gate trench 6, and a step is formed between them to recess the gate electrode 8. It has a recessed shape. The inside of the gate trench 6 is filled by arranging the interlayer insulating film 9 in the recess shape so as to fill the step.

A source electrode 10 corresponding to a first electrode, a gate wiring layer (not shown), and the like are formed on the interlayer insulating film 9 . Source electrode 10 is brought into contact with contact regions of n ⁺ -type source region 4 and p-type base region 3 through contact holes in interlayer insulating film 9 . The gate wiring layer is brought into contact with the gate electrode 8 in a cross section different from that in FIG.

Furthermore, a drain electrode 11 corresponding to a second electrode electrically connected to the n ⁺ -type substrate 1 is formed on the back side of the n ⁺ -type substrate 1 . With such a structure, a vertical MOSFET having an n-channel type inverted trench gate structure is formed. A cell region is configured by arranging a plurality of cells of such vertical MOSFETs. A SiC semiconductor device is constructed by constructing a peripheral breakdown voltage structure, such as a guard ring (not shown), so as to surround the cell region in which such a vertical MOSFET is formed.

Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described. However, in the method of manufacturing the SiC semiconductor device of the present embodiment, the steps other than the step of forming the gate electrode 8 may be performed by any known steps. This will be mainly described, and the other steps will be briefly described.

First, a wafer-shaped n ⁺ -type substrate 1 made of SiC is prepared as a semiconductor substrate, and then an n ⁻ -type drift layer 2 is epitaxially grown on the main surface of the n ⁺ -type substrate 1 . Then, after forming a p-type base region 3 and an n ⁺ -type source region 4 on the n ⁻ -type drift layer 2 by epitaxial growth or ion implantation, a mask (not shown) is formed on the surface of the n ⁺ -type source region 4, A p-type impurity is ion-implanted to form a p-type contact region 3a. Subsequently, a mask (not shown) is placed on the surfaces of the p-type base region 3 and the n ⁺ -type source region 4, and a trench gate structure forming region of the mask is opened. Thereafter, gate trenches 6 are formed by performing anisotropic etching such as RIE (Reactive Ion Etching) using a mask. Then, after removing the mask, the gate insulating film 7 is formed by, for example, CVD (chemical vapor deposition) or thermal oxidation, and then the step of forming the gate electrode 8 is performed.

Here, conventionally, the formation of the gate electrode 8 was performed by each step shown in FIG. Specifically, as in step (a) of FIG. 2, a polysilicon film 20 is formed on the surface of the gate insulating film 7 so as to fill the inside of the gate trench 6, and then, as in step (b), the gate is formed. Polysilicon film 20 is etched back so as to form a recess in trench 6 . Then, as shown in step (c), a mask 21 having openings at positions where the polysilicon film 20 is left is placed, and impurities are doped into the polysilicon film 20 from above the mask 21 . Thereby, the gate electrode 8 is formed.

However, when the gate electrode 8 is formed by such a process, the recess amount varies due to the difference in etching rate between the center and the outer edge of the wafer, as described above. FIG. 3 shows the state after etching back of the polysilicon film 20 at the outer edge position (1) and the central position (2) of the wafer 100 as shown in FIG. As shown in FIG. 3, it can be seen that there is a difference in the height of the step between the upper surface of the n ⁺ -type source region 4 and the upper surface of the gate electrode 8 between the position (1) and the position (2). . This difference causes variations in the threshold voltage Vth of the vertical MOSFET. This means that SiC semiconductor devices satisfying the required specifications cannot be manufactured between wafers or between lots.

Therefore, in this embodiment, the formation of the gate electrode 8 is performed by each process shown in FIG. Specifically, as in step (a) of FIG. 5, after forming a polysilicon film 20 on the surface of the gate insulating film 7 formed in the gate trench 6 or the like, as in step (b), ion An implantation process is performed to dope the polysilicon film 20 with ions. The ions to be doped at this time are ions capable of increasing the etching rate of the polysilicon film 20 compared to the case of not being implanted. can be used, C (carbon), Ar (argon), etc. can also be used. Also, the range of the ion implantation is set to be shorter than the thickness of the polysilicon film 20 from the surface of the polysilicon film 20 by a predetermined length. If the thickness of the polysilicon film 20 is about 1 .mu.m, the ions are implanted to a depth shorter than the thickness by a predetermined length, for example, 0.5 .mu.m. As a result, a doped polysilicon layer 20a into which ions are implanted in the polysilicon film 20 is formed, and a non-doped polysilicon layer 20b is formed thereunder. Become.

Subsequently, as shown in step (c), the polysilicon film 20 is etched back. At this time, since the doped polysilicon layer 20a is damaged by the ion implantation, the etching rate becomes higher than that of the non-doped polysilicon layer 20b. Therefore, the doped polysilicon layer 20a is quickly removed at both the center and the outer edge of the wafer, and the etching rate is greatly reduced when the non-doped polysilicon layer 20b is reached. Then, the non-doped polysilicon layer 20b is etched back at a slow etching rate.

Here, since the etching rate differs between the wafer center and the outer edge as described above, the recess amount may vary when the polysilicon film 20 is etched back. However, since the doped polysilicon layer 20a is removed at a high etching rate, even if there is a difference in etching rate between the center and the outer edge of the wafer, the difference in time until removal is completed is not large. Therefore, the difference in etching rate when etching back the non-doped polysilicon layer 20b affects the variation in the recess amount. The film thickness of 20b is thin. Therefore, compared with the case where the film thickness to be etched back is thick, the influence of the difference in etching rate is limited, and the variation in the recess amount between the center and the outer edge of the wafer can be reduced. As a result, the recess amount of polysilicon for forming the gate electrode 8 can be made uniform, and variations in the threshold voltage Vth can be suppressed.

Thereafter, as shown in step (d), a mask 21 having openings corresponding to the gate electrode 8 is placed, and then impurity ions are implanted to complete the gate electrode 8 made of doped polysilicon. do.

Further, after forming an interlayer insulating film 9 by CVD or the like, the interlayer insulating film 9 is patterned to remove unnecessary portions so that the interlayer insulating film 9 remains in the gate trenches 6 . Note that the interlayer insulating film 9 is left only in the gate trenches 6 in the cell area, but is left in the peripheral area and the like. In the cell region, the interlayer insulating film 9 is removed to expose the n ⁺ -type source region 4 and the p-type contact region 3a to form contact holes.

Although the subsequent steps are not shown, the source electrode 10 is formed by forming a film of an electrode material on the surface of the interlayer insulating film 9 and then patterning it. Further, steps such as forming a drain electrode 11 on the back side of the n ⁺ -type substrate 1 are performed. Thereby, the SiC semiconductor device having the vertical MOSFET according to the present embodiment shown in FIG. 1 is completed.

As described above, in this embodiment, when the polysilicon film 20 is etched back to form the gate electrode 8, ions are implanted into the polysilicon film 20 to form the doped polysilicon layer 20a. This increases the etching rate. Therefore, even if there is a difference in etching rate between the center and the outer edge of the wafer, the time difference until the removal of the doped polysilicon layer 20a is completed can be reduced. Therefore, the variation in the recess amount due to the etching rate difference can be limited to the effect of the etching rate difference when removing the already thin non-doped polysilicon layer 20b, and the recess amount between the center and the outer edge of the wafer. variation can be reduced. As a result, the recess amount of polysilicon for forming the gate electrode 8 can be made uniform, and variations in the threshold voltage Vth can be suppressed.

Furthermore, in the method of manufacturing the SiC semiconductor device of the present embodiment, when forming the doped polysilicon layer 20a on the polysilicon film 20, the non-doped polysilicon layer 20b is formed in a predetermined range based on the range of ion implantation. It is made to remain thick. Therefore, the SiC surface and the gate insulating film 7 can be prevented from being implanted with ions, and the occurrence of damage due to the ion implantation can be suppressed.

(Second embodiment)
A second embodiment will be described. This embodiment is different from the first embodiment in the method of ion implantation, and is otherwise the same as the first embodiment, so only the differences from the first embodiment will be described.

As shown in FIG. 6, when the polysilicon film 20 is formed, a depression may remain at a position corresponding to the gate trench 6 on the surface of the polysilicon film 20 due to the influence of the depression of the gate trench 6 . . That is, the polysilicon film 20 is formed uniformly on the bottom and side surfaces of the gate trench 6, fills the inside of the gate trench 6, and then forms a film on it. The thickness becomes thin, and the recesses described above tend to remain. If a depression remains at a position corresponding to the gate trench 6 when the polysilicon film 20 is etched back, the depression will remain at the central portion of the gate electrode 8 . Depending on the film thickness variation of the polysilicon film 20, as shown in FIG. If such a cavity 20d is generated, the interlayer insulation film 9 enters the cavity 20d when the interlayer insulation film 9 is formed in a later process. Further, when the heat treatment process is performed, the interlayer insulating film 9 in the cavity 20d thermally expands and stress is applied, which causes gate leak failure. In such a case, it also leads to a decrease in the non-defective product rate.

Therefore, in the present embodiment, when forming the doped polysilicon layer 20a, oblique ion implantation is performed so that the ion implantation direction is oblique to the normal direction of the SiC surface. Specifically, the formation of the gate electrode 8 is performed by each step shown in FIG.

First, as shown in step (a) of FIG. 8, a polysilicon film 20 is formed on the surface of the gate insulating film 7 formed in the gate trench 6 or the like. At this time, a depression 20c may remain at a position corresponding to the gate trench 6 on the surface of the polysilicon film 20, as shown in the drawing.

Next, as in step (b), an ion implantation step is performed, and ions are doped into the polysilicon film 20 by performing oblique ion implantation. Oblique ion implantation can be realized by inclining the sample with respect to the direction of ion implantation. More specifically, ion implantation is performed by tilting the sample with respect to the direction of ion implantation, and then ion implantation is performed by tilting the sample in the opposite direction at the same angle, thereby performing oblique ion implantation. At this time, the ions implanted into the depression 20c are implanted to a position deeper than the portion not forming the depression 20c by the depth of the depression 20c. However, by performing the oblique ion implantation, it is possible to shift the position where ions are most deeply implanted from the central portion of the gate trench 6 .

At this time, the inclination angle θ of the oblique ion implantation, that is, the angle formed with respect to the normal to the SiC surface is arbitrary, but it is preferable that the position where the ions are implanted to the deepest extent is outside the gate trench 6 . It is preferable to set the angle to The position where ions are implanted to the deepest point can be controlled based on the tilt angle θ of the oblique ion implantation and the range of the ion implantation. Therefore, by adjusting the tilt angle θ of the oblique ion implantation in consideration of the ion implantation range, the position where the ions are most deeply implanted can be outside the gate trench 6 .

Subsequently, as shown in step (c), the polysilicon film 20 is etched back. At this time as well, since the doped polysilicon layer 20a has a high etching rate, it is removed quickly at both the center and the outer edge of the wafer, and when the non-doped polysilicon layer 20b is reached, the etching rate increases. significantly slower. Then, the non-doped polysilicon layer 20b is etched back at a slow etching rate. As a result, as in the first embodiment, the effect of the difference in etching rate is limited, and variations in the recess amount between the center and the outer edge of the wafer can be reduced. Therefore, the recess amount of polysilicon for forming the gate electrode 8 can be made uniform, and variations in the threshold voltage Vth can be suppressed.

Thereafter, as shown in step (d), a mask 21 having openings corresponding to the gate electrodes 8 is placed, and then impurity ions are implanted to form the gate electrodes 8 made of doped polysilicon. Complete.

As described above, in the present embodiment, when forming the doped polysilicon layer 20a on the polysilicon film 20, the oblique ion implantation is performed. Therefore, when the recess 20c is formed, the position where the ions are implanted to the deepest position can be shifted from the central portion of the gate trench 6. Next, as shown in FIG. At the position where the ions are implanted to the deepest point, the shape of the recess 20c remains even after the polysilicon film 20 is etched back. However, since the portion where the depression remains can be located outside the central portion of the gate trench 6, the non-doped polysilicon layer 20b can be etched back without the depression in the central portion of the gate trench 6. FIG. Therefore, it is possible to suppress the generation of a cavity 20d called "seam" or "su" in the central portion of the gate trench 6. FIG. In particular, if the position where the ions are most deeply implanted is outside the gate trench 6, it is possible to prevent the recess from remaining in the gate trench 6 and further suppress the generation of the cavity 20d. Since the generation of the cavity 20d can be suppressed, the inter-layer insulating film 9 can be prevented from entering the cavity 20d in the subsequent process, and the occurrence of the gate leak can be suppressed. Therefore, it is possible to suppress a decrease in the non-defective product rate.

(Third embodiment)
A third embodiment will be described. This embodiment defines the ion implantation depth with respect to the first and second embodiments, and is otherwise the same as the first and second embodiments. Only different parts will be explained.

In the first and second embodiments, the range of ion implantation is determined in advance corresponding to the assumed film thickness of the polysilicon film 20, and then the ions for forming the doped polysilicon layer 20a are used. Doing the injection process. However, the film thickness of the polysilicon film 20 is not always constant. Therefore, in this embodiment, the range of ion implantation is adjusted according to the film thickness of the polysilicon film 20 .

Specifically, the process according to the flowchart shown in FIG. 9 is performed during the step of forming the gate electrode 8 . First, the polysilicon film 20 is formed in step S100, and then the film thickness of the polysilicon film 20 is measured in step S110. Any method may be used to measure the film thickness of the polysilicon film 20. For example, a film thickness measuring device based on spectroscopy may be used.

After an ion implantation step is performed as step S120, the polysilicon film 20 is etched back as step S130. At this time, in the ion implantation step of step S120, the film thickness data measured in step S110 is fed back to adjust the ion implantation conditions, specifically the acceleration voltage, and control the ion implantation range. This makes it possible to keep the thickness of the non-doped polysilicon layer 20b remaining on the SiC surface constant.

In this manner, even if the film thickness of the polysilicon film 20 differs between wafers and lots, after removing the doped polysilicon layer 20a, the non-doped polysilicon layer 20b having a constant thickness is etched. By controlling the back, the recess amount can be made constant. Since the etching rate of doped polysilicon layer 20a is high, the etchback time for removing doped polysilicon layer 20a is short. That is, even if the thickness of the doped polysilicon layer 20a is changed by adjusting the acceleration voltage during ion implantation, the difference in etchback time of the doped polysilicon layer 20a is small. Therefore, the etch-back time of the polysilicon film 20 can be roughly considered as the etch-back time of the non-doped polysilicon layer 20b. Therefore, if the thickness of the non-doped polysilicon layer 20b is constant, even if the thickness of the polysilicon film 20 is different, the difference in the etching back time of the entire polysilicon film 20 is small, and the variation in the recess amount is reduced. It can be made more uniform.

As described above, the thickness of the non-doped polysilicon layer 20b is set at a constant value by adjusting the acceleration voltage for ion implantation when forming the doped polysilicon layer 20a based on the film thickness measurement result of the polysilicon film 20. . As a result, the recess amount can be made more uniform, and variations in the threshold voltage Vth can be suppressed.

(Other embodiments)
Although the present disclosure has been described based on the above embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

(1) For example, in each of the above embodiments, only the case of using the polysilicon film 20 to form the gate electrode 8 in the trench gate structure was explained, but the same polysilicon film 20 may be used to form other things. be. For example, the polysilicon film 20 may be used to form a PN diode for temperature sensing. In this case, before etching back the polysilicon film 20, a mask is formed in the polysilicon film 20 by photolithography so as to cover the position where the PN diode is to be formed. Then, the polysilicon film 20 is etched back while the position where the PN diode is to be formed is covered with a mask. In this way, when forming other objects using the polysilicon film 20, it is possible to etch back while leaving a necessary portion. In that case, for example, in the flowchart of FIG. 9 described in the third embodiment, a photolithography process for forming a mask covering a desired position of the polysilicon film 20 may be included between steps S110 and S120. good.

(2) In the above-described embodiments, an example of a vertical MOSFET having a trench gate structure has been described. Of course, other configurations may be provided with the above-described vertical MOSFET as a basic structure. For example, by providing a p-type deep layer under the trench gate structure, it is possible to provide various structures such as a structure for suppressing the rise of equipotential lines to the trench gate structure and improving the withstand voltage.

(3) In addition, in each of the above embodiments, the case of using SiC as a semiconductor material has been described as an example, but the present invention can also be applied to a semiconductor device using Si or other compound semiconductors as a semiconductor material.

(4) Further, in the above embodiment, the structure in which the n ⁺ -type substrate 1 is prepared as the semiconductor layer and the n ⁻ -type drift layer 2 of the first conductivity type is epitaxially grown on the n ⁺ -type substrate 1 is taken as an example. rice field. However, this is also an example, and the impurity concentration is made higher than that of the n ⁻ type drift layer 2 by using the semiconductor substrate forming the n ⁻ type drift layer 2 and implanting ions into the rear surface side thereof. A semiconductor layer may be formed.

(5) In addition, in each of the above-described embodiments, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. may be a p-channel type vertical MOSFET obtained by inverting . Further, in the above description, a vertical MOSFET is taken as an example of a semiconductor element having a trench gate structure, but the present invention can also be applied to an IGBT having a similar trench gate structure. In the case of an n-channel type IGBT, the conductivity type of the n ⁺ -type substrate 1 is simply changed from n-type to p-type in each of the above-described embodiments, and other structures and manufacturing methods are the same as in each of the above-described embodiments. is.

REFERENCE SIGNS LIST 1 n ⁺ type substrate, 2 n ⁻ type drift layer, 3 p type base region 3a p type contact region, 4 n ⁺ type source region 6 gate trench 7 gate insulating film, 8 gate electrode, 9 Interlayer insulating film 20 Polysilicon film 20a Doped polysilicon layer 20b Non-doped polysilicon layer 100 Wafer

Claims (4)

A method for manufacturing a semiconductor device having a semiconductor element with a trench gate structure,
preparing a structure in which a drift layer (2) of a first conductivity type having a lower impurity concentration than the semiconductor layer (1) is formed on a semiconductor layer (1) of a first or second conductivity type;
forming a second conductivity type channel layer (3) on the drift layer;
forming a first conductivity type region (4) having a first conductivity type impurity concentration higher than that of the drift layer on the channel layer;
forming a gate trench (6) through said first conductivity type region and said channel layer;
forming a gate insulating film (7) covering an inner wall surface of the gate trench;
forming a gate electrode (8) on the gate insulating film;
forming an interlayer insulating film (9) covering the gate electrode in the gate trench;
forming a first electrode (10) electrically connected to the first conductivity type region;
forming a second electrode (11) on the back side of the semiconductor layer,
forming the gate electrode,
forming a polysilicon film (20) on the surface of the gate insulating film so as to fill the inside of the gate trench;
By implanting ions into the polysilicon film in a range shorter than the thickness of the polysilicon film, a doped polysilicon layer (20a) in which the ions are implanted is formed, and the doped polysilicon layer (20a) is formed. forming a non-doped polysilicon layer (20b) under the silicon layer;
Etching back the doped polysilicon layer and etching back the non-doped polysilicon layer until the top surface is lower than the surface of the first conductivity type region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is oblique ion implantation. By forming the polysilicon film, a depression (20d) is formed at a position corresponding to the central portion of the gate trench in the surface of the polysilicon film,
3. The method according to claim 2, wherein when said ion implantation is performed, said oblique ion implantation is performed such that a position where ions are most deeply implanted based on said recess is outside said gate trench. A method of manufacturing a semiconductor device. After forming the polysilicon film, measuring the film thickness of the polysilicon film;
3. The thickness of said non-doped polysilicon layer on the surface of said first conductivity type region is kept constant by adjusting conditions of said ion implantation based on the result of thickness measurement of said polysilicon film. A method of manufacturing the semiconductor device according to 1.

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