JP2022536065A - Efficient Error Correction of Codewords Encoded by Binary Symmetric Invariant Product Codes - Google Patents

Abstract

A decoder for decoding a binary symmetric invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access binary symmetric invariant product codes buffered within the data array along only the first dimension. The decoder also includes an error storage array for storing error locations and detecting and correcting errors in data accessed from the data array along a first dimension and into a second dimension in the error storage array. and a first correction circuit configured to store error locations along. A first correction circuit obtains an error location based on the data symmetry of the symmetric invariant product code. The decoder is also accessed from the data array based on the error locations stored in the error storage array prior to receipt by the first correction circuit of the data accessed from the data array along the first dimension. A second correction circuit is included for correcting the data.

Description

TECHNICAL FIELD This disclosure relates to data processing, and more particularly, utilizing binary symmetry-invariant product codes (e.g., half product codes), e.g., in data storage systems or data communication systems. Efficient error correction of data encoded as .

Error correction coding is utilized in data storage systems or data communication systems to improve the accuracy with which data can be recovered from a data channel. By encoding the data according to an error correction code (ECC) prior to feeding the data to the channel, errors in the channel output can be identified and corrected to an extent dependent on the characteristics of the ECC. Many such ECC schemes are known. One well-known class of ECC schemes is based on product codes. A product code uses a two-component ECC code to encode the rows and columns of a notional two-dimensional array of input data.

The basic structure of a conventional product code is shown schematically in FIG. An input data symbol (which can in general be q ^ary symbols with q possible symbol values, where q≧2) is in a conceptual array with n ₂ rows and n ₁ columns of symbol positions. assigned to each symbol position. In this example, the k ₂ ×k ₁ data symbols are each in the k ₂ -by- k ₁ subarray at the intersection of the first k ₂ rows and the first k ₁ columns of the n ₂ -by- n ₁ array. is assigned to the position of The resulting array of input data symbols is encoded by separately encoding the rows and columns of the array. A first ECC code C1 is used to encode the k _i symbol data words in _each row of the array into C1 codewords of length n1. This example uses systematic encoding, whereby the input data is kept in codewords. Specifically, the n ₁ code symbols of the C1 codeword are obtained by adding (n ₁ −k ₁ ) parity symbols after the k ₁ symbol data word in a given row. . A second ECC code C2 then converts the k ₂ symbols in each column of the array to a length n ₂ C2 code by adding (n ₂ −k ₂ ) parity symbols at the end of each column. used to encode words. The n ₂ ×n ₁ code symbols in the resulting array form the output codeword of the product code. An extension of this basic concept is that an interleaved product code applies the C2 code over s>1 equally spaced columns of the array, resulting in n ₁ /s C2 codewords.

A product code may provide a real encoder/decoder implementation, the decoder of which is hard-decision based, thus avoiding various complexity and latency issues associated with soft-decision decoding. Some decoders for interleaved product codes use graph-based iterative decoding techniques defined from the basic code structure. Briefly, a _bipartite graph can be defined with n2 right nodes, each corresponding to a C1 codeword, and n1 _/ s left nodes, corresponding to each C2 codeword. Each right node is connected to each left node by s edges. The s edges connecting a pair of nodes represent the s common symbols of the intersections of the C1 and C2 codewords for those nodes in the above conceptual array. Iterative decoding is performed graph-based by decoding the C1 codewords one by one and then decoding the C2 codewords one by one. Edges away from the appropriate node are corrected for each successfully decoded codeword. The process is repeated until decoding is complete, ie no more errors are detected by the decoder, or a predetermined maximum number of iterations is reached (in which case the decoder may declare a decoding failure).

Another ECC scheme based on product codes is described in J. Justesen, "Error correcting coding for OTN", IEEE Communications Magazine, September 2010, and J. Justesen, Performance of Product Codes and Related Structures with Iterative Decoding, IEEE Transactions on Communications, 2011, it was proposed in the context of Optical Transport Networks (OTN). These codes, called half-product codes (HPC), are product codes that use the same code for row code C1 and column code C2. Each component code C1 and C2 is a rate k/n code, where n is the code length (i.e., the number of symbols in a codeword) and k is the dimension (i.e., the number of data symbols encoded into each codeword). In one case, the resulting product code C has length N=n ² , dimension K=k ² , and rate (k/n) ² . A codeword of C may be defined by a symbol matrix X (n rows and n columns) corresponding to the conceptual array described above, where each row and column of X is a codeword of a row/column code. The corresponding half-product code C _H is then defined by C _H ={X−X ^T :XεC}, where X ^T is the transposed matrix of X.

If X is a codeword, then X ^T is also a codeword since the row and column codes are the same. By construction, every codeword _YH of C _H has a zero main diagonal (either main diagonal can be a zero main diagonal, but here a zero main diagonal is defined as (n rows n columns) symbol (defined as a line of symbols running diagonally across the matrix _YH from the upper right symbol to the lower left symbol). That is, all symbols on the zero main diagonal have the value zero. From the definition of C _H we know that Y _H =Y _H ^T , so the set of n(n−1)/2 symbols in the triangular subarrays on each side of the zero main diagonal are identical. These n(n−1)/2 symbols thus define the codeword Y _H such that the half-product code has effective length N _H =n(n−1)/2. With HPC, encoding and iterative decoding are performed conventionally as with product codes, but the input data is restricted to triangular subarrays on either side of the zero main diagonal, and HPC has dimension K _H =k ( k-1)/2 is given.

An exemplary prior art HPC 200 is shown in FIG. To form HPC 200 , original input data 204 are placed in a square array under zero main diagonal 202 . Symmetric duplicate data 206 is then formed by copying the original input data 204 , transposing the original input data, and placing the resulting data on the zero main diagonal 202 . Parity data 208 is then calculated separately for each row and each column (using, for example, Bose-Chaudhuri-Hocquenghem (BCH) error correction functionality). After encoding, only the portion of the array above or below the zero main diagonal 202 needs to be stored and/or transmitted for data symmetry.

As data is retrieved from memory or received via data transmission, HPC 200 may be rebuilt by duplicating and transposing the retrieved/received data to populate the array. As shown in FIG. 3, any errors that occur during data storage, retention, retrieval, and transmission, or a combination thereof, are symmetrical about the zero principal diagonal of the reconstructed array. During conventional decoding (i.e., an error correction process in which rows and columns are iteratively processed to correct row and column errors), the data in the array are first accessed in row format and then in column format. be accessed.

In real-world implementations, standard software techniques generally do not duplicate data in CPU memory, but operate on only one set of data and benefit from implicit correction of duplication errors. FIG. 3 assumes that rows are processed from the bottom of the array to the top. If only one copy of each bit is stored in CPU memory, then in essence correcting the erroneous row at A, B, and C results in three subsequent rows containing those bit values. Correct values for A, B, and C are obtained. Although seemingly efficient, this software-based approach has much higher latency than hardware-based solutions and is therefore not suitable for truly high-performance applications.

To achieve high performance decoding, hardware implementations of HPC decoding typically form the entire HPC array (including replicated data 206) in memory, then iterate each row one by one and then each column one by one. decrypted Although this approach provides much higher performance than conventional software implementations, the disclosure recognizes that the circuitry that allows data to be accessed in both row and column formats is very expensive. . The present disclosure also understands that conventional hardware implementations require reading and correcting both row and column data independently, i.e. hardware HPC decoding implementations do not benefit from array symmetry. ing.

In at least one embodiment, the decoder performs, in hardware, iterative decoding of codewords encoded by a binary symmetric invariant product code, such as a half product code (HPC). A symmetric invariant product code buffered in a data array is accessed along only the first dimension of the data array and errors in the data of the symmetric invariant product code are detected and corrected by error correction circuitry. . When an error is detected, the error location for the orthogonal second dimension of the data array is stored in an error storage array, the error location being determined based on the known data symmetry of the symmetric invariant product code. . Based on the stored error locations, errors are corrected "on the fly" as the data is accessed from the data array and sent to the error correction circuitry.

According to one aspect, a decoder is provided for decoding a binary symmetric invariant product code, the decoder being a data array having orthogonal first and second dimensions, along the first dimension only: A data array configured to access binary symmetric invariant product codes buffered in the data array; an error storage array for storing error locations; and a data array along a first dimension. a first correction circuit configured to detect and correct errors in data accessed from the symmetric invariant product code and to store error locations along the second dimension in an error storage array; a first correction circuit for determining error locations based on data symmetry; and storage in an error storage array prior to receipt by the first correction circuit of data accessed from the data array along a first dimension. and a second correction circuit for correcting data accessed from the data array based on the detected error location.

According to another aspect, a method of decoding a binary symmetric invariant product code is provided, the method buffering along only the first dimension into a data array having orthogonal first and second dimensions. accessing a binary symmetric invariant product code; first correction circuitry detecting and correcting errors in data accessed from the data array along a first dimension; a circuit determining error locations along a second dimension in the error storage array based on data symmetry of the symmetric invariant product code; storing the error locations in the error storage array; A second correction circuit corrects the data accessed from the data array based on the error locations stored in the error storage array prior to receipt by the first correction circuit of the data accessed from the data array along the and correcting.

According to another aspect there is provided a computer program comprising program code means adapted to perform the method of the preceding paragraph when the computer program is run on a computer.

Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings.

Fig. 2 shows a prior art product code; 1 illustrates a prior art half-product code (HPC); FIG. FIG. 1 illustrates prior art HPC with symmetrical data errors; 1 depicts a high-level block diagram of a data storage system according to one embodiment; FIG. 1 depicts a high-level block diagram of a data communication system according to one embodiment; FIG. 5 illustrates an exemplary implementation of the data storage system of FIG. 4; FIG. 5 illustrates an exemplary implementation of the data storage system of FIG. 4; FIG. FIG. 4 illustrates an exemplary decoder according to one embodiment; 4 depicts a high-level logic flowchart of an exemplary process for a decoder to decode a binary symmetric invariant product code, according to one embodiment. FIG. 4 illustrates correction of errors in an exemplary HPC by a decoder, according to one embodiment; FIG. 4 illustrates correction of errors in an exemplary HPC by a decoder, according to one embodiment; FIG. 4 illustrates correction of errors in an exemplary HPC by a decoder, according to one embodiment; FIG. 4 illustrates correction of errors in an exemplary HPC by a decoder, according to one embodiment;

In accordance with at least one embodiment, the present application is directed to a decoder that performs, in hardware circuitry, iterative decoding of codewords encoded by a binary symmetric invariant product code, such as a half product code (HPC). The symmetric invariant product code buffered in the data array is accessed along only the first dimension of the data array and errors in the data of the symmetric invariant product code are detected and corrected by the first error correction circuit. Corrected. When an error is detected, the error location for the orthogonal second dimension of the data array is stored in an error storage array, the error location being determined based on the known data symmetry of the symmetric invariant product code. . As data is accessed from the data array and sent to the first error correction circuit, errors are corrected "on the fly" by the second correction circuit based on the stored error locations. The present application is further directed to related methods and program products.

Although the solution described herein can be applied to conventional HPC as discussed above, the solution disclosed herein uses multiple types of component codes per row and column It is to be understood that it is also applicable to symmetric invariant product codes formed from multiple types of component codes. Similarly, another extension of HPC can be obtained by using multiple types of component codes in code construction. For example, two types of component codes with the same length n but different error correction capabilities t ₁ and t ₂ may be used. In the HPC case, we require that the first half of the rows/columns are codewords from the t ₁ error correction component code and the second half of the rows/columns are codewords from the t ₂ error component code. can be

Referring again to the figures, and specifically to FIG. 4, there is a high level block diagram of an exemplary embodiment of a data storage system 400 for reading and writing ECC encoded data on a data storage device. Data storage system 400 includes a recording channel that includes memory 404 (eg, flash memory or other non-volatile random access memory (NVRAM)) and read/write device 406 for reading and writing data in memory 404. 402 included. Although shown as a single block in FIG. 4, memory 404 is a data storage unit that can span, for example, a single chip or die to multiple storage banks each containing multiple packages of memory chips. It can have any desired configuration. Read/write device 406 addresses memory cells for read and write purposes by applying appropriate voltages to an array of wordlines and bitlines in memory 404 to perform read and write operations in a known manner. to implement.

Data storage system 400 further includes encoder 410 and decoder 412 . Encoder 410 encodes input data into code symbols according to a binary symmetric invariant product code (eg, HPC) and outputs the code symbols to recording channel 402 . Decoder 412 processes the readback symbols obtained from memory 404 by read/write unit 406 to decode the symmetric invariant product code, thus recovering and outputting the original input data.

As further shown in FIG. 5, symmetric invariant product codes such as HPC also find application in data communication systems such as data communication system 500 . The transmitter of data communication system 500 includes encoder 510, modulator 508, and transmitting device (TX) 506 as described above with reference to FIG. Code symbols output by encoder 510 are provided via modulator 508 to transmitting device 506 , which generates signals for transmitting the code symbols over communication link 504 . Communication links 504 may include physical (wired or wireless) links or logical links via one or more physical links. a data communication system receiver receiving device (RX) 516 for receiving signals transmitted over link 504; demodulator 518 for demodulating the received signals; and a decoder 512 as previously described for decoding the resulting code symbols.

In a preferred embodiment, the functions of encoders 410, 510 and decoders 412, 512 are implemented in hardware circuits (ie, integrated circuits) to achieve high performance. However, in other embodiments, the functions of encoders 410, 510 and decoders 412, 512 may be implemented in hardware executing program instructions in software and/or firmware. For example, encoding and decoding may be performed, in whole or in part, by executing software that configures one or more processors as encoders and/or decoders to perform the encoding and decoding.

6-7, more detailed block diagrams of exemplary implementations of data storage systems such as data storage system 400 in FIG. 4 are shown. FIG. 6 illustrates a data processing environment 600 including one or more hosts, such as processor system 602 having one or more processors 604 that process instructions and data. Additionally, processor system 602 has local storage 606 (e.g., dynamic random access memory) that may store program code, operands, or results of execution of processes performed by one or more processors 604, or a combination thereof. • May include memory (DRAM) or disk). In various embodiments, processor system 602 may be, for example, a mobile computing device (such as a smart phone or tablet), a laptop or desktop personal computer system, a server computer system (International Business Machines Corporation), or a mainframe computer system. Processor system 602 may also be any ARM(R), POWER(R), Intel x86(R), or any combination of memory caches, memory controllers, local storage, I/O bus hubs, etc. It may be an embedded processor system using various processors, such as other processors in .

Each processor system 602 is coupled to data storage system 620 via I/O channel 610 either directly (i.e., without any intervening device) or indirectly (i.e., through at least one intermediate device). It further includes an input/output (I/O) adapter 608 that is In various embodiments, I/O channel 610 may be, for example, Fiber Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand, Transmission Control Protocol/ Any one or combination of known or later developed communication protocols may be utilized, including Internet Protocol (TCP/IP), Peripheral Component Interconnect Express (PCIe), and the like. I/O requests communicated over I/O channel 610 include read requests, in which processor system 602 requests data from data storage system 620 , and read requests, in which processor system 602 requests data to be stored in data storage system 620 . and a write request requesting a

Although not required, in the illustrated embodiment, data storage system 620 includes a plurality of interface interfaces through which data storage system 620 receives and responds to host I/O requests via I/O channel 610. Includes card 622 . Each interface card 622 is coupled to each of multiple Redundant Array of Inexpensive Disks (RAID) controllers 624 to facilitate fault tolerance and load balancing. Each of the RAID controllers 624 is coupled (eg, by a PCIe bus) to a non-volatile storage medium, which in the illustrated example includes multiple flash cards 626 carrying NAND flash memory. Alternate and/or additional non-volatile storage devices may be utilized in other embodiments.

In the illustrated embodiment, operation of data storage system 620 is managed by redundant system management controller (SMC) 623 , which is coupled to interface card 622 and RAID controller 624 . In various embodiments, system management controller 623 may be implemented utilizing hardware or hardware executing firmware and/or software.

FIG. 7 shows a more detailed block diagram of an exemplary embodiment of flash card 626 of data storage system 620 of FIG. Flash card 626 includes a gateway 730 that acts as an interface between flash card 626 and RAID controller 624 . Gateway 730 is coupled to a general purpose processor (GPP) 732, which performs preprocessing on I/O requests received by gateway 730 or schedules servicing of I/O requests by flash card 626. , or configured (eg, by program code) to do both. GPP 732 processes data created, referenced, or modified, or a combination thereof, by GPP 732 during processing or data flowing through gateway 730 that is destined for one or more of flash controllers 740. It is coupled to GPP memory 734 (eg, dynamic random access memory (DRAM)), which can be conveniently buffered.

Gateway 730 is further coupled to multiple flash controllers 740 , each of which controls a respective NAND flash memory system 750 . Flash controller 740 may be implemented, for example, by an application specific integrated circuit (ASIC), field programmable gate array (FPGA), or microprocessor, or combination thereof, each with an associated flash controller memory. 742 (eg, DRAM). In embodiments where flash controller 740 is implemented with an FPGA, GPP 732 may program and configure flash controller 740 during power-up of data storage system 620 . After power-up, during normal operation, flash controller 740 reads data stored within NAND flash memory system 750 and/or stores data within NAND flash memory system 750. Receives read and write requests from gateway 730 requesting to perform Flash controller 740 may, for example, access NAND flash memory system 750 to read the requested data from or write to NAND flash memory system 750, or These requests are serviced by accessing a memory cache (not shown) associated with NAND flash memory system 750 .

Flash controller 740 implements a Flash Translation Layer (FTL) that provides logical-to-physical address translation that allows access to specific memory locations within NAND Flash memory system 750 . In general, an I/O request received by flash controller 740 from a host device such as processor system 602 identifies the logical block address (LBA) at which data is to be accessed (read or written), and the LBA for write requests. , and write data to be stored in data storage system 620 . An I/O request may also specify the amount (or size) of data to be accessed. Other information may also be communicated depending on the protocols and features supported by data storage system 620 . The flash translation layer translates LBAs received from RAID controller 624 into physical addresses assigned to corresponding physical locations within NAND flash memory system 750 . Flash controller 740 performs address translation, or logical and physical addresses in a logical-to-physical translation data structure, such as a logical-to-physical translation table (LPT), which may be conveniently stored in flash controller memory 742. , or both.

NAND flash memory system 750 can take many forms in various embodiments. In the embodiment shown in FIG. 7, each NAND flash memory system 750 includes multiple (eg, 32) individually addressable NAND flash memory storage devices 752 . In the illustrated example, flash memory storage device 752 is a substrate mounted flash memory module, such as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), or Quad It takes the form of a Level Cell (QLC) NAND flash memory module. Preferably, the fidelity of data read from flash memory storage device 752 is enhanced through the implementation of ECC encoding, for example by flash controller 740 and/or higher level controllers such as GPP 732 and RAID controller 624. be done. In the illustrated embodiment, ECC encoding and decoding is implemented at least in flash controller 740 by encoder 744 and decoder 746 .

Referring now to FIG. 8, an exemplary embodiment of decoder 800 is shown in accordance with one embodiment. Decoder 800 can be used to implement any of decoders 412, 512, or 746, which decodes data encoded using a binary symmetric invariant product code (eg, HPC).

As shown in FIG. 8, decoder 800 includes control circuitry 802 that controls the decoding of uncorrected codewords encoded using a binary symmetric invariant product code. Further, decoder 800 includes a data array 804 that buffers the binary symmetric invariant product code as the binary symmetric invariant product code is decoded. As is conventional, the data array 804 includes orthogonal, equal-sized first and second dimensions, referred to herein as rows and columns, respectively. In contrast to conventional decoders, data array 804 is preferably buffered therein such that it decodes only along one of its first and second dimensions and not along the other. It includes circuitry that allows access to a binary symmetric invariant product code. Such limitations greatly reduce the cost of implementing decoder 800 in hardware circuits. For simplicity, the following assumes that the data array 804 is accessed only row by row and not column by column, but the data symmetry of the binary symmetric invariant product code buffered in the data array 804 Given , it should be appreciated that the choice of dimension to be accessed is completely arbitrary.

Data array 804 is coupled to column correction circuitry 806 , which, based on error location information stored in error storage array 810 , provides individual corrections within row codewords read from data array 804 . is configured to correct the bit positions of 'on the fly' as needed. The row codeword, possibly modified by column correction circuit 806, is then fully decoded by row correction circuit 808. FIG. Row correction circuit 808 may implement, for example, a Bose-Chaudhuri-Hocquenghem (BCH) error correction function, as is known in the art. Upon decoding the row codeword, row correction circuit 808 records the location of any corrected errors in error storage array 810 . In addition, row correction circuit 808 writes the decoded row codeword back into data array 804 (with any corrections made by column correction circuit 806 and/or row correction circuit 808).

Referring now to FIG. 9, a high-level logic flowchart of an exemplary process for decoding a binary symmetric invariant product code by a decoder such as decoder 800 of FIG. 8 is shown in one embodiment. The process of FIG. 9 begins at block 900 and then proceeds to block 902, which illustrates decoder 800 receiving a portion of a binary symmetric invariant product code, hereinafter assumed to be HPC. As noted above, HPC may be received by decoder 800 from, for example, recording channel 402 of data storage system 400 or transmission link 504 of data communication system 500 . In response to receiving the portion of the HPC, the control circuit 802 of the decoder 800 fills the portion of the data array 804 with the received portion of the HPC (eg, the triangular portion of the array below the zero main diagonal) and The data in the received portion is replicated to form a full data symmetric HPC in data array 804 .

Following block 902 , control circuitry 802 directs iterative decoding of HPC along only a single dimension of data array 804 . Thus, in one example, the control circuit 802 causes the HPC to be accessed and decoded by row codewords rather than by column codewords. By eliminating the HPC access along the second dimension, the latency to decode the HPC is cut in half.

The control circuit 802 begins the iterative decoding process at block 904 by determining whether all row codewords of HPC buffered in the data array 804 have been accessed for decoding. If so, the process proceeds to block 920, described below. If not, the process proceeds to block 910; At block 910 , control circuit 802 causes the first or next row codeword of HPC to be read from data array 804 . As indicated by block 912, when the row codeword is sent to row correction circuit 808 for decoding, column correction circuit 806 causes the bits of the row codeword identified as containing errors by error storage array 808 to be If so, it is corrected (ie, inverted) "on the fly" and the row codeword with such correction is forwarded to row correction circuit 808 . In response to receiving a row codeword, possibly modified by column correction circuit 806, row correction circuit 808 decodes the codeword utilizing the parity portion of the codeword to correct any errors. (block 914). As noted above, in one embodiment, row correction circuit 808 may utilize, for example, conventional BCH error correction functionality. As further shown in block 914, if any errors in the row codeword are corrected, the row correction circuit 808 records the error location in the error storage array 810 so that the column correction circuit 806 stores the error location information. It allows for correcting bits in one or more additional row codewords based on the known data symmetry of HPC. At block 916 , row correction circuit 808 writes the decoded row codeword back to its original location in data array 802 . The process then returns to block 904 .

Referring now to block 920, control circuit 802 determines whether any errors were detected in any of the row codewords of the HPC during the last iteration over all of the row codewords. If no errors were detected in any of the row codewords during the last iteration, then the HPC was successfully decoded and the process proceeds to block 922 where control circuit 802 causes the row codewords of the decoded HPC to Words are shown to be output from data array 804 , for example to processor system 602 or to components of data communication system 500 . Thereafter, the process of FIG. 9 ends at block 924. FIG. However, if the control circuit 802 determines at block 920 that at least one error was found in at least one row codeword during the last iteration over all of the HPC row codewords, then at block 926 the control circuit 802 , HPC, determine whether the maximum number of iterations (eg, 3) over the row codewords has been implemented. If not, the process of FIG. 9 returns through page connector A to block 910 and subsequent blocks as described. However, if control circuit 802 determines at block 926 that the maximum number of iterations over all of the HPC row codewords has been performed, then the process of FIG. If there is, start it.

10-13, an example of error correction in an exemplary HPC by the decoder of FIG. 8 utilizing the process of FIG. 9 is provided. In this example, data array 804 has 20 rows and 20 columns, numbered R0 through R19 and C0 through C19, respectively. In this example, HPC is encoded using the Bose-Chaudhuri-Hocquenghem (BCH) error correction function, which can correct up to three errors in a given row (or column) with zero latency. Assume that As a result of this error correction capability, error storage array 810 preferably includes capacity for storing up to three error locations per row. The error storage arrays are all initialized to "invalid" values (empty) so that column correction circuit 806 initially does not perform any corrections on row codewords read from data array 804 .

After all input HPCs are established in data array 804, control circuit 802 causes row codewords to be read out from data array 804 in iterative and sequential order, starting with row R0, and column correction for BCH decoding. It is passed through circuit 806 to row correction circuit 808 . As shown in FIG. 10, the row codewords in rows R0 and R1 do not contain any errors, while the row codeword in row R2 initially contains three errors in columns C10, C4, and C3. In response to detecting these bit errors, row correction circuit 808 updates error storage array 810, which may be represented as shown in Table 1. As shown, error storage array 810 records three errors to be corrected: bits in rows R3, R4, and R10 in column C2. As should be noted, these three errors are symmetrical to the errors detected in columns C3, C4, and C10 of row R2.

行Ｒ２内の誤りの訂正に続いて、行訂正回路８０８はデータ・アレイ８０４を更新し、図１１に示されるように、データ・アレイ８０４は一時的に非対称となる。

Following correction of the error in row R2, row correction circuit 808 updates data array 804, making data array 804 temporarily asymmetric, as shown in FIG.

Continuing with the example, the row codeword in row R3 is then read from data array 804 and passed through column correction circuit 806 to row correction circuit 808 . When this row codeword is transmitted, column correction circuit 806 corrects the error in column C2 and resets error storage array 810 to remove "3" from the entry corresponding to column C2 in error storage array 810. Update. When row correction circuit 808 performs BCH decoding on the row codeword of row R3, since the only error has already been corrected by column correction circuit 806 before the row codeword is received by row correction circuit 808, no errors found. Accordingly, row correction circuit 808 will not store any new error locations in error storage array 810, and error storage array 810 will therefore appear as shown in Table II below. After row correction circuit 808 writes the corrected row codeword back into row R3, data array 804 will appear as shown in FIG.

The row codeword in row R4 is then read from data array 804 and passed through column correction circuit 806 to row correction circuit 808 . As shown, the row codeword for row R4 initially contains four errors, more errors than can be corrected by the BCH algorithm implemented by row correction circuit 808. FIG. However, since column correction circuit 806 corrects the bits in column 2 of the row codeword prior to receipt of the row codeword by row correction circuit 808 based on information provided by error storage array 810, the row correction circuit 808 can perfectly decode the row codeword given that there are 3 errors instead of 4 after column correction. After row correction circuit 808 decodes the row codeword and updates data array 802 and error storage array 810, data array 802 will appear as shown in FIG. It will have the states shown in Table III below.

This decoding process will continue iteratively across row R19. After the first iteration over all rows of data array 802 is completed, error storage array 810 is not cleared and the second iteration begins. This process will continue until one of the following two termination conditions is met. (1) the HPC does not contain any errors (i.e., all row codewords of the HPC are decoded by the row correction circuit 808 without any errors being found), or (2) the maximum iteration limit is reached (i.e. , HPC is not corrected).

In the above discussion, for ease of explanation, we have ignored the effects of latency and pipelining in actual hardware implementations. To illustrate the additional impact of latency and pipelining, the latency of row correction circuit 808 is 5 cycles, meaning that when a particular row codeword initiates BCH decoding, the resulting correction is 5 clock cycles. Assume that it will not be available until after the cycle. With this assumption, the location of the error in row R2 will not be available for correction of subsequent rows until row R7 is entering row correction circuit 808. FIG. Accordingly, row correction circuit 808 records corrections to column C2 of rows R3, R4, and R10 in error storage array 810 based on decoding row R2, but this error location information becomes available. Previously, the codewords for rows R3 and R4 would have been received in row correction circuit 808 . As a result, the row codewords for rows R3 and R4 will be " They can be column corrected "on the fly", but by the time error storage array 810 reflects the error locations within these row codewords, they have already been processed by row correction circuit 808. FIG. Fortunately, the failure of column correction circuit 806 to correct these column errors in this first iteration does not affect the final result of BCH decoding. Column correction circuit 806 utilizes any error location information recorded in error storage array 810 to correct bits (eg, bits in column C2 of row codewords for rows R3 and R4) in the next pass. Because it does. Simulations and analysis demonstrate that the latency does not result in any significant decoding performance loss for the ideal zero-latency case, as discussed.

In a preferred embodiment, row correction circuit 808 is designed with its decoding latency and directs the storage of error locations in the error storage array according to its decoding latency. Thus, for example, row correction circuit 808 intelligently directs storage of error locations in column C2 of row R10 in error storage array 810 before storage of error locations in column C2 of rows R3 and R4. obtain. This intelligent direction of error location storage in error storage array 810 ensures that, to the maximum extent possible, symmetrical errors (e.g., errors in column C2 of row R10) are detected in the row codeword in which the corresponding error is detected. It is guaranteed that it can be corrected by column correction circuit 806 during the same iteration over .

In the examples given above, the effects of parallelization are also not explicitly discussed. In at least some embodiments, it is desirable to improve decoding throughput through the implementation of parallel instances of column correction logic within column correction circuit 806 and parallel instances of decoding logic within row correction circuit 808 . For example, in one embodiment, row correction circuitry 808 may include four instances of decoding logic capable of decoding four codewords per clock cycle, and column correction circuitry 806 may likewise include four codewords per clock cycle. It may contain four instances of column correction logic that can correct bits within one codeword. In such an embodiment, one instance of logic is on rows R0, R4, R8, R12, . . . A second instance of logic processes row codewords such as rows R1, R5, R9, R13, etc., determined by the dimensions of the data array modulo the number of logic instances. preferably. Note that error locations corrected by any instance of column correction logic may be detected by any instance of decoding logic.

As described, in at least one embodiment a decoder for decoding a binary symmetric invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access binary symmetric invariant product codes buffered within the data array along only the first dimension. The decoder also includes an error storage array for storing error locations and detecting and correcting errors in data accessed from the data array along a first dimension and into a second dimension in the error storage array. and a first correction circuit configured to store error locations along. A first correction circuit obtains an error location based on the data symmetry of the symmetric invariant product code. The decoder is also accessed from the data array based on the error locations stored in the error storage array prior to receipt by the first correction circuit of the data accessed from the data array along the first dimension. A second correction circuit is included for correcting the data.

The described embodiments can provide significant advantages over prior art decoders in both cost and performance. For example, by eliminating the requirement to access binary symmetric invariant product codes along both dimensions, circuit cost and area can be significantly reduced, especially for large binary symmetric invariant product codes, which can be 300 or more bits in each dimension. reduced. Moreover, by eliminating the need to access binary symmetric invariant product codes along both dimensions, decoding latency can be reduced by up to half. Moreover, the described embodiments exploit data symmetry to detect such symmetric errors, rather than waiting for them to be "rediscovered" and corrected during decoding of subsequent codewords. Correct "on the fly".

The invention can be a system, method, or computer program product, or a combination thereof. A computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to implement aspects of the present invention.

A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium can be, for example, without limitation, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disc, Included are punched cards, mechanically encoded devices such as raised structures in grooves in which instructions are recorded, and any suitable combination of the above. As used herein, computer-readable storage medium refers to radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or transmissions transmitted through wires. should not be construed as being transient in nature, such as electrical signals that

The computer readable program instructions described herein can be transferred from a computer readable storage medium to a respective computing/processing device or over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or combinations thereof. can be downloaded to an external computer or external storage device via A network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or combinations thereof. A network adapter card or network interface within each computing/processing device receives computer-readable program instructions from the network for storage within a computer-readable storage medium within the respective computing/processing device. Transfer program instructions.

Computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine language instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or Smalltalk(R) instructions. source code written in any combination of one or more programming languages, including object-oriented programming languages such as C++, and conventional procedural programming languages such as the "C" programming language or similar programming languages; It can be either object code. The computer-readable program instructions reside entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or It can run entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or (e.g., through an Internet service provider Connections can be made to external computers (through the Internet, using In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) are programmed with a computer readable program to implement aspects of the invention. Computer readable program instructions may be executed to personalize the electronic circuit by utilizing the state information of the instructions.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be executed via a processor of a computer or other programmable data processing apparatus to perform the functions/acts specified in one or more blocks of the flowchart illustrations and/or block diagrams. A processor may be provided to a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a means for implementation to create a machine. These computer readable program instructions also produce an article of manufacture in which the computer readable storage medium storing the instructions contains instructions for implementing aspects of the functions/operations specified in one or more blocks of the flowcharts and/or block diagrams. , may be stored in a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

Computer readable program instructions may also be instructions that execute on a computer, other programmable apparatus, or another device to implement the functions/acts specified in one or more blocks of the flowchart illustrations and/or block diagrams. A computer-implemented process is loaded onto a computer, other programmable data processing apparatus, or another device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device, such that can be generated.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block of a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, may each perform a specified function or operation, or implement a combination of dedicated hardware and computer instructions. Note also that it can be implemented by a ware-based system.

Although the invention has been illustrated and described with reference to one or more preferred embodiments, various changes in form and detail may be made therein without departing from the spirit and scope of the invention. will be understood by those skilled in the art. For example, although aspects have been described in terms of a data storage system including a flash controller that directs certain functions, alternatively, a data storage system processed by a processor to perform such functions or cause such functions to be performed. It should be understood that the present invention can be implemented as a program product including a storage device storing program code that can be executed. As used herein, "storage device" is specifically defined to include only legal articles of manufacture and exclude essentially signal media, essentially transitory signals, and essentially forms of energy. be.

Additionally, although embodiments have been described that include the use of NAND flash memory, it is understood that embodiments of the present invention can also be used with any other type of non-volatile random access memory (NVRAM). sea bream.

The above-described figures and written descriptions of specific structures and functions below are not presented to limit the scope of applicant's invention or the scope of the appended claims. Rather, the drawings and written description are provided to teach one skilled in the art to make and use the invention for which patent protection is sought. Those skilled in the art will appreciate that not all features of the commercial embodiments of the invention have been described or illustrated for clarity and understanding. Those skilled in the art will appreciate that the development of an actual commercial embodiment that incorporates aspects of the present invention will require a number of implementation-specific decisions to achieve the developer's ultimate goal for the commercial embodiment. Yo. Such implementation-specific decisions may include, but are not limited to, system-related, business-related, government-related compliance, and other constraints that may vary by particular implementation, location, and from time to time. high. In the absolute sense a developer's effort can be complex and time consuming, yet such an effort would be a routine undertaking for those skilled in the art with the benefit of this disclosure. It is to be understood that the invention disclosed and taught herein is susceptible to numerous and various modifications and alternative forms. Finally, and without limitation, the use of singular terms such as "a" is not intended to limit the number of items.

Claims (21)

A decoder for decoding a binary symmetric invariant product code, comprising:
A data array having orthogonal first and second dimensions, configured to access binary symmetric invariant product codes buffered within said data array along said first dimension only. , the data array;
an error storage array for storing error locations;
configured to detect and correct errors in data accessed from the data array along the first dimension and store error locations along the second dimension in the error storage array; a first correction circuit for determining the error location based on data symmetry of the symmetric invariant product code;
accessing from the data array based on the error locations stored in the error storage array prior to receipt by the first correction circuitry of data accessed from the data array along the first dimension; and a second correction circuit for correcting the data that has been processed. 2. The decoder of claim 1, wherein said binary symmetric invariant product code is a half product code (HPC). 2. The decoder of claim 1, wherein said data array is configured to access said binary symmetric invariant product codes buffered therein only row by row. 2. The decoder of claim 1, wherein said first correction circuit updates said data array with corrected data. The decoder iteratively accesses codewords of the binary symmetric invariant product code buffered in the data array along the first dimension only, whereby at least a portion of the codewords are: 5. The decoder of claim 4, accessed multiple times along the first dimension. The decoder iteratively accessing codewords of the binary symmetric invariant product code based on the first time the decoder reaches a predetermined number of iterations and fails to detect an error in the binary symmetric invariant product code. 6. The decoder of claim 5, suspending. wherein the first correction circuit is configured to decode multiple codewords per clock cycle;
2. The decoder of claim 1, wherein said second correction circuit is configured to apply the correction indicated by said error storage array to multiple codewords per clock cycle. 2. The decoder of claim 1, wherein said first correction circuit directs storage of said error locations in said error storage array according to latency of said decoder. a non-volatile memory system;
A data storage system comprising a controller coupled to said non-volatile memory system, said controller including the decoder of claim 1 . a demodulator configured to receive modulated coded data from a communication channel, demodulate the modulated coded data, and output coded data;
2. A data communication system according to claim 1, comprising a decoder coupled to said demodulator and receiving as input encoded data comprising said binary symmetric invariant product code. A method of decoding a binary symmetric invariant product code, comprising:
accessing a binary symmetric invariant product code buffered in a data array having orthogonal first and second dimensions along only the first dimension;
a first correction circuit detecting and correcting errors in data accessed from the data array along the first dimension;
The first correction circuit determines error locations along the second dimension in an error storage array based on data symmetry of the symmetric invariant product code, and stores the error locations in an error storage array. and
prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, a second correction circuit based on the error locations stored in the error storage array; and correcting said data accessed from said data array. 12. The method of claim 11, wherein the binary symmetric invariant product code is a half product code (HPC). 12. The method of claim 11, wherein said accessing comprises accessing said binary symmetric invariant product code buffered in said data array only row by row. 12. The method of claim 11, further comprising said first correction circuit updating said data array with corrected data. The accessing iteratively accesses codewords of the binary symmetric invariant product code buffered in the data array along only the first dimension, thereby at least a portion of the codewords. is accessed multiple times along the first dimension. discontinuing iteratively accessing codewords of the binary symmetric invariant product code based on reaching a predetermined number of iterations and not detecting an error in the binary symmetric invariant product code for the first time. 16. The method of claim 15, further comprising: wherein said first correction circuit detecting and correcting errors includes said first correction circuit detecting and correcting errors in multiple codewords per clock cycle;
12. The method of claim 11, wherein said second correction circuit correcting said data comprises said second correction circuit applying the correction indicated by said error storage array to a plurality of codewords per clock cycle. described method. 12. The method of claim 11, further comprising: said first correction circuit directing storage of said error locations in said error storage array according to decoding latency. 12. The method of claim 11, further comprising retrieving a portion of said binary symmetric invariant product code from a non-volatile memory system. 12. The method of claim 11, further comprising receiving a portion of said binary symmetric invariant product code from a communication link. A computer program comprising program code means adapted to implement a method according to any one of claims 11 to 20 when the computer program is run on a computer.

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