JP2022189566A - Gate driver, semiconductor device, switching power supply - Google Patents

Abstract

To reduce gate losses associated with transistor on/off.SOLUTION: A gate driver 12L has a gate drive circuit 121 configured to charge and discharge the gate capacitance CissL of a transistor 11L, and a capacitor circuit 122 configured to store at least some charge when the gate capacitance CissL is discharged and use that charge the next time it is charged.SELECTED DRAWING: Figure 2

Description

The invention disclosed in this specification relates to a gate driver, a semiconductor device using the same, and a switching power supply.

Gate drivers are widely used as means for driving transistors.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2021-061663 A

However, conventional gate drivers have room for improvement in terms of reducing gate loss (switching loss) accompanying turning on and off of transistors.

In view of the above problems found by the inventors of the present application, the invention disclosed in the present specification provides a gate driver capable of reducing gate loss associated with turning on and off of a transistor, and a gate driver using the same. An object of the present invention is to provide a semiconductor device and a switching power supply.

For example, the gate driver disclosed in this specification includes a gate driving circuit configured to charge and discharge a gate capacitance of a transistor, and storing at least a portion of the charge when the gate capacitance is discharged. and a capacitor circuit configured to utilize the next charge.

Other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description and accompanying drawings that follow.

According to the invention disclosed in this specification, it is possible to provide a gate driver capable of reducing the gate loss associated with turning on/off a transistor, a semiconductor device using the same, and a switching power supply. Become.

FIG. 1 is a diagram showing the main configuration of a semiconductor device. FIG. 2 is a diagram showing a first embodiment of a gate driver. FIG. 3 is a diagram (first phase) showing an example of gate driving operation by the gate driver of the first embodiment. FIG. 4 is a diagram (second phase) showing an example of gate driving operation by the gate driver of the first embodiment. FIG. 5 is a diagram (third phase) showing an example of the gate driving operation by the gate driver of the first embodiment. FIG. 6 is a diagram (fourth phase) showing an example of the gate driving operation by the gate driver of the first embodiment. FIG. 7 is a diagram (timing chart) showing an example of gate driving operation by the gate driver of the first embodiment. FIG. 8 is a diagram showing a second embodiment of the gate driver. FIG. 9 is a diagram (first phase) showing an example of the gate driving operation by the gate driver of the second embodiment. FIG. 10 is a diagram (second phase) showing an example of the gate driving operation by the gate driver of the second embodiment. FIG. 11 is a diagram (third phase) showing an example of the gate driving operation by the gate driver of the second embodiment. FIG. 12 is a diagram (fourth phase) showing an example of the gate driving operation by the gate driver of the second embodiment. FIG. 13 is a diagram (timing chart) showing an example of gate driving operation by the gate driver of the second embodiment. FIG. 14 is a diagram showing a third embodiment of the gate driver. FIG. 15 is a diagram (first phase) showing an example of gate driving operation by the gate driver of the third embodiment. FIG. 16 is a diagram (second phase) showing an example of the gate driving operation by the gate driver of the third embodiment. FIG. 17 is a diagram (third phase) showing an example of the gate driving operation by the gate driver of the third embodiment. FIG. 18 is a diagram (fourth phase) showing an example of the gate driving operation by the gate driver of the third embodiment. FIG. 19 is a diagram (timing chart) showing an example of gate driving operation by the gate driver of the third embodiment. FIG. 20 is a diagram showing a configuration example of a switching power supply.

<Semiconductor device>
FIG. 1 is a diagram showing the essential configuration of a semiconductor device (for example, around a switch output stage of a power supply controller IC or a motor driver IC). A semiconductor device 10 of this configuration example has a half-bridge output circuit 11, a gate driver 12, a bootstrap circuit 13, a power supply terminal PVIN, and a switch terminal SW.

The half-bridge output circuit 11 includes an upper transistor 11H and a lower transistor 11L, and outputs a rectangular wave switch voltage Vsw from a switch terminal SW corresponding to a connection node between both transistors.

The upper transistor 11H is connected between a power supply terminal PVIN (=application terminal for input voltage Vin) and switch terminal SW (=output terminal for switch voltage Vsw), and is turned on/off according to an upper gate signal GH. be. An NMOSFET [N-channel type metal oxide semiconductor field effect transistor] or the like can be suitably used as the upper transistor 11H. In that case, the upper transistor 11H is turned on when GH=H (≈Vb) and turned off when GH=L (≈Vsw). A PMOSFET [P-channel type MOSFET] can be used instead of the NMOSFET as the upper transistor 11H. In that case, the bootstrap circuit 13 becomes unnecessary.

The lower transistor 11L is connected between the switch terminal SW and the ground terminal PGND, and is turned on/off according to the lower gate signal GL. An NMOSFET or the like can be suitably used as the lower transistor 11L. In that case, the lower transistor 11L is turned on when GL=H (≈Vin) and turned off when GL=L (≈PGND).

The gate driver 12 includes an upper gate driver 12H and a lower gate driver 12L, and turns on/off the upper transistor 11H and the lower transistor 11L, respectively.

Upper gate driver 12H includes PMOSFET 12H1, NMOSFET 12H2, and driver 12H3.

The source of the PMOSFET 12H1 is connected to the output end of the bootstrap circuit 13 (=the end to which the boot voltage Vb is applied). The drains of PMOSFET 12H1 and NMOSFET 12H2 are both connected to the gate of upper transistor 11H. The source of the NMOSFET 12H2 is connected to the switch terminal SW (=source of the upper transistor 11H). Gates of the PMOSFET 12H1 and NMOSFET 12H2 are both connected to the output terminal of the driver 12H3.

The driver 12H3 turns on/off the PMOSFET 12H1 and NMOSFET 12H2 based on the upper control signal SH.

For example, when an inverter is used as the driver 12H3, the PMOSFET 12H1 is turned on and the NMOSFET 12H2 is turned off when the upper control signal SH is at high level. At this time, the charging current IcH flowing through the PMOSFET 12H1 charges the gate capacitance CissH of the upper transistor 11H. Therefore, the upper gate signal GH becomes high level (≈Vb).

Conversely, when the upper control signal SH is at low level, the PMOSFET 12H1 is turned off and the NMOSFET 12H2 is turned on. At this time, the discharge current IdH flowing through the NMOSFET 12H2 discharges the gate capacitance CissH of the upper transistor 11H. Therefore, the upper gate signal GH becomes low level (≈Vsw).

Lower gate driver 12L includes PMOSFET 12L1, NMOSFET 12L2, and driver 12L3.

The source of the PMOSFET 12L1 is connected to the application terminal of the input voltage Vin. The drains of PMOSFET 12L1 and NMOSFET 12L2 are both connected to the gate of lower transistor 11L. The source of the NMOSFET 12L2 is connected to the ground terminal PGND. Gates of the PMOSFET 12L1 and NMOSFET 12L2 are both connected to the output end of the driver 12L3.

The driver 12L3 turns on/off the PMOSFET 12L1 and the NMOSFET 12L2 based on the lower control signal SL.

For example, when an inverter is used as the driver 12L3, the PMOSFET 12L1 is turned on and the NMOSFET 12L2 is turned off when the lower control signal SL is at high level. At this time, the charging current IcL flowing through the PMOSFET 12L1 charges the gate capacitance CissL of the lower transistor 11L. Therefore, the lower gate signal GL becomes high level (≈Vin).

Conversely, when the lower control signal SL is at low level, the PMOSFET 12L1 is turned off and the NMOSFET 12L2 is turned on. At this time, the discharge current IdL flowing through the NMOSFET 12L2 discharges the gate capacitance CissL of the lower transistor 11L. Therefore, the lower gate signal GL becomes low level (≈PGND).

Bootstrap circuit 13 includes capacitor 131 and switch 132 . A first terminal of each of the capacitor 131 and the switch 132 is connected to the output terminal of the bootstrap circuit 13 (=application terminal of the boot voltage Vb). A second terminal of the capacitor 131 is connected to the switch terminal SW (=application terminal of the switch voltage Vsw). A second end of the switch 132 is connected to the power supply terminal PVIN (=applying end of the input voltage Vin). The switch 132 is turned off during the on period of the upper transistor 11H and turned on during the off period of the upper transistor 11H.

The bootstrap circuit 13 described above generates a boot voltage Vb (≈Vsw+Vin) that is always higher than the switch voltage Vsw by the voltage across the capacitor 131 (≈Vin). That is, the boot voltage Vb becomes Vb≈2Vin during the high level period (Vsw≈Vin) of the switch voltage Vsw, and becomes Vb≈Vin during the low level period (Vsw≈PGND) of the switch voltage Vsw.

The boot voltage Vb generated in this manner is supplied to the upper gate driver 12H and used as the high level of the upper gate signal GH (=gate voltage for turning on the upper transistor 11H). Therefore, during the ON period of the upper transistor 11H, the high level (≈Vb) of the upper gate signal GH is raised to a voltage value (≈2Vin) higher than the high level (≈Vin) of the switch voltage Vsw. , the upper transistor 11H can be reliably turned on.

By the way, in the gate driver 12 of this configuration example, when turning off the upper transistor 11H and the lower transistor 11L, all the charges accumulated in the gate capacitances CissH and CissL are discarded, and the upper transistor 11H and the lower transistor 11L are discharged. A gate loss (switching loss) accompanies each ON/OFF. In the following, we propose a novel embodiment that can reduce this gate loss.

<Gate Driver (First Embodiment)>
FIG. 2 is a diagram showing a first embodiment of the lower gate driver 12L. The lower gate driver 12L of the first embodiment includes a gate drive circuit 121 and a capacitor circuit 122. FIG.

The gate drive circuit 121 is a circuit block configured to charge and discharge the gate capacitance CissL of the lower transistor 11L, and includes switches SW1 and SW2. The switch SW1 corresponds to the PMOSFET 12L1 in FIG. 1, and is connected between the application terminal (=power supply terminal) of the input voltage Vin and the gate of the lower transistor 11L. The switch SW2 corresponds to the NMOSFET 12L2 in FIG. 1 and is connected between the gate and source of the lower transistor 11L.

Capacitor circuit 122 is a circuit block configured to store at least part of electric charge when discharging gate capacitance CissL and utilize the electric charge at the next charging, and includes capacitor C11 and switch SW11.

Capacitor C11 and switch SW11 are connected in series between the gate and source of lower transistor 11L. Referring to this drawing, the first end of the capacitor C11 (=the end to which the charging voltage Vcp is applied) is connected to the first end of the switch SW11. The second end of capacitor C11 is connected to the source of lower transistor 11L. A second end of the switch SW11 is connected to the gate of the lower transistor 11L.

In this figure, the lower gate driver 12L is taken as an example, but the upper gate driver 12H may have basically the same configuration.

3, 4, 5 and 6 are diagrams respectively showing an example of gate driving operation by the lower side gate driver 12L of the first embodiment (first phase, second phase, third phase and fourth phase). Fig. 3 is a diagram of each operating state).

FIG. 7 is a timing chart showing an example of the gate driving operation by the lower side gate driver 12L of the first embodiment. (solid line), the voltage waveforms of the lower gate signal GL (small dashed line) and the switch voltage Vsw (large dashed line) are depicted. For convenience of explanation, it is assumed that the capacitor C11 has already accumulated charge due to the gate driving operation before time t11.

Below, the gate drive operation by the lower gate driver 12L of the first embodiment will be described in detail with reference to FIGS. 3 to 7. FIG.

When the lower gate driver 12L of the first embodiment switches the lower transistor 11L from the OFF state to the ON state, in other words, when charging the gate capacitance CissL of the lower transistor 11L, after the first phase, It becomes the second phase.

In the lower gate driver 12L of the first embodiment, the first phase means that the switch SW11 is on and the switches SW1 and SW2 are turned on, as shown in FIGS. 3 and 7 (time t11 to t12). are both off.

In addition, in the lower gate driver 12L of the first embodiment, the second phase means that the switch SW1 is on and the switches SW11 and SW2 are turned on, as shown in FIGS. 4 and 7 (time t12 to t13). are both off.

First, in the first phase, as indicated by the dashed arrow in FIG. 3, charging of the gate capacitance CissL (=discharging of the capacitor C11) is performed using the charging voltage Vcp of the capacitor C11. In other words, part of the charge stored in the capacitor C11 is distributed to the gate capacitance CissL. Therefore, in the first phase, as shown from time t11 to time t12 in FIG. 7, the lower gate signal GL rises from the low level (≈PGND) and the charging voltage Vcp drops until GL=Vcp. equilibrate.

When the lower gate signal GL exceeds the on-threshold voltage of the lower transistor 11L, the lower transistor 11L is turned on, so that the switch voltage Vsw becomes low level (≈PGND). Referring to FIG. 7, at time t11, the switch voltage Vsw drops to a negative potential ( = forward voltage drop of the body diode associated with the lower transistor 11L) to a low level (≈PGND).

Next, in the second phase, as indicated by the dashed arrow in FIG. 4, the input voltage Vin is used to continue charging the gate capacitance CissL. Therefore, the lower gate signal GL rises to a high level (≈Vin), as shown from time t12 to t13 in FIG. As a result, the on-resistance value of the lower transistor 11L further decreases, and the switch voltage Vsw is maintained at a low level (≈PGND).

In the second phase, the switch SW11 is turned off, so the capacitor C11 is not charged using the input voltage Vin. Therefore, the charging voltage Vcp remains maintained at substantially the same potential as in the first phase.

On the other hand, the lower gate driver 12L of the first embodiment entered the third phase when switching the lower transistor 11L from the ON state to the OFF state, in other words, when discharging the gate capacitance CissL of the lower transistor 11L. Then comes the fourth phase.

In the lower gate driver 12L of the first embodiment, the third phase means that the switch SW11 is on and the switches SW1 and SW2 are turned on, as shown in FIGS. 5 and 7 (time t13 to t14). are both off.

In addition, in the lower gate driver 12L of the first embodiment, the fourth phase means that the switch SW2 is on and the switches SW11 and SW11 are turned on, as shown in FIGS. It refers to the operation phase in which both SW1 are in the OFF state.

First, in the third phase, as indicated by the dashed arrow in FIG. 5, the lower gate signal GL is used to charge the capacitor C11 (=discharge the gate capacitance CissL). In other words, part of the charge stored in the gate capacitance CissL is distributed to the capacitor C11.

Therefore, in the third phase, as shown from time t13 to time t14 in FIG. 7, the lower gate signal GL drops from the high level (≈Vin) and the charging voltage Vcp rises until GL=Vcp. equilibrate. However, in the third phase, the lower gate signal GL does not fall below the ON threshold voltage of the lower transistor 11L, and the lower transistor 11L is still in the ON state, so the switch voltage Vsw becomes low level (≈PGND). maintained.

Next, in the fourth phase, as indicated by the dashed arrow in FIG. 6, the discharge of the gate capacitance CissL continues toward the ground terminal PGND. Therefore, as shown after time t14 in FIG. 7, the lower gate signal GL drops to the low level (≈PGND), so the lower transistor 11L is turned off.

In FIG. 7, after time t14, the switch voltage Vsw changes from a low level (≈PGND) to a negative potential (= The forward voltage drop of the body diode that

Also, in the fourth phase, since the switch SW11 is in the OFF state, the charges accumulated in the capacitor C11 are not discharged toward the ground terminal PGND. Therefore, the charging voltage Vcp remains maintained at substantially the same potential as in the third phase.

By repeating the above series of gate driving operations, at least part of the charge is stored in the capacitor C11 when the gate capacitance CissL is discharged, and the charge stored in the capacitor C11 is used when the gate capacitance CissL is charged next time. can be done. Therefore, it is possible to reduce the gate loss (switching loss) associated with turning on/off the lower transistor 11L.

It should be noted that the capacitance value of the capacitor C11 may be set to any value within a range in which charges can be appropriately redistributed between the capacitor C11 and the gate capacitance CissL. For example, when the capacitance values of the capacitor C11 and the gate capacitance CissL are set to the same value (for example, 100 pF), the gate loss (switching loss) is reduced to about 1/3 compared to the conventional configuration without the capacitor circuit 122. can be reduced.

<Gate Driver (Second Embodiment)>
FIG. 8 is a diagram showing a second embodiment of the lower gate driver 12L. The lower gate driver 12L of the second embodiment includes a gate drive circuit 121 and a capacitor circuit 122, as in the first embodiment (FIG. 2).

The gate drive circuit 121 is a circuit block configured to charge and discharge the gate capacitance CissL of the lower transistor 11L, and includes switches SW1 and SW2 and a driver DRV. The switch SW1 corresponds to the PMOSFET 12L1 in FIG. 1, and is connected between the output node n1 (=applying terminal of the charging voltage Vcp) of the capacitor circuit 122 and the gate of the lower transistor 11L. The switch SW2 corresponds to the NMOSFET 12L2 in FIG. 1 and is connected between the gate and source of the lower transistor 11L. A driver DRV corresponds to the driver 12L3 in FIG. 1 and turns on/off the switches SW1 and SW2.

Capacitor circuit 122 is a circuit block configured to store at least part of electric charge when discharging gate capacitance CissL and utilize the electric charge at the next charging, and includes variable capacitor VCAP and switch SW21.

The switch SW21 is connected between the application terminal (=power supply terminal) of the input voltage Vin and the output node n1.

The variable capacitor VCAP is connected between the output node n1 and the source of the lower transistor 11L, and is configured to switch the capacitance value. Referring to this figure, the variable capacitor VCAP includes capacitors C21 and C22 and switches SW22, SW23 and SW24.

First ends of the capacitors C21 and SW23 are both connected to the output node n1. A second end of the capacitor C21 is connected to a first end of each of the switches SW22 and SW24. Second ends of the switches SW23 and SW24 are both connected to the first end of the capacitor C22. Second ends of the switch SW22 and the capacitor C22 are both connected to the source of the lower transistor 11L.

The capacitor circuit 122 described above outputs the charging voltage Vcp of the variable capacitor VCAP from the output node n1 to the gate driving circuit 121 (details will be described later).

In this figure, the lower gate driver 12L is taken as an example, but the upper gate driver 12H may have basically the same configuration.

9, 10, 11 and 12 respectively show an example of the gate driving operation by the lower gate driver 12L of the second embodiment (first phase, second phase, third phase and fourth phase). Fig. 3 is a diagram of each operating state).

FIG. 13 is a timing chart showing an example of the gate driving operation by the lower side gate driver 12L of the second embodiment. Voltage waveforms of the voltage Vcp (solid line), the lower gate signal GL (small dashed line), and the switch voltage Vsw (large dashed line) are depicted. For convenience of explanation, it is assumed that charges have already been stored in the capacitors C21 and C22 by the gate driving operation before time t21.

Below, the gate driving operation by the lower gate driver 12L of the second embodiment will be described in detail with reference to FIGS. 9 to 13. FIG.

As in the first embodiment (FIG. 2), the lower gate driver 12L of the second embodiment changes the gate capacitance of the lower transistor 11L when switching the lower transistor 11L from the OFF state to the ON state. When charging CissL, the first phase is followed by the second phase.

In the lower gate driver 12L of the second embodiment, the first phase means that the switches SW1, SW22, and SW23 are all in the ON state, as shown in FIGS. 9 and 13 (time t21 to t22). refers to the operation phase in which the switches SW2, SW21 and SW24 are all in the off state.

In particular, focusing on the variable capacitor VCAP, in the first phase, the capacitors C21 and C22 are connected in parallel between the output node n1 and the ground terminal PGND. That is, when the capacitance values of the capacitors C21 and C22 are both Cp, the capacitance value of the variable capacitor VCAP is 2Cp (=corresponding to the first capacitance value).

In addition, in the lower gate driver 12L of the second embodiment, the second phase means that the switches SW1 and SW24 are both in the ON state as shown in FIGS. 10 and 13 (time t22 to t23), It refers to the operation phase in which the switches SW2, SW21, SW22 and SW23 are all in the off state.

In particular, focusing on the variable capacitor VCAP, in the second phase, the capacitors C21 and C22 are connected in series between the output node n1 and the ground terminal PGND. That is, when the capacitance values of the capacitors C21 and C22 are both Cp, the capacitance value of the variable capacitor VCAP is Cp/2 (=corresponding to the second capacitance value).

First, in the first phase, as indicated by the dashed arrow in FIG. 9, the gate capacitance CissL is charged (=the variable capacitor VCAP is discharged) using the charging voltage Vcp of the variable capacitor VCAP. In other words, part of the charge stored in the variable capacitor VCAP is distributed to the gate capacitance CissL. Therefore, in the first phase, as shown from time t21 to time t22 in FIG. 13, the lower gate signal GL rises from the low level (≈PGND) and the charging voltage Vcp drops until GL=Vcp. equilibrate.

The charging voltage Vcp (=voltage value Vcp1) in the equilibrium state of the first phase is expressed by the following equation (1).

When the lower gate signal GL exceeds the on-threshold voltage of the lower transistor 11L, the lower transistor 11L is turned on, so that the switch voltage Vsw becomes low level (≈PGND). Referring to FIG. 13, at time t21, the upper transistor 11H and the lower transistor 11L are simultaneously turned off (=dead time for preventing through current), and the switch voltage Vsw changes from high level (≈Vin) to negative. After dropping to the potential (=the forward voltage drop of the body diode associated with the lower transistor 11L), the switch voltage Vsw rises from the negative potential to the low level (≈PGND) as the simultaneous off state is resolved. It is

Next, in the second phase, as indicated by the dashed arrow in FIG. 10, following the first phase, charging of the gate capacitance CissL using the charging voltage Vcp of the variable capacitor VCAP is continued. However, in the second phase, the capacitors C21 and C22 forming the variable capacitor VCAP are switched from the parallel connection state to the series connection state. In other words, the capacitance value of the variable capacitor VCAP is switched from the first capacitance value (=2Cp) to the second capacitance value (=Cp/2).

Therefore, in the second phase, as indicated by times t22 to t23 in FIG. 13, the charging voltage Vcp of the variable capacitor VCAP rises, and following this, the lower gate signal GL also rises. As a result, the on-resistance value of the lower transistor 11L further decreases, and the switch voltage Vsw is maintained at a low level (≈PGND).

The charging voltage Vcp (=voltage value Vcp2) in the equilibrium state of the second phase is expressed by the following equation (2).

Thus, in the second phase, the lower gate signal GL can be increased by switching the capacitors C21 and C22 from the parallel connection state to the series connection state.

On the other hand, when the lower gate driver 12L of the second embodiment switches the lower transistor 11L from the on state to the off state, in other words, the lower transistor 11L When the gate capacitance CissL is discharged, the third phase is followed by the fourth phase.

In the lower gate driver 12L of the second embodiment, the third phase means that the switches SW1, SW22 and SW23 are all in the ON state as shown in FIGS. 11 and 13 (time t23 to t24). refers to the operation phase in which the switches SW2, SW21 and SW24 are all in the off state.

Focusing particularly on the variable capacitor VCAP, in the third phase, the capacitors C21 and C22 are connected in parallel between the output node n1 and the ground terminal PGND. That is, when the capacitance values of the capacitors C21 and C22 are both Cp, the capacitance value of the variable capacitor VCAP is 2Cp (=corresponding to the first capacitance value).

In addition, in the lower gate driver 12L of the second embodiment, the fourth phase means that the switches SW2, SW21, SW22, and SW23 are This refers to an operation phase in which the switches SW1 and SW24 are both in the ON state and in the OFF state.

Focusing particularly on the variable capacitor VCAP, in the fourth phase, the capacitors C21 and C22 are connected in parallel between the output node n1 and the ground terminal PGND. That is, when the capacitance values of the capacitors C21 and C22 are both Cp, the capacitance value of the variable capacitor VCAP is 2Cp (=corresponding to the first capacitance value).

First, in the third phase, the capacitors C21 and C22 forming the variable capacitor VCAP are switched from the series connection state to the parallel connection state. In other words, the capacitance value of the variable capacitor VCAP is switched from the second capacitance value (=Cp/2) to the first capacitance value (=2Cp). As a result, in the third phase, the lower gate signal GL is used to charge the variable capacitor VCAP (=discharge the gate capacitance CissL), as indicated by the dashed arrow in FIG. That is, part of the charge stored in the gate capacitance CissL is distributed to the variable capacitor VCAP.

Therefore, in the third phase, as indicated by times t23 to t24 in FIG. 13, the charging voltage Vcp of the variable capacitor VCAP drops, and following this, the lower gate signal GL also drops. However, in the third phase, the lower gate signal GL does not fall below the ON threshold voltage of the lower transistor 11L, and the lower transistor 11L is still in the ON state, so the switch voltage Vsw becomes low level (≈PGND). maintained.

The charging voltage Vcp (=voltage value Vcp3) in the equilibrium state of the third phase is expressed by the following equation (3).

Thus, in the third phase, by switching the capacitors C21 and C22 from the series connection state to the parallel connection state, the charge stored in the gate capacitance CissL can be recovered to the variable capacitor VCAP.

Next, in the fourth phase, as indicated by the dashed arrow in FIG. 12, the variable capacitor VCAP is charged using the input voltage Vin, and the gate capacitance CissL continues to be discharged toward the ground terminal PGND. Therefore, as shown after time t24 in FIG. 12, the lower gate signal GL drops to the low level (≈PGND), so the lower transistor 11L is turned off.

Thus, in the fourth phase, the charge Qoff (=2Cp×Vin) is stored in the variable capacitor VCAP, and the charge Qdis (=Ciss×Vcp3) remaining in the gate capacitance CissL at the end of the third phase is It is discarded towards ground PGND.

In FIG. 12, after time t24, the switch voltage Vsw changes from a low level (≈PGND) to a negative potential (= The forward voltage drop of the body diode that

By repeating the above series of gate driving operations, at least part of the charge is stored in the variable capacitor VCAP when the gate capacitance CissL is discharged, and the charge stored in the variable capacitor VCAP is used when the gate capacitance CissL is charged next time. can do. Therefore, it is possible to reduce the gate loss (switching loss) associated with turning on/off the lower transistor 11L.

<Gate Driver (Third Embodiment)>
FIG. 14 is a diagram showing a third embodiment of the lower gate driver 12L. The lower gate driver 12L of the first embodiment includes a gate drive circuit 121 and a capacitor circuit 122, like the first embodiment (FIG. 2) and the second embodiment (FIG. 8).

The gate drive circuit 121 is a circuit block configured to charge and discharge the gate capacitance CissL of the lower transistor 11L, and includes switches SW31, SW32, SW33 and SW34. The switch SW31 is connected between the application terminal of the input voltage Vin (=corresponding to the power supply terminal) and the first terminal of the capacitor circuit 122 (=the application terminal of the node voltage Vcp+). The switch SW32 is connected between the first end of the capacitor circuit 122 and the gate of the lower transistor 11L. The switch SW33 is connected between the gate of the lower transistor 11L and the second end of the capacitor circuit 122 (=node voltage Vcp− application end). The switch SW34 is connected between the second end of the capacitor circuit 122 and the source of the lower transistor 11L.

Capacitor circuit 122 is a circuit block configured to store at least part of electric charge when discharging gate capacitance CissL and utilize the electric charge at the next charging, and includes capacitor C31. Note that the first terminal of the capacitor C31 corresponds to the first terminal of the capacitor circuit 122 (=application terminal of the node voltage Vcp+). Also, the second terminal of the capacitor C31 corresponds to the second terminal of the capacitor circuit 122 (=application terminal of the node voltage Vcp-). That is, the capacitor C31 can be understood as the capacitor circuit 122 itself.

In this figure, the lower gate driver 12L is taken as an example, but the upper gate driver 12H may have basically the same configuration.

15, 16, 17 and 18 respectively show an example of the gate driving operation by the lower gate driver 12L of the third embodiment (first phase, second phase, third phase and fourth phase). Fig. 3 is a diagram of each operating state).

FIG. 19 is a timing chart showing an example of the gate driving operation by the lower side gate driver 12L of the third embodiment. ), node voltage Vcp− (chain line), lower gate signal GL (small dashed line), and switch voltage Vsw (large dashed line). For convenience of explanation, it is assumed that charges have already been accumulated in the capacitor C31 by the gate driving operation before time t31.

Below, the gate driving operation by the lower gate driver 12L of the third embodiment will be described in detail with reference to FIGS. 15 to 19. FIG.

As in the first embodiment (FIG. 2) and the second embodiment (FIG. 8), the lower gate driver 12L of the third embodiment switches the lower transistor 11L from the off state to the on state. For example, when charging the gate capacitance CissL of the lower transistor 11L, the first phase is followed by the second phase.

In the lower gate driver 12L of the third embodiment, the first phase means that the switches SW32 and SW34 are both on as shown in FIGS. 15 and 19 (time t31 to t32), This refers to the operation phase in which both the switches SW31 and SW33 are in the off state.

In addition, in the lower gate driver 12L of the third embodiment, the second phase means that the switches SW31 and SW32 are both on as shown in FIGS. 16 and 19 (time t32 to t33), It refers to the operation phase in which both the switches SW33 and SW34 are in the off state.

First, in the first phase, as indicated by the dashed arrow in FIG. 15, the charging voltage Vcp of the capacitor C31 (=differential voltage between the node voltage Vcp+ and the node voltage Vcp-) is used to charge the gate capacitance CissL (=capacitor C31 discharge) is performed. In other words, part of the charge stored in the capacitor C31 is distributed to the gate capacitance CissL.

Therefore, in the first phase, as indicated by times t31 to t32 in FIG. 19, as the lower gate signal GL rises from the low level (≈PGND), the node voltage Vcp+ drops, and equilibrium occurs when GL=Vcp+. do. In addition, the node voltage Vcp- decreases to the negative potential as the node voltage Vcp+ decreases at time t31, and then converges to the ground potential. At this time, the charging voltage Vcp (=differential voltage between the node voltage Vcp+ and the node voltage Vcp−) is reduced by the charge distributed to the gate capacitance CissL.

When the lower gate signal GL exceeds the on-threshold voltage of the lower transistor 11L, the lower transistor 11L is turned on, so that the switch voltage Vsw becomes low level (≈PGND). Referring to FIG. 19, at time t31, the switch voltage Vsw drops to a negative potential ( = forward voltage drop of the body diode associated with the lower transistor 11L) to a low level (≈PGND).

Next, in the second phase, as indicated by the dashed arrow in FIG. 16, charging of the gate capacitance CissL is continued using the input voltage Vin. Therefore, the lower gate signal GL rises to the high level (≈Vin) as shown from time t32 to t33 in FIG. As a result, the on-resistance value of the lower transistor 11L further decreases, and the switch voltage Vsw is maintained at a low level (≈PGND).

In the second phase, the switches SW33 and SW34 are both off, so the capacitor C31 is not charged with the input voltage Vin. Referring to FIG. 19, when the node voltage Vcp+ rises to the input voltage Vin due to the switching from the first phase to the second phase, the node voltage Vcp- also rises with the same behavior. Therefore, the charging voltage Vcp (=differential voltage between the node voltage Vcp+ and the node voltage Vcp−) is maintained at substantially the same potential as at the time of switching from the first phase to the second phase.

On the other hand, when the lower gate driver 12L of the third embodiment switches the lower transistor 11L from the ON state to the OFF state, as in the first embodiment (FIG. 2) and the second embodiment (FIG. 8), In other words, when the gate capacitance CissL of the lower transistor 11L is discharged, the third phase is followed by the fourth phase.

In the lower gate driver 12L of the third embodiment, the third phase means that the switches SW32 and SW34 are both on as shown in FIGS. 17 and 19 (time t33 to t34), This refers to the operation phase in which both the switches SW31 and SW33 are in the off state.

In addition, in the lower gate driver 12L of the third embodiment, the fourth phase means that the switches SW33 and SW34 are both on as shown in FIGS. 18 and 19 (after time t34 or before time t31). indicates an operation phase in which both the switches SW31 and SW32 are in the off state.

First, in the third phase, as indicated by the dashed arrow in FIG. 17, the lower gate signal GL is used to charge the capacitor C31 (=discharge the gate capacitance CissL). That is, part of the charge stored in the gate capacitance CissL is distributed to the capacitor C31.

Therefore, in the third phase, the lower gate signal GL and the node voltage Vcp+ drop from the high level (≈Vin), and the node voltage Vcp- drops to the ground potential, as shown at times t33 to t34 in FIG. . At this time, the charging voltage Vcp (=differential voltage between the node voltage Vcp+ and the node voltage Vcp−) increases by the charge distributed from the gate capacitance CissL. However, in the third phase, the lower gate signal GL does not fall below the ON threshold voltage of the lower transistor 11L, and the lower transistor 11L is still in the ON state, so the switch voltage Vsw becomes low level (≈PGND). maintained.

Next, in the fourth phase, as indicated by the dashed arrow in FIG. 18, the discharge of the gate capacitance CissL continues toward the ground terminal PGND. Therefore, as shown after time t34 in FIG. 19, the lower gate signal GL drops to the low level (≈PGND), so the lower transistor 11L is turned off.

In FIG. 19, after time t34, the switch voltage Vsw changes from a low level (≈PGND) to a negative potential (= ), and then the switch voltage Vsw rises to a high level (≈Vin) by turning on the upper transistor 11H.

Also, in the fourth phase, the switches SW31 and SW32 are both off, so the charge accumulated in the capacitor C31 is not discharged toward the ground terminal PGND. Referring to FIG. 19, when the node voltage Vcp- drops to the ground potential with the switching from the third phase to the fourth phase, the node voltage Vcp+ also drops with the same behavior. Therefore, the charging voltage Vcp (=the differential voltage between the node voltage Vcp+ and the node voltage Vcp−) remains substantially the same as when the third phase is switched to the fourth phase.

By repeating the above series of gate driving operations, at least part of the charge is stored in the capacitor C31 when the gate capacitance CissL is discharged, and the charge stored in the capacitor C31 is used when the gate capacitance CissL is charged next time. can be done. Therefore, it is possible to reduce the gate loss (switching loss) associated with turning on/off the lower transistor 11L.

<Switching power supply>
FIG. 20 is a diagram showing a configuration example of a switching power supply. The switching power supply 1 of this configuration example has the aforementioned semiconductor device 10 and various discrete components (inductor L, capacitor C, and resistors R1 and R2) externally attached thereto.

The semiconductor device 10 is used as a so-called power supply controller IC, and has a controller 14 and a feedback terminal FB in addition to the aforementioned half-bridge output circuit 11, gate driver 12, and bootstrap circuit 13. FIG.

Outside the semiconductor device 10, the power supply terminal PVIN of the semiconductor device 10 is connected to the application end of the input voltage Vin. A switch terminal SW of the semiconductor device 10 is connected to a first end of the inductor L. As shown in FIG. A second end of the inductor L and a first end of the capacitor C are both connected to the application end of the output voltage Vout. A second end of the capacitor C is connected to ground. Resistors R1 and R2 are connected in series between the terminal to which the output voltage Vout is applied and the ground terminal. A connection node between the resistors R1 and R2 (=applying terminal of the feedback voltage Vfb) is connected to the feedback terminal FB of the semiconductor device 10 .

The inductor L and capacitor C described above together with the half-bridge output circuit 11 built in the semiconductor device 10 form a step-down switch output stage SWO. The switch output stage SWO rectifies and smoothes the square-wave switch voltage Vsw output from the switch terminal SW of the semiconductor device 10 to generate an output voltage Vout.

In the half bridge output circuit 11, the upper transistor 11H corresponds to an output element, and the lower transistor 11L corresponds to a synchronous rectification element. If a diode rectification method is used instead of the synchronous rectification method, the lower transistor 11L may be replaced with a diode. Also, the half-bridge output circuit 11 can be externally attached to the semiconductor device 10 .

The controller 14 generates the upper control signal SH and the lower control signal SL such that the feedback voltage Vfb (={R2/(R1+R2)}×Vout) input to the feedback terminal FB matches the target value. Complementarily turns on/off the transistor 11H and the lower transistor 11L. The term “complementary” here refers not only to the case where the on/off states of the upper transistor 11H and the lower transistor 11L are completely reversed, but also to the simultaneous off period (so-called dead period) to prevent through current. It should be understood in a broad sense as including the case where time) is provided.

It should be noted that the higher the drive frequency of the switching power supply 1, the greater the gate loss associated with turning on/off the upper transistor 11H and the lower transistor 11L. In view of this, it is desirable to apply any one of the first to third embodiments (FIGS. 2, 8, or 14) described above as the circuit configuration of the gate driver 12 to reduce the gate loss. I can say

<Summary>
The following provides a general description of the various embodiments described above.

For example, the gate driver disclosed in this specification includes a gate driving circuit configured to charge and discharge a gate capacitance of a transistor, and storing at least a portion of the charge when the gate capacitance is discharged. and a capacitor circuit configured to use at the time of next charging (first configuration).

In addition, in the gate driver having the first configuration, the capacitor circuit includes a capacitor and a switch, and the capacitor and the switch are configured to be connected in series between the gate and the main electrode of the transistor. A configuration (second configuration) may be used.

In the gate driver according to the second configuration, the gate drive circuit includes a first switch connected between a power supply terminal and the gate of the transistor, the gate of the transistor and the gate of the transistor. A configuration (third configuration) including a second switch configured to be connected to the main electrode may be employed.

In the gate driver according to the third configuration, the first end of the capacitor is connected to the first end of the switch, and the second end of the capacitor is connected to the main electrode of the transistor. a second end of the switch is connected to the gate of the transistor; a first end of the first switch is connected to the power supply terminal; The first terminals of the two switches are both connected to the gate of the transistor, and the second terminal of the second switch is connected to the gate of the transistor (fourth configuration). good.

In addition, the gate driver according to the third or fourth configuration has a first phase in which the switch is in an ON state and both the first switch and the second switch are in an OFF state when the gate capacitance is charged. After that, a second phase occurs in which the first switch is on and both the switch and the second switch are off. When the gate capacitance is discharged, the switch is on and the second phase is on. After a third phase in which both the first switch and the second switch are in an off state, a fourth phase in which the second switch is in an on state and both the switch and the first switch are in an off state; A configuration (fifth configuration) may be used.

In the gate driver according to the first configuration, the capacitor circuit includes a switch configured to be connected between a power supply end and an output node, and a switch connected between the output node and the main electrode of the transistor. A configuration (sixth configuration) may be employed in which a connected variable capacitor configured to switch a capacitance value is included, and the charged voltage of the variable capacitor is output from the output node to the gate drive circuit.

In the gate driver according to the sixth configuration, the gate drive circuit includes a first switch connected between the output node and the gate of the transistor, the gate of the transistor and the gate of the transistor. A configuration (seventh configuration) including a second switch configured to be connected to the main electrode may be employed.

In the gate driver according to the seventh configuration, when the gate capacitance is charged, the first switch is on, both the switch and the second switch are off, and the variable capacitor is the first capacitance. After entering the first phase, the first switch is in the ON state, the switch and the second switch are both in the OFF state, and the variable capacitor is a second capacitor smaller than the first capacitance value. When the gate capacitance is discharged, the first switch is on, both the switch and the second switch are off, and the variable capacitor has the first capacitance value. After the third phase, a fourth phase in which the first switch is in the off state, the switch and the second switch are both in the on state, and the variable capacitor has the first capacitance value ( 8th configuration).

In the gate driver according to the first configuration, the gate drive circuit includes a first switch configured to be connected between a power supply terminal and a first terminal of the capacitor circuit, and the switch of the capacitor circuit. a second switch configured to be connected between a first end and a gate of said transistor; and a second switch configured to be connected between said gate of said transistor and a second end of said capacitor circuit. A configuration (ninth configuration) may include a third switch and a fourth switch configured to be connected between the second end of the capacitor circuit and the main electrode of the transistor.

In the gate driver according to the ninth configuration, both the second switch and the fourth switch are in an ON state and both the first switch and the third switch are in an OFF state when the gate capacitance is charged. After the first phase, the gate When the capacitor is discharged, after a third phase in which both the second switch and the fourth switch are in an ON state and both the first switch and the third switch are in an OFF state, the third switch and the fourth switch are both on, and both the first switch and the second switch are off, in a fourth phase (tenth configuration).

Further, the semiconductor device disclosed in this specification includes a gate driver having any one of the first to tenth configurations, and the transistor configured to be turned on/off by the gate driver. configuration (eleventh configuration).

Further, a switching power supply disclosed in this specification includes: a semiconductor device having the eleventh configuration; and a switch output stage configured to generate an output voltage from an input voltage by switching driving of the transistor. (12th configuration).

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

1 switching power supply 10 semiconductor device 11 half bridge output circuit 11H upper transistor (NMOSFET)
11L Lower side transistor (NMOSFET)
12 gate driver 121 gate drive circuit 122 capacitor circuit 12H upper gate driver 12H1 PMOSFET
12H2 NMOSFET
12H3 Driver 12L Lower Gate Driver 12L1 PMOSFET
12L2 NMOSFET
12L3 Driver 13 Bootstrap Circuit 131 Capacitor 132 Switch 14 Controller C Capacitor C11, C21, C22, C31 Capacitor CissH, CissL Gate Capacitance DRV Driver FB Feedback Terminal L Inductor n1 Output Node PVIN Power Terminal R1, R2 Resistor SW Switch Terminal SW1, SW2 Switch SW11 Switch SW21 to SW24 Switch SW31 to SW34 Switch SWO Switch output stage VCAP Variable capacitor

Claims (12)

a gate drive circuit configured to charge and discharge the gate capacitance of the transistor;
a capacitor circuit configured to store at least part of electric charge when the gate capacitance is discharged and to utilize the electric charge at the next charging;
a gate driver. the capacitor circuit includes a capacitor and a switch;
2. The gate driver of claim 1, wherein the capacitor and the switch are configured to be connected in series between the gate and main electrode of the transistor. The gate drive circuit is configured to be connected between a first switch configured to be connected between a power supply terminal and the gate of the transistor, and the gate of the transistor and the main electrode. 3. The gate driver of claim 2, comprising a second switch that is switched. a first end of the capacitor is connected to a first end of the switch;
a second end of the capacitor is connected to the main electrode of the transistor;
a second end of the switch is connected to a gate of the transistor;
a first end of the first switch is connected to the power supply end;
both the second end of the first switch and the first end of the second switch are connected to the gate of the transistor;
a second end of the second switch is connected to the gate of the transistor;
4. The gate driver according to claim 3. When the gate capacitance is charged, after a first phase in which the switch is in the ON state and both the first switch and the second switch are in the OFF state, the first switch is in the ON state and the a second phase in which both the switch and the second switch are in an off state;
When the gate capacitance is discharged, after a third phase in which the switch is in the ON state and both the first switch and the second switch are in the OFF state, the second switch is in the ON state and the 5. The gate driver according to claim 3 or 4, wherein the switch and the first switch are both turned off in a fourth phase. The capacitor circuit includes a switch configured to be connected between a power supply terminal and an output node, and a switch configured to be connected between the output node and a main electrode of the transistor so that a capacitance value can be switched. 2 . The gate driver according to claim 1 , comprising a variable capacitor connected to said gate driver, and outputting the charged voltage of said variable capacitor from said output node to said gate drive circuit. The gate drive circuit is configured to be connected between a first switch configured to be connected between the output node and a gate of the transistor and between the gate and the main electrode of the transistor. 7. The gate driver of claim 6, comprising a second switch that is switched. During charging of the gate capacitance, after a first phase in which the first switch is in an ON state, both the switch and the second switch are in an OFF state, and the variable capacitor has a first capacitance value, the a second phase in which the first switch is in an ON state, both the switch and the second switch are in an OFF state, and the variable capacitor has a second capacitance value smaller than the first capacitance value;
When the gate capacitance is discharged, after a third phase in which the first switch is on, both the switch and the second switch are off, and the variable capacitor has the first capacitance value, 8. The gate driver according to claim 7, wherein a fourth phase is entered in which the first switch is off, both the switch and the second switch are on, and the variable capacitor has the first capacitance value. The gate drive circuit includes a first switch configured to be connected between a power supply terminal and a first end of the capacitor circuit, and between the first end of the capacitor circuit and the gate of the transistor. a second switch configured to be connected; a third switch configured to be connected between the gate of the transistor and a second end of the capacitor circuit; and the second switch of the capacitor circuit. 2. The gate driver of claim 1, comprising a fourth switch configured to be connected between an end and a main electrode of said transistor. During charging of the gate capacitance, after a first phase in which both the second switch and the fourth switch are in an ON state and both the first switch and the third switch are in an OFF state, the a second phase in which both the first switch and the second switch are in an ON state and the third switch and the fourth switch are both in an OFF state;
When the gate capacitance is discharged, after a third phase in which both the second switch and the fourth switch are in an ON state and both the first switch and the third switch are in an OFF state, the 10. The gate driver according to claim 9, wherein a fourth phase is entered in which both the third switch and the fourth switch are in an ON state and both the first switch and the second switch are in an OFF state. a gate driver according to any one of claims 1 to 10;
the transistor configured to be turned on/off by the gate driver;
A semiconductor device having a semiconductor device according to claim 11;
a switched output stage configured to generate an output voltage from an input voltage by switching driving the transistor;
A switching power supply having

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