JP2022181432A - Receiving device, method, and program - Google Patents

Abstract

To provide a receiving device, a method, and a program that can optimize a PLL circuit of the receiving device for the purpose of suppressing delay fluctuations due to IP packets and reducing delay.SOLUTION: A receiving device 1 according to the present disclosure includes: a PLL circuit 2 that receives a plurality of division packets and outputs a synchronization signal; a calculation unit 3 that calculates transmission speed of a received signal; and a control unit 4 that controls loop bandwidth of the PLL circuit 2 based on the calculated transmission speed.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a receiving device, method and program.

In recent years, due to the spread of IP transmission lines accompanying the digitization of broadcasting and the expansion of the use of the Internet, RTP (Real Time Transport Protocol) is used as a communication protocol in IPTV services, material transmission for broadcasting, and the like. Further, MPEG2-TS over IP is widely used in which MPEG2-TS is IP-packetized using RTP and transmitted over an IP transmission line network. When passing through an IP transmission line network, for example, unlike MPEG2-TS, which is transmitted by coaxial cables in the DVB-ASI signal format, delay fluctuations in IP packet arrival time occur. Therefore, by adding an RTP time stamp in RTP, the packet transmission timing in the transmitting device can be restored in the receiving device as well.

At this time, the receiving device needs to generate a clock signal synchronized with the RTP timestamp. However, when the clock signal is generated in the receiving device, there is a problem that fluctuations in arrival time of IP packets have an effect. One method for solving such problems is a method using a PLL (Phase Locked Loop) circuit. A method of suppressing jitter caused by fluctuations in IP packet arrival times is used by the loop bandwidth of the PLL circuit. Patent document 1 relates to a clock signal generation system that extracts a time stamp from a received packet and changes the output characteristics of a PLL circuit based on the difference between the extracted time stamp and a clock signal that is generated according to an input voltage. Techniques are disclosed.

JP 2015-002358 A

In order to suppress fluctuations in IP packet arrival times in the PLL circuit, it is necessary for the receiver to implement a narrowband PLL circuit. Therefore, it takes a long time to synchronize with the clock signal of the transmitter, resulting in a large stationary phase error. In addition, a large phase difference occurs in the process of synchronizing with the clock signal of the transmitting device, which may cause an increase in the amount of buffering in the receiving device and an increase in the amount of delay. Furthermore, due to the increasing demand for real-time communication, it is necessary to reduce the buffer capacity of the receiving device due to the need to reduce the amount of delay. Therefore, in the PLL circuit of the receiver, speeding up the synchronization time and reducing the stationary phase error and the phase difference in the synchronization process are required in order to cope with fluctuations in the IP packet arrival time and to reduce the amount of delay.

The present disclosure has been made to solve such problems, and is a receiving apparatus and method capable of optimizing a PLL circuit for the purpose of suppressing delay fluctuations due to IP packets and reducing delay. and to provide programs.

The receiving device according to the present disclosure includes a PLL circuit that receives a packet divided into a plurality of pieces and outputs a synchronization signal, a calculation unit that calculates the transmission speed of the received signal, and the PLL circuit based on the calculated transmission speed. a controller for controlling the loop bandwidth of the

The reception method according to the present disclosure includes the step of calculating the transmission speed of a received signal, and controlling the loop bandwidth of a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal based on the calculated transmission speed. the step of

The program according to the present disclosure is a process of calculating the transmission speed of a received signal, and based on the calculated transmission speed, receives a plurality of divided packets and outputs a synchronization signal. Controls the loop bandwidth of the PLL circuit. It is a receiving program that causes a computer to execute processing.

Advantageous Effects of Invention According to the present disclosure, it is possible to provide a receiving device, method, and program capable of optimizing the PLL circuit of the receiving device for the purpose of suppressing delay fluctuations due to IP packets and reducing delay.

1 is a configuration diagram of a receiving device according to Embodiment 1 of the present disclosure; FIG. FIG. 2 is a configuration diagram of a receiving device according to a second embodiment of the present disclosure; FIG. FIG. 11 is a configuration diagram of a receiving device according to Embodiment 3 of the present disclosure; Fig. 10 is a diagram showing IP packet arrival intervals without packet arrival fluctuations when the associated receiving device has a packet rate of 20 Mbps and 60 Mbps; Fig. 10 shows respective IP packet arrival intervals for packet rates of 20 Mbps and 60 Mbps when the associated receiving device fluctuates by 0.3 ms for the first packet arrival; FIG. 10 is a diagram showing respective jitter images for packet rates of 20 Mbps and 60 Mbps when the arrival of the first packet at the associated receiver fluctuates by 0.3 ms;

Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Also, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.

<Study history leading up to the idea of the receiving device according to the embodiment>
IP packets transmitted to the transmitting device are received by the receiving device via network devices such as routers and switches in a network such as an IP network. When an IP packet is congested with other packets in a network device, it is not transmitted and latency occurs. Packet arrival fluctuations occur due to this latency.

The associated receiving device comprises PLL circuits and buffers to receive IP-packetized MPEG2-TS using RTP. If the receiving device does not have a function of dynamically changing control according to the transmission rate, fluctuations in the output timing of packets in the subsequent stage of the buffer, ie, jitter, occur due to the output rate conditions of the transmitting device. At this time, the loop bandwidth of the PLL circuit is determined based on the jitter output at the low rate, which is the worst jitter value in the actual measurements. As a result, the PLL circuit has a narrow band, it takes a long time to synchronize with the clock signal of the transmitter, and the stationary phase error increases. In addition, a large phase difference occurs in the receiving device in the process of synchronizing with the clock signal of the transmitting device, which may cause an increase in the amount of buffering and an increase in the amount of IP packet delay.

FIG. 4 shows the arrival intervals at which IP packets are received by the associated receiving device without packet arrival fluctuations for packet rates of 20 Mbps and 60 Mbps. The horizontal axis of FIG. 4 is the time axis showing arrival of packets at each packet rate. The packet arrival interval without fluctuation is 0.525 ms when the packet rate is 20 Mbps, and 0.175 ms when the packet rate is 60 Mbps. The packet arrival interval is the packet arrival interval when MPEG2-TS packets are output using RTP.

FIG. 5 shows the respective IP packet arrival intervals for packet rates of 20 Mbps and 60 Mbps when the associated receiving device fluctuates by 0.3 ms for the first packet arrival. Since the packet arrival delay is 0.3 ms when the packet rate is 60 Mbps, the packet interval of 0.175 ms is shorter. Therefore, when the next packet arrives during the 0.3 ms delay, it becomes an operation of continuously outputting to the receiving side. On the other hand, when the packet rate is 20 Mbps, the packet arrival delay of 0.3 ms is greater than the packet interval of 0.525 ms, so there is no effect of the arrival delay on the packet that arrives next to the delayed packet.

FIG. 6 shows jitter images for packet rates of 20 Mbps and 60 Mbps when the first packet arrival at the associated receiver fluctuates by 0.3 ms. When the packet shown in FIG. 5 is input, a large jitter appears in the PLL circuit of the receiver when the first delayed packet is input at 60 Mbps. However, the jitter due to the delay of +0.3 ms gradually decreases in successively input packets. On the other hand, when the packet rate is 20 Mbps, jitter due to the delay of 0.3 ms appears between the first +0.3 ms delay packet and the next packet. Jitter with large amplitude appears.

In the above example, the case where the first packet arrives is 0.3 ms, but the case where the first packet arrives is 10 ms and 100 ms. As the amount of packets to be transmitted increases, the period and amplitude of jitter appear smaller when viewed from the PLL circuit of the receiver. That is, the appearance of fluctuations in the packet arrival interval changes depending on the IP packet transmission rate.

When the transmission rate is high, using the above properties, even if the loop bandwidth of the PLL circuit is increased to reduce the lock-in time, the steady-state phase error, or the phase difference until synchronizing with the transmission side, the PLL A receiving apparatus has been devised that can make the amount of jitter output from a circuit equal to that in the case of a low transmission rate.

<Embodiment 1>
The configuration of the receiving device 1 according to this embodiment will be described with reference to FIG. FIG. 1 is a configuration diagram of a receiving device 1 according to this embodiment. A receiver 1 includes a PLL circuit 2 , a calculator 3 and a controller 4 .

The PLL circuit 2 receives the divided packets and outputs a synchronization signal. The calculator 3 calculates the transmission speed of the received signal. The controller 4 controls the loop bandwidth of the PLL circuit 2 based on the transmission rate calculated by the calculator 3 .

According to the receiving device 1 of the present embodiment, it is possible to optimize the PLL circuit for the purpose of suppressing delay fluctuations due to IP packets and reducing delay.

<Embodiment 2>
The configuration of the receiving device 10 according to this embodiment will be described with reference to FIG. FIG. 2 is a configuration diagram of the receiving device 10 in this embodiment. The receiving device 10 includes a buffer/RTP payload extractor 11 , a PLL unit 12 , a transmission rate calculator 13 and a controller 14 . The receiving device 10 receives a packet that is divided into a plurality of packets and transmitted from a transmitting device (not shown). Packets received by the receiving device 10 are RTP packets, but are not limited to these, and receive various packets.

The buffer/RTP payload extraction unit 11 temporarily stores the received RTP packets. Further, the buffer/RTP payload extraction unit 11 outputs a signal generated in RTP or MPEG2-TS format at the timing of the RTP time stamp in the received RTP packet based on the RTP synchronization clock signal.

The PLL unit 12 outputs a clock signal, which is a synchronization signal of the RTP time stamp of the transmitting apparatus, from the RTP time stamp, which is the time stamp information in the received RTP packet. The transmission rate calculator 13 calculates the transmission rate of the received signal, typically using the packet rate of the received RTP packet.

Based on the transmission rate calculated by the control section 14 and the transmission rate calculation section 13, the loop bandwidth and buffer amount of the PLL section 12 are calculated. The control unit 14 controls the loop bandwidth and buffer amount of the PLL unit 12 based on the calculation result. If the calculated transmission speed is high, the control unit 14 may control the loop bandwidth of the PLL unit 12 to widen. Note that the loop bandwidth may also be referred to as a Loop Gain value.

When the delay amount of the IP packet is larger than the packet interval, the delay fluctuation of the IP packets does not follow the probability distribution, and the delayed packets are continuously input to the receiving side immediately after their arrival. Even on the same network and under the same conditions of packet input fluctuations, the appearance of jitter on the receiving side changes according to the packet rate of the input RTP packets. The receiving apparatus 10 in the present embodiment applies such properties and changes the loop bandwidth of the PLL unit 12 and the amount of buffering according to the packet rate of the input RTP packets, thereby reducing jitter. It realizes reduction and low latency.

<Embodiment 3>
The configuration of the receiving device 10 according to this embodiment will be described with reference to FIG. FIG. 3 is a configuration diagram of the receiving device 10 in this embodiment. The receiving device 10 includes a buffer 21, an RTP termination/time difference calculator 22, an RTP counter 23, a filter circuit 24, a transmission rate calculator 25, a filter controller 26, a D/A converter 27, a VCXO 28, and TS conversion/output control. A portion 29 is provided. The receiving device 10 receives a signal transmitted from a transmitting device (not shown).

An RTP packet transmitted from a transmitter and received via a transmission path is input to a buffer 21 and an RTP termination/time difference calculator 22 . Upon receiving the RTP packet, the RTP termination/time difference calculator 22 extracts the RTP timestamp from the input RTP packet. Also, the RTP termination/time difference calculator 22 takes out the RTP Time from the RTP counter 23 . The RTP termination/time difference calculator 22 calculates the time difference between the RTP timestamp and the RTP Time. After that, the RTP termination/time difference calculator 22 outputs the calculated time difference to the filter circuit 24 .

The RTP termination/time difference calculator 22 also extracts the RTP Sequence Number, which is the sequence number assigned to the received RTP packet. The RTP termination/time difference calculator 22 outputs the RTP Sequence Number together with the RTP timestamp to the transmission rate calculator 25 .

The transmission rate calculator 25 calculates the transmission rate by calculating the difference between the time stamp information extracted from the received packet and the sequence number assigned to the packet. That is, the transmission rate calculator 25 calculates the transmission rate, which is the transmission rate of the received RTP packets, from the difference value of RTP timestamp/RTP Sequence N between a plurality of RTP packets. The transmission rate calculator 25 outputs the calculated transmission speed (transmission rate) to the filter controller 26 .

The filter control unit 26 changes the coefficients of the loop filter circuit 24 based on the transmission rate of the RTP packets on the transmission line. The filter circuit 24 may have Nth order coefficients and each coefficient can be changed. When the coefficient is changed, the filter circuit 24 outputs the filtered time difference to the D/A converter 27 .

The D/A converter 27 converts the received digital signal of the RTP packet into an analog signal and outputs it to the VCXO 28 . The VCXO 28 changes the frequency of the output clock signal based on the signal voltage of the input RTP packet. The VCXO 28 synchronizes the RTP Time in the RTP counter 23 with the input RTP timestamp by changing the frequency of the output clock signal.

The RTP counter 23 increments the counter value using the input clock signal. Also, the RTP counter 23 updates the counter value to the RTP Time from the RTP termination/time difference calculator 22 at the timing of arrival of the first received RTP packet.

The TS conversion/output control unit 29 outputs the payload data of the RTP packet to the subsequent stage at the timing when the RTP timestamp of the RTP packet extracted from the buffer 21 and the RTP Time obtained by adding the Offset Time setting become the same value. do. By the operation described above, the Offset Time value becomes the delay amount in the buffer 21 .

According to the receiving device 10 of the present embodiment, it is possible to optimize the PLL circuit for the purpose of suppressing delay fluctuations due to IP packets and reducing delay.

<Other embodiments>
The receiving device 1 according to the present disclosure includes, for example, an embodiment as a receiving method. That is, the receiving method comprises the steps of: calculating the transmission rate of a received signal; and controlling the loop bandwidth of a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal based on the calculated transmission rate. Prepare.

In the above examples, the programs can be stored and provided to computers using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Non-transitory computer-readable media include, for example, magnetic recording media, magneto-optical recording media, CD-ROMs (Read Only Memory), CD-Rs, CD-R/Ws, and semiconductor memories. Examples of semiconductor memories include mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory). The program may also be supplied to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired channels, such as wires and optical fibers, or wireless channels.

The above program performs a process of calculating the transmission rate of a received signal and a process of controlling the loop bandwidth of a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal based on the calculated transmission rate. This is a receiving program that is executed by

It should be noted that the present disclosure is not limited to the above embodiments, and can be modified as appropriate without departing from the scope of the present disclosure.

1, 10 receiver 2 PLL circuit 3 calculation unit 4 control unit 11 buffer/RTP payload extraction unit 12 PLL units 13, 25 transmission rate calculation unit 14 control unit 21 buffer 22 RTP termination/time difference calculation unit 23 RTP counter 24 filter circuit 26 filter control unit 27 D/A converter 28 VCXO
29 TS conversion/output control unit

Claims (7)

a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal;
a calculation unit that calculates the transmission speed of the received signal;
a control unit that controls the loop bandwidth of the PLL circuit based on the calculated transmission rate;
a receiving device. If the calculated transmission rate is high, the control unit controls to widen the loop bandwidth of the PLL circuit.
The receiving device according to claim 1. The control unit controls the amount of buffer provided in the receiving device based on the calculated transmission rate.
3. The receiving device according to claim 1 or 2. The calculation unit calculates the transmission speed by calculating a difference between a plurality of packets using time stamp information extracted from the received packet and a sequence number assigned to the packet.
The receiving device according to any one of claims 1-3. The packet received by the calculation unit is an RTP packet,
5. The receiving device according to claim 4. calculating the transmission rate of the received signal;
a step of controlling a loop bandwidth of a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal based on the calculated transmission rate;
receiving method. a process of calculating a transmission speed of a received signal;
a process of controlling the loop bandwidth of a PLL circuit that receives a plurality of divided packets and outputs a synchronization signal based on the calculated transmission rate;
A receiving program that causes a computer to execute

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