JP2022175446A - Method of manufacturing semiconductor package, semiconductor package, semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

To provide a method for obtaining a semiconductor package which can be stably joined by a method accompanied by high-temperature heating, to a member which warps to form a convex curved shape on a surface side where the semiconductor package is joined at high temperature.SOLUTION: A method of manufacturing a semiconductor package comprises: arranging a semiconductor member 3 on a substrate 2 including glass cloth; and forming a sealing resin layer 4 for sealing the semiconductor member 3 on the substrate 2 by a method of molding the sealing resin layer while heating thermosetting sealing resin and thereby forming a sealing structure 1 which has the substrate 2, the semiconductor member 3, and the sealing resin layer 4. The sealing structure 1 is so formed as to warp to form the convex curved shape on the side of the sealing resin layer 4 at 260°C.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a method of manufacturing a semiconductor package, a semiconductor package, a semiconductor device, and a method of manufacturing a semiconductor device.

As the size and thickness of semiconductor packages are reduced, there are cases where warpage occurs during mounting on a motherboard or the like, or during the semiconductor package assembly process. Therefore, for example, Patent Document 1 discloses a method of temporarily fixing a warp correction substrate to the surface of a sealing material of a semiconductor package, reflow-mounting the semiconductor package, and then removing the warp correction substrate in order to suppress warpage. Patent Document 2 discloses a method of laminating a first resin film layer containing a filler and a second resin film layer having a filler content lower than that of the first resin film layer to reduce the amount of warpage deformation. .

JP 2016-072254 A JP 2016-012713 A

A semiconductor package having a substrate and a semiconductor chip and a sealing resin layer provided on one surface of the substrate is slightly bent so as to form a convex curved shape at room temperature toward the substrate side or the sealing resin layer side. sometimes against Warping in which a convex curved shape is formed on the substrate side is called "smile warping", and warping in which a convex curved shape is formed on the semiconductor chip and sealing resin layer side is called "crisis". It is sometimes called "warp".

A member on which a semiconductor package is mounted often warps at a high temperature such that a convex curved shape is formed on the side opposite to the surface on which the semiconductor package is mounted. At high temperatures, the semiconductor package to be mounted may warp to form a convex curved shape, and the direction of the warp is different from the direction of the warp of the semiconductor package, which impairs the stability of the connection. There is concern that it will be easy. For example, when manufacturing a package-on-package type semiconductor device comprising a bottom package and a top package, a certain type of bottom package may warp toward the top package at high temperatures, and the direction of warpage is the direction of the top package. A stable connection may be easily compromised due to the misalignment of the warp direction.

Therefore, the present disclosure is to stably join a member having a property of warping so that a convex curved shape is formed on the surface side to which the semiconductor package is joined at high temperature by a method involving heating at high temperature. To provide a method for obtaining a semiconductor package capable of

One aspect of the present disclosure is to dispose a semiconductor member having a semiconductor chip on a substrate including a glass cloth, and heat a thermosetting sealing resin to form a sealing resin layer that seals the semiconductor member. forming on the substrate by a method comprising molding while forming a semiconductor package, thereby forming an encapsulation structure having the substrate, the semiconductor member, and the encapsulation resin layer. I will provide a. The sealing structure is formed so as to warp at 260° C. so as to form a convex curved shape on the sealing resin layer side.

Another aspect of the present disclosure includes a substrate including glass cloth, a semiconductor member mounted on the substrate, and a sealing resin layer formed on the substrate and sealing the semiconductor member. The Company provides semiconductor packages. The semiconductor package warps at 260° C. so that a convex curved shape is formed on the sealing resin layer side.

In the above method or semiconductor package according to one aspect of the present disclosure, the glass cloth may include S-glass fibers, T-glass fibers, or both. In the above method or semiconductor package according to one aspect of the present disclosure, the storage modulus of the substrate at 260° C. may be 10 GPa or more.

Yet another aspect of the present disclosure relates to a package-on-package type semiconductor device including a bottom package and a top package, which are joined together. The top package is the above semiconductor package, and the bottom package warps at 260° C. so that a convex curved shape is formed on the top package side.

Yet another aspect of the present disclosure manufactures a package-on-package type semiconductor device including bonding a top package to a bottom package by a method including heating the top package to 200° C. or higher. provide a way. The top package is the above semiconductor package, and the bottom package warps at 260° C. so that a convex curved shape is formed on the top package side.

According to the present disclosure, a member that warps at a high temperature so that a convex curved shape is formed on the surface side to which the semiconductor package is bonded is stably bonded by a method involving heating at a high temperature. A method is provided for obtaining a capable semiconductor package.

1A-1D are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor package; 1A-1D are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor package; 1A-1D are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor package; 1A-1D are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor package; FIG. 4 is a cross-sectional view showing an example of a sealing structure warped at 260° C.;

Hereinafter, embodiments for implementing the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, the constituent elements (including element steps and the like) are not essential unless otherwise specified. The same applies to numerical values and their ranges, which do not limit the present disclosure.

In the present disclosure, the numerical range indicated using "-" includes the numerical values before and after "-" as the minimum and maximum values, respectively.

In the numerical ranges described step by step in the present disclosure, the upper limit or lower limit of one numerical range may be replaced with the upper or lower limit of another numerical range described step by step. . Moreover, in the numerical ranges described in the present disclosure, the upper or lower limits of the numerical ranges may be replaced with the values shown in the examples.

In the present disclosure, each component may contain multiple types of applicable substances. When there are multiple types of substances corresponding to each component in the composition, the content rate or content of each component is the total content rate or content of the multiple types of substances present in the composition unless otherwise specified. means quantity.

In the present disclosure, the term "layer" includes not only the case where the layer is formed in the entire region when observing the region where the layer exists, but also the case where it is formed only in part of the region. included.

In the present disclosure, the term "laminate" indicates stacking layers, and two or more layers may be bonded, or two or more layers may be detachable.

When embodiments are described in the present disclosure with reference to drawings, the configurations of the embodiments are not limited to the configurations shown in the drawings. In addition, the sizes of the members in each drawing are conceptual, and the relative relationship between the sizes of the members is not limited to this.

1, 2, 3 and 4 are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor package. This method consists of placing a plurality of semiconductor members 3 on one main surface 2S1 of the substrate 2 as shown in FIG. 4 on the substrate 2, thereby forming the encapsulation structure 1 having the substrate 2, the semiconductor member 3 and the encapsulation resin layer 4, and dividing the encapsulation structure 1 as shown in FIG. thereby forming a semiconductor package 10 shown in FIG. 4 including one or more semiconductor members 3 . The sealing structure 1 is formed so as to warp toward the sealing resin layer 4 at 260°C.

Substrate 2 may comprise an insulating substrate comprising a resin layer and a glass cloth embedded within the resin layer. An insulating substrate including a resin layer and glass cloth is formed, for example, from one or more layers of prepreg including glass cloth and a resin composition impregnated in the glass cloth. In that case, the resin layer of the board|substrate 2 contains the hardened|cured material of a thermosetting resin composition. The thermosetting resin composition contained in the prepreg may be in a semi-cured B-stage state.

The substrate 2 may be a coreless substrate or a wiring substrate having an insulating substrate and wiring connected to the semiconductor member 3 . The wiring board is formed of, for example, a metal-clad laminate having an insulating substrate and metal foils laminated on both sides thereof.

A metal-clad laminate is formed, for example, by stacking 1 to 20 sheets of prepreg, placing a metal foil such as copper foil or aluminum foil on one or both sides of the laminate, and heating and pressing the entire laminate. be. For heating and pressing, for example, multi-stage presses, multi-stage vacuum presses, continuous molding, autoclave molding machines can be used. The heating and pressing conditions for forming the metal clad laminate are, for example, a temperature of 100 to 250° C., a pressure of 0.2 to 10 MPa, a temperature increase rate of 1 to 10° C./min, and a heating time of 0.1 to 5 hours. may be A multilayer board can also be produced by laminating a prepreg and an inner-layer wiring board.

The glass cloth included in the substrate 2 may contain S-glass fibers, T-glass fibers, or both. A substrate containing a glass cloth containing these glass fibers can particularly easily form the sealing structure 1 that warps toward the sealing resin layer 4 at 260°C.

The thickness of the glass cloth may be 5-100 μm, 5-80 μm, or 5-50 μm. From the viewpoint of heat resistance, moisture resistance, processability, etc., the glass cloth may be surface-treated with a silane coupling agent or the like, or may be mechanically opened.

The thermosetting resin composition for forming the resin layer of the substrate 2 can be one commonly used for forming substrates on which semiconductor chips are mounted. For example, the thermosetting resin composition may contain a polyimide and a thermoplastic elastomer having an acid anhydride group. The polyimide may be a siloxane-modified polyimide having siloxane groups. The thermoplastic elastomer having acid anhydride groups may be, for example, a maleic anhydride-modified hydrogenated styrene-butadiene copolymer elastomer. Alternatively, the thermosetting resin composition may comprise an amine compound with two primary amino groups, an amine compound with acidic substituents, and a maleimide compound with two N-substituted maleimide groups.

The thermosetting resin composition for forming the resin layer of the substrate 2 may contain at least one phosphorus-containing compound selected from phosphonium salts and phosphine-Lewis acid complexes. The thermosetting resin composition may contain at least one thermosetting resin of an epoxy resin or a cyanate resin. The thermosetting resin composition may further contain an inorganic filler. The inorganic filler may be silica particles, for example.

The thickness of the substrate 2 may be, for example, 200 μm or less, 50-200 μm, 50-150 μm, or 50-100 μm.

If the storage elastic modulus of the substrate 2 at 260°C is high, there is a tendency that the sealing structure 1 is likely to be warped at 260°C so as to form a convex curved shape toward the sealing resin layer 4 side. Therefore, for example, the storage elastic modulus of the substrate 2 at 260° C. may be 10 GPa or more. The upper limit of the storage modulus of the substrate 2 at 260° C. is not particularly limited, but may be 20 GPa, for example.

The semiconductor member 3 illustrated in FIG. 1 has a laminated structure including two semiconductor chips 31 and 32 . The semiconductor member 3 includes an adhesive layer 31A interposed between the semiconductor chip 31 of the first layer and the substrate 2, and an adhesive layer 32A interposed between the semiconductor chip 31 of the first layer and the semiconductor chip 32 of the second layer. and The semiconductor member may be a laminate including two or more layers of semiconductor chips like the semiconductor member 3 in FIG. 1, or may have a single layer of semiconductor chips. The number of semiconductor chips forming one semiconductor member may be 1-4 or 1-2. The semiconductor chips 31 and 32 may be silicon chips, for example. The thickness of each of the semiconductor chips 31 and 32 may be, for example, 250 μm or less, 20-250 μm, 20-100 μm, or 20-70 μm.

The adhesive layers 31A and 32A may be layers formed from an adhesive containing a thermosetting component, for example. The adhesive that forms the adhesive layers 31A and 32A may contain, for example, an epoxy resin, a curing agent, and a curing accelerator. The thickness of the adhesive layers 31A and 32A may be, for example, 100 μm or less, 5-100 μm, 5-80 μm, or 5-60 μm. The adhesive layers 31A and 32A may not be provided.

The total thickness of the semiconductor chips 31 and 32 and the adhesive layer 31A or 32A may be, for example, 255 μm or less, 25-255 μm, 25-150 μm, or 25-80 μm.

The thickness of the semiconductor member 3 may be, for example, 300 μm or less, 25-300 μm, 25-250 μm, or 25-200 μm. The thickness of the semiconductor member 3 means the sum of the thickness of the semiconductor chips 31 and 32 and the thickness of the adhesive layers 31A and 32A.

Wires may be provided to connect the semiconductor chips 31 and 32 and the wiring of the substrate 2 . The semiconductor chips 31 and 32 may be flip-chip mounted. In that case, between the semiconductor chip 31 on the first layer and the wiring of the substrate 2, and between the semiconductor chip 32 on the second layer and the semiconductor chip 31 on the first layer. There may be solder balls between and there may be capillary underfill (CUF) or underfill introduced by mold underfill.

For the semiconductor member 3, for example, a semiconductor chip 31 of the first layer and a chip with an adhesive layer having an adhesive layer 31A are arranged on the substrate 2, and then a semiconductor of the second layer is placed on the semiconductor chip 31 of the first layer. It is arranged on one main surface 2S1 of the substrate 2 by a method including arranging a chip 32 and a chip with an adhesive layer having an adhesive layer 32A. In this method, the semiconductor chip 31 may be thermocompression bonded to the substrate 2 via the adhesive layer 31A, and the semiconductor chip 32 may be thermocompression bonded to the underlying semiconductor chip 31 via the adhesive layer 32A. For this purpose, a chip with an adhesive layer having the semiconductor chip 31 and a chip with an adhesive layer having the semiconductor chip 32 may be stacked and then thermocompression bonded together. Alternatively, the semiconductor chip 31 of the first layer may be thermocompression bonded to the substrate 2 via the adhesive layer 31A, and then the semiconductor chip 32 of the second layer may be thermocompressed to the semiconductor chip 31 via the adhesive layer 32A. The temperature for thermocompression bonding (hereinafter also referred to as “mounting temperature”) may be, for example, 60 to 150°C. When the mounting temperature is 60° C. or higher, good adhesion between the semiconductor chip 31 and the substrate 2 can be easily ensured. When the mounting temperature is 150° C. or less, excessive bleeding out of the adhesive layer due to thermocompression bonding can be suppressed. From a similar point of view, the mounting temperature may be 70 to 140.degree. C. or 80 to 130.degree.

After the semiconductor member 3 is placed on the substrate 2, the adhesive layers 31A and 32A may be semi-cured or cured by heating the semiconductor member 3, if necessary. The heating temperature therefor may be, for example, 100 to 200.degree. C. or 110 to 130.degree. The heating temperature may be, for example, raised to 80 to 200° C. over 10 minutes to 1 hour, or may be raised to 100 to 150° C. over 20 minutes to 50 minutes. After raising the temperature to 100 to 200° C., the semiconductor member 3 may be heated for 10 to 120 minutes. In order to facilitate removal of air bubbles between the substrate or semiconductor chip and the adhesive layer, the semiconductor member 3 may be heated under a pressurized environment. When the adhesive layers 31A and 32B are semi-cured, the thermal history during the formation of the encapsulating resin layer following this step and possibly post-curing can further cure the adhesive layers. For example, an oven such as a generally commercially available clean oven can be used for heating to harden or semi-harden the adhesive layers 31A and 32A.

After the semiconductor member 3 is placed on the substrate 2, a sealing resin layer 4 for sealing the semiconductor member 3 is formed on one main surface 2S1 of the substrate 2 as shown in FIG. , the sealing structure 1 having the semiconductor member 3 and the sealing resin layer 4 is formed. The semiconductor member 3 is embedded inside the sealing resin layer 4 to be formed. The encapsulating resin layer 4 can be formed by a method including molding while heating a thermosetting encapsulating resin in a mold. For example, the substrate 2 and the semiconductor member 3 arranged on the substrate 2 may be placed in a mold and molded while heating the sealing resin in the mold. The molding method may be, for example, compression molding or transfer molding. The heating temperature for molding the sealing resin may be, for example, 110 to 200.degree. C. or 150 to 180.degree.

In the case of compression molding, for example, a sealing resin is melted by heating in a depressurized mold. The speed at which the inside of the mold is decompressed, that is, the decompression speed tends to decrease as the decompression progresses. When the pressure drop becomes 5 torr or less per second, it is considered that the decompression limit pressure has been reached, and the time from the initial pressure at the start of decompression to reaching the decompression limit pressure is defined as the "decompression limit pressure reaching time". be. The pressure reduction speed can be defined by the following formula (1).
(Decompression rate) = (initial pressure - decompression limit pressure) / (decompression limit pressure reaching time) (1)
The unit of initial pressure and decompression limit pressure is "torr", and the unit of decompression limit pressure reaching time is "second". The vacuum rate in compression molding may be 10 torr/sec to 350 torr/sec, 50 torr/sec to 330 torr/sec, or 150 torr/sec to 310 torr/sec.

The thickness of the sealing resin layer 4 may be, for example, 450 μm or less, 150-450 μm, or 200-400 μm. The thickness of the encapsulating resin layer 4 may be greater than the thickness of the substrate 2 .

The thickness of the sealing structure 1 may be, for example, 650 μm or less, 200-650 μm, or 300-500 μm.

A sealing structure 1 having a substrate 2, a semiconductor member 3, and a sealing resin layer 4 is formed at 260° C. so that a convex curved shape is formed on the sealing resin layer 4 side, as shown in FIG. Warp. When the sealing structure 1 is placed on the plane P so that the substrate 2 is in contact with the plane P, and the sealing structure 1 is heated to 260° C. in that state, the sealing resin layer 4 of the substrate 2 is The sealing structure 1 warps so that the central portion of the main surface 2S2 on the opposite side is separated from the plane P. At this time, the maximum value of the distance between the central portion of the main surface 2S2 and the plane P is defined as the warp amount of the cry warp. The sealing structure 1 that exhibits such cry warp at a high temperature of 260°C can be obtained by using, for example, a glass cloth containing S glass fiber, T glass fiber, or both, and a base that exhibits a large storage modulus at 260°C. It can be formed by at least one method selected from using the material 2 and increasing the ratio of the volume of the sealing resin layer 4 to the volume of the substrate 2 .

The encapsulating resin for forming the encapsulating resin layer 4 may be selected from those commonly used for encapsulating semiconductor chips, and may be, for example, an epoxy resin composition. The sealing resin may be in the form of granules (cylindrical granules) or powder, for example. The epoxy resin composition may contain an epoxy resin and, if necessary, a curing agent, a coupling agent, a curing accelerator, a filler, a coloring agent, and other additives. The sealing resin, which is a powdery powder, is formed into a powder by, for example, pulverizing agglomerates obtained by cooling a melt-kneaded product obtained by a mixing roll, an extruder, or the like, and optionally sieving the powder accordingly. The sealing resin, which is a granule-like powder, can be obtained, for example, by a method in which a melt-kneaded material is extruded through a small hole into strands and cut. The powder obtained may be sieved if desired.

The sealing resin layer 4 may be post-cured by further heating the formed sealing structure 1 . For heating (heating and keeping) for post-curing, for example, an oven such as a generally commercially available clean oven can be used. The heating temperature for post-curing the sealing resin layer 4 may be, for example, 110 to 200.degree. C. or 150 to 180.degree. The heating time for post-curing the sealing resin layer 4 may be, for example, 30 minutes to 7 hours, or 1 hour to 6 hours.

As shown in FIG. 3, the encapsulation structure 1 is divided as necessary, thereby obtaining the semiconductor package 10 shown in FIG. 4 including one or more semiconductor members 3. FIG. The sealing structure 1 is split, for example by cutting with a rotary blade 7 . For cutting the sealing structure 1, a commercially available cutting device such as a dicer to which a rotary blade can be attached can be used. Examples of commercially available dicing saws include full-automatic dicing saw 6000 series and semi-automatic dicing saw 3000 series manufactured by DISCO Corporation. Examples of commercially available blades include dicing blade NBC-ZH05 series and NBC-ZH series manufactured by DISCO Corporation. A laser may be used to cut the sealing structure 1 instead of the rotating blade. As an example of a commercially available laser cutting device, there is a fully automatic laser saw 7000 series manufactured by DISCO Corporation.

As with the sealing structure 1, the semiconductor package 10 manufactured by the method exemplified above is warped at 260° C. so that a convex curved shape is formed toward the sealing resin layer 4 side. The amount of warpage of the semiconductor package 10 at 260° C. may be, for example, 10 μm or more, 20 μm or more, 30 μm or more, 40 μm or more, or 50 μm or more, or may be 100 μm or less, 90 μm or less, or 80 μm or less. Here, the amount of warpage is measured when the semiconductor package 10 is placed on a flat surface with the substrate 2 in contact with the flat surface, and the semiconductor package is heated to 260° C. in that state. It means the maximum value of the distance from the main surface 2S2 on the opposite side.

The semiconductor package 10 can be used, for example, as a top package of a package-on-package type semiconductor device including a bottom package and a top package. In particular, when the bottom package is warped at 260° C. so that a convex curved shape is formed on the top package side, that is, when the semiconductor package exhibits cry warp, since the warp directions of the top package and the bottom package are the same, A stable connection is easily maintained. For example, a fan-out semiconductor package having a semiconductor chip and a rewiring layer provided on the circuit surface of the semiconductor chip tends to exhibit cry warpage at high temperatures.

A package-on-package type semiconductor device can be manufactured, for example, by a method including bonding a top package to a bottom package by a method including heating the top package to 200° C. or higher. The heating temperature for bonding may be, for example, 300° C. or less.

Although the embodiments of the semiconductor package and the manufacturing method thereof have been described above, the present disclosure is not limited to the embodiments illustrated above, and various modifications are possible without departing from the gist of the disclosure.

EXAMPLES Hereinafter, the present invention will be described more specifically with reference to Examples. However, the present invention is not limited to these examples.

1. Sealing resin (epoxy resin composition)
1-1. The following materials were prepared.
(a) Epoxy resin E1: biphenyl aralkyl type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., product name: NC-3000, epoxy equivalent: 280 g / eq),
・ E2: Biphenyl type epoxy resin (manufactured by Mitsubishi Chemical Corporation, product name: YX-4000, epoxy equivalent: 196 g / eq, melting point: 106 ° C.)
(b) Curing agent H1: Biphenyl aralkyl-type phenol resin (manufactured by Meiwa Kasei Co., Ltd., product name: MEHC-7800, hydroxyl equivalent: 106 g / eq, softening point: 66 ° C.)
・ H2: Trisphenylmethane type phenol resin (manufactured by Air Water Inc., product name: HE910-10, hydroxyl equivalent: 100 g / eq, softening point: 83 ° C.)
(c) Curing accelerator A1: adduct of triphenylphosphine and 1,4-benzoquinone (d) inorganic filler (filler)
・ F1: Silica filler with an average particle size of 0.6 μm (manufactured by Admatechs Co., Ltd., product name: SO-25HV)
・ F2: Silica filler with an average particle size of 9.9 μm (manufactured by Denka Co., Ltd., product name: FB-302X)
(e) Silane coupling agent C1: N-phenyl-3-aminopropyltrimethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., product name: KBM-573)
・C2: 3-glycidoxypropyltriethoxysilane (manufactured by Shin-Etsu Chemical Co., Ltd., product name: KBM-403)
(f) pigment (colorant)
・ P1: Carbon black (manufactured by Mitsubishi Chemical Corporation, product name: MA600MJ)

1-2. Preparation of epoxy resin composition 42 parts by mass of epoxy resin E1, 58 parts by mass of epoxy resin E2, 50 parts by mass of curing agent H1, 30 parts by mass of curing agent H2, 2 parts by mass of curing accelerator A1, silane coupling 7 parts by mass of agent C1, 5 parts by mass of silane coupling agent C2, 4 parts by mass of pigment P1, and inorganic fillers F1 and F2 (F1:F2=1:9 (mass ratio)) are mixed by a mixer. Then, the mixture was melt-kneaded by a kneader heated to 110°C. The total proportion of inorganic fillers was 77.5% by volume with respect to the total volume of the mixture. An epoxy resin composition, which is a kneaded product in a molten state, was supplied to a cylindrical outer peripheral portion having a plurality of small holes. The epoxy resin composition melted and extruded through the small holes was cooled and pulverized to obtain a powder of the epoxy resin composition.

1-3. Preparation of Sample for Evaluation Measurement of Encapsulating Resin A test piece for measuring the linear expansion coefficient and storage elastic modulus was prepared from the encapsulating resin by molding and curing using a transfer molding machine. Molding and curing were performed under conditions of a molding temperature of 175° C. and a molding time of 90 seconds. The specimens were post-cured by heating at 175°C for 5 hours. Using the post-cured test piece, the linear expansion coefficient and storage modulus were measured according to the following procedures. Table 1 shows the measurement results.

Coefficient of linear expansion (α1, α2)
TMA high precision two-sample thermal analysis (manufactured by Seiko Instruments Inc., product name: SS6100) was used under the conditions of a load of 10 g and a temperature increase rate of 5° C./min. A coefficient of linear expansion α was calculated from the measurement results by the following equation.
α=l/(L・Δt)
L = length of long side of test piece at room temperature (25°C) (mm)
l = elongation (mm)
Δt = measured temperature difference (°C)
The linear expansion coefficient α between the two measurement temperatures of 80° C. and 100° C. is α1, and the linear expansion coefficient α between the two measurement temperatures of 200° C. and 230° C. is α2.

Storage modulus The dynamic viscoelasticity of the test piece was measured using a dynamic viscoelasticity measuring device RDSII manufactured by Rheometrics under the conditions of frequency: 1 Hz, temperature range: 30 to 300 ° C., heating rate: 5 ° C./min. It was measured. From the measurement results, the storage modulus at 30°C or 260°C was determined.

Mold Shrinkage Ratio The molding shrinkage ratio (%) of the sealing resin was measured by the following procedure.
(1) Using a mold with dimensions of 127 mm length × 6.4 mm height × 12.7 mm width at room temperature (25 ° C.), epoxy was molded by transfer molding under the conditions of 180 ° C., 90 seconds, and 6.9 MPa. An as-molded test piece was produced from the resin composition. The as-molded specimens were post-cured by heating at 175° C. for 5 hours.
(2) The test piece was cooled to room temperature (25° C.), after which the dimensions of the test piece were measured with vernier calipers. Test pieces 1 and 2 were produced under the same molding conditions, and their dimensions were measured.
(3) From the dimensions of the test piece measured at room temperature and the dimensions of the mold measured at room temperature, the mold shrinkage rate (%) was calculated by the following formula. In the following formula, D1 is the lengthwise dimension (mm) of the mold used for molding the test piece 1, d1 is the lengthwise dimension (mm) of the test piece 1, and D2 is the lengthwise dimension of the test piece 2. d2 is the dimension (mm) in the length direction of the mold used for molding, and d2 is the dimension (mm) in the length direction of the test piece 2. Table 1 shows the determined molding shrinkage.

2. Substrate 2-1. Synthesis of siloxane-modified polyimide In a reaction vessel with a volume of 2 liters that can be heated and cooled with a thermometer, a stirrer, and a water meter with a reflux condenser, both terminal amino-modified siloxane compounds (manufactured by Shin-Etsu Chemical Co., Ltd., trade name : X-22-161A, functional group equivalent of amino group: 800 g/mol) 72 g, bis(4-maleimidophenyl)methane (manufactured by K.I. Kasei Co., Ltd., trade name: BMI) 252 g, and propylene glycol monomethyl ether 270 g was added. A reaction was carried out at 110° C. for 3 hours to obtain a polyimide solution containing siloxane-modified polyimide.

2-2. Preparation of prepreg and substrate Example 1
A polyimide solution containing 80 parts by mass of siloxane-modified polyimide, 20 parts by mass of a thermoplastic elastomer (Tuftec (registered trademark) M1913, maleic anhydride-modified hydrogenated styrene-butadiene copolymer resin, Asahi Kasei Chemicals Co., Ltd.), and 100 parts by mass. Part inorganic filler (SC2050-KNK (trade name), spherical fused silica, Admatechs Co., Ltd., average particle size: 0.5 μm) and methyl ethyl ketone as a solvent were mixed to obtain a total concentration of components other than the solvent. A uniform varnish was produced with 55% by weight of This varnish is impregnated into a T-glass cloth (IPC product number #1017, Nitto Boseki Co., Ltd.), and the solvent is removed by heating at 130 ° C. for 10 minutes, so that the content of the thermosetting resin composition is 70% by mass. Got some prepreg. Two layers of the obtained prepreg were laminated, and the laminate was heated and pressed to cure the thermosetting resin composition, thereby producing a coreless substrate having an area of 240×74 mm ² and a thickness of 100 μm.

Comparative example 1
A prepreg having a thermosetting resin composition content of 72% by mass was produced in the same manner as in Example 1, except that the T glass cloth was replaced with an E glass cloth (IPC product number #1017, Nitto Boseki Co., Ltd.). , a coreless substrate was produced using this.

2-3. Substrate Evaluation The linear expansion coefficient and storage elastic modulus of the obtained coreless substrate were measured by the following procedure. Table 1 shows the measurement results.
Coefficient of linear expansion (α1, α2)
A test piece having a length of 30 mm, a width of 5 mm, and a thickness of 100 μm was cut from the coreless substrate. The coefficient of linear expansion of the test piece is measured twice continuously under tensile conditions of a load of 10 g and a heating rate of 5 ° C./min using TMA high-precision two-sample thermal analysis (manufactured by Seiko Instruments Inc., product name: SS6100). did. A coefficient of linear expansion α was calculated from the second measurement result by the following equation.
α=l/(L・Δt)
L = length of long side of test piece at room temperature (25°C) (mm)
l = elongation (mm)
Δt = measured temperature difference (°C)
The linear expansion coefficient α between the two measurement temperatures of 28°C and 32°C is α1, and the linear expansion coefficient α between the two measurement temperatures of 258°C and 2620°C is α2. Table 1 shows the measurement results.

Storage Elastic Modulus A test piece having a length of 30 mm, a width of 5 mm, and a thickness of 100 μm was cut out from the coreless substrate of Example 1 or Comparative Example 1. The dynamic viscoelasticity of the test piece was measured using a dynamic viscoelasticity measuring device RDSII manufactured by Rheometrics under the conditions of frequency: 10 Hz, temperature range: 30 to 300°C, and heating rate: 5°C/min. From the measurement results, the storage modulus at 30°C or 260°C was obtained.

3. Production and Evaluation of Semiconductor Package On the coreless substrate of Example 1 or Comparative Example 1, a test dummy chip (thickness: 70 μm) with a die attach film (area: 10×5 mm ² , thickness: 10 μm) was attached. Using a die bonder (manufactured by Fasford Technology Co., Ltd., product name: DB830plus+), two layers are laminated in the thickness direction of the coreless substrate, and two semiconductor members, which are laminated bodies composed of two layers of dummy chips, are formed. formed. Similarly, a total of 60 sets of two semiconductor members were formed on the coreless substrate.

A sealing structure having a coreless substrate, a semiconductor member, and a sealing resin layer formed by forming a sealing resin layer (thickness: 290 μm) for sealing a semiconductor member on a coreless substrate by compression molding of the epoxy resin composition described above. got a body The compression molding conditions were a molding temperature of 175° C., a molding time of 120 seconds, and a decompression rate of 90 torr/second. A compression device (manufactured by TOWA Co., Ltd., product name: PMC1040-S) was used for compression molding.

The sealed structure was cut using a full-auto dicer (DAD3350, rotating blade, manufactured by Disco Co., Ltd.) into individual pieces each having a size of 15×15 mm ² and containing two dummy chip semiconductor members. A semiconductor package for evaluation was obtained. Sixty semiconductor packages were obtained from one sealing structure.

Evaluation of Warpage The amount of warpage at 260° C. of 24 semiconductor packages arbitrarily selected from 60 packages was measured using a thermoire warpage measuring device (manufactured by AKROMETRIX, product name: TherMoire AXP). The warp amount of cry warp was taken as a positive (+) value, and the warp amount of smile warp was taken as a negative (-) value. The measurement of the amount of warpage and the definition of the direction of warpage conformed to JEDEC standard JESD22-B112B. An average value of the amount of warpage of 24 semiconductor packages was obtained.

From the results shown in Table 1, it was confirmed that a semiconductor package exhibiting cry warpage at 260° C. was obtained by the method of Example 1.

DESCRIPTION OF SYMBOLS 1... Encapsulation structure 2... Substrate 2S1, 2S2... Main surface of substrate 3... Semiconductor member 4... Sealing resin layer 7... Rotating blade 10... Semiconductor package 31, 32... Semiconductor chip 31A , 32A... Adhesion layer.

Claims (14)

arranging a semiconductor member having a semiconductor chip on a substrate including a glass cloth;
A sealing resin layer that seals the semiconductor member is formed on the substrate by a method including molding a thermosetting sealing resin while heating, whereby the substrate, the semiconductor member and the sealing are formed. forming a sealing structure having a resin layer;
including
The sealing structure is formed so as to warp at 260° C. so that a convex curved shape is formed on the sealing resin layer side,
A method of manufacturing a semiconductor package. 2. The method of claim 1, wherein the glass cloth comprises S-glass fibers, T-glass fibers, or both. 3. The method according to claim 1, wherein the substrate has a storage modulus at 260[deg.] C. of 10 GPa or more. The method according to any one of claims 1 to 3, wherein the temperature to which the encapsulating resin is heated during molding is 110-200°C. The method according to any one of claims 1 to 4, wherein the semiconductor member has a thickness of 300 µm or less. A method according to any one of claims 1 to 5, wherein the substrate has a thickness of 200 µm or less. The method according to any one of claims 1 to 6, wherein the sealing resin layer has a thickness of 450 µm or less. A method according to any preceding claim, wherein the encapsulation structure has a thickness of 650 µm or less. A semiconductor package comprising a substrate containing glass cloth, a semiconductor member mounted on the substrate, and a sealing resin layer formed on the substrate and sealing the semiconductor member,
A semiconductor package, wherein the semiconductor package is warped at 260° C. so that a convex curved shape is formed on the side of the sealing resin layer. 10. The semiconductor package of claim 9, wherein the glass cloth comprises S-glass fibers, T-glass fibers, or both. 11. The semiconductor package according to claim 9, wherein said substrate has a storage modulus at 260[deg.] C. of 10 GPa or more. 12. The semiconductor package according to claim 9, wherein said semiconductor package comprises a bottom package and a top package and is used as a top package of a package-on-package type semiconductor device in which these are joined. A package-on-package type semiconductor device comprising a bottom package and a top package that are joined together,
The top package is the semiconductor package according to any one of claims 9 to 11,
A semiconductor device according to claim 1, wherein the bottom package warps at 260° C. to form a convex curved shape toward the top package. A method of manufacturing a package-on-package type semiconductor device comprising bonding a top package to a bottom package by a method comprising heating the top package to 200° C. or higher, the method comprising:
The top package is the semiconductor package according to any one of claims 9 to 11,
A method, wherein the bottom package warps at 260° C. to form a convex curved shape toward the top package.

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