JP2022173969A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which can stabilize a characteristic.SOLUTION: According to an embodiment, a semiconductor device contains a silicon carbide member. The silicon carbide member contains: an operation region including at least one of a diode and a transistor; and a first element region including a first element. The first element region contains a first region and a second region. A first direction from the first region to the second region is along a [1-100] direction of the silicon carbide member. The operation region is between the first region and the second region in the first direction. The first element region does not include a region overlapped with the operation region in a second direction along a [11-20] direction of the silicon carbide member. Or, the first element region contains a third region overlapped with the operation region in the second direction. A first length along the first direction of the first region is longer than a third length along the second direction of the third region, and a second length along the first direction of the second region is longer than the third length.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD Embodiments of the present invention relate to semiconductor devices.

For example, there is a semiconductor device containing silicon carbide. Semiconductor devices are desired to have stable characteristics.

JP 2019-075411 A

An embodiment of the present invention provides a semiconductor device capable of stabilizing characteristics.

According to an embodiment of the invention, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode and a transistor, and a first element region including at least one first element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region to the second region is along the [1-100] direction of the silicon carbide member. The operating area is between the first area and the second area in the first direction. The first element region does not include a region overlapping the operation region in the second direction along the [11-20] direction of the silicon carbide member. Alternatively, the first elemental region includes a third region that overlaps the active region in the second direction, and a first length of the first region along the first direction is equal to the second elemental region of the third region. A second length along the first direction of the second region is longer than the third length.

FIG. 1 is a schematic diagram illustrating the semiconductor device according to the first embodiment. FIG. 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment. FIG. 3 is a schematic diagram illustrating the semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating part of the semiconductor device according to the first embodiment. FIG. 5 is a schematic cross-sectional view illustrating part of the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.

Each embodiment of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the size ratio between portions, and the like are not necessarily the same as the actual ones. Even when the same parts are shown, the dimensions and ratios may be different depending on the drawing.
In the present specification and each figure, the same reference numerals are given to the same elements as those described above with respect to the previous figures, and detailed description thereof will be omitted as appropriate.

(First embodiment)
1 and 2 are schematic diagrams illustrating the semiconductor device according to the first embodiment.
FIG. 1 is a plan view. 2 is a cross-sectional view taken along line A1-A2 of FIG. 1. FIG.

As shown in FIGS. 1 and 2, semiconductor device 110 according to the embodiment includes silicon carbide member 80 .

Silicon carbide member 80 includes silicon carbide (SiC). Silicon carbide member 80 includes an operating region 80A and a first element region 81 . The active region 80A includes at least one of diodes and transistors. An example of the operating area 80A will be described later.

The first element region 81 contains the first element. The first element contains at least one selected from the group consisting of Ar, V, Al and B. The first element region 81 contains, for example, SiC and the first element.

The first element region 81 includes a first region 81a and a second region 81b. The first direction from first region 81 a to second region 81 b is along the [1-100] direction of silicon carbide member 80 .

In this specification, in notations such as "[1-100]", "-" indicates that a "bar" is attached to the number after "-".

Let the first direction ([1-100] direction) be the Y-axis direction. One direction perpendicular to the Y-axis direction is defined as the X-axis direction. A direction perpendicular to the Y-axis direction and the X-axis direction is defined as the Z-axis direction.

The X-axis direction may be inclined with respect to the [11-20] direction (see FIG. 4, etc., to be described later). The angle between the X-axis direction and the [11-20] direction may be, for example, 0 degrees or more and 10 degrees or less. In this way, the X-axis direction may follow the [11-20] direction while being inclined at a small angle with respect to the [11-20] direction.

The motion area 80A is between the first area 81a and the second area 81b in the first direction (Y-axis direction).

First element region 81 does not include, for example, a region overlapping operation region 80A in the second direction along the [11-20] direction of silicon carbide member 80 . The second direction corresponds to, for example, the X-axis direction.

Alternatively, as will be described later, the first element region 81 may include a region (such as a third region described later) that overlaps the operating region 80A in the second direction (X-axis direction). In this case, the width of the third region is smaller than the widths of the first region 81a and the second region 81b. An example in which the first element region 81 includes the third region and the like will be described later.

In the semiconductor device 110 illustrated in FIGS. 1 and 2, the first element region 81 does not include a region overlapping the active region 80A in the second direction along the [11-20] direction. In the semiconductor device 110, a first region 81a and a second region 81b are provided that overlap with the operating region 80A in the first direction (Y-axis direction) along the [1-100] direction. The first region 81a and the second region 81b do not contribute to operation. In the embodiment, the first region 81 a and the second region 81 b have the function of stabilizing the characteristics of the semiconductor device 110 .

As shown in FIG. 2, silicon carbide member 80 includes a base 10s and first semiconductor region 10 provided on base 10s. The base 10s is, for example, a SiC substrate. The first semiconductor region 10 is, for example, an n-type SiC layer. For example, basal plane dislocations 71 (BPDs) are present in the substrate 10s. The basal plane dislocations 71 are along the {0001} plane of the substrate 10s. The basal plane dislocations 71 cause stacking faults during operation of the semiconductor device 110 . Stacking faults change the operating voltage in the semiconductor device 110 . For example, the forward voltage Vf changes and Vf deterioration occurs. For example, stacking faults may reduce the withstand voltage. It is preferable to suppress basal plane dislocations 71 .

As a result of studies by the inventors of the present application, it was found that basal plane dislocations 71 glide (move) in silicon carbide member 80 . For example, basal plane dislocations 71 glide along the directions of arrows 88A and 88B shown in FIG. 1 (along the [1-100] direction). When basal plane dislocations 71 reach the operating region 80A, stacking faults are formed during operation, resulting in unstable operation as described above.

The glide of basal plane dislocations 71 is likely to occur, for example, due to the treatment of introducing impurities into silicon carbide member 80 (for example, ion implantation) in operation region 80A and the subsequent heat treatment. The glide of basal plane dislocations 71 may be related, for example, to stresses in silicon carbide member 80 caused by these processes.

As a result of studies by the inventors of the present application, it was found that the glide of the basal plane dislocations 71 can be suppressed by providing the first element regions 81 described above. As described above, basal plane dislocations 71 glide along a first direction along the [1-100] direction. Therefore, the first element region 81 that suppresses the glide of the basal plane dislocations 71 is provided at a position in the first direction with respect to the operating region 80A. That is, the first area 81a and the second area 81b are provided so as to sandwich the operation area 80A in the first direction. As a result, the glide velocity of the basal plane dislocations 71 becomes substantially zero in the first region 81a and the second region 81b. The first region 81a and the second region 81b can suppress the basal plane dislocations 71 from reaching the operating region 80A. One reason for the suppression of glide by the first region 81a and the second region 81b is, for example, that stress is relieved by these regions.

The first element region 81 (first region 81 a and second region 81 b ) is a region that does not contribute to the operation of the semiconductor device 110 . The area of the first element region 81 is preferably as small as practically possible. Thereby, for example, the operating current per unit area can be increased. For example, costs can be suppressed. A more practical semiconductor device can be obtained.

In the semiconductor device 110, a first region 81a and a second region 81b are provided as the first element region 81 for suppressing glide. The first element region 81 does not include a region overlapping the active region 80A in the second direction along the [11-20] direction. As a result, a practical semiconductor device with stable characteristics and a small area of the first element region 81 can be provided.

FIG. 3 is a schematic diagram illustrating the semiconductor device according to the first embodiment.
As shown in FIG. 3 , semiconductor device 111 according to the embodiment also includes silicon carbide member 80 . Also in this example, silicon carbide member 80 includes operating region 80A and first element region 81 . In the semiconductor device 111, the first element region 81 includes a first region 81a, a second region 81b and a third region 81c. In this example, the first element region 81 includes a fourth region 81d. Other configurations of the semiconductor device 111 may be the same as those of the semiconductor device 110 .

The first direction from first region 81 a to second region 81 b is along the [1-100] direction of silicon carbide member 80 . Also in this case, the operating area 80A is between the first area 81a and the second area 81b in the first direction. The third area 81c overlaps the operating area 80A in the second direction along the [11-20] direction. For example, the operating area 80A is between the third area 81c and the fourth area 81d in the second direction.

The areas of the third region 81c and the fourth region 81d are smaller than the areas of the first region 81a and the second region 81b.

For example, as shown in FIGS. 1 and 3, the length along the first direction of the first region 81a is defined as a first length L1. Let the length along the first direction of the second region 81b be a second length L2. As already explained, the first direction is along the [1-100] direction.

For example, as shown in FIGS. 1 and 3, the length along the second direction of the third region 81c is defined as a third length L3. The length along the second direction of the fourth region 81d is defined as a fourth length L4. As already explained, the second direction is along the [11-20] direction.

In embodiments, the first length L1 is longer than the third length L3. The second length L2 is longer than the third length L3. The first length L1 is longer than the fourth length L4. The second length L2 is longer than the fourth length L4. Since the first length L1 and the second length L2 are long, the glide of the basal plane dislocations 71 can be effectively suppressed. Since the third length L3 and the fourth length L4 are short, the operating current per unit area can be increased. For example, costs can be suppressed. A more practical semiconductor device can be obtained.

In the embodiment, the first length L1 is preferably 10 times or more and 40 times or less the third length L3, for example. The second length L2 is preferably 10 to 40 times the third length L3. The first length L1 is preferably, for example, 10 to 40 times the fourth length L4. The second length L2 is preferably 10 to 40 times the fourth length L4. As a result, the area of the semiconductor device can be effectively reduced while the glide of the basal plane dislocations 71 is effectively suppressed.

In the embodiment, each of the first length L1 and the second length L2 is preferably 10 μm or more, for example. This can suppress the glided basal plane dislocations 71 from reaching the active region 80A. Each of the first length L1 and the second length L2 may be 20 μm or more. The glided basal plane dislocations 71 can be more reliably prevented from reaching the operating region 80A. Each of the first length L1 and the second length L2 may be, for example, 1000 μm or less. When each of the first length L1 and the second length L2 exceeds 1000 μm, for example, the effect of the glided basal plane dislocations 71 reaching the active region 80A is saturated.

The concentration of the first element in the first region 81a is preferably, for example, 1×10 ¹⁵ cm ⁻² or more and 3×10 ¹⁵ cm ⁻² or less. The concentration of the first element in the second region 81b is preferably, for example, 1×10 ¹⁵ cm ⁻² or more and 3×10 ¹⁵ cm ⁻² or less. Such concentrations effectively suppress glide of basal plane dislocations 71 .

In the embodiment, the first region 81a and the second region 81b can suppress the basal plane dislocations 71 from reaching the operating region 80A. For example, the density of basal plane dislocations 71 in the first region 81a is higher than the density of basal plane dislocations 71 in the active region 80A. For example, the density of basal plane dislocations 71 in the second region 81b is higher than the density of basal plane dislocations 71 in the active region 80A.

For example, as shown in FIG. 2, the first region 81a and the second region 81b may contain basal plane dislocations 71 and the active region 80A may not contain basal plane dislocations 71. FIG.

As shown in FIG. 2, the thickness of silicon carbide member 80 along the third direction is assumed to be thickness W1. The third direction is along the Z-axis direction, for example. The third direction intersects a plane containing the first direction and the second direction. In the embodiment, first length L1 is preferably 10 times or more and 50 times or less as large as thickness W1 of silicon carbide member 80 . For example, the appropriate first length L1 when the thickness W1 is thick may be shorter than the appropriate first length L1 when the thickness W1 is thin.

In the embodiment, a plurality of structures corresponding to a plurality of semiconductor devices may be formed on one wafer, and the plurality of structures may be divided to manufacture a plurality of semiconductor devices. In the dividing step, basal plane dislocations 71 may multiply with at least one end of a plurality of semiconductor devices as a base point. Such basal plane dislocations 71 may also glide. Stacking faults may grow based on such basal plane dislocations 71 . The first element region 81 according to the embodiment can prevent such basal plane dislocations 71 from reaching the operating region 80A.

As shown in FIGS. 1 and 3, silicon carbide member 80 may include second element region 82 . The second element region 82 contains a second element. The second element includes, for example, at least one selected from the group consisting of B, Al and Ga. The second element region 82 is p-type. For example, the second element region 82 includes a first partial region 82a, a second partial region 82b, a third partial region 82c and a fourth partial region 82d.

The first partial area 82a is between the first area 81a and the operating area 80A in the first direction ([1-100] direction). The second partial area 82b is between the operating area 80A and the second area 81b in the first direction. The operating area 80A is between the third partial area 82c and the fourth partial area 82d in the second direction ([11-20] direction).

The second element region 82 is, for example, a junction termination region. The second element region 82 makes it easier to obtain, for example, a high withstand voltage.

The length along the first direction of the first partial region 82a is defined as length LL1. Let length LL2 be the length along the first direction of second partial region 82b. The length along the second direction of the third partial region 82c is set to a length LL3. The length along the second direction of the fourth partial region 82d is assumed to be length LL4. These lengths (widths) are sufficiently shorter than the first length L1 and so on.

For example, the first length L1 is preferably 20 times or more the length LL1 of the first partial region 82a. The second length L2 is preferably longer than one time the length LL2 of the second partial region 82b. For example, each of the first length L1 and the second length L2 is preferably longer than one time the length LL3 of the third partial region 82c. Each of the first length L1 and the second length L2 is preferably longer than one time the length LL4 of the fourth partial region 82d.

As shown in FIGS. 1 and 3, the second elemental region 82 may surround the active region 80A in a plane containing the first direction and the second direction (substantially the XY plane). The second element region 82 may be annular, for example.

As shown in FIG. 3, when silicon carbide member 80 includes third region 81c, third partial region 82c is between third region 81c and operating region 80A in the second direction. When silicon carbide member 80 includes fourth region 81d, fourth partial region 82d is between operating region 80A and fourth region 81d in the second direction. As already explained, the first length L1 is longer than the fourth length L4 along the second direction of the fourth region 81d. The second length L2 is longer than the fourth length L4.

As shown in FIGS. 1 and 3, silicon carbide member 80 may further include a third element region 83 . The third element region 83 contains the third element. The third element contains at least one selected from the group consisting of N, P and As. The third element region 83 is, for example, n-type. The third element region 83 includes a fifth partial region 83e, a sixth partial region 83f, a seventh partial region 83g and an eighth partial region 83h.

The fifth partial region 83e is between the first region 81a and the first partial region 82a in the first direction. The sixth partial region 83f is between the second partial region 82b and the second region 81b in the first direction. The third partial area 82c is between the seventh partial area 83g and the operating area 80A in the second direction. The fourth partial area 82d is between the operating area 80A and the eighth partial area 83h in the second direction.

The length along the first direction of the fifth partial region 83e is defined as length LL5. The length along the first direction of the sixth partial region 83f is defined as length LL6. The length of the seventh partial region 83g along the second direction is defined as a length LL7. The length along the second direction of the eighth partial region 83h is defined as length LL8.

The first length L1 is preferably longer than one time the length LL5 of the fifth partial region 83e. The second length L2 is preferably 20 times or more the length LL6 of the sixth partial region 83f. Each of the first length L1 and the second length L2 is preferably 20 times or more the length LL7 of the seventh partial region 83g. Each of the first length L1 and the second length L2 is preferably 20 times or more the length LL8 of the eighth partial region 83h.

As shown in FIG. 3, when silicon carbide member 80 includes third region 81c, seventh partial region 83g is between third region 81c and third partial region 82c in the second direction. When silicon carbide member 80 includes fourth region 81d, eighth partial region 83h is between fourth partial region 82d and fourth region 81d in the second direction. The first length L1 is longer than the fourth length L4 along the second direction of the fourth region 81d. The second length L2 is longer than the fourth length L4.

The second element region 82 and the third element region 83 are included in the termination region 80T (see FIG. 2), for example. The second elemental region 82 may be separated from the third elemental region 83 .

As shown in FIG. 2, the first region 81a has a length t1 along the Z-axis direction. The Z-axis direction intersects a plane containing the first direction and the second direction. The second region 81b has a length t2 along the Z-axis direction. The length t1 corresponds to the thickness of the first region 81a. The length t2 corresponds to the thickness of the second region 81b. Each of the length t1 and the length t2 may be, for example, 0.2 to 10 times the thickness (the length along the Z-axis direction) of the second element region 82 . Each of the length t1 and the length t2 may be, for example, 0.2 to 10 times the thickness of the third element region 83 (the length along the Z-axis direction).

As shown in FIGS. 1 and 3, the semiconductor device 110 or the semiconductor device 111 may include an electrode 50E. The electrode 50E is electrically connected to at least one of the diodes and transistors provided in the active region 80A. The first element region 81 is preferably in a floating state with respect to the electrode 50E. This suppresses hole injection. Although the first element region 81 is conductive, the first element region 81 is in a floating state with respect to the electrode 50E, which facilitates suppression of forward voltage deterioration during energization.

FIG. 4 is a schematic cross-sectional view illustrating part of the semiconductor device according to the first embodiment.
4 is a cross-sectional view taken along line B1-B2 of FIG. 1. FIG. FIG. 4 corresponds to at least a portion of the active area 80A. As shown in FIG. 4, in this example, active area 80A includes transistor 10T.

The transistor 10T includes a first electrode 51 , a second electrode 52 , a third electrode 53 and an insulating portion 61 . The stacking direction from the first electrode 51 to the second electrode 52 intersects a plane (substantially the XY plane) including the first direction and the second direction. The stacking direction is, for example, the Z-axis direction.

At least part of operating region 80A of silicon carbide member 80 is between first electrode 51 and third electrode 53 in the stacking direction (Z-axis direction). The operating region 80</b>A includes a first conductivity type first semiconductor region 10 , a second conductivity type second semiconductor region 20 , and a first conductivity type third semiconductor region 30 . The first conductivity type is one of n-type and p-type. The second conductivity type is the other of n-type and p-type. Hereinafter, it is assumed that the first conductivity type is the n-type and the second conductivity type is the p-type.

The first semiconductor region 10 and the third semiconductor region 30 contain SiC and a fourth element. The fourth element contains at least one selected from the group consisting of N, P and As. The second semiconductor region 20 contains SiC and a fifth element. The fifth element contains at least one selected from the group consisting of B, Al and Ga.

The first semiconductor region 10 includes a first semiconductor portion 10a and a second semiconductor portion 10b. The direction from the second semiconductor portion 10b to the third electrode 53 is along the stacking direction (Z-axis direction). The crossing direction from the second semiconductor portion 10b to the first semiconductor portion 10a crosses the stacking direction (Z-axis direction). In this example, the cross direction corresponds to the X-axis direction.

The direction from the first semiconductor portion 10a to the third semiconductor region 30 is along the stacking direction (Z-axis direction). The second semiconductor region 20 includes a third semiconductor portion 20c and a fourth semiconductor portion 20d. The third semiconductor portion 20c is between the first semiconductor portion 10a and the third semiconductor region 30 in the stacking direction (Z-axis direction). The fourth semiconductor portion 20d is between part of the second semiconductor portion 10b and the third semiconductor region 30 in the cross direction (X-axis direction).

The first electrode 51 is electrically connected to the first semiconductor region 10 . The second electrode 52 is electrically connected with the third semiconductor region 30 . At least part of the insulating portion 61 is located between the second semiconductor portion 10 b and the third electrode 53 and between the fourth semiconductor portion 20 d and the third electrode 53 .

In the semiconductor device 110 , the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53 . The potential of the third electrode 53 may be a potential based on the potential of the second electrode 52 . The first electrode 51 functions, for example, as a drain electrode. The second electrode 52 functions, for example, as a source electrode. The third electrode 53 functions as a gate electrode. The base 10s is, for example, of the first conductivity type. The semiconductor device 110 is, for example, a MOSFET.

In this example, the second semiconductor region 20 includes a fifth semiconductor portion 20e. In the X-axis direction, the third semiconductor region 30 is between the fourth semiconductor portion 20d and the fifth semiconductor portion 20e. The second electrode 52 is electrically connected to the fifth semiconductor portion 20e. The active region 80A in the semiconductor device 111 may also have the same configuration as the configuration illustrated in FIG.

FIG. 5 is a schematic cross-sectional view illustrating part of the semiconductor device according to the first embodiment.
FIG. 5 is a cross-sectional view corresponding to line B1-B2 in FIG. FIG. 5 corresponds to at least a portion of active area 80A. As shown in FIG. 5, in the semiconductor device 112 according to the embodiment, the active region 80A includes the transistor 10T.

As shown in FIG. 5, in semiconductor device 112, active region 80A of silicon carbide member 80 includes second conductivity type (p-type) substrate 10sA. The base 10 sA is between the first electrode 51 and the first semiconductor region 10 . The semiconductor device 112 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The configuration of the semiconductor device 112 other than the above (the first element region 81 and the like) may be the same as the configuration of the semiconductor devices 110 and 111 .

(Second embodiment)
FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
FIG. 6 illustrates the active region 80A and termination region 80T. As shown in FIG. 6, in the semiconductor device 113 according to the embodiment, the operating region 80A includes the diode 10D.

As shown in FIG. 6, diode 10D includes first electrode 51 and second electrode 52 . The stacking direction (Z-axis direction) from the first electrode 51 to the second electrode 52 intersects a plane (substantially the XY plane) including the first direction and the second direction. At least part of operating region 80A of silicon carbide member 80 is between first electrode 51 and second electrode 52 in the stacking direction (Z-axis direction).

The active region 80A includes a first conductivity type first semiconductor region 10 and a second conductivity type second semiconductor region 20 . The first semiconductor region 10 is between the first electrode 51 and the second electrode 52 . The second semiconductor region 20 is between the first semiconductor region 10 and the second electrode 52 . The first electrode 51 is electrically connected to the first semiconductor region 10 . The second electrode 52 is electrically connected with the second semiconductor region 20 . The first electrode 51 is, for example, a cathode electrode. The second electrode 52 is, for example, an anode electrode.

The semiconductor device 113 may be the same as the semiconductor device 110 except for the active region 80A and the termination region 80T. In semiconductor device 113, silicon carbide member 80 includes first element region 81 (eg, first region 81a and second region 81b). Glide of the basal plane dislocations 71 is also suppressed in the semiconductor device 113 . A semiconductor device having stable characteristics can be provided.

In the embodiment, at least one of the first electrode 51 and the second electrode 52 contains at least one selected from the group consisting of Al, Cu and Au, for example. For example, the third electrode 53 (eg, gate electrode) contains at least one selected from the group consisting of TiN, Al, Ru, W, and TaSiN. The insulating portion 61 includes, for example, at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide.

In an embodiment, information on impurity concentration is obtained by, for example, SIMS (Secondary Ion Mass Spectrometry). In the above, the impurity concentration may be, for example, the carrier concentration. Information on relative levels of impurity concentration can be obtained, for example, based on information on relative levels of carrier concentration obtained by SCM (Scanning Capacitance Microscopy).

The concentration of the first element in the first region 81a is preferably, for example, 1.67×10 ¹⁹ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. The concentration of the first element in the second region 81b is preferably, for example, 1.67×10 ¹⁹ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. Such concentrations effectively suppress glide of basal plane dislocations 71 .

In one example, the dose amount of the first element in the first region 81a is, for example, 1×10 ¹⁵ cm ⁻² or more and 3×10 ¹⁵ cm ⁻² or less. In one example, the dose amount of the first element in the second region 81b is, for example, 1×10 ¹⁵ cm ⁻² or more and 3×10 ¹⁵ cm ⁻² or less. Such a dose effectively suppresses the glide of the basal plane dislocations 71 . The introduction of the first element into these regions may be performed, for example, by ion implantation. The thicknesses of the first region 81a and the second region 81b (length t1 and length t2: see FIG. 2) are, for example, 0.4 μm or more and 0.8 μm or less (eg, approximately 0.6 μm).

For example, the concentration (unit: cm ⁻³ ) of the first element in the first region 81a and the second region 81b is the second element region 82 (first partial region 82a, second partial region 82b, third partial region 82c and It is preferably 1 to 20 times the concentration (unit: cm ⁻³ ) of the second element (B, Al, Ga, etc.) in the fourth partial region 82d, etc.).

For example, the concentration (unit: cm ⁻³ ) of the first element in the first region 81a and the second region 81b is the third element region 83 (fifth partial region 83e, sixth partial region 83f, seventh partial region 83g and It is preferably 10 times or more and 200 times or less than the concentration (unit: cm ⁻³ ) of the third element (N, P, As, etc.) in the eighth partial region 83h, etc.).

As shown in FIG. 2, the first semiconductor region 10 includes a portion overlapping the first region 81a in the Z-axis direction. The thicknesses of the first region 81a and the second region 81b (length t1 and length t2, respectively) are, for example, the portions of the first semiconductor region 10 overlapping the first region 81a in the Z-axis direction. It is preferably 1/100 or more and 1/15 or less of the thickness (length along the Z-axis direction).

According to the embodiments, it is possible to provide a semiconductor device capable of stabilizing characteristics.

In the specification of the present application, "electrically connected state" includes a state in which a plurality of conductors are physically in contact with each other and current flows between the plurality of conductors. "Electrically connected state" includes a state in which another conductor is inserted between a plurality of conductors and current flows between the plurality of conductors.

In the present specification, "perpendicular" and "parallel" include not only strict perpendicularity and strict parallelism, but also variations in the manufacturing process, for example, and may be substantially perpendicular and substantially parallel. .

The embodiments of the present invention have been described above with reference to specific examples. However, the invention is not limited to these specific examples. For example, a person skilled in the art can carry out the present invention in the same way by appropriately selecting specific configurations of each element such as a silicon carbide member, a semiconductor region, a substrate, an electrode and an insulating portion included in a semiconductor device from a range known to those skilled in the art. However, as long as the same effect can be obtained, it is included in the scope of the present invention.

Any combination of two or more elements of each specific example within the technically possible range is also included in the scope of the present invention as long as it includes the gist of the present invention.

In addition, based on the semiconductor device described above as an embodiment of the present invention, all semiconductor devices that can be implemented by those skilled in the art by appropriately modifying the design also belong to the scope of the present invention as long as they include the gist of the present invention. .

In addition, within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications and modifications, and it is understood that these modifications and modifications also belong to the scope of the present invention. .

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 10... First semiconductor region 10D... Diode 10T... Transistor 10a, 10b... First and second semiconductor portions 10s, 10sA... Substrate 20... Second semiconductor region 20c to 20e... Third to fifth semiconductors Part 30 Third semiconductor region 50E Electrode 51 to 53 First to third electrodes 61 Insulating portion 71 Basal plane dislocation 80 Silicon carbide member 80A Operating region 80T Terminating region 81 First element region 81a to 81d First to fourth region 82 Second element region 82a to 82d First to fourth partial region 83 Third element region 83e to 83h Third 5 to eighth partial regions 88A, 88B... arrows 110 to 113... semiconductor devices L1 to L4... first to fourth lengths LL1 to LL8... lengths W1... thicknesses t1, t2... lengths

Claims (20)

comprising a silicon carbide member;
The silicon carbide member is
an active region including at least one of a diode and a transistor;
a first element region containing at least one first element selected from the group consisting of Ar, V, Al and B;
including
The first element region includes a first region and a second region, the first direction from the first region to the second region is along the [1-100] direction of the silicon carbide member, and the operation region is between the first region and the second region in the first direction;
The first element region does not include a region overlapping the operation region in the second direction along the [11-20] direction of the silicon carbide member, or the first element region does not overlap the operation region in the second direction. a third region overlapping the region, wherein a first length along the first direction of the first region is longer than a third length along the second direction of the third region; A semiconductor device, wherein a second length along the first direction is longer than the third length. The first length is 10 times or more and 50 times or less than the third length,
2. The semiconductor device according to claim 1, wherein said second length is 10 to 50 times as long as said third length. the concentration of the first element in the first region is 1.67×10 ¹⁹ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less;
3. The semiconductor device according to claim 1, wherein the concentration of said first element in said second region is 1.67×10 ¹⁹ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. the density of basal plane dislocations in the first region is higher than the density of basal plane dislocations in the active region;
4. The semiconductor device according to claim 1, wherein a density of basal plane dislocations in said second region is higher than said density of said basal plane dislocations in said active region. the first region and the second region comprise basal plane dislocations;
4. The semiconductor device according to claim 1, wherein said active region does not contain basal plane dislocations. of claims 1 to 5, wherein said first length is 10 times or more and 50 times or less than the thickness of said silicon carbide member along a third direction intersecting a plane including said first direction and said second direction. The semiconductor device according to any one of the above. The silicon carbide member further includes a second element region,
The second element region contains a second element containing at least one selected from the group consisting of B, Al and Ga,
the second element region includes a first partial region, a second partial region, a third partial region and a fourth partial region;
the first partial region is between the first region and the operating region in the first direction;
the second partial region is between the operating region and the second region in the first direction;
6. The semiconductor device according to claim 1, wherein said active region is between said third partial region and said fourth partial region in said second direction. The first length is 20 times or more the length of the first partial region along the first direction,
8. The semiconductor device according to claim 7, wherein said second length is 20 times or more the length along said first direction of said second partial region. 9. The semiconductor device according to claim 7, wherein said second element region surrounds said operation region in a plane including said first direction and said second direction. The silicon carbide member includes the third region,
9. The semiconductor device according to claim 7, wherein said third partial region is between said third region and said operating region. The silicon carbide member includes a fourth region,
the fourth partial area is between the operation area and the fourth area;
The first length is longer than a fourth length along the second direction of the fourth region,
the second length is longer than the fourth length;
11. The semiconductor device according to claim 10. The silicon carbide member further includes a third element region,
The third element region contains a third element containing at least one selected from the group consisting of N, P and As,
the third element region includes a fifth partial region, a sixth partial region, a seventh partial region and an eighth partial region;
the fifth partial area is between the first partial area and the first partial area;
the sixth partial region is between the second partial region and the second region;
the third partial area is between the seventh partial area and the operating area;
10. The semiconductor device according to claim 7, wherein said fourth partial region is between said operating region and said eighth partial region. The first length is 20 times or more the length of the fifth partial region along the first direction,
13. The semiconductor device according to claim 12, wherein said second length is 20 times or more the length along said first direction of said sixth partial region. The silicon carbide member includes the third region,
The seventh partial area is between the third partial area and the third partial area,
14. The semiconductor device according to claim 12 or 13. The silicon carbide member includes a fourth region,
the eighth partial region is between the fourth partial region and the fourth region;
The first length is longer than a fourth length along the second direction of the fourth region,
the second length is longer than the fourth length;
15. The semiconductor device according to claim 14. with electrodes,
the electrode is electrically connected to at least one of the diode and the transistor;
16. The semiconductor device according to claim 1, wherein said first element region is in a floating state with respect to said electrode. the transistor includes a first electrode, a second electrode, a third electrode, and an insulating portion;
a stacking direction from the first electrode to the second electrode intersects a plane including the first direction and the second direction;
at least part of the operating region is between the first electrode and the third electrode in the stacking direction;
The operating region is
a first semiconductor region of a first conductivity type;
a second conductivity type second semiconductor region;
a third semiconductor region of the first conductivity type;
including
the first semiconductor region includes a first semiconductor portion and a second semiconductor portion;
the direction from the second semiconductor portion to the third electrode is along the stacking direction,
a crossing direction from the second semiconductor portion to the first semiconductor portion crosses the stacking direction;
A direction from the first semiconductor portion to the third semiconductor region is along the stacking direction,
the second semiconductor region includes a third semiconductor portion and a fourth semiconductor portion;
the third semiconductor portion is between the first semiconductor portion and the third semiconductor region in the stacking direction;
the fourth semiconductor portion is between a portion of the second semiconductor portion and the third semiconductor region in the cross direction;
the first electrode is electrically connected to the first semiconductor region;
the second electrode is electrically connected to the third semiconductor region;
17. Any one of claims 1 to 16, wherein at least part of said insulating portion is between said second semiconductor portion and said third electrode and between said fourth semiconductor portion and said third electrode. The semiconductor device according to . the active region includes a base of the second conductivity type;
18. The semiconductor device according to claim 17, wherein said substrate is between said first electrode and said first semiconductor region. the diode includes a first electrode and a second electrode;
a stacking direction from the first electrode to the second electrode intersects a plane including the first direction and the second direction;
at least part of the operating region is between the first electrode and the second electrode in the stacking direction;
The operating region is
a first semiconductor region of a first conductivity type;
a second conductivity type second semiconductor region;
including
the first semiconductor region is between the first electrode and the second electrode;
the second semiconductor region is between the first semiconductor region and the second electrode;
the first electrode is electrically connected to the first semiconductor region;
17. The semiconductor device according to claim 1, wherein said second electrode is electrically connected to said second semiconductor region. 20. The semiconductor device according to claim 1, wherein each of said first length and said second length is 10 μm or more.

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