JP2022171546A - Impedance conversion circuit and amplification module - Google Patents

Abstract

To provide an impedance conversion circuit that facilitates securement of isolation between a node on the input side and a node on the output side.SOLUTION: Both ends of a first main line are respectively defined as a first node and a third node, and a high frequency signal is transmitted between the first node and the third node. Both ends of the second main line are respectively defined as a second node and a fourth node, and a high frequency signal is transmitted between the second node and the fourth node. One end of a first sub-line is connected to the second node. A second sub-line is electromagnetically coupled to the first main line. One end of the second sub-line is connected to the first node, and the other end is connected to the end of the first sub-line not connected to the second node. The second sub-line is electromagnetically coupled to the second main line. A first capacitor is connected in parallel to at least one of at least a portion of the second main line and at least a portion of the second sub-line.SELECTED DRAWING: Figure 1

Description

The present invention relates to an impedance conversion circuit and an amplification module.

In a high-frequency power amplifier using a differential amplifier circuit, a balanced-unbalanced conversion circuit (balun) is connected to the input side and the output side of the differential amplifier circuit. When the high-frequency power amplifier is composed of a plurality of stages of differential amplifier circuits, a differential signal impedance conversion circuit is inserted between the stages. The following Non-Patent Document 1 discloses a Guanella type balanced-unbalanced conversion circuit. FIG. 39 shows an equivalent circuit diagram of the Ganella-type balanced-unbalanced conversion circuit disclosed in Non-Patent Document 1. As shown in FIG.

The Guanella-type balanced-unbalanced conversion circuit includes a first node P1, a second node P2, a third node P3, and a fourth node P4. A first node P1 and a third node P3 are connected by a first main line 101, and a second node P2 and a fourth node P4 are connected by a second main line . A first sub-line 103 and a second sub-line 104 are coupled to the first main line 101 and the second main line 102, respectively. As an example, the turns ratio (line length ratio) between the first main line 101 and the first sub-line 103 and the turns ratio (line length ratio) between the second main line 102 and the second sub-line 104 are both one pair. 1.

The first node P1 and the second node P2 are connected to one ends of the second sub-line 104 and the first sub-line 103, respectively, and are connected to the other ends of the second sub-line 104 and the first sub-line 103. parts are connected to each other.

The second node P2 is connected to ground. A first node P1 is used as a node for single-ended signals, and a third node P3 and a fourth node P4 are used as nodes for differential signals.

When a load is connected between the third node P3 and the fourth node P4, the impedance of the load side viewed from the first node P1 is 1/4 times the load impedance. Conversely, when a load is connected to the first node P1, the impedance of the load side viewed from the third node P3 and the fourth node P4 is four times the load impedance. Thus, the Ganella-type balanced-unbalanced conversion circuit has a function of impedance conversion.

Hua-Yen et. al., "Design of Step-Down Broadband and Low-Loss Ruthroff-Type Baluns Using IPD Technology", IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 6, JUNE 2014

In the Guanella-type balanced-unbalanced conversion circuit, the fourth node P4 is connected to the ground via the second main line 102 . When the balanced-unbalanced conversion circuit shown in FIG. 39 is configured with an integrated passive device (IPD) using a resin substrate, a low-temperature co-fired ceramic (LTCC) substrate, a semiconductor substrate, or the like, the substrate is not made of a magnetic material. 2 It is difficult to sufficiently increase the inductance of the transmission line such as the main line 102 . As a result, the isolation between the fourth node P4 and the ground becomes insufficient, causing phase imbalance and the like in differential signals. Also, the insertion loss increases especially at low frequencies.

The transmission line transformer shown in FIG. 39, in which the second node P2 of the balanced-unbalanced conversion circuit is not grounded, can be used as a differential signal impedance conversion circuit. In this case, sufficient isolation may not be ensured between the first node P1 and the third node P3 and between the second node P2 and the fourth node P4.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an impedance conversion circuit that facilitates ensuring isolation between a node on the input side and a node on the output side, and an amplifier module equipped with this impedance conversion circuit.

According to one aspect of the invention,
a first main line whose both ends are a first node and a third node, respectively, and which transmits a high frequency signal between the first node and the third node;
a second main line having both ends as a second node and a fourth node, and transmitting a high frequency signal between the second node and the fourth node;
a first sub-line having one end connected to the second node and electromagnetically coupled to the first main line;
One end is connected to the first node, the other end is connected to the end of the first sub-line not connected to the second node, and is electromagnetically connected to the second main line. a second sub-line to be coupled;
An impedance conversion circuit is provided that includes a first capacitor connected in parallel to at least one of at least a portion of the second main line and at least a portion of the second sub-line.

According to another aspect of the invention,
the impedance conversion circuit described above;
An amplifier module is provided comprising a differential amplifier having a pair of differential output nodes respectively connected to said first node and said second node.

An inductance component of at least one of at least a portion of the second main line and at least a portion of the second sub-line and the first capacitor resonate in parallel at a certain frequency. When parallel resonance occurs, the impedance of the parallel circuit becomes a high impedance state. Therefore, it is possible to ensure sufficient isolation between the second node and the fourth node.

FIG. 1A is an equivalent circuit diagram of the impedance conversion circuit according to the first embodiment, FIG. 1B is a diagram schematically showing the cross-sectional structure of the impedance conversion circuit according to the first embodiment, and FIG. It is a graph which shows the passage coefficient S24 from P4 to the 2nd node P2. FIG. 2A is an equivalent circuit diagram of the impedance conversion circuit according to the first modification of the first embodiment, and FIG. 2B is a graph showing the passage coefficient S24 from the fourth node P4 to the second node P2. FIG. 3A is an equivalent circuit diagram of the impedance conversion circuit according to the second modification of the first embodiment, and FIG. 3B is a graph showing the passage coefficient S24 from the fourth node P4 to the second node P2. FIG. 4A is an equivalent circuit diagram of the impedance conversion circuit according to the second embodiment, and FIG. 4B is a diagram schematically showing the cross-sectional structure of the impedance conversion circuit according to the second embodiment. FIG. 5A is a graph showing the insertion loss of the impedance conversion circuits according to the second embodiment and the comparative example, and FIG. 5B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. FIG. 6A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the second embodiment and the comparative example, and FIG. 6B is a graph showing the phase imbalance of the impedance conversion circuit. FIG. 7 is a graph showing the passage coefficient S24 from the fourth node P4 to the second node P2 of the impedance conversion circuits according to the second embodiment and the comparative example. FIG. 8 is an equivalent circuit diagram of the impedance conversion circuit according to the third embodiment. 9A is a graph showing the insertion loss of the impedance conversion circuits according to the third example and the comparative example, and FIG. 9B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. FIG. 10A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the third example and the comparative example, and FIG. 10B is a graph showing the phase imbalance of the impedance conversion circuit. FIG. 11 is an equivalent circuit diagram of the impedance conversion circuit according to the fourth embodiment. FIG. 12A is a graph showing the insertion loss of the impedance conversion circuits according to the fourth example and the comparative example, and FIG. 12B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. FIG. 13A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the fourth example and the comparative example, and FIG. 13B is a graph showing the phase imbalance of the impedance conversion circuit. FIG. 14 is a schematic equivalent circuit diagram of the impedance conversion circuit according to the fifth embodiment. FIG. 15 is a schematic equivalent circuit diagram of an impedance conversion circuit according to a modification of the fifth embodiment. FIG. 16 is a schematic equivalent circuit diagram of an impedance conversion circuit according to another modification of the fifth embodiment. FIG. 17 is a schematic equivalent circuit diagram of an impedance conversion circuit according to still another modification of the fifth embodiment. FIG. 18 is a schematic equivalent circuit diagram of an impedance conversion circuit according to still another modification of the fifth embodiment. FIG. 19 is a schematic equivalent circuit diagram of an impedance conversion circuit according to still another modification of the fifth embodiment. FIG. 20 is an equivalent circuit diagram of the impedance conversion circuit according to the sixth embodiment. FIG. 21 is an equivalent circuit diagram of an impedance conversion circuit according to a modification of the sixth embodiment. FIG. 22 is a schematic equivalent circuit diagram of the impedance conversion circuit according to the seventh embodiment. FIG. 23 is an equivalent circuit diagram of the impedance conversion circuit according to the eighth embodiment. 24A is a graph showing the insertion loss of the impedance conversion circuits according to the eighth embodiment and the comparative example, and FIG. 24B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. 25A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the eighth embodiment and the comparative example, and FIG. 25B is a graph showing the phase imbalance of the impedance conversion circuit. FIG. 26 is an equivalent circuit diagram of the impedance conversion circuit according to the ninth embodiment. FIG. 27A is an equivalent circuit diagram of the impedance conversion circuit according to the tenth embodiment, and FIG. 27B is a graph showing the passage coefficient S24 from the fourth node P4 to the second node P2. FIG. 28A is an equivalent circuit diagram of the impedance conversion circuit according to the first modification of the tenth embodiment, and FIG. 28B is a graph showing simulation results of the passage coefficient S24 from the fourth node P4 to the second node P2. . FIG. 29 is an equivalent circuit diagram of the impedance conversion circuit according to the second modification of the tenth embodiment. 30A is a graph showing the insertion loss of the impedance conversion circuits according to the second modified example and the comparative example of the tenth embodiment, and FIG. 30B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. FIG. 31A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the second modified example and the comparative example of the tenth embodiment, and FIG. 31B is a graph showing the phase imbalance of the impedance conversion circuits. FIG. 32 is an equivalent circuit diagram of the impedance conversion circuit according to the eleventh embodiment. 33A is a graph showing the insertion loss of the impedance conversion circuits according to the eleventh embodiment and the comparative example, and FIG. 33B is a graph showing the common-mode rejection ratio of the impedance conversion circuits. 34A is a graph showing the amplitude imbalance of the impedance conversion circuits according to the eleventh embodiment and the comparative example, and FIG. 34B is a graph showing the phase imbalance of the impedance conversion circuit. FIG. 35 is an equivalent circuit diagram of the impedance conversion circuit according to the twelfth embodiment. FIG. 36 is an exploded perspective view showing the conductor pattern of the impedance conversion circuit according to the twelfth embodiment. FIG. 37 is a block diagram of a high frequency power amplifier according to the thirteenth embodiment. FIG. 38 is a block diagram of a high frequency power amplifier according to a modification of the thirteenth embodiment. FIG. 39 is an equivalent circuit diagram of the Ganella-type balanced-unbalanced conversion circuit disclosed in Non-Patent Document 1. As shown in FIG.

[First embodiment]
An impedance conversion circuit according to a first embodiment will be described with reference to FIGS. 1A, 1B, and 1C.

FIG. 1A is an equivalent circuit diagram of the impedance conversion circuit according to the first embodiment. The impedance conversion circuit according to the first embodiment includes a first main line 11, a second main line 12, a first sub-line 21, and a second sub-line 22 for transmitting high frequency signals, and further includes a capacitor Cp2. In FIG. 1A, the first sub-line 21 and the second sub-line 22 are hatched. A first sub-line 21 and a second sub-line 22 are electromagnetically coupled to the first main line 11 and the second main line 12 that transmit high-frequency signals, respectively. Both ends of the first main line 11 are called a first node P1 and a third node P3, respectively, and both ends of the second main line 12 are called a second node P2 and a fourth node P4, respectively.

The end of the first sub-line 21 corresponding to the end of the first main line 11 on the side of the first node P1 is connected to the second node P2. The end of the second sub-line 22 corresponding to the end of the second main line 12 on the side of the second node P2 is connected to the first node P1. The end of the first sub-line 21 corresponding to the end of the first main line 11 on the side of the third node P3, and the end of the second sub-line 22 corresponding to the end of the second main line 12 on the side of the fourth node P4. are connected to each other.

A capacitor Cp2 is connected in parallel to the second main line 12 .

When a high-frequency current flows through the first main line 11 , an odd-mode current flows through the first sub-line 21 . Similarly, when a high-frequency current flows through the second main line 12 , an odd-mode current flows through the second sub-line 22 . In FIG. 1A, the antiparallel arrows attached to the two mutually coupled transmission lines represent that odd-mode currents flow in the two mutually coupled transmission lines.

As an example, both the turns ratio (line length ratio) between the first main line 11 and the first sub-line 21 and the turns ratio (line length ratio) between the second main line 12 and the second sub-line 22 are It is one to one. The impedance transformation ratio between the first main line 11 and the first sub-line 21 is equal to the impedance transformation ratio between the second main line 12 and the second sub-line 22 . Therefore, the voltage across the first sub line 21 is equal to the voltage across the first main line 11 . Similarly, the voltage across the second sub-line 22 is equal to the voltage across the second main line 12 . In other words, the voltage V1 between the end of the first main line 11 on the side of the first node P1 and the corresponding end of the first sub line 21 and the end of the first main line 11 on the side of the third node P3 and the voltage V3 between the corresponding ends of the first sub-lines 21 are equal. Similarly, the voltage V2 between the end of the second main line 12 on the side of the second node P2 and the corresponding end of the second sub line 22 and the end of the second main line 12 on the side of the fourth node P4 and the voltage V4 between the corresponding ends of the second sub-lines 22 are equal.

The first node P1, the second node P2, the third node P3, and the fourth node P4 are the first connection terminal T1, the second connection terminal T2, the third connection terminal T3, and the fourth connection terminal for external connection, respectively. Directly connected to T4. The fourth connection terminal T4 is used as a ground terminal. The ground terminal is connected to the ground potential of the mounting board or the like.

FIG. 1B is a diagram schematically showing the cross-sectional structure of the impedance conversion circuit according to the first embodiment. FIG. 1B does not show a specific cross section of the impedance conversion circuit, but is a schematic illustration focusing on electrical connections and electromagnetic couplings of transmission lines. The first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 may be transmission lines such as microstrip lines. In FIG. 1B, illustration of the ground plane of the microstrip line is omitted.

The impedance conversion circuit according to the first embodiment comprises a laminated substrate 30 including a plurality of dielectric layers and a plurality of conductor layers alternately laminated. For the laminated substrate 30, for example, a multilayer resin substrate in which resin layers are laminated can be used. Examples of multilayer resin substrates include printed wiring boards. Also, a multilayer resin substrate using a liquid crystal polymer having a lower dielectric constant may be used, or a multilayer resin substrate using a fluororesin may be used. In addition, as the laminated substrate 30, for example, a ceramic multilayer substrate in which ceramic layers are laminated may be used. Examples of ceramic multilayer substrates include low-temperature co-fired ceramics (LTCC) substrates and substrates using ceramics that are fired at high temperatures. Furthermore, a semiconductor substrate provided with multiple wiring layers may be used as the laminated substrate 30 . A conductor in which the first main line 11 and the second main line 12 are arranged on the same conductor layer, and the first sub-line 21 and the second main line 22 are arranged on the first main line 11 and the second main line 12 They are arranged in the same conductor layer adjacent to the layer in the thickness direction.

A pair of lands for mounting the capacitor Cp2 is provided on the upper surface, which is one surface of the laminated substrate 30, and the capacitor Cp2 is surface-mounted on the pair of lands. A first connection terminal T1, a second connection terminal T2, a third connection terminal T3, and a fourth connection terminal T4 are provided on the bottom surface of the laminated substrate 30 opposite to the top surface. A first main line 11, a second main line 12, a first sub-line 21, a second sub-line 22, a first connection terminal T1, a second connection terminal T2, a third connection terminal T3, and The impedance conversion circuit shown in FIG. 1A is configured by connecting the fourth connection terminal T4 and the land on the upper surface through vias and conductor patterns in the laminated substrate 30 . In FIG. 1B, these vias and conductor patterns are represented by solid lines with black dots at both ends.

Next, the operation of the impedance conversion circuit according to the first embodiment will be explained.
When differential signals RF+ and RF- are input to a terminal pair consisting of the first connection terminal T1 and the second connection terminal T2, a single-ended signal RF is output from the third connection terminal T3. The magnitude (rms value) of the voltage between the first connection terminal T1 and the second connection terminal T2 is denoted as V0. At this time, voltages V1 and V2 are equal to voltage V0 (ie, V1=V2=V0). In the first embodiment, since V1=V3 and V2=V4 are established, the voltages V3 and V4 are also equal to the voltage V0 (that is, V3=V4=V0). At this time, the voltage of the third connection terminal T3 becomes twice V0.

The magnitude (effective value) of the current flowing through the first main line 11 and the second main line 12 is denoted as I0. The magnitude of the odd-mode current flowing through the first sub-line 21 and the second sub-line 22 is also equal to I0. Therefore, the magnitude of the current flowing into and out of the first connection terminal T1 and the second connection terminal T2 is equal to twice I0. Also, the magnitude of the current flowing in and out of the third connection terminal T3 is equal to I0.

Thus, the voltage of the single-ended signal RF is twice the voltage of the differential signals RF+, RF-, and the current of the single-ended signal RF is half the current of the differential signals RF+, RF-. Therefore, when a load impedance is connected between the third connection terminal T3 and the fourth connection terminal T4, the impedance viewed from the first connection terminal T1 and the second connection terminal T2 is 1/1 of the load impedance. quadruple. Conversely, when a load impedance is connected between the first connection terminal T1 and the second connection terminal T2, the impedance seen from the third connection terminal T3 on the load side is four times the load impedance.

The impedance conversion circuit according to the first embodiment has a function of performing balanced-unbalanced conversion and impedance conversion.

Furthermore, since the capacitor Cp2 is connected in parallel to the second main line 12, the second main line 12 and the capacitor Cp2 resonate in parallel at a certain frequency. At this resonance frequency, a high impedance state exists between the second node P2 and the fourth node P4.

Next, the excellent effects of the first embodiment will be described in comparison with an impedance conversion circuit according to a comparative example. In the impedance conversion circuit according to the comparative example, the capacitor Cp2 of the impedance conversion circuit according to the first embodiment is not connected.

In the impedance conversion circuit according to the comparative example, the second node P2 is connected to ground via the second main line 12 . When a resin substrate, a low-temperature co-fired ceramic (LTCC) substrate, a semiconductor substrate on which a multilayer wiring layer is formed, or the like is used as the laminated substrate 30, the second main line 12 can be produced more easily than when a substrate made of a magnetic material is used. It is difficult to make the self-inductance large enough. Therefore, the isolation between the second node P2 and the ground becomes insufficient. Decreased isolation results in increased insertion loss, decreased common mode rejection ratio, increased amplitude imbalance and phase imbalance.

In the impedance conversion circuit according to the first embodiment, the capacitor Cp2 is connected in parallel with the second main line 12. As shown in FIG. Therefore, parallel resonance occurs between the inductance component of the second main line 12 and the capacitor Cp2 at a certain frequency. When parallel resonance occurs, a high impedance state is established between the second node P2 and the fourth node P4, that is, the ground. Therefore, it is possible to ensure sufficient isolation between the second node P2 and the ground.

In a configuration in which a first node P1 and a second node P2 are respectively connected to a pair of differential output nodes or differential input nodes of a differential amplifier, the capacitance of the capacitor Cp2 is such that parallel resonance occurs in the operating frequency band of the differential amplifier. can improve the characteristics of the impedance conversion circuit in the operating frequency band. The impedance conversion circuit according to the first embodiment is mounted, for example, on an RF front-end module.

FIG. 1C is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". The solid line in the graph indicates the simulation result of the impedance conversion circuit according to the first embodiment with the capacitor Cp2 connected, and the dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example without the capacitor Cp2 connected.

The simulation conditions are as follows.
The length, width, and thickness of the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 are set to 2000 μm, 25 μm, and 3 μm, respectively. Both the line spacing between the first main line 11 and the first sub-line 21 and the line spacing between the second main line 12 and the second sub-line 22 were set to 3 μm. The capacitance of capacitor Cp2 was set to 0.7 pF. The dielectric constant of the laminated substrate 30 is set to 4.

In the comparative example, isolation is ensured between the second node P2 and the fourth node P4 only near the frequency of 2.5 GHz. On the other hand, when the capacitor Cp2 is connected, isolation is ensured even in the vicinity of the frequency of 7 GHz. Therefore, it is possible to ensure sufficient isolation between the second node P2 and the fourth node P4 even when operating near the frequency of 7 GHz.

Next, with reference to FIGS. 2A and 2B, an impedance conversion circuit according to a first modification of the first embodiment will be described.

FIG. 2A is an equivalent circuit diagram of the impedance conversion circuit according to the first modification of the first embodiment. In the first embodiment (FIG. 1A), the capacitor Cp2 is connected in parallel with the second main line 12, but in the first modification of the first embodiment, the capacitor Cp2 is connected to the second main line 12. Instead, a capacitor Cp1 is connected in parallel with the first main line 11.

FIG. 2B is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". The solid line in the graph indicates the simulation result of the impedance conversion circuit (FIG. 2A) according to the first modified example of the first embodiment, and the dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example to which the capacitor Cp1 is not connected. .

The simulation conditions other than the capacitance of the capacitor Cp1 are the same as the simulation conditions shown in FIG. 1C. The capacitance of capacitor Cp1 was set to 0.7 pF. Also in this modified example, as in the first example (FIG. 1C), sufficient isolation is ensured in the vicinity of the frequency of 7 GHz.

Next, an impedance conversion circuit according to a second modification of the first embodiment will be described with reference to FIGS. 3A and 3B.

FIG. 3A is an equivalent circuit diagram of the impedance conversion circuit according to the second modification of the first embodiment. In the first embodiment (FIG. 1A), the capacitor Cp2 is connected to both ends of the second main line 12, but in the second modification of the first embodiment, the second node P2 side of the second main line 12 A capacitor Cp2 is connected between the end and the middle point of the second main line 12 .

FIG. 3B is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". The solid line in the graph indicates the simulation result of the impedance conversion circuit (FIG. 3A) according to the second modification of the first embodiment, and the dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example to which the capacitor Cp2 is not connected. .

The simulation conditions are the same as the simulation conditions shown in FIG. 1C. The length of the portion of the second main line 12 that is connected in parallel with the capacitor Cp2 is 1000 μm. In the second modification of the first embodiment, the parallel resonance frequency of the second main line 12 and the capacitor Cp2 is changed as compared with the first embodiment (FIG. 1A), so that sufficient isolation is achieved in the vicinity of the frequency of 8 GHz. is ensured. By changing the length of the portion of the second main line 12 that is connected in parallel with the capacitor Cp2, it is possible to change the frequency range in which sufficient isolation is ensured.

[Second embodiment]
Next, an impedance conversion circuit according to a second embodiment will be described with reference to FIGS. 4A to 7. FIG. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the first embodiment (FIGS. 1A and 1B) will be omitted.

FIG. 4A is an equivalent circuit diagram of the impedance conversion circuit according to the second embodiment, and FIG. 4B is a diagram schematically showing the cross-sectional structure of the impedance conversion circuit according to the second embodiment. The second embodiment includes a capacitor Cp1 connected in parallel to the first main line 11 in addition to the capacitor Cp2 connected in parallel to the second main line 12 . Capacitor Cp1 (FIG. 4B) is mounted on the upper surface of laminated substrate 30, like capacitor Cp2.

A simulation was performed to confirm the excellent effects of the second embodiment. This simulation will be described below.

The insertion loss, common mode rejection ratio (CMRR), amplitude imbalance, and phase imbalance of the impedance conversion circuit according to the second embodiment and the impedance conversion circuit according to the comparative example were obtained by simulation. The impedance conversion circuit according to the comparative example has the same configuration as the impedance conversion circuit according to the second embodiment with the capacitors Cp1 and Cp2 removed. The simulation conditions are the same as those of the first embodiment described with reference to FIG. 1C. The capacitances of the capacitors Cp1 and Cp2 were both set to 0.7 pF.

FIG. 5A is a graph showing insertion loss of an impedance conversion circuit. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the insertion loss in the unit of "dB". Note that the insertion loss increases downward on the vertical axis. Here, the insertion loss means the insertion loss when the first connection terminal T1 and the second connection terminal T2 are driven by differential signals and the single-ended signal is output from the third connection terminal T3. A solid line and a broken line in the graph of FIG. 5A indicate the insertion loss of the impedance conversion circuits according to the second example and the comparative example, respectively. It can be seen that the insertion loss of the impedance conversion circuit according to the second embodiment is improved in the frequency range below about 5.3 GHz.

FIG. 5B is a graph showing the common-mode rejection ratio CMRR of the impedance conversion circuit. The horizontal axis represents frequency in the unit of "GHz", and the vertical axis represents the common mode rejection ratio in the unit of "dB". A solid line and a dashed line in the graph of FIG. 5B indicate the common-mode rejection ratios according to the second example and the comparative example, respectively. The definition of the common mode rejection ratio is explained below.

When the responses of the single-ended signals output from the third connection terminal T3 when the first connection terminal T1 and the second connection terminal T2 are driven by the differential signal and the in-phase signal are denoted by SSD12 and SSC12, respectively, the same The phase signal rejection ratio CMRR is defined as CMRR=SSD12/SSC12. When the impedance conversion circuit is an ideal balun, the response SSC12 of the single-ended signal output from the third connection terminal T3 when the first connection terminal T1 and the second connection terminal T2 are driven by the in-phase signal is almost zero. is. Therefore, it can be said that the larger the value of the common-mode rejection ratio CMRR, the better the characteristics of the balun.

As shown in FIG. 5B, in the frequency range of approximately 2 GHz to 6.5 GHz, the common-mode signal rejection ratio of the impedance conversion circuit according to the second embodiment is larger than that of the impedance conversion circuit according to the comparative example. That is, the characteristics as a balun are improved.

6A and 6B are graphs showing amplitude imbalance and phase imbalance, respectively, of an impedance transformation circuit. The horizontal axis of FIGS. 6A and 6B represents frequency in units of "GHz", the vertical axis of FIG. 6A represents amplitude imbalance in units of "dB", and the vertical axis of FIG. 6B represents phase imbalance in units of "degrees". ”. A solid line and a broken line in the graphs of FIGS. 6A and 6B indicate simulation results of the impedance conversion circuits according to the second example and the comparative example, respectively. Definitions of amplitude imbalance and phase imbalance are described below.

The response of the single-ended signal output from the third connection terminal T3 when the first connection terminal T1 is driven with the single-ended signal is denoted by S13, and the response of the single-ended signal output from the third connection terminal T3 when the second connection terminal T2 is driven with the single-ended signal is denoted by S13. The response of the single-ended signal output from the connection terminal T3 is denoted as S23. Imbalance IMB is defined as IMB=-S13/S23. Amplitude imbalance and phase imbalance are the amplitude and phase components, respectively, of imbalance IMB. It can be said that the closer the amplitude imbalance is to 0 dB and the closer the phase imbalance is to 0 degrees, the better the characteristics of the balanced-to-unbalanced conversion circuit.

As shown in FIGS. 6A and 6B, by adopting the configuration of the impedance conversion circuit according to the second embodiment, the amplitude imbalance and phase imbalance are improved in the frequency range of about 6 GHz or less. Recognize.

FIG. 7 is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". A solid line in the graph indicates the simulation result of the impedance conversion circuit according to the second embodiment, and a dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example.

In the first embodiment (FIG. 1C), sufficient isolation is ensured in the vicinity of the frequency of 7 GHz, but in the second embodiment, sufficient isolation is ensured in the vicinity of the frequency of 5 GHz. The frequency range in which sufficient isolation is ensured can be changed by adjusting the capacitances of the capacitors Cp1 and Cp2. Also in the second embodiment, it is possible to ensure sufficient isolation between the second node P2 and the fourth node P4 in a specific frequency range.

From the simulation results shown in FIGS. 5A to 7, the characteristics of the impedance conversion circuit are improved by connecting the capacitors Cp1 and Cp2 in parallel to the first main line 11 and the second main line 12, respectively. was confirmed.

In addition to connecting the capacitor Cp2 in parallel with the second main line 12, by connecting the capacitor Cp1 in parallel with the first main line 11, the first main line 11 and the second main line 12 Symmetry can be maintained. In order to maintain symmetry, it is preferable to equalize the inductances of the first main line 11 and the second main line 12 and equalize the capacitances of the capacitors Cp1 and Cp2.

[Third embodiment]
Next, an impedance conversion circuit according to a third embodiment will be described with reference to FIGS. 8 to 10B. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 7 will be omitted.

FIG. 8 is an equivalent circuit diagram of the impedance conversion circuit according to the third embodiment. In the second embodiment (FIG. 4A), the turns ratio (line length ratio) between the first main line 11 and the first sub-line 21 and the turns ratio (line length ratio) between the second main line 12 and the second sub-line 22 ratio) are both 1:1. On the other hand, in the third embodiment, the turns ratio (line length ratio) between the first main line 11 and the first sub-line 21 and the turns ratio (line length ratio) between the second main line 12 and the second sub-line 22 ratio) are both 2 to 1.

In the second embodiment (FIG. 4A), capacitors Cp1 and Cp2 are connected to both ends of the first main line 11 and the second main line 12, respectively. On the other hand, in the third embodiment, the capacitor Cp1 is connected in parallel with a portion of the first main line 11 and the other capacitor Cp2 is connected in parallel with a portion of the second main line 12 . For example, the capacitor Cp2 is connected between the second node P2 and the midpoint of the second main line 12. That is, the capacitor Cp2 is connected in parallel with a part of the inductance component of the second main line 12 . Capacitor Cp1 is similarly connected between first node P1 and the midpoint of first main line 11 .

Next, the operation of the impedance conversion circuit according to the third embodiment will be explained.
In the impedance conversion circuit according to the third embodiment, the voltage between the third connection terminal T3 and the fourth connection terminal T4 is three times the voltage between the first connection terminal T1 and the second connection terminal T2. . Also, the current that flows into and out of the third connection terminal T3 is ⅓ times the current that flows into and out of the first connection terminal T1 and the second connection terminal T2.

Thus, the voltage of the single-ended signal RF appearing at the third connection terminal T3 is three times the voltage of the differential signals RF+ and RF- appearing at the first connection terminal T1 and the second connection terminal T2, and the single-ended signal The RF current is 1/3 times the current of the differential signals RF+ and RF-. Therefore, when a load impedance is connected between the third connection terminal T3 and the fourth connection terminal T4, the impedance viewed from the first connection terminal T1 and the second connection terminal T2 is 1/1 of the load impedance. Nine times. Conversely, when a load impedance is connected between the first connection terminal T1 and the second connection terminal T2, the impedance seen from the third connection terminal T3 on the load side is nine times the load impedance. Thus, the impedance conversion ratio of the impedance conversion circuit according to the third embodiment is nine.

Further, in the third embodiment, a portion of the second main line 12 and the capacitor Cp2 are in parallel resonance. When a portion of the second main line 12 and the capacitor Cp2 are in parallel resonance, the state between the second node P2 and the fourth node P4 (ground) becomes a high impedance state. Therefore, as in the second embodiment, sufficient isolation between the second node P2 and the ground can be ensured. Further, by connecting the capacitor Cp1 in parallel to a part of the first main line 11, the symmetry between the first main line 11 and the second main line 12 can be maintained.

Next, with reference to FIGS. 9A to 10B, the results of simulation performed to confirm the excellent effects of the third embodiment will be described. The first main line 11 and the second main line 12 of the impedance conversion circuit to be simulated had a length of 3200 μm and a width of 30 μm. The length of the first sub-line 21 and the second sub-line 22 was set to 1600 μm, and the width was set to 34 μm. The capacitance of capacitors Cp1 and Cp2 was set to 0.3 pF. Other simulation conditions are the same as the simulation conditions shown in FIG. 1C of the first embodiment.

9A, 9B, 10A, and 10B show the insertion loss, common-mode rejection ratio, and amplitude of the impedance conversion circuit in the same manner as FIGS. 5A, 5B, 6A, and 6B of the second embodiment, respectively. 4 is a graph showing the degree of imbalance and the degree of phase imbalance; A solid line and a dashed line in these graphs indicate the simulation results of the impedance conversion circuit according to the third embodiment and the comparative example that does not include the capacitors Cp1 and Cp2, respectively.

As shown in FIG. 9A, the impedance conversion circuit according to the third example shows no improvement in terms of insertion loss compared to the impedance conversion circuit according to the comparative example. As shown in FIG. 9B, in the impedance conversion circuit according to the third embodiment, the common mode signal rejection ratio is improved in the frequency range of approximately 3 GHz to 5.3 GHz. As shown in FIG. 10A, in the impedance conversion circuit according to the third embodiment, the amplitude imbalance is improved in the frequency range of approximately 2 GHz to 5 GHz. As shown in FIG. 10B, in the impedance conversion circuit according to the third embodiment, the degree of phase imbalance is improved in the frequency range of approximately 3 GHz to 5 GHz.

From the simulation results shown in FIGS. 9A to 10B, by connecting the capacitors Cp1 and Cp2 in parallel to a portion of the first main line 11 and a portion of the second main line 12, respectively, the characteristics of the impedance conversion circuit was confirmed to be improved.

Next, a modified example of the third embodiment will be described.
In the third embodiment, the turns ratio (line length ratio) between the first main line 11 and the first sub-line 21 and the turns ratio (line length ratio) between the second main line 12 and the second sub-line 22 are Both are 2 to 1. The turns ratio may be other than 2:1. Thereby, the impedance conversion ratio can be adjusted.

[Fourth embodiment]
Next, an impedance conversion circuit according to a fourth embodiment will be described with reference to FIGS. 11 to 13B. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the third embodiment described with reference to FIGS. 8 to 10B will be omitted.

FIG. 11 is an equivalent circuit diagram of the impedance conversion circuit according to the fourth embodiment. In the impedance conversion circuit (FIG. 8) according to the third embodiment, the capacitor Cp2 is connected in parallel with a portion of the second main line 12, and the capacitor Cp1 is connected in parallel with a portion of the first main line 11. ing. On the other hand, in the fourth embodiment, the capacitor Cp2 is connected across the second main line 12 and the capacitor Cp1 is connected across the first main line 11 .

The impedance transformation ratio of the impedance transformation circuit according to the fourth embodiment is the same as that of the impedance transformation circuit according to the third embodiment.

Next, the excellent effects of the fourth embodiment will be described.
In the fourth embodiment, the parallel resonance of the entire second main line 12 and the capacitor Cp2 ensures sufficient isolation between the second node P2 and the fourth node P4 (ground). can. Further, since the capacitor Cp1 is connected in parallel to the first main line 11, symmetry between the first main line 11 and the second main line 12 can be ensured.

Next, with reference to the drawings from FIG. 12A to FIG. 13B, the result of simulation performed to confirm the excellent effect of the fourth embodiment will be described. The first main line 11 and the second main line 12 of the impedance conversion circuit to be simulated had a length of 3200 μm and a width of 30 μm. The length of the first sub-line 21 and the second sub-line 22 was set to 1600 μm, and the width was set to 34 μm. The capacitance of capacitors Cp1 and Cp2 was set to 0.3 pF. Other simulation conditions are the same as the simulation conditions shown in FIG. 1C of the first embodiment.

12A, 12B, 13A, and 13B show the insertion loss, common-mode rejection ratio, and amplitude of the impedance conversion circuit in the same manner as FIGS. 8A, 8B, 9A, and 9B of the third embodiment, respectively. 4 is a graph showing the degree of imbalance and the degree of phase imbalance; A solid line and a dashed line in these graphs indicate the simulation results of the impedance conversion circuit according to the fourth embodiment and the comparative example that does not include the capacitors Cp1 and Cp2, respectively.

As shown in FIG. 12A, the impedance conversion circuit according to the fourth example exhibits improved insertion loss in the frequency range of approximately 1.5 GHz to 3 GHz, compared to the impedance conversion circuit according to the comparative example. As shown in FIG. 12B, in the impedance conversion circuit according to the fourth embodiment, the common-mode rejection ratio is improved in the frequency range of approximately 2 GHz to 4.2 GHz. As shown in FIG. 13A, in the impedance conversion circuit according to the fourth embodiment, the amplitude imbalance is improved in the frequency range of approximately 2 GHz to 4 GHz. As shown in FIG. 13B, in the impedance conversion circuit according to the fourth embodiment, the degree of phase imbalance is improved in the frequency range of approximately 3 GHz to 4 GHz.

From the simulation results shown in FIGS. 12A to 13B, the characteristics of the impedance conversion circuit are improved by connecting the capacitors Cp1 and Cp2 in parallel to the first main line 11 and the second main line 12, respectively. was confirmed.

[Fifth embodiment]
Next, the impedance conversion circuit according to the fifth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 7 will be omitted.

FIG. 14 is a schematic equivalent circuit diagram of the impedance conversion circuit according to the fifth embodiment. In FIG. 14, the transmission line transformer 40 comprising the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 of the impedance conversion circuit according to the second embodiment (FIG. 4A) is indicated by broken lines. showing. The transmission line transformer 40 has a first node P1, a second node P2, a third node P3, and a fourth node P4 as input/output nodes for high-frequency signals.

In the second embodiment (FIG. 4A), the first node P1 and the third node P3 are directly connected to the first connection terminal T1 and the third connection terminal T3, respectively, and the second node P2 and the fourth node P4 are connected to , are directly connected to the second connection terminal T2 and the fourth connection terminal T4, respectively. On the other hand, in the fifth embodiment, between the first node P1 and the first connection terminal T1, between the second node P2 and the second connection terminal T2, and between the third node P3 and the third connection terminal T3. and between the fourth node P4 and the fourth connection terminal T4, capacitors Cdc1, Cdc2, Cdc3, and Cdc4 are inserted in series, respectively.

The first connection terminal T1 and the second connection terminal T2 are used as input/output terminals for the differential signals RF+ and RF-, and the third connection terminal T3 is used as an input/output terminal for the single-ended signal RF. be. A fourth connection terminal T4 is connected to the ground.

Capacitors Cdc1, Cdc2, Cdc3, and Cdc4 function as impedance matching capacitors and DC cut capacitors.

Next, the excellent effects of the fifth embodiment will be described.
In the fifth embodiment, by connecting the capacitors Cdc1, Cdc2, Cdc3, and Cdc4, the DC component of the signal input to the transmission line transformer 40 and the signal output from the transmission line transformer 40 can be removed. . Furthermore, by appropriately setting the capacitances of the capacitors Cdc1, Cdc2, Cdc3, and Cdc4, the input impedance of the impedance conversion circuit can be adjusted to a target value.

Next, an impedance conversion circuit according to a modification of the fifth embodiment will be described. In the fifth embodiment, the capacitors Cdc1, Cdc2, Cdc3 and Cdc4 are connected to the first node P1, the second node P2, the third node P3 and the fourth node P4. A capacitor may be connected to only one side. As the transmission line transformer 40, in addition to the configuration according to the second embodiment, the configurations of the impedance conversion circuits according to the first embodiment (FIG. 1A), the third embodiment (FIG. 8), and the fourth embodiment (FIG. 11) may be used.

Next, impedance conversion circuits according to other various modifications of the fifth embodiment will be described with reference to FIGS. 15 to 19. FIG. 15, 16, 17, 18, and 19 are schematic equivalent circuit diagrams of impedance conversion circuits according to modifications of the fifth embodiment.

In the modification shown in FIG. 15, inductors Lz1, Lz2, Lz3 and Lz4 are used in place of the capacitors Cdc1, Cdc2, Cdc3 and Cdc4 of the impedance conversion circuit according to the fifth embodiment. Depending on the inductance of the inductor Lz4 and the design frequency of the impedance conversion circuit, the impedance of the inductor Lz4 is sufficiently low, so that the fourth node P4 can be kept grounded at high frequencies. In this case, the inductor Lz4 has a function of matching impedance.

In the modification shown in FIG. 16, instead of the capacitors Cdc1, Cdc2, Cdc3 and Cdc4 of the impedance conversion circuit according to the fifth embodiment (FIG. 14), a capacitor Cmn1 is provided between the first node P1 and the second node P2. A capacitor Cmn2 is connected between the third node P3 and the fourth node P4.

In the modification shown in FIG. 17, inductors Lmn1 and Lmn2 are used instead of the capacitors Cmn1 and Cmn2 of the modification shown in FIG. In the modification shown in FIG. 18, in addition to the capacitors Cdc1, Cdc2, Cdc3 and Cdc4 of the impedance conversion circuit according to the fifth embodiment (FIG. 14), a capacitor Cmn1 is further provided between the first node P1 and the second node P2. , and a capacitor Cmn2 is connected between the third node P3 and the fourth node P4. In the modification shown in FIG. 19, inductors Lmn1 and Lmn2 are used instead of the capacitors Cmn1 and Cmn2 of the modification shown in FIG.

Between the first node P1 and the first connection terminal T1, between the second node P2 and the second connection terminal T2, between the third node P3 and the third connection terminal T3, and a reactance element may be inserted in series to at least one between the fourth node P4 and the fourth connection terminal T4. Further, a reactance element may be inserted in parallel with the transmission line transformer 40 between the first node P1 and the second node P2 and/or between the third node P3 and the fourth node P4. . By adjusting the capacitance or inductance of these reactance elements, the input impedance of the impedance conversion circuit can be adjusted to a target value.

[Sixth embodiment]
Next, an amplifier module according to a sixth embodiment will be described with reference to FIG. The amplifier module according to the sixth embodiment incorporates the impedance conversion circuit (FIG. 4A) according to the second embodiment. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 6B will be omitted.

FIG. 20 is an equivalent circuit diagram of the impedance conversion circuit according to the sixth embodiment. In the impedance conversion circuit according to the sixth embodiment, the power supply circuit 41 is connected to the portion where the first sub-line 21 and the second sub-line 22 are connected to each other. The power supply circuit 41 includes a choke coil Lch, a bypass capacitor Cbp, and a power supply terminal Vcc.

A portion where the first sub-line 21 and the second sub-line 22 are connected to each other is connected to the power supply terminal Vcc via the choke coil Lch. A power supply voltage is applied to the power supply terminal Vcc from an external power supply circuit. A bypass capacitor Cbp is connected between the power supply terminal Vcc and the ground.

A pair of output terminals of the differential amplifier 42 are connected to the first connection terminal T1 and the second connection terminal T2, respectively. For example, the differential amplifier 42 includes emitter-grounded bipolar transistors Q1 and Q2, and the collectors of the bipolar transistors Q1 and Q2 are connected to the first connection terminal T1 and the second connection terminal T2, respectively.

A power supply voltage is applied from the power supply terminal Vcc through the choke coil Lch and the second sub-line 22 to the collector of the bipolar transistor Q1. Further, the power supply voltage is applied to the collector of the bipolar transistor Q2 from the power supply terminal Vcc through the choke coil Lch and the first sub-line 21 .

Next, the excellent effects of the sixth embodiment will be described.
In the sixth embodiment, power can be supplied through the impedance conversion circuit to the differential amplifier 42 connected to the first connection terminal T1 and the second connection terminal T2. Also, power can be supplied to two bipolar transistors Q1 and Q2 via one choke coil Lch.

Next, an impedance conversion circuit according to a modification of the sixth embodiment will be described with reference to FIG.

FIG. 21 is an equivalent circuit diagram of an impedance conversion circuit according to a modification of the sixth embodiment. In this modification, a capacitor Cdc3 is inserted in series between the third node P3 and the third connection terminal T3, and a capacitor Cdc4 is inserted in series between the fourth node P4 and the fourth connection terminal T4 (ground). It is By inserting the capacitors Cdc3 and Cdc4, it is possible to adjust the impedance of the differential amplifier 42 looking at the load side.

[Seventh embodiment]
Next, the impedance conversion circuit according to the seventh embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the sixth embodiment described with reference to FIG. 20 will be omitted.

FIG. 22 is a schematic equivalent circuit diagram of the impedance conversion circuit according to the seventh embodiment. In the sixth embodiment (FIG. 20), a power supply circuit 41 is connected to a portion where the first sub-line 21 and the second sub-line 22 are connected to each other. In contrast, in the seventh embodiment, the power supply circuit 41 is connected to the first connection terminal T1 and the second connection terminal T2 on the differential signal input side.

For example, the power supply terminal Vcc is connected to the first connection terminal T1 and the second connection terminal T2 via choke coils Lch1 and Lch2, respectively. The power supply terminal Vcc is further connected to the ground via a bypass capacitor Cbp. In the sixth embodiment (FIG. 20), the first connection terminal T1 and the first node P1 are directly connected, and the second connection terminal T2 and the second node P2 are directly connected. In contrast, in the seventh embodiment, the capacitor Cdc1 is connected in series between the first connection terminal T1 and the first node P1, and the capacitor Cdc2 is connected between the second connection terminal T2 and the second node P2. are connected in series. Further, similarly to the modification of the sixth embodiment (FIG. 21), capacitors Cdc3 are provided between the third node P3 and the third connection terminal T3 and between the fourth node P4 and the fourth connection terminal T4, respectively. , Cdc4 are connected.

Next, the excellent effects of the seventh embodiment will be described.
In the seventh embodiment, power can be supplied to the differential amplifier 42 from the power supply circuit 41 connected to the first connection terminal T1 and the second connection terminal T2 of the impedance conversion circuit. In the sixth embodiment, in order to supply power to the differential amplifier 42 via the first sub-line 21 and the second sub-line 22, the voltage between the differential amplifier 42 and the first node P1 and the differential amplifier 42 and the second node P2 cannot be inserted in series. In contrast, in the seventh embodiment, capacitors Cdc1 and Cdc2 can be inserted in series between the differential amplifier 42 and the first node P1 and between the differential amplifier 42 and the second node P2, respectively. can. Therefore, an excellent effect is obtained that the degree of freedom of impedance adjustment is increased.

[Eighth embodiment]
Next, the impedance conversion circuit according to the eighth embodiment will be described with reference to FIGS. 23 to 25B. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 6B will be omitted.

FIG. 23 is an equivalent circuit diagram of the impedance conversion circuit according to the eighth embodiment. In the second embodiment (FIG. 4A), the fourth connection terminal T4 connected to the fourth node is used as a ground terminal, and the fourth node P4 is connected to the ground. In contrast, in the eighth embodiment, the second connection terminal T2 connected to the second node P2 is used as a ground terminal, and the second node P2 is connected to the ground.

In the eighth embodiment, the first connection terminal T1 is used as an input/output terminal for the single-ended signal RF, and the third connection terminal T3 and the fourth connection terminal T4 are input/output terminals for the differential signals RF+ and RF-. used as In the second embodiment (FIG. 4A), when the differential signals RF+ and RF- are converted to the single-ended signal RF, the impedance viewed from the load side is converted to 1/4 times, and the single-ended signal RF is converted to the differential signal RF. When converting to signals RF+ and RF-, the impedance looking at the load side is quadrupled. Conversely, in the eighth embodiment, when the differential signals RF+ and RF- are converted to the single-ended signal RF, the impedance viewed from the load side is quadrupled, and the single-ended signal RF is converted to When converting to differential signals RF+ and RF-, the impedance viewed from the load side is converted to 1/4 times.

Next, the excellent effects of the eighth embodiment will be described. In the eighth embodiment, similarly to the second embodiment, since the capacitor Cp2 is connected in parallel to the second main line 12, sufficient isolation between the fourth node P4 and the second node P2 (ground) is ensured. can be secured. Furthermore, since the capacitor Cp1 is also connected in parallel to the first main line 11, the symmetry between the first main line 11 and the second main line 12 can be maintained.

Next, with reference to the drawings from FIG. 24A to FIG. 25B, the result of simulation performed to confirm the excellent effects of the eighth embodiment will be described. The length of each of the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 of the impedance conversion circuit to be simulated was set to 2000 μm, and the width was set to 25 μm. The capacitance of capacitors Cp1 and Cp2 was set to 0.7 pF. Other simulation conditions are the same as the simulation conditions in the first embodiment shown in FIG. 1C.

24A, 24B, 25A, and 25B show the insertion loss, common-mode rejection ratio, and amplitude of the impedance conversion circuit in the same manner as FIGS. 5A, 5B, 6A, and 6B of the second embodiment, respectively. 4 is a graph showing the degree of imbalance and the degree of phase imbalance; Solid lines and broken lines in the graphs of FIGS. 24A, 24B, 25A, and 24B respectively indicate the simulation results of the impedance conversion circuit according to the eighth embodiment and the comparative example that does not include the capacitors Cp1 and Cp2. The insertion loss shown in FIG. 24A is the insertion loss when the third connection terminal T3 and the fourth connection terminal T4 are driven by the differential signals RF+ and RF- and a single-ended signal is output from the first connection terminal T1. means.

As shown in FIG. 24A, the impedance conversion circuit according to the eighth embodiment exhibits improved insertion loss in the frequency range of approximately 1.5 GHz to 6 GHz, compared to the impedance conversion circuit according to the comparative example. As shown in FIG. 24B, in the impedance conversion circuit according to the eighth embodiment, the common-mode rejection ratio is improved in the frequency range of approximately 2 GHz to 7 GHz. As shown in FIG. 25A, in the impedance conversion circuit according to the eighth embodiment, the amplitude imbalance is improved in the frequency range of approximately 3 GHz to 8 GHz. As shown in FIG. 25B, in the impedance conversion circuit according to the eighth embodiment, the degree of phase imbalance is improved in the frequency range of approximately 3 GHz to 6 GHz.

From the simulation results shown in FIGS. 24A to 25B, it has been confirmed that the characteristics of the impedance conversion circuit are improved even in the configuration in which the second node P2 is grounded.

[Ninth embodiment]
Next, the impedance conversion circuit according to the ninth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 6B will be omitted.

FIG. 26 is an equivalent circuit diagram of the impedance conversion circuit according to the ninth embodiment. The impedance conversion circuit according to the second embodiment (FIG. 4A) functions as a balanced-unbalanced conversion circuit by connecting the fourth node P4 to the ground. In contrast, in the ninth embodiment, none of the nodes of the impedance conversion circuit are grounded. Both the terminal pair consisting of the first connection terminal T1 and the second connection terminal T2 and the terminal pair consisting of the third connection terminal T3 and the fourth connection terminal T4 are used as input/output terminals for the differential signals RF+ and RF-. be. That is, the impedance conversion circuit according to the ninth embodiment operates as a differential signal impedance conversion circuit on both the input side and the output side.

Next, the excellent effects of the ninth embodiment will be described.
In the ninth embodiment, by connecting the capacitor Cp1 in parallel to the first main line 11, the isolation between the first node P1 and the third node P3 can be increased in the frequency range including the parallel resonance frequency. . By connecting the capacitor Cp2 in parallel with the second main line 12, the isolation between the second node P2 and the fourth node P4 can be increased in the frequency range including the parallel resonance frequency.

[Tenth embodiment]
Next, a tenth embodiment will be described with reference to FIGS. 27A and 27B. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the first embodiment described with reference to FIGS. 1A to 1C will be omitted.

FIG. 27A is an equivalent circuit diagram of the impedance conversion circuit according to the tenth embodiment. In the first embodiment (FIG. 1A), the capacitor Cp2 is connected in parallel with the second main line 12. As shown in FIG. On the other hand, in the tenth embodiment, the capacitor Cp4 is connected in parallel with the second sub-line 22 .

Next, the excellent effects of the tenth embodiment will be described.
Since the capacitor Cp4 is connected in parallel to the second sub-line 22, parallel resonance occurs between the inductance component of the second sub-line 22 and the capacitor Cp4 at a certain frequency. A high impedance state is established between both ends of the second sub-line 22 in the frequency range including this resonance frequency. Therefore, the impedance between the second node P2 and the fourth node P4 (ground) at both ends of the second main line 12 electromagnetically coupled to the second sub-line 22 is brought into a high impedance state. As a result, sufficient isolation can be ensured between the second node P2 and the ground.

FIG. 27B is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". A solid line in the graph indicates the simulation result of the impedance conversion circuit according to the tenth embodiment, and a dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example to which the capacitor Cp4 is not connected.

The simulation conditions other than the capacitor-related conditions are the same as the simulation conditions in the first embodiment described with reference to FIG. 1C. Note that the capacitance of the capacitor Cp4 was set to 0.7 pF.

In the comparative example, isolation is ensured between the second node P2 and the fourth node P4 only near the frequency of 2.5 GHz. On the other hand, when the capacitor Cp4 is connected, isolation is ensured even near the frequency of 7.3 GHz. Therefore, sufficient isolation can be ensured between the second node P2 and the fourth node P4 even when operating near the frequency of 7.3 GHz.

Next, a first modification of the tenth embodiment will be described with reference to FIGS. 28A and 28B.
FIG. 28A is an equivalent circuit diagram of the impedance conversion circuit according to the first modification of the tenth embodiment. In this modified example, the capacitor Cp4 (FIG. 27A) is not connected, and the capacitor Cp3 is connected in parallel to the first sub-line 21 .

FIG. 28B is a graph showing simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents the frequency in the unit of "GHz", and the vertical axis represents the pass coefficient S24 in the unit of "dB". The solid line in the graph indicates the simulation result of the impedance conversion circuit according to the first modification of the tenth embodiment, and the dashed line indicates the simulation result of the impedance conversion circuit according to the comparative example to which the capacitor Cp3 is not connected.

The simulation conditions other than the capacitor-related conditions are the same as the simulation conditions in the first embodiment described with reference to FIG. 1C. Note that the capacitance of the capacitor Cp3 was set to 0.7 pF.

It can be seen that in the first modified example of the tenth embodiment, isolation is ensured even in the vicinity of the frequency of 7.5 GHz.

Next, an impedance conversion circuit according to a second modification of the tenth embodiment will be described with reference to FIGS. 29 to 31B.

FIG. 29 is an equivalent circuit diagram of the impedance conversion circuit according to the second modification of the tenth embodiment. In the tenth embodiment (FIG. 27A), a capacitor Cp4 is connected in parallel with the second sub-line 22. As shown in FIG. In this modification, a capacitor VCp3 is also connected in parallel to the first sub-line 21 as well.

Next, the excellent effects of the second modification of the tenth embodiment will be described. Also in the second modification of the tenth embodiment, isolation between the second node P2 and the ground can be ensured as in the tenth embodiment. Furthermore, since the capacitors Cp3 and Cp4 are connected in parallel to the first sub-line 21 and the second sub-line 22, respectively, the coupling transmission line made up of the first main line 11 and the first sub-line 21 and the second main line Symmetry with the coupled transmission line consisting of the line 12 and the second sub-line 22 can be maintained.

Next, with reference to FIGS. 30A to 31B, results of a simulation performed to confirm the excellent effects of the second modification of the tenth embodiment will be described. The length of the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 of the impedance conversion circuit to be simulated was set to 2000 μm, and the width was set to 25 μm. The capacitance of capacitors Cp3 and Cp4 was set to 0.7 pF.

30A, 30B, 31A, and 31B show the insertion loss, common-mode rejection ratio, and amplitude of the impedance conversion circuit in the same manner as FIGS. 5A, 5B, 6A, and 6B of the second embodiment, respectively. 4 is a graph showing the degree of imbalance and the degree of phase imbalance; A solid line and a dashed line in these graphs indicate the simulation results of the impedance conversion circuit according to the second modification of the tenth embodiment and the comparative example that does not include the capacitors Cp3 and Cp4, respectively.

As shown in FIG. 30A, in the impedance conversion circuit according to the second modification of the tenth embodiment, the insertion loss is improved in the frequency range of approximately 2 GHz to 5.5 GHz compared to the impedance conversion circuit according to the comparative example. be done. As shown in FIG. 30B, in the impedance conversion circuit according to the second modification of the tenth embodiment, the common-mode signal rejection ratio is improved in the frequency range of about 2 GHz to 5.5 GHz. As shown in FIG. 31A, in the impedance conversion circuit according to the second modification of the tenth embodiment, the amplitude imbalance is improved in the frequency range of approximately 1.5 GHz to 6 GHz. As shown in FIG. 31B, in the impedance conversion circuit according to the second modification of the tenth embodiment, the degree of phase imbalance is improved in the frequency range of approximately 3 GHz to 6 GHz.

From the simulation results shown in FIGS. 30A to 31B, the characteristics of the impedance conversion circuit are improved by connecting the capacitors Cp3 and Cp4 in parallel to the first sub-line 21 and the second sub-line 22, respectively. was confirmed.

[11th embodiment]
Next, the impedance conversion circuit according to the eleventh embodiment will be described with reference to FIGS. 32 to 34B. Hereinafter, the description of the configuration common to the impedance conversion circuit according to the second embodiment described with reference to FIGS. 4A to 7 will be omitted.

FIG. 32 is an equivalent circuit diagram of the impedance conversion circuit according to the eleventh embodiment. In the second embodiment (FIG. 4A), capacitors Cp1 and Cp2 are connected in parallel to the first main line 11 and the second main line 12, respectively. On the other hand, in the eleventh embodiment, capacitors Cp3 and Cp4 are also connected in parallel to the first sub-line 21 and the second sub-line 22, respectively.

Next, the excellent effects of the eleventh embodiment will be described.
In the eleventh embodiment, parallel resonance occurs between the second main line 12 and the capacitor Cp2, and parallel resonance occurs between the second sub-line 22 and the capacitor Cp4. A high impedance state exists between the second node P2 and the fourth node P4 (ground) in the frequency range including this resonance frequency. Therefore, sufficient isolation can be ensured between the second node P2 and the ground. Also, since the capacitor Cp1 is connected in parallel to the first main line 11 and the capacitor Cp2 is connected in parallel to the first sub-line 21, the coupled transmission line composed of the first main line 11 and the first sub-line 21 , and the symmetry of the coupled transmission line composed of the second main line 12 and the second sub-line 22 can be maintained.

Next, with reference to the drawings from FIG. 33A to FIG. 34B, the result of simulation performed to confirm the excellent effect of the eleventh embodiment will be described. The length of the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 of the impedance conversion circuit to be simulated was set to 2000 μm, and the width was set to 25 μm. The capacitance of capacitors Cp1, Cp2, Cp3, and Cp4 was 0.7 pF. Other simulation conditions are the same as the simulation conditions in the first embodiment shown in FIG. 1C.

33A, 33B, 34A, and 34B show the insertion loss, common-mode rejection ratio, and amplitude of the impedance conversion circuit in the same manner as FIGS. 5A, 5B, 6A, and 6B of the second embodiment, respectively. 4 is a graph showing the degree of imbalance and the degree of phase imbalance; A solid line and a dashed line in these graphs indicate the simulation results of the impedance conversion circuit according to the eleventh embodiment and the comparative example that does not include the capacitors Cp1, Cp2, Cp3 and Cp4, respectively.

As shown in FIG. 33A, the impedance conversion circuit according to the eleventh embodiment exhibits improved insertion loss in the frequency range of about 2 GHz to 4.5 GHz compared to the impedance conversion circuit according to the comparative example. As shown in FIG. 33B, in the impedance conversion circuit according to the eleventh embodiment, the common-mode rejection ratio is improved in the frequency range of approximately 1 GHz to 5 GHz. As shown in FIG. 34A, in the impedance conversion circuit according to the eleventh embodiment, the amplitude imbalance is improved in the frequency range of approximately 1.5 GHz to 6 GHz. As shown in FIG. 34B, in the impedance conversion circuit according to the eleventh embodiment, the degree of phase imbalance is improved in the frequency range of approximately 3 GHz to 4.5 GHz.

From the simulation results shown in FIGS. 33A to 34B, the capacitors Cp1 and Cp2 are connected in parallel to the first main line 11 and the second main line 12, respectively, and the first sub-line 21 and the second sub-line are connected in parallel. It was confirmed that the characteristics of the impedance conversion circuit are improved by connecting capacitors Cp3 and Cp4 in parallel to 22, respectively.

[Twelfth embodiment]
Next, the impedance conversion circuit according to the twelfth embodiment will be described with reference to FIGS. 35 and 36. FIG.

FIG. 35 is an equivalent circuit diagram of the impedance conversion circuit according to the twelfth embodiment. In the impedance conversion circuit according to the twelfth embodiment, the capacitors Cdc1 and Cdc2 of the impedance conversion circuit (FIG. 22) according to the seventh embodiment are omitted, and instead a capacitor Cmn1 is provided between the first node P1 and the second node P2. It is connected.

FIG. 36 is an exploded perspective view showing the conductor pattern of the impedance conversion circuit according to the twelfth embodiment. The impedance conversion circuit according to the twelfth embodiment is composed of a laminated substrate in which dielectric layers and conductor layers are alternately laminated. A surface conductor layer L0 is disposed on the upper surface of the laminated substrate, and in the laminated substrate, counted from the upper surface, a first conductor layer L1, a second conductor layer L2, a third conductor layer L3, and a fourth layer. of conductor layers L4 are arranged. Although not shown in FIG. 36, a fifth conductor layer functioning as a ground plane is arranged under the fourth conductor layer L4. This ground plane may function as a microstrip line ground plane for the first main line 11 , the second main line 12 , the first sub-line 21 and the second sub-line 22 . Furthermore, conductor patterns used as the first connection terminal T1, the second connection terminal T2, the third connection terminal T3, the fourth connection terminal T4 (ground terminal), and the power supply terminal Vcc are arranged on the lower surface of the laminated substrate. ing.

Conductor patterns functioning as a first node P1, a second node P2, a third node P3, and a fourth node P4 are arranged on the surface conductor layer L0. Furthermore, a conductor pattern connected to the third connection terminal T3, the fourth connection terminal T4, the power supply terminal Vcc, a conductor pattern L0A connected to the ground, and a relay conductor pattern L0B are arranged.

Conductor patterns forming the first main line 11 and the second main line 12 are arranged on the first conductor layer L1. The first main line 11 and the second main line 12 have a spiral shape with about 5/4 turns. When viewed from the top side, the first main line 11 turns clockwise from the inner peripheral end to the outer peripheral end, and the second main line 12 turns counterclockwise from the inner peripheral end to the outer peripheral end.

Conductor patterns forming the first sub-line 21 and the second sub-line 22 are arranged on the second conductor layer L2. The first sub-line 21 has a shape that substantially overlaps the first main line 11 in plan view, and the second sub-line 22 has a shape that substantially overlaps the second main line 12 in plan view.

Conductor patterns L3A and L4A are arranged on the third conductor layer L3 and the fourth conductor layer L4, respectively. In addition to these conductor patterns, inner-layer lands for relaying vias are arranged on the conductor layers L1, L2, L3, and L4. In FIG. 36, the display of the inner land is omitted.

The outer end of the first main line 11 is connected to the conductor pattern of the first node P1 via vias, and the inner end of the first main line 11 is connected to the conductor pattern of the third node P3 via vias. ing. The outer end of the second main line 12 is connected to the conductor pattern of the second node P2 via vias, and the inner end of the second main line 12 is connected to the conductor pattern of the fourth node P4 via vias. ing.

The outer end of the first main line 11 is connected to the outer end of the second sub-line 22 via vias. The end of the second main line 12 on the outer peripheral side is connected to the end of the first sub-line 21 on the outer peripheral side via vias. The inner peripheral side end of the first sub-line 21 is connected to the inner peripheral side end of the second sub-line 22 via vias, the conductor pattern L3A, and vias. The conductor pattern connected to the power supply terminal Vcc is connected to the relay conductor pattern L0B via the via, the conductor pattern L4A, and the via.

The conductor pattern of the surface conductor layer L0 is used as terminals for mounting surface mount components. A capacitor Cp1 is mounted on the conductor pattern of the first node P1 and the conductor pattern of the third node P3. A capacitor Cp2 is mounted on the conductor pattern of the second node P2 and the conductor pattern of the fourth node P4. A capacitor Cmn1 is mounted on the conductor pattern of the first node P1 and the conductor pattern of the second node P2.

A choke coil Lch1 is mounted on the conductor pattern of the first node P1 and the conductor pattern connected to the power supply terminal Vcc. A choke coil Lch2 is mounted on the conductor pattern of the second node P2 and the relay conductor pattern L0B.

A bypass capacitor Cbp is mounted on the conductor pattern connected to the power supply terminal Vcc and the conductor pattern L0A. The conductor pattern L0A is connected to the ground. A capacitor Cdc3 is mounted on the conductor pattern connected to the third connection terminal T3 and the conductor pattern of the third node P3. A capacitor Cdc4 is mounted on the conductor pattern connected to the fourth connection terminal T4 and the conductor pattern of the fourth node P4.

Next, the excellent effects of the twelfth embodiment will be described.
By arranging the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 on a common laminated substrate, it is possible to reduce the size of the impedance conversion circuit. By configuring the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 with spiral-shaped conductor patterns, the self-inductance of these transmission lines can be increased. . By overlapping the first main line 11 and the first sub-line 21 in plan view, the electromagnetic coupling between the two can be strengthened. The same applies to the second main line 12 and the second sub-line 22 .

Next, an impedance conversion circuit according to a modification of the twelfth embodiment will be described.
In the twelfth embodiment, surface-mounted components are used as the capacitors Cp1, Cp2, Cdc3, Cdc4, the bypass capacitor Cbp, and the choke coils Lch1, Lch2. may be configured.

In the twelfth embodiment, the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22 are spiral-shaped, but these transmission lines constitute a distributed constant circuit. and may be of other shapes. For example, these transmission lines may be straight.

[Thirteenth embodiment]
Next, a high frequency power amplifier according to a thirteenth embodiment will be described with reference to FIG.
FIG. 37 is a block diagram of a high frequency power amplifier according to the thirteenth embodiment. The high frequency power amplifier according to the thirteenth embodiment includes a plurality of differential amplifiers 51D connected in multiple stages. An unbalanced/balanced conversion circuit 50IB for converting a single-ended signal into a differential signal is connected to the input side of the first-stage differential amplifier 51D. The unbalanced/balanced conversion circuit 50IB has a function of converting the single-ended signal RFin into differential signals RF+ and RF- and performing impedance matching.

As the unbalanced/balanced conversion circuit 50IB, for example, the impedance conversion circuit (FIG. 4A) according to the second embodiment is used. A single-ended signal RFin is input to the third connection terminal T3, and differential signals RF+ and RF- are output from the first connection terminal T1 and the second connection terminal T2. The fourth connection terminal T4 is connected to ground. An impedance conversion circuit according to another embodiment having an unbalanced/balanced conversion function may be used as the unbalanced/balanced conversion circuit 50IB.

An impedance conversion circuit 50BB is connected as an inter-stage impedance matching circuit between the multiple stages of the differential amplifiers 51D. For the differential signal impedance conversion circuit 50BB, for example, the impedance conversion circuit (FIG. 26) according to the ninth embodiment is used. A differential signal is input from one terminal pair of a terminal pair consisting of a first connection terminal T1 and a second connection terminal T2 and a terminal pair consisting of a third connection terminal T3 and a fourth connection terminal T4. A differential signal is output from the terminal pair.

A balanced-unbalanced conversion circuit 50BI for converting a differential signal into a single-ended signal is connected to the output side of the final-stage differential amplifier 51D. The balanced-unbalanced conversion circuit 50BI has a function of converting the differential signals RF+ and RF- into a single-ended signal RFout and performing impedance matching.

For example, the impedance conversion circuit (FIG. 4A) according to the second embodiment is used for the balanced-unbalanced conversion circuit 50BI. Differential signals RF+ and RF- are input to the first connection terminal T1 and the second connection terminal T2, and a single-ended signal RFout is output from the third connection terminal T3. The fourth connection terminal T4 is connected to ground. An impedance conversion circuit according to another embodiment having a balance-unbalance conversion function may be used as the balance-unbalance conversion circuit 50BI.

Next, the excellent effects of the thirteenth embodiment will be described.
In the thirteenth embodiment, the impedance conversion circuit (FIG. 4A) according to the second embodiment or the like is used for the first-stage unbalanced-to-balanced conversion circuit 50IB and the final-stage balanced-to-unbalanced conversion circuit 50BI. The circuit 50BB uses the impedance conversion circuit (FIG. 26) according to the ninth embodiment. Therefore, sufficient isolation can be ensured between the input-side connection terminal and the output-side connection terminal.

Next, a modification of the thirteenth embodiment will be described.
In the thirteenth embodiment, the impedance conversion circuits according to the above embodiments are used as the first-stage unbalanced-to-balanced conversion circuit 50IB, the inter-stage impedance conversion circuit 50BB, and the final-stage balanced-to-unbalanced conversion circuit 50BI. The impedance conversion circuit according to the above-described embodiment may be used only for part of the unbalanced-to-balanced conversion circuit 50IB, the inter-stage impedance conversion circuit 50BB, and the final-stage balanced-to-unbalanced conversion circuit 50BI.

Next, a high-frequency power amplifier according to another modification of the thirteenth embodiment will be described with reference to FIG. FIG. 38 is a block diagram of a high frequency power amplifier according to another modification of the thirteenth embodiment. In this modification, single-ended signal amplifiers 51S are used for the input-side multiple stages of the multiple stages of amplifiers, and differential amplifiers 51D are used for the remaining multiple stages of amplifiers. An impedance conversion circuit 50II for impedance matching is connected between the input side of the first-stage amplifier 51S and the stage of the single-ended signal amplifier 51S.

An unbalanced/balanced conversion circuit 50IB is connected between the rearmost single-ended signal amplifier 51S and the frontmost differential amplifier 51D. The configuration on the downstream side of the unbalanced/balanced conversion circuit 50IB is the same as the configuration of the high frequency power amplifier (FIG. 37) according to the thirteenth embodiment.

As in this modification, the single-ended signal amplifier 51S and the differential amplifier 51D may be combined to form a multi-stage high-frequency power amplifier.

It goes without saying that each of the above-described embodiments is an example, and partial substitutions or combinations of configurations shown in different embodiments are possible. Similar actions and effects due to similar configurations of multiple embodiments will not be sequentially referred to for each embodiment. Furthermore, the invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

11 First main line 12 Second main line 21 First sub line 22 Second sub line 30 Laminated substrate 40 Transmission line transformer 41 Power supply circuit 42 Differential amplifier 50BB Differential signal impedance conversion circuit 50BI Balanced unbalanced conversion circuit 50IB Unbalanced balanced conversion circuit 50II Single-ended signal impedance conversion circuit 51D Differential amplifier 51S Single-ended signal amplifier 101 First main line 102 Second main line 103 First sub-line 104 Second sub-line

Claims (15)

a first main line whose both ends are a first node and a third node, respectively, and which transmits a high frequency signal between the first node and the third node;
a second main line having both ends as a second node and a fourth node, and transmitting a high frequency signal between the second node and the fourth node;
a first sub-line connected to the second node and electromagnetically coupled to the first main line;
One end is connected to the first node, the other end is connected to the end of the first sub-line not connected to the second node, and is electromagnetically connected to the second main line. a second sub-line to be coupled;
and a first capacitor connected in parallel to at least one of at least a portion of the second main line and at least a portion of the second sub-line. 2. The impedance conversion circuit according to claim 1, wherein said first capacitor is connected to both ends of said second main line. 3. The impedance conversion circuit according to claim 2, wherein said first capacitor is connected in parallel with said second main line. 4. The capacitor according to claim 1, further comprising a second capacitor connected in parallel to at least one of at least a portion of said first main line and at least a portion of said first sub-line. Impedance conversion circuit. A parallel reactance element having one terminal connected to the first node and the other terminal connected to the second node, or a parallel reactance element having one terminal connected to the third node and the other terminal connected to the fourth node 5. The impedance conversion circuit according to claim 1, further comprising connected parallel reactance elements. a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal connected to the first node, the second node, the third node, and the fourth node, respectively; The impedance conversion circuit according to any one of claims 1 to 5. 7. The impedance conversion circuit according to claim 6, wherein one of said second connection terminal and said fourth connection terminal is a ground terminal connected to a ground potential. A balanced-unbalanced transformation for outputting a signal input from one node pair of a node pair of the first node and the second node and a node pair of the third node and the fourth node from the other node pair. 8. The impedance conversion circuit according to claim 7, constituting a circuit. Between the first node and the first connection terminal, between the second node and the second connection terminal, between the third node and the third connection terminal, and between the fourth node and the third connection terminal. 9. The impedance conversion circuit according to any one of claims 6 to 8, further comprising a series reactance element inserted in series with at least one of the four connection terminals. a power terminal;
10. The device according to any one of claims 1 to 9, further comprising a choke coil connected between a portion where said first sub-line and said second sub-line are connected to each other and said power supply terminal. Impedance transformation circuit as described. a power terminal;
a first choke coil connected between the power supply terminal and the first connection terminal;
10. The impedance conversion circuit according to claim 6, further comprising a second choke coil connected between said power supply terminal and said second connection terminal. further comprising a laminated substrate in which dielectric layers and conductor layers are alternately laminated;
12. The impedance conversion circuit according to claim 1, wherein said first main line and said second main line are arranged in a conductor layer of said laminated substrate. 13. The impedance conversion circuit according to claim 12, wherein the laminated substrate includes a ceramic multilayer substrate, a multilayer resin substrate, or a semiconductor substrate on which a multilayer wiring layer is formed. An impedance conversion circuit according to claim 9 or 10,
and a differential amplifier in which one of a pair of differential output nodes and a pair of differential input nodes are connected to the first node and the second node, respectively. an impedance conversion circuit according to any one of claims 1 to 13;
a differential amplifier in which one of a pair of differential output nodes and a pair of differential input nodes are respectively connected to the first node and the second node;
The first capacitor and at least a portion of the second main line or at least a portion of the second sub line connected in parallel to the first capacitor resonate in parallel at a certain frequency in the operating frequency band of the differential amplifier. amplification module.

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